cmdide.c revision 1.28
1 /* $NetBSD: cmdide.c,v 1.28 2008/03/18 20:46:36 cube Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: cmdide.c,v 1.28 2008/03/18 20:46:36 cube Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_cmd_reg.h> 44 45 46 static int cmdide_match(device_t, cfdata_t, void *); 47 static void cmdide_attach(device_t, device_t, void *); 48 49 CFATTACH_DECL_NEW(cmdide, sizeof(struct pciide_softc), 50 cmdide_match, cmdide_attach, NULL, NULL); 51 52 static void cmd_chip_map(struct pciide_softc*, struct pci_attach_args*); 53 static void cmd0643_9_chip_map(struct pciide_softc*, struct pci_attach_args*); 54 static void cmd0643_9_setup_channel(struct ata_channel*); 55 static void cmd_channel_map(struct pci_attach_args *, struct pciide_softc *, 56 int); 57 static int cmd_pci_intr(void *); 58 static void cmd646_9_irqack(struct ata_channel *); 59 static void cmd680_chip_map(struct pciide_softc*, struct pci_attach_args*); 60 static void cmd680_setup_channel(struct ata_channel*); 61 static void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *, 62 int); 63 64 static const struct pciide_product_desc pciide_cmd_products[] = { 65 { PCI_PRODUCT_CMDTECH_640, 66 0, 67 "CMD Technology PCI0640", 68 cmd_chip_map 69 }, 70 { PCI_PRODUCT_CMDTECH_643, 71 0, 72 "CMD Technology PCI0643", 73 cmd0643_9_chip_map, 74 }, 75 { PCI_PRODUCT_CMDTECH_646, 76 0, 77 "CMD Technology PCI0646", 78 cmd0643_9_chip_map, 79 }, 80 { PCI_PRODUCT_CMDTECH_648, 81 0, 82 "CMD Technology PCI0648", 83 cmd0643_9_chip_map, 84 }, 85 { PCI_PRODUCT_CMDTECH_649, 86 0, 87 "CMD Technology PCI0649", 88 cmd0643_9_chip_map, 89 }, 90 { PCI_PRODUCT_CMDTECH_680, 91 0, 92 "Silicon Image 0680", 93 cmd680_chip_map, 94 }, 95 { 0, 96 0, 97 NULL, 98 NULL 99 } 100 }; 101 102 static int 103 cmdide_match(device_t parent, cfdata_t match, void *aux) 104 { 105 struct pci_attach_args *pa = aux; 106 107 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 108 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 109 return (2); 110 } 111 return (0); 112 } 113 114 static void 115 cmdide_attach(device_t parent, device_t self, void *aux) 116 { 117 struct pci_attach_args *pa = aux; 118 struct pciide_softc *sc = device_private(self); 119 120 sc->sc_wdcdev.sc_atac.atac_dev = self; 121 122 pciide_common_attach(sc, pa, 123 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 124 125 } 126 127 static void 128 cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 129 int channel) 130 { 131 struct pciide_channel *cp = &sc->pciide_channels[channel]; 132 bus_size_t cmdsize, ctlsize; 133 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 134 int interface, one_channel; 135 136 /* 137 * The 0648/0649 can be told to identify as a RAID controller. 138 * In this case, we have to fake interface 139 */ 140 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 141 interface = PCIIDE_INTERFACE_SETTABLE(0) | 142 PCIIDE_INTERFACE_SETTABLE(1); 143 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 144 CMD_CONF_DSA1) 145 interface |= PCIIDE_INTERFACE_PCI(0) | 146 PCIIDE_INTERFACE_PCI(1); 147 } else { 148 interface = PCI_INTERFACE(pa->pa_class); 149 } 150 151 sc->wdc_chanarray[channel] = &cp->ata_channel; 152 cp->name = PCIIDE_CHANNEL_NAME(channel); 153 cp->ata_channel.ch_channel = channel; 154 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 155 156 /* 157 * Older CMD64X doesn't have independent channels 158 */ 159 switch (sc->sc_pp->ide_product) { 160 case PCI_PRODUCT_CMDTECH_649: 161 one_channel = 0; 162 break; 163 default: 164 one_channel = 1; 165 break; 166 } 167 168 if (channel > 0 && one_channel) { 169 cp->ata_channel.ch_queue = 170 sc->pciide_channels[0].ata_channel.ch_queue; 171 } else { 172 cp->ata_channel.ch_queue = 173 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 174 } 175 if (cp->ata_channel.ch_queue == NULL) { 176 aprint_error("%s %s channel: " 177 "can't allocate memory for command queue", 178 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 179 return; 180 } 181 cp->ata_channel.ch_ndrive = 2; 182 183 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 184 "%s channel %s to %s mode\n", cp->name, 185 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 186 "configured" : "wired", 187 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 188 "native-PCI" : "compatibility"); 189 190 /* 191 * with a CMD PCI64x, if we get here, the first channel is enabled: 192 * there's no way to disable the first channel without disabling 193 * the whole device 194 */ 195 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 196 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 197 "%s channel ignored (disabled)\n", cp->name); 198 cp->ata_channel.ch_flags |= ATACH_DISABLED; 199 return; 200 } 201 202 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 203 } 204 205 static int 206 cmd_pci_intr(void *arg) 207 { 208 struct pciide_softc *sc = arg; 209 struct pciide_channel *cp; 210 struct ata_channel *wdc_cp; 211 int i, rv, crv; 212 u_int32_t priirq, secirq; 213 214 rv = 0; 215 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 216 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 217 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 218 cp = &sc->pciide_channels[i]; 219 wdc_cp = &cp->ata_channel; 220 /* If a compat channel skip. */ 221 if (cp->compat) 222 continue; 223 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 224 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 225 crv = wdcintr(wdc_cp); 226 if (crv == 0) { 227 aprint_error("%s:%d: bogus intr\n", 228 device_xname( 229 sc->sc_wdcdev.sc_atac.atac_dev), i); 230 sc->sc_wdcdev.irqack(wdc_cp); 231 } else 232 rv = 1; 233 } 234 } 235 return rv; 236 } 237 238 static void 239 cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 240 { 241 int channel; 242 243 /* 244 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 245 * and base addresses registers can be disabled at 246 * hardware level. In this case, the device is wired 247 * in compat mode and its first channel is always enabled, 248 * but we can't rely on PCI_COMMAND_IO_ENABLE. 249 * In fact, it seems that the first channel of the CMD PCI0640 250 * can't be disabled. 251 */ 252 253 #ifdef PCIIDE_CMD064x_DISABLE 254 if (pciide_chipen(sc, pa) == 0) 255 return; 256 #endif 257 258 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 259 "hardware does not support DMA\n"); 260 sc->sc_dma_ok = 0; 261 262 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 263 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 264 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 265 266 wdc_allocate_regs(&sc->sc_wdcdev); 267 268 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 269 channel++) { 270 cmd_channel_map(pa, sc, channel); 271 } 272 } 273 274 static void 275 cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 276 { 277 int channel; 278 pcireg_t rev = PCI_REVISION(pa->pa_class); 279 280 /* 281 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 282 * and base addresses registers can be disabled at 283 * hardware level. In this case, the device is wired 284 * in compat mode and its first channel is always enabled, 285 * but we can't rely on PCI_COMMAND_IO_ENABLE. 286 * In fact, it seems that the first channel of the CMD PCI0640 287 * can't be disabled. 288 */ 289 290 #ifdef PCIIDE_CMD064x_DISABLE 291 if (pciide_chipen(sc, pa) == 0) 292 return; 293 #endif 294 295 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 296 "bus-master DMA support present"); 297 pciide_mapreg_dma(sc, pa); 298 aprint_verbose("\n"); 299 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 300 if (sc->sc_dma_ok) { 301 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 302 switch (sc->sc_pp->ide_product) { 303 case PCI_PRODUCT_CMDTECH_649: 304 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 305 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 306 sc->sc_wdcdev.irqack = cmd646_9_irqack; 307 break; 308 case PCI_PRODUCT_CMDTECH_648: 309 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 310 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 311 sc->sc_wdcdev.irqack = cmd646_9_irqack; 312 break; 313 case PCI_PRODUCT_CMDTECH_646: 314 if (rev >= CMD0646U2_REV) { 315 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 316 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 317 } else if (rev >= CMD0646U_REV) { 318 /* 319 * Linux's driver claims that the 646U is broken 320 * with UDMA. Only enable it if we know what we're 321 * doing 322 */ 323 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 324 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 325 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 326 #endif 327 /* explicitly disable UDMA */ 328 pciide_pci_write(sc->sc_pc, sc->sc_tag, 329 CMD_UDMATIM(0), 0); 330 pciide_pci_write(sc->sc_pc, sc->sc_tag, 331 CMD_UDMATIM(1), 0); 332 } 333 sc->sc_wdcdev.irqack = cmd646_9_irqack; 334 break; 335 default: 336 sc->sc_wdcdev.irqack = pciide_irqack; 337 } 338 } 339 340 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 341 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 342 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 343 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 344 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel; 345 346 ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 347 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 348 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 349 DEBUG_PROBE); 350 351 wdc_allocate_regs(&sc->sc_wdcdev); 352 353 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 354 channel++) 355 cmd_channel_map(pa, sc, channel); 356 357 /* 358 * note - this also makes sure we clear the irq disable and reset 359 * bits 360 */ 361 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 362 ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 363 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 364 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 365 DEBUG_PROBE); 366 } 367 368 static void 369 cmd0643_9_setup_channel(struct ata_channel *chp) 370 { 371 struct ata_drive_datas *drvp; 372 u_int8_t tim; 373 u_int32_t idedma_ctl, udma_reg; 374 int drive, s; 375 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 376 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 377 378 idedma_ctl = 0; 379 /* setup DMA if needed */ 380 pciide_channel_dma_setup(cp); 381 382 for (drive = 0; drive < 2; drive++) { 383 drvp = &chp->ch_drive[drive]; 384 /* If no drive, skip */ 385 if ((drvp->drive_flags & DRIVE) == 0) 386 continue; 387 /* add timing values, setup DMA if needed */ 388 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 389 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 390 if (drvp->drive_flags & DRIVE_UDMA) { 391 /* UltraDMA on a 646U2, 0648 or 0649 */ 392 s = splbio(); 393 drvp->drive_flags &= ~DRIVE_DMA; 394 splx(s); 395 udma_reg = pciide_pci_read(sc->sc_pc, 396 sc->sc_tag, CMD_UDMATIM(chp->ch_channel)); 397 if (drvp->UDMA_mode > 2 && 398 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 399 CMD_BICSR) & 400 CMD_BICSR_80(chp->ch_channel)) == 0) 401 drvp->UDMA_mode = 2; 402 if (drvp->UDMA_mode > 2) 403 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 404 else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2) 405 udma_reg |= CMD_UDMATIM_UDMA33(drive); 406 udma_reg |= CMD_UDMATIM_UDMA(drive); 407 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 408 CMD_UDMATIM_TIM_OFF(drive)); 409 udma_reg |= 410 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 411 CMD_UDMATIM_TIM_OFF(drive)); 412 pciide_pci_write(sc->sc_pc, sc->sc_tag, 413 CMD_UDMATIM(chp->ch_channel), udma_reg); 414 } else { 415 /* 416 * use Multiword DMA. 417 * Timings will be used for both PIO and DMA, 418 * so adjust DMA mode if needed 419 * if we have a 0646U2/8/9, turn off UDMA 420 */ 421 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 422 udma_reg = pciide_pci_read(sc->sc_pc, 423 sc->sc_tag, 424 CMD_UDMATIM(chp->ch_channel)); 425 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 426 pciide_pci_write(sc->sc_pc, sc->sc_tag, 427 CMD_UDMATIM(chp->ch_channel), 428 udma_reg); 429 } 430 if (drvp->PIO_mode >= 3 && 431 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 432 drvp->DMA_mode = drvp->PIO_mode - 2; 433 } 434 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 435 } 436 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 437 } 438 pciide_pci_write(sc->sc_pc, sc->sc_tag, 439 CMD_DATA_TIM(chp->ch_channel, drive), tim); 440 } 441 if (idedma_ctl != 0) { 442 /* Add software bits in status register */ 443 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 444 idedma_ctl); 445 } 446 } 447 448 static void 449 cmd646_9_irqack(struct ata_channel *chp) 450 { 451 u_int32_t priirq, secirq; 452 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 453 454 if (chp->ch_channel == 0) { 455 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 456 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 457 } else { 458 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 459 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 460 } 461 pciide_irqack(chp); 462 } 463 464 static void 465 cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 466 { 467 int channel; 468 469 if (pciide_chipen(sc, pa) == 0) 470 return; 471 472 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 473 "bus-master DMA support present"); 474 pciide_mapreg_dma(sc, pa); 475 aprint_verbose("\n"); 476 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 477 if (sc->sc_dma_ok) { 478 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 479 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 480 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 481 sc->sc_wdcdev.irqack = pciide_irqack; 482 } 483 484 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 485 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 486 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 487 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 488 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel; 489 490 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 491 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 492 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 493 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 494 495 wdc_allocate_regs(&sc->sc_wdcdev); 496 497 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 498 channel++) 499 cmd680_channel_map(pa, sc, channel); 500 } 501 502 static void 503 cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 504 int channel) 505 { 506 struct pciide_channel *cp = &sc->pciide_channels[channel]; 507 bus_size_t cmdsize, ctlsize; 508 int interface, i, reg; 509 static const u_int8_t init_val[] = 510 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 511 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 512 513 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 514 interface = PCIIDE_INTERFACE_SETTABLE(0) | 515 PCIIDE_INTERFACE_SETTABLE(1); 516 interface |= PCIIDE_INTERFACE_PCI(0) | 517 PCIIDE_INTERFACE_PCI(1); 518 } else { 519 interface = PCI_INTERFACE(pa->pa_class); 520 } 521 522 sc->wdc_chanarray[channel] = &cp->ata_channel; 523 cp->name = PCIIDE_CHANNEL_NAME(channel); 524 cp->ata_channel.ch_channel = channel; 525 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 526 527 cp->ata_channel.ch_queue = 528 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 529 if (cp->ata_channel.ch_queue == NULL) { 530 aprint_error("%s %s channel: " 531 "can't allocate memory for command queue", 532 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 533 return; 534 } 535 cp->ata_channel.ch_ndrive = 2; 536 537 /* XXX */ 538 reg = 0xa2 + channel * 16; 539 for (i = 0; i < sizeof(init_val); i++) 540 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 541 542 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 543 "%s channel %s to %s mode\n", cp->name, 544 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 545 "configured" : "wired", 546 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 547 "native-PCI" : "compatibility"); 548 549 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 550 } 551 552 static void 553 cmd680_setup_channel(struct ata_channel *chp) 554 { 555 struct ata_drive_datas *drvp; 556 u_int8_t mode, off, scsc; 557 u_int16_t val; 558 u_int32_t idedma_ctl; 559 int drive, s; 560 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 561 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 562 pci_chipset_tag_t pc = sc->sc_pc; 563 pcitag_t pa = sc->sc_tag; 564 static const u_int8_t udma2_tbl[] = 565 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 566 static const u_int8_t udma_tbl[] = 567 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 568 static const u_int16_t dma_tbl[] = 569 { 0x2208, 0x10c2, 0x10c1 }; 570 static const u_int16_t pio_tbl[] = 571 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 572 573 idedma_ctl = 0; 574 pciide_channel_dma_setup(cp); 575 mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4); 576 577 for (drive = 0; drive < 2; drive++) { 578 drvp = &chp->ch_drive[drive]; 579 /* If no drive, skip */ 580 if ((drvp->drive_flags & DRIVE) == 0) 581 continue; 582 mode &= ~(0x03 << (drive * 4)); 583 if (drvp->drive_flags & DRIVE_UDMA) { 584 s = splbio(); 585 drvp->drive_flags &= ~DRIVE_DMA; 586 splx(s); 587 off = 0xa0 + chp->ch_channel * 16; 588 if (drvp->UDMA_mode > 2 && 589 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 590 drvp->UDMA_mode = 2; 591 scsc = pciide_pci_read(pc, pa, 0x8a); 592 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 593 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 594 scsc = pciide_pci_read(pc, pa, 0x8a); 595 if ((scsc & 0x30) == 0) 596 drvp->UDMA_mode = 5; 597 } 598 mode |= 0x03 << (drive * 4); 599 off = 0xac + chp->ch_channel * 16 + drive * 2; 600 val = pciide_pci_read(pc, pa, off) & ~0x3f; 601 if (scsc & 0x30) 602 val |= udma2_tbl[drvp->UDMA_mode]; 603 else 604 val |= udma_tbl[drvp->UDMA_mode]; 605 pciide_pci_write(pc, pa, off, val); 606 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 607 } else if (drvp->drive_flags & DRIVE_DMA) { 608 mode |= 0x02 << (drive * 4); 609 off = 0xa8 + chp->ch_channel * 16 + drive * 2; 610 val = dma_tbl[drvp->DMA_mode]; 611 pciide_pci_write(pc, pa, off, val & 0xff); 612 pciide_pci_write(pc, pa, off+1, val >> 8); 613 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 614 } else { 615 mode |= 0x01 << (drive * 4); 616 off = 0xa4 + chp->ch_channel * 16 + drive * 2; 617 val = pio_tbl[drvp->PIO_mode]; 618 pciide_pci_write(pc, pa, off, val & 0xff); 619 pciide_pci_write(pc, pa, off+1, val >> 8); 620 } 621 } 622 623 pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode); 624 if (idedma_ctl != 0) { 625 /* Add software bits in status register */ 626 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 627 idedma_ctl); 628 } 629 } 630
Indexes created Tue Sep 23 23:09:58 GMT 2025