cmdide.c revision 1.30
1 /* $NetBSD: cmdide.c,v 1.30 2010/11/05 18:07:24 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: cmdide.c,v 1.30 2010/11/05 18:07:24 jakllsch Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_cmd_reg.h> 39 40 41 static int cmdide_match(device_t, cfdata_t, void *); 42 static void cmdide_attach(device_t, device_t, void *); 43 44 CFATTACH_DECL_NEW(cmdide, sizeof(struct pciide_softc), 45 cmdide_match, cmdide_attach, NULL, NULL); 46 47 static void cmd_chip_map(struct pciide_softc*, struct pci_attach_args*); 48 static void cmd0643_9_chip_map(struct pciide_softc*, struct pci_attach_args*); 49 static void cmd0643_9_setup_channel(struct ata_channel*); 50 static void cmd_channel_map(struct pci_attach_args *, struct pciide_softc *, 51 int); 52 static int cmd_pci_intr(void *); 53 static void cmd646_9_irqack(struct ata_channel *); 54 static void cmd680_chip_map(struct pciide_softc*, struct pci_attach_args*); 55 static void cmd680_setup_channel(struct ata_channel*); 56 static void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *, 57 int); 58 59 static const struct pciide_product_desc pciide_cmd_products[] = { 60 { PCI_PRODUCT_CMDTECH_640, 61 0, 62 "CMD Technology PCI0640", 63 cmd_chip_map 64 }, 65 { PCI_PRODUCT_CMDTECH_643, 66 0, 67 "CMD Technology PCI0643", 68 cmd0643_9_chip_map, 69 }, 70 { PCI_PRODUCT_CMDTECH_646, 71 0, 72 "CMD Technology PCI0646", 73 cmd0643_9_chip_map, 74 }, 75 { PCI_PRODUCT_CMDTECH_648, 76 0, 77 "CMD Technology PCI0648", 78 cmd0643_9_chip_map, 79 }, 80 { PCI_PRODUCT_CMDTECH_649, 81 0, 82 "CMD Technology PCI0649", 83 cmd0643_9_chip_map, 84 }, 85 { PCI_PRODUCT_CMDTECH_680, 86 0, 87 "Silicon Image 0680", 88 cmd680_chip_map, 89 }, 90 { 0, 91 0, 92 NULL, 93 NULL 94 } 95 }; 96 97 static int 98 cmdide_match(device_t parent, cfdata_t match, void *aux) 99 { 100 struct pci_attach_args *pa = aux; 101 102 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 103 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 104 return (2); 105 } 106 return (0); 107 } 108 109 static void 110 cmdide_attach(device_t parent, device_t self, void *aux) 111 { 112 struct pci_attach_args *pa = aux; 113 struct pciide_softc *sc = device_private(self); 114 115 sc->sc_wdcdev.sc_atac.atac_dev = self; 116 117 pciide_common_attach(sc, pa, 118 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 119 120 } 121 122 static void 123 cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 124 int channel) 125 { 126 struct pciide_channel *cp = &sc->pciide_channels[channel]; 127 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 128 int interface, one_channel; 129 130 /* 131 * The 0648/0649 can be told to identify as a RAID controller. 132 * In this case, we have to fake interface 133 */ 134 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 135 interface = PCIIDE_INTERFACE_SETTABLE(0) | 136 PCIIDE_INTERFACE_SETTABLE(1); 137 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 138 CMD_CONF_DSA1) 139 interface |= PCIIDE_INTERFACE_PCI(0) | 140 PCIIDE_INTERFACE_PCI(1); 141 } else { 142 interface = PCI_INTERFACE(pa->pa_class); 143 } 144 145 sc->wdc_chanarray[channel] = &cp->ata_channel; 146 cp->name = PCIIDE_CHANNEL_NAME(channel); 147 cp->ata_channel.ch_channel = channel; 148 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 149 150 /* 151 * Older CMD64X doesn't have independent channels 152 */ 153 switch (sc->sc_pp->ide_product) { 154 case PCI_PRODUCT_CMDTECH_649: 155 one_channel = 0; 156 break; 157 default: 158 one_channel = 1; 159 break; 160 } 161 162 if (channel > 0 && one_channel) { 163 cp->ata_channel.ch_queue = 164 sc->pciide_channels[0].ata_channel.ch_queue; 165 } else { 166 cp->ata_channel.ch_queue = 167 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 168 } 169 if (cp->ata_channel.ch_queue == NULL) { 170 aprint_error("%s %s channel: " 171 "can't allocate memory for command queue", 172 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 173 return; 174 } 175 cp->ata_channel.ch_ndrive = 2; 176 177 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 178 "%s channel %s to %s mode\n", cp->name, 179 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 180 "configured" : "wired", 181 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 182 "native-PCI" : "compatibility"); 183 184 /* 185 * with a CMD PCI64x, if we get here, the first channel is enabled: 186 * there's no way to disable the first channel without disabling 187 * the whole device 188 */ 189 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 190 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 191 "%s channel ignored (disabled)\n", cp->name); 192 cp->ata_channel.ch_flags |= ATACH_DISABLED; 193 return; 194 } 195 196 pciide_mapchan(pa, cp, interface, cmd_pci_intr); 197 } 198 199 static int 200 cmd_pci_intr(void *arg) 201 { 202 struct pciide_softc *sc = arg; 203 struct pciide_channel *cp; 204 struct ata_channel *wdc_cp; 205 int i, rv, crv; 206 u_int32_t priirq, secirq; 207 208 rv = 0; 209 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 210 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 211 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 212 cp = &sc->pciide_channels[i]; 213 wdc_cp = &cp->ata_channel; 214 /* If a compat channel skip. */ 215 if (cp->compat) 216 continue; 217 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 218 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 219 crv = wdcintr(wdc_cp); 220 if (crv == 0) { 221 aprint_error("%s:%d: bogus intr\n", 222 device_xname( 223 sc->sc_wdcdev.sc_atac.atac_dev), i); 224 sc->sc_wdcdev.irqack(wdc_cp); 225 } else 226 rv = 1; 227 } 228 } 229 return rv; 230 } 231 232 static void 233 cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 234 { 235 int channel; 236 237 /* 238 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 239 * and base addresses registers can be disabled at 240 * hardware level. In this case, the device is wired 241 * in compat mode and its first channel is always enabled, 242 * but we can't rely on PCI_COMMAND_IO_ENABLE. 243 * In fact, it seems that the first channel of the CMD PCI0640 244 * can't be disabled. 245 */ 246 247 #ifdef PCIIDE_CMD064x_DISABLE 248 if (pciide_chipen(sc, pa) == 0) 249 return; 250 #endif 251 252 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 253 "hardware does not support DMA\n"); 254 sc->sc_dma_ok = 0; 255 256 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 257 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 258 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 259 260 wdc_allocate_regs(&sc->sc_wdcdev); 261 262 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 263 channel++) { 264 cmd_channel_map(pa, sc, channel); 265 } 266 } 267 268 static void 269 cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 270 { 271 int channel; 272 pcireg_t rev = PCI_REVISION(pa->pa_class); 273 274 /* 275 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 276 * and base addresses registers can be disabled at 277 * hardware level. In this case, the device is wired 278 * in compat mode and its first channel is always enabled, 279 * but we can't rely on PCI_COMMAND_IO_ENABLE. 280 * In fact, it seems that the first channel of the CMD PCI0640 281 * can't be disabled. 282 */ 283 284 #ifdef PCIIDE_CMD064x_DISABLE 285 if (pciide_chipen(sc, pa) == 0) 286 return; 287 #endif 288 289 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 290 "bus-master DMA support present"); 291 pciide_mapreg_dma(sc, pa); 292 aprint_verbose("\n"); 293 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 294 if (sc->sc_dma_ok) { 295 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 296 switch (sc->sc_pp->ide_product) { 297 case PCI_PRODUCT_CMDTECH_649: 298 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 299 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 300 sc->sc_wdcdev.irqack = cmd646_9_irqack; 301 break; 302 case PCI_PRODUCT_CMDTECH_648: 303 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 304 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 305 sc->sc_wdcdev.irqack = cmd646_9_irqack; 306 break; 307 case PCI_PRODUCT_CMDTECH_646: 308 if (rev >= CMD0646U2_REV) { 309 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 310 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 311 } else if (rev >= CMD0646U_REV) { 312 /* 313 * Linux's driver claims that the 646U is broken 314 * with UDMA. Only enable it if we know what we're 315 * doing 316 */ 317 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 318 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 319 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 320 #endif 321 /* explicitly disable UDMA */ 322 pciide_pci_write(sc->sc_pc, sc->sc_tag, 323 CMD_UDMATIM(0), 0); 324 pciide_pci_write(sc->sc_pc, sc->sc_tag, 325 CMD_UDMATIM(1), 0); 326 } 327 sc->sc_wdcdev.irqack = cmd646_9_irqack; 328 break; 329 default: 330 sc->sc_wdcdev.irqack = pciide_irqack; 331 } 332 } 333 334 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 335 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 336 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 337 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 338 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel; 339 340 ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 341 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 342 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 343 DEBUG_PROBE); 344 345 wdc_allocate_regs(&sc->sc_wdcdev); 346 347 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 348 channel++) 349 cmd_channel_map(pa, sc, channel); 350 351 /* 352 * note - this also makes sure we clear the irq disable and reset 353 * bits 354 */ 355 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 356 ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 357 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 358 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 359 DEBUG_PROBE); 360 } 361 362 static void 363 cmd0643_9_setup_channel(struct ata_channel *chp) 364 { 365 struct ata_drive_datas *drvp; 366 u_int8_t tim; 367 u_int32_t idedma_ctl, udma_reg; 368 int drive, s; 369 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 370 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 371 372 idedma_ctl = 0; 373 /* setup DMA if needed */ 374 pciide_channel_dma_setup(cp); 375 376 for (drive = 0; drive < 2; drive++) { 377 drvp = &chp->ch_drive[drive]; 378 /* If no drive, skip */ 379 if ((drvp->drive_flags & DRIVE) == 0) 380 continue; 381 /* add timing values, setup DMA if needed */ 382 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 383 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 384 if (drvp->drive_flags & DRIVE_UDMA) { 385 /* UltraDMA on a 646U2, 0648 or 0649 */ 386 s = splbio(); 387 drvp->drive_flags &= ~DRIVE_DMA; 388 splx(s); 389 udma_reg = pciide_pci_read(sc->sc_pc, 390 sc->sc_tag, CMD_UDMATIM(chp->ch_channel)); 391 if (drvp->UDMA_mode > 2 && 392 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 393 CMD_BICSR) & 394 CMD_BICSR_80(chp->ch_channel)) == 0) 395 drvp->UDMA_mode = 2; 396 if (drvp->UDMA_mode > 2) 397 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 398 else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2) 399 udma_reg |= CMD_UDMATIM_UDMA33(drive); 400 udma_reg |= CMD_UDMATIM_UDMA(drive); 401 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 402 CMD_UDMATIM_TIM_OFF(drive)); 403 udma_reg |= 404 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 405 CMD_UDMATIM_TIM_OFF(drive)); 406 pciide_pci_write(sc->sc_pc, sc->sc_tag, 407 CMD_UDMATIM(chp->ch_channel), udma_reg); 408 } else { 409 /* 410 * use Multiword DMA. 411 * Timings will be used for both PIO and DMA, 412 * so adjust DMA mode if needed 413 * if we have a 0646U2/8/9, turn off UDMA 414 */ 415 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 416 udma_reg = pciide_pci_read(sc->sc_pc, 417 sc->sc_tag, 418 CMD_UDMATIM(chp->ch_channel)); 419 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 420 pciide_pci_write(sc->sc_pc, sc->sc_tag, 421 CMD_UDMATIM(chp->ch_channel), 422 udma_reg); 423 } 424 if (drvp->PIO_mode >= 3 && 425 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 426 drvp->DMA_mode = drvp->PIO_mode - 2; 427 } 428 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 429 } 430 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 431 } 432 pciide_pci_write(sc->sc_pc, sc->sc_tag, 433 CMD_DATA_TIM(chp->ch_channel, drive), tim); 434 } 435 if (idedma_ctl != 0) { 436 /* Add software bits in status register */ 437 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 438 idedma_ctl); 439 } 440 } 441 442 static void 443 cmd646_9_irqack(struct ata_channel *chp) 444 { 445 u_int32_t priirq, secirq; 446 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 447 448 if (chp->ch_channel == 0) { 449 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 450 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 451 } else { 452 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 453 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 454 } 455 pciide_irqack(chp); 456 } 457 458 static void 459 cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 460 { 461 int channel; 462 463 if (pciide_chipen(sc, pa) == 0) 464 return; 465 466 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 467 "bus-master DMA support present"); 468 pciide_mapreg_dma(sc, pa); 469 aprint_verbose("\n"); 470 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 471 if (sc->sc_dma_ok) { 472 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 473 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 474 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 475 sc->sc_wdcdev.irqack = pciide_irqack; 476 } 477 478 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 479 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 480 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 481 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 482 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel; 483 484 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 485 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 486 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 487 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 488 489 wdc_allocate_regs(&sc->sc_wdcdev); 490 491 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 492 channel++) 493 cmd680_channel_map(pa, sc, channel); 494 } 495 496 static void 497 cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 498 int channel) 499 { 500 struct pciide_channel *cp = &sc->pciide_channels[channel]; 501 int interface, i, reg; 502 static const u_int8_t init_val[] = 503 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 504 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 505 506 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 507 interface = PCIIDE_INTERFACE_SETTABLE(0) | 508 PCIIDE_INTERFACE_SETTABLE(1); 509 interface |= PCIIDE_INTERFACE_PCI(0) | 510 PCIIDE_INTERFACE_PCI(1); 511 } else { 512 interface = PCI_INTERFACE(pa->pa_class); 513 } 514 515 sc->wdc_chanarray[channel] = &cp->ata_channel; 516 cp->name = PCIIDE_CHANNEL_NAME(channel); 517 cp->ata_channel.ch_channel = channel; 518 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 519 520 cp->ata_channel.ch_queue = 521 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 522 if (cp->ata_channel.ch_queue == NULL) { 523 aprint_error("%s %s channel: " 524 "can't allocate memory for command queue", 525 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 526 return; 527 } 528 cp->ata_channel.ch_ndrive = 2; 529 530 /* XXX */ 531 reg = 0xa2 + channel * 16; 532 for (i = 0; i < sizeof(init_val); i++) 533 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 534 535 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 536 "%s channel %s to %s mode\n", cp->name, 537 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 538 "configured" : "wired", 539 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 540 "native-PCI" : "compatibility"); 541 542 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 543 } 544 545 static void 546 cmd680_setup_channel(struct ata_channel *chp) 547 { 548 struct ata_drive_datas *drvp; 549 u_int8_t mode, off, scsc; 550 u_int16_t val; 551 u_int32_t idedma_ctl; 552 int drive, s; 553 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 554 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 555 pci_chipset_tag_t pc = sc->sc_pc; 556 pcitag_t pa = sc->sc_tag; 557 static const u_int8_t udma2_tbl[] = 558 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 559 static const u_int8_t udma_tbl[] = 560 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 561 static const u_int16_t dma_tbl[] = 562 { 0x2208, 0x10c2, 0x10c1 }; 563 static const u_int16_t pio_tbl[] = 564 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 565 566 idedma_ctl = 0; 567 pciide_channel_dma_setup(cp); 568 mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4); 569 570 for (drive = 0; drive < 2; drive++) { 571 drvp = &chp->ch_drive[drive]; 572 /* If no drive, skip */ 573 if ((drvp->drive_flags & DRIVE) == 0) 574 continue; 575 mode &= ~(0x03 << (drive * 4)); 576 if (drvp->drive_flags & DRIVE_UDMA) { 577 s = splbio(); 578 drvp->drive_flags &= ~DRIVE_DMA; 579 splx(s); 580 off = 0xa0 + chp->ch_channel * 16; 581 if (drvp->UDMA_mode > 2 && 582 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 583 drvp->UDMA_mode = 2; 584 scsc = pciide_pci_read(pc, pa, 0x8a); 585 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 586 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 587 scsc = pciide_pci_read(pc, pa, 0x8a); 588 if ((scsc & 0x30) == 0) 589 drvp->UDMA_mode = 5; 590 } 591 mode |= 0x03 << (drive * 4); 592 off = 0xac + chp->ch_channel * 16 + drive * 2; 593 val = pciide_pci_read(pc, pa, off) & ~0x3f; 594 if (scsc & 0x30) 595 val |= udma2_tbl[drvp->UDMA_mode]; 596 else 597 val |= udma_tbl[drvp->UDMA_mode]; 598 pciide_pci_write(pc, pa, off, val); 599 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 600 } else if (drvp->drive_flags & DRIVE_DMA) { 601 mode |= 0x02 << (drive * 4); 602 off = 0xa8 + chp->ch_channel * 16 + drive * 2; 603 val = dma_tbl[drvp->DMA_mode]; 604 pciide_pci_write(pc, pa, off, val & 0xff); 605 pciide_pci_write(pc, pa, off+1, val >> 8); 606 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 607 } else { 608 mode |= 0x01 << (drive * 4); 609 off = 0xa4 + chp->ch_channel * 16 + drive * 2; 610 val = pio_tbl[drvp->PIO_mode]; 611 pciide_pci_write(pc, pa, off, val & 0xff); 612 pciide_pci_write(pc, pa, off+1, val >> 8); 613 } 614 } 615 616 pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode); 617 if (idedma_ctl != 0) { 618 /* Add software bits in status register */ 619 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 620 idedma_ctl); 621 } 622 } 623
Indexes created Thu Sep 25 16:09:42 GMT 2025