cmdide.c revision 1.38.2.2
1 /* $NetBSD: cmdide.c,v 1.38.2.2 2017/12/03 11:37:07 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: cmdide.c,v 1.38.2.2 2017/12/03 11:37:07 jdolecek Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/atomic.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_cmd_reg.h> 39 40 #define CMDIDE_ACT_CHANNEL_NONE 0xff 41 42 static int cmdide_match(device_t, cfdata_t, void *); 43 static void cmdide_attach(device_t, device_t, void *); 44 45 CFATTACH_DECL_NEW(cmdide, sizeof(struct pciide_softc), 46 cmdide_match, cmdide_attach, pciide_detach, NULL); 47 48 static void cmd_chip_map(struct pciide_softc*, const struct pci_attach_args*); 49 static void cmd0643_9_chip_map(struct pciide_softc*, 50 const struct pci_attach_args*); 51 static void cmd0643_9_setup_channel(struct ata_channel*); 52 static void cmd_channel_map(const struct pci_attach_args *, 53 struct pciide_softc *, int); 54 static int cmd064x_claim_hw(struct ata_channel *, int); 55 static void cmd064x_free_hw(struct ata_channel *); 56 static int cmd_pci_intr(void *); 57 static void cmd646_9_irqack(struct ata_channel *); 58 static void cmd680_chip_map(struct pciide_softc*, 59 const struct pci_attach_args*); 60 static void cmd680_setup_channel(struct ata_channel*); 61 static void cmd680_channel_map(const struct pci_attach_args *, 62 struct pciide_softc *, int); 63 64 /* Older CMD64X doesn't have independent channels */ 65 static const struct pciide_product_desc pciide_cmd_products[] = { 66 { PCI_PRODUCT_CMDTECH_640, 67 IDE_SHARED_CHANNELS, 68 "CMD Technology PCI0640", 69 cmd_chip_map 70 }, 71 { PCI_PRODUCT_CMDTECH_643, 72 IDE_SHARED_CHANNELS, 73 "CMD Technology PCI0643", 74 cmd0643_9_chip_map, 75 }, 76 { PCI_PRODUCT_CMDTECH_646, 77 IDE_SHARED_CHANNELS, 78 "CMD Technology PCI0646", 79 cmd0643_9_chip_map, 80 }, 81 { PCI_PRODUCT_CMDTECH_648, 82 IDE_SHARED_CHANNELS, 83 "CMD Technology PCI0648", 84 cmd0643_9_chip_map, 85 }, 86 { PCI_PRODUCT_CMDTECH_649, 87 0, 88 "CMD Technology PCI0649", 89 cmd0643_9_chip_map, 90 }, 91 { PCI_PRODUCT_CMDTECH_680, 92 0, 93 "Silicon Image 0680", 94 cmd680_chip_map, 95 }, 96 { 0, 97 0, 98 NULL, 99 NULL 100 } 101 }; 102 103 static int 104 cmdide_match(device_t parent, cfdata_t match, void *aux) 105 { 106 struct pci_attach_args *pa = aux; 107 108 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 109 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 110 return (2); 111 } 112 return (0); 113 } 114 115 static void 116 cmdide_attach(device_t parent, device_t self, void *aux) 117 { 118 struct pci_attach_args *pa = aux; 119 struct pciide_softc *sc = device_private(self); 120 121 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 122 123 sc->sc_wdcdev.sc_atac.atac_dev = self; 124 125 pciide_common_attach(sc, pa, 126 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 127 128 } 129 130 static void 131 cmd_channel_map(const struct pci_attach_args *pa, struct pciide_softc *sc, 132 int channel) 133 { 134 struct pciide_channel *cp = &sc->pciide_channels[channel]; 135 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 136 int interface; 137 bool one_channel = ISSET(sc->sc_pp->ide_flags, IDE_SHARED_CHANNELS); 138 139 /* 140 * The 0648/0649 can be told to identify as a RAID controller. 141 * In this case, we have to fake interface 142 */ 143 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 144 interface = PCIIDE_INTERFACE_SETTABLE(0) | 145 PCIIDE_INTERFACE_SETTABLE(1); 146 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 147 CMD_CONF_DSA1) 148 interface |= PCIIDE_INTERFACE_PCI(0) | 149 PCIIDE_INTERFACE_PCI(1); 150 } else { 151 interface = PCI_INTERFACE(pa->pa_class); 152 } 153 154 sc->wdc_chanarray[channel] = &cp->ata_channel; 155 cp->name = PCIIDE_CHANNEL_NAME(channel); 156 cp->ata_channel.ch_channel = channel; 157 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 158 159 if (channel > 0 && one_channel) { 160 /* Channels are not independant, need synchronization */ 161 sc->sc_wdcdev.sc_atac.atac_claim_hw = cmd064x_claim_hw; 162 sc->sc_wdcdev.sc_atac.atac_free_hw = cmd064x_free_hw; 163 sc->sc_cmd_act_channel = CMDIDE_ACT_CHANNEL_NONE; 164 } 165 166 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 167 "%s channel %s to %s mode%s\n", cp->name, 168 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 169 "configured" : "wired", 170 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 171 "native-PCI" : "compatibility", 172 one_channel ? ", channel non-independant" : ""); 173 174 /* 175 * with a CMD PCI64x, if we get here, the first channel is enabled: 176 * there's no way to disable the first channel without disabling 177 * the whole device 178 */ 179 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 180 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 181 "%s channel ignored (disabled)\n", cp->name); 182 cp->ata_channel.ch_flags |= ATACH_DISABLED; 183 return; 184 } 185 186 pciide_mapchan(pa, cp, interface, cmd_pci_intr); 187 } 188 189 /* 190 * Check if we can execute next xfer on the channel. 191 * Called with chp channel lock held. 192 */ 193 static int 194 cmd064x_claim_hw(struct ata_channel *chp, int maysleep) 195 { 196 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 197 198 return atomic_cas_uint(&sc->sc_cmd_act_channel, 199 CMDIDE_ACT_CHANNEL_NONE, chp->ch_channel) 200 == CMDIDE_ACT_CHANNEL_NONE; 201 } 202 203 /* Allow another channel to run. Called with ochp channel lock held. */ 204 static void 205 cmd064x_free_hw(struct ata_channel *ochp) 206 { 207 struct pciide_softc *sc = CHAN_TO_PCIIDE(ochp); 208 uint oact = atomic_cas_uint(&sc->sc_cmd_act_channel, 209 ochp->ch_channel, CMDIDE_ACT_CHANNEL_NONE); 210 struct ata_channel *nchp; 211 212 KASSERT(oact == ochp->ch_channel); 213 214 /* Start the other channel(s) */ 215 for(uint i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 216 /* Skip the current channel */ 217 if (i == oact) 218 continue; 219 220 nchp = &sc->pciide_channels[i].ata_channel; 221 if (nchp->ch_ndrives == 0) 222 continue; 223 224 atastart(nchp); 225 } 226 } 227 228 static int 229 cmd_pci_intr(void *arg) 230 { 231 struct pciide_softc *sc = arg; 232 struct pciide_channel *cp; 233 struct ata_channel *wdc_cp; 234 int i, rv, crv; 235 u_int32_t priirq, secirq; 236 237 rv = 0; 238 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 239 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 240 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 241 cp = &sc->pciide_channels[i]; 242 wdc_cp = &cp->ata_channel; 243 /* If a compat channel skip. */ 244 if (cp->compat) 245 continue; 246 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 247 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 248 crv = wdcintr(wdc_cp); 249 if (crv == 0) { 250 aprint_error("%s:%d: bogus intr\n", 251 device_xname( 252 sc->sc_wdcdev.sc_atac.atac_dev), i); 253 sc->sc_wdcdev.irqack(wdc_cp); 254 } else 255 rv = 1; 256 } 257 } 258 return rv; 259 } 260 261 static void 262 cmd_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 263 { 264 int channel; 265 266 /* 267 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 268 * and base addresses registers can be disabled at 269 * hardware level. In this case, the device is wired 270 * in compat mode and its first channel is always enabled, 271 * but we can't rely on PCI_COMMAND_IO_ENABLE. 272 * In fact, it seems that the first channel of the CMD PCI0640 273 * can't be disabled. 274 */ 275 276 #ifdef PCIIDE_CMD064x_DISABLE 277 if (pciide_chipen(sc, pa) == 0) 278 return; 279 #endif 280 281 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 282 "hardware does not support DMA\n"); 283 sc->sc_dma_ok = 0; 284 285 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 286 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 287 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 288 sc->sc_wdcdev.wdc_maxdrives = 2; 289 290 wdc_allocate_regs(&sc->sc_wdcdev); 291 292 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 293 channel++) { 294 cmd_channel_map(pa, sc, channel); 295 } 296 } 297 298 static void 299 cmd0643_9_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 300 { 301 int channel; 302 pcireg_t rev = PCI_REVISION(pa->pa_class); 303 304 /* 305 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 306 * and base addresses registers can be disabled at 307 * hardware level. In this case, the device is wired 308 * in compat mode and its first channel is always enabled, 309 * but we can't rely on PCI_COMMAND_IO_ENABLE. 310 * In fact, it seems that the first channel of the CMD PCI0640 311 * can't be disabled. 312 */ 313 314 #ifdef PCIIDE_CMD064x_DISABLE 315 if (pciide_chipen(sc, pa) == 0) 316 return; 317 #endif 318 319 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 320 "bus-master DMA support present"); 321 pciide_mapreg_dma(sc, pa); 322 aprint_verbose("\n"); 323 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 324 if (sc->sc_dma_ok) { 325 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 326 switch (sc->sc_pp->ide_product) { 327 case PCI_PRODUCT_CMDTECH_649: 328 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 329 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 330 sc->sc_wdcdev.irqack = cmd646_9_irqack; 331 break; 332 case PCI_PRODUCT_CMDTECH_648: 333 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 334 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 335 sc->sc_wdcdev.irqack = cmd646_9_irqack; 336 break; 337 case PCI_PRODUCT_CMDTECH_646: 338 if (rev >= CMD0646U2_REV) { 339 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 340 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 341 } else if (rev >= CMD0646U_REV) { 342 /* 343 * Linux's driver claims that the 646U is broken 344 * with UDMA. Only enable it if we know what we're 345 * doing 346 */ 347 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 348 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 349 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 350 #endif 351 /* explicitly disable UDMA */ 352 pciide_pci_write(sc->sc_pc, sc->sc_tag, 353 CMD_UDMATIM(0), 0); 354 pciide_pci_write(sc->sc_pc, sc->sc_tag, 355 CMD_UDMATIM(1), 0); 356 } 357 sc->sc_wdcdev.irqack = cmd646_9_irqack; 358 break; 359 default: 360 sc->sc_wdcdev.irqack = pciide_irqack; 361 } 362 } 363 364 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 365 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 366 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 367 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 368 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel; 369 sc->sc_wdcdev.wdc_maxdrives = 2; 370 371 ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 372 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 373 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 374 DEBUG_PROBE); 375 376 wdc_allocate_regs(&sc->sc_wdcdev); 377 378 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 379 channel++) 380 cmd_channel_map(pa, sc, channel); 381 382 /* 383 * note - this also makes sure we clear the irq disable and reset 384 * bits 385 */ 386 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 387 ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 388 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 389 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 390 DEBUG_PROBE); 391 } 392 393 static void 394 cmd0643_9_setup_channel(struct ata_channel *chp) 395 { 396 struct ata_drive_datas *drvp; 397 u_int8_t tim; 398 u_int32_t idedma_ctl, udma_reg; 399 int drive, s; 400 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 401 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 402 403 idedma_ctl = 0; 404 /* setup DMA if needed */ 405 pciide_channel_dma_setup(cp); 406 407 for (drive = 0; drive < 2; drive++) { 408 drvp = &chp->ch_drive[drive]; 409 /* If no drive, skip */ 410 if (drvp->drive_type == ATA_DRIVET_NONE) 411 continue; 412 /* add timing values, setup DMA if needed */ 413 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 414 if (drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) { 415 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 416 /* UltraDMA on a 646U2, 0648 or 0649 */ 417 s = splbio(); 418 drvp->drive_flags &= ~ATA_DRIVE_DMA; 419 splx(s); 420 udma_reg = pciide_pci_read(sc->sc_pc, 421 sc->sc_tag, CMD_UDMATIM(chp->ch_channel)); 422 if (drvp->UDMA_mode > 2 && 423 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 424 CMD_BICSR) & 425 CMD_BICSR_80(chp->ch_channel)) == 0) 426 drvp->UDMA_mode = 2; 427 if (drvp->UDMA_mode > 2) 428 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 429 else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2) 430 udma_reg |= CMD_UDMATIM_UDMA33(drive); 431 udma_reg |= CMD_UDMATIM_UDMA(drive); 432 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 433 CMD_UDMATIM_TIM_OFF(drive)); 434 udma_reg |= 435 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 436 CMD_UDMATIM_TIM_OFF(drive)); 437 pciide_pci_write(sc->sc_pc, sc->sc_tag, 438 CMD_UDMATIM(chp->ch_channel), udma_reg); 439 } else { 440 /* 441 * use Multiword DMA. 442 * Timings will be used for both PIO and DMA, 443 * so adjust DMA mode if needed 444 * if we have a 0646U2/8/9, turn off UDMA 445 */ 446 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 447 udma_reg = pciide_pci_read(sc->sc_pc, 448 sc->sc_tag, 449 CMD_UDMATIM(chp->ch_channel)); 450 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 451 pciide_pci_write(sc->sc_pc, sc->sc_tag, 452 CMD_UDMATIM(chp->ch_channel), 453 udma_reg); 454 } 455 if (drvp->PIO_mode >= 3 && 456 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 457 drvp->DMA_mode = drvp->PIO_mode - 2; 458 } 459 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 460 } 461 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 462 } 463 pciide_pci_write(sc->sc_pc, sc->sc_tag, 464 CMD_DATA_TIM(chp->ch_channel, drive), tim); 465 } 466 if (idedma_ctl != 0) { 467 /* Add software bits in status register */ 468 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 469 idedma_ctl); 470 } 471 } 472 473 static void 474 cmd646_9_irqack(struct ata_channel *chp) 475 { 476 u_int32_t priirq, secirq; 477 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 478 479 if (chp->ch_channel == 0) { 480 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 481 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 482 } else { 483 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 484 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 485 } 486 pciide_irqack(chp); 487 } 488 489 static void 490 cmd680_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 491 { 492 int channel; 493 494 if (pciide_chipen(sc, pa) == 0) 495 return; 496 497 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 498 "bus-master DMA support present"); 499 pciide_mapreg_dma(sc, pa); 500 aprint_verbose("\n"); 501 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 502 if (sc->sc_dma_ok) { 503 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 504 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 505 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 506 sc->sc_wdcdev.irqack = pciide_irqack; 507 } 508 509 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 510 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 511 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 512 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 513 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel; 514 sc->sc_wdcdev.wdc_maxdrives = 2; 515 516 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 517 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 518 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 519 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 520 521 wdc_allocate_regs(&sc->sc_wdcdev); 522 523 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 524 channel++) 525 cmd680_channel_map(pa, sc, channel); 526 } 527 528 static void 529 cmd680_channel_map(const struct pci_attach_args *pa, struct pciide_softc *sc, 530 int channel) 531 { 532 struct pciide_channel *cp = &sc->pciide_channels[channel]; 533 int interface, i, reg; 534 static const u_int8_t init_val[] = 535 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 536 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 537 538 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 539 interface = PCIIDE_INTERFACE_SETTABLE(0) | 540 PCIIDE_INTERFACE_SETTABLE(1); 541 interface |= PCIIDE_INTERFACE_PCI(0) | 542 PCIIDE_INTERFACE_PCI(1); 543 } else { 544 interface = PCI_INTERFACE(pa->pa_class); 545 } 546 547 sc->wdc_chanarray[channel] = &cp->ata_channel; 548 cp->name = PCIIDE_CHANNEL_NAME(channel); 549 cp->ata_channel.ch_channel = channel; 550 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 551 552 /* XXX */ 553 reg = 0xa2 + channel * 16; 554 for (i = 0; i < sizeof(init_val); i++) 555 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 556 557 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 558 "%s channel %s to %s mode\n", cp->name, 559 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 560 "configured" : "wired", 561 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 562 "native-PCI" : "compatibility"); 563 564 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 565 } 566 567 static void 568 cmd680_setup_channel(struct ata_channel *chp) 569 { 570 struct ata_drive_datas *drvp; 571 u_int8_t mode, off, scsc; 572 u_int16_t val; 573 u_int32_t idedma_ctl; 574 int drive, s; 575 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 576 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 577 pci_chipset_tag_t pc = sc->sc_pc; 578 pcitag_t pa = sc->sc_tag; 579 static const u_int8_t udma2_tbl[] = 580 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 581 static const u_int8_t udma_tbl[] = 582 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 583 static const u_int16_t dma_tbl[] = 584 { 0x2208, 0x10c2, 0x10c1 }; 585 static const u_int16_t pio_tbl[] = 586 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 587 588 idedma_ctl = 0; 589 pciide_channel_dma_setup(cp); 590 mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4); 591 592 for (drive = 0; drive < 2; drive++) { 593 drvp = &chp->ch_drive[drive]; 594 /* If no drive, skip */ 595 if (drvp->drive_type == ATA_DRIVET_NONE) 596 continue; 597 mode &= ~(0x03 << (drive * 4)); 598 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 599 s = splbio(); 600 drvp->drive_flags &= ~ATA_DRIVE_DMA; 601 splx(s); 602 off = 0xa0 + chp->ch_channel * 16; 603 if (drvp->UDMA_mode > 2 && 604 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 605 drvp->UDMA_mode = 2; 606 scsc = pciide_pci_read(pc, pa, 0x8a); 607 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 608 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 609 scsc = pciide_pci_read(pc, pa, 0x8a); 610 if ((scsc & 0x30) == 0) 611 drvp->UDMA_mode = 5; 612 } 613 mode |= 0x03 << (drive * 4); 614 off = 0xac + chp->ch_channel * 16 + drive * 2; 615 val = pciide_pci_read(pc, pa, off) & ~0x3f; 616 if (scsc & 0x30) 617 val |= udma2_tbl[drvp->UDMA_mode]; 618 else 619 val |= udma_tbl[drvp->UDMA_mode]; 620 pciide_pci_write(pc, pa, off, val); 621 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 622 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 623 mode |= 0x02 << (drive * 4); 624 off = 0xa8 + chp->ch_channel * 16 + drive * 2; 625 val = dma_tbl[drvp->DMA_mode]; 626 pciide_pci_write(pc, pa, off, val & 0xff); 627 pciide_pci_write(pc, pa, off+1, val >> 8); 628 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 629 } else { 630 mode |= 0x01 << (drive * 4); 631 off = 0xa4 + chp->ch_channel * 16 + drive * 2; 632 val = pio_tbl[drvp->PIO_mode]; 633 pciide_pci_write(pc, pa, off, val & 0xff); 634 pciide_pci_write(pc, pa, off+1, val >> 8); 635 } 636 } 637 638 pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode); 639 if (idedma_ctl != 0) { 640 /* Add software bits in status register */ 641 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 642 idedma_ctl); 643 } 644 } 645
Indexes created Wed Oct 01 19:09:53 GMT 2025