cmdide.c revision 1.39
1 /* $NetBSD: cmdide.c,v 1.39 2017/10/07 16:05:33 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: cmdide.c,v 1.39 2017/10/07 16:05:33 jdolecek Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_cmd_reg.h> 38 39 40 static int cmdide_match(device_t, cfdata_t, void *); 41 static void cmdide_attach(device_t, device_t, void *); 42 43 CFATTACH_DECL_NEW(cmdide, sizeof(struct pciide_softc), 44 cmdide_match, cmdide_attach, pciide_detach, NULL); 45 46 static void cmd_chip_map(struct pciide_softc*, const struct pci_attach_args*); 47 static void cmd0643_9_chip_map(struct pciide_softc*, 48 const struct pci_attach_args*); 49 static void cmd0643_9_setup_channel(struct ata_channel*); 50 static void cmd_channel_map(const struct pci_attach_args *, 51 struct pciide_softc *, int); 52 static int cmd_pci_intr(void *); 53 static void cmd646_9_irqack(struct ata_channel *); 54 static void cmd680_chip_map(struct pciide_softc*, 55 const struct pci_attach_args*); 56 static void cmd680_setup_channel(struct ata_channel*); 57 static void cmd680_channel_map(const struct pci_attach_args *, 58 struct pciide_softc *, int); 59 60 static const struct pciide_product_desc pciide_cmd_products[] = { 61 { PCI_PRODUCT_CMDTECH_640, 62 0, 63 "CMD Technology PCI0640", 64 cmd_chip_map 65 }, 66 { PCI_PRODUCT_CMDTECH_643, 67 0, 68 "CMD Technology PCI0643", 69 cmd0643_9_chip_map, 70 }, 71 { PCI_PRODUCT_CMDTECH_646, 72 0, 73 "CMD Technology PCI0646", 74 cmd0643_9_chip_map, 75 }, 76 { PCI_PRODUCT_CMDTECH_648, 77 0, 78 "CMD Technology PCI0648", 79 cmd0643_9_chip_map, 80 }, 81 { PCI_PRODUCT_CMDTECH_649, 82 0, 83 "CMD Technology PCI0649", 84 cmd0643_9_chip_map, 85 }, 86 { PCI_PRODUCT_CMDTECH_680, 87 0, 88 "Silicon Image 0680", 89 cmd680_chip_map, 90 }, 91 { 0, 92 0, 93 NULL, 94 NULL 95 } 96 }; 97 98 static int 99 cmdide_match(device_t parent, cfdata_t match, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 103 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 104 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 105 return (2); 106 } 107 return (0); 108 } 109 110 static void 111 cmdide_attach(device_t parent, device_t self, void *aux) 112 { 113 struct pci_attach_args *pa = aux; 114 struct pciide_softc *sc = device_private(self); 115 116 sc->sc_wdcdev.sc_atac.atac_dev = self; 117 118 pciide_common_attach(sc, pa, 119 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 120 121 } 122 123 static void 124 cmd_channel_map(const struct pci_attach_args *pa, struct pciide_softc *sc, 125 int channel) 126 { 127 struct pciide_channel *cp = &sc->pciide_channels[channel]; 128 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 129 int interface, one_channel; 130 131 /* 132 * The 0648/0649 can be told to identify as a RAID controller. 133 * In this case, we have to fake interface 134 */ 135 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 136 interface = PCIIDE_INTERFACE_SETTABLE(0) | 137 PCIIDE_INTERFACE_SETTABLE(1); 138 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 139 CMD_CONF_DSA1) 140 interface |= PCIIDE_INTERFACE_PCI(0) | 141 PCIIDE_INTERFACE_PCI(1); 142 } else { 143 interface = PCI_INTERFACE(pa->pa_class); 144 } 145 146 sc->wdc_chanarray[channel] = &cp->ata_channel; 147 cp->name = PCIIDE_CHANNEL_NAME(channel); 148 cp->ata_channel.ch_channel = channel; 149 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 150 151 /* 152 * Older CMD64X doesn't have independent channels 153 */ 154 switch (sc->sc_pp->ide_product) { 155 case PCI_PRODUCT_CMDTECH_649: 156 one_channel = 0; 157 break; 158 default: 159 one_channel = 1; 160 break; 161 } 162 163 if (channel > 0 && one_channel) { 164 cp->ata_channel.ch_queue = 165 sc->pciide_channels[0].ata_channel.ch_queue; 166 } else { 167 cp->ata_channel.ch_queue = ata_queue_alloc(1); 168 } 169 if (cp->ata_channel.ch_queue == NULL) { 170 aprint_error("%s %s channel: " 171 "can't allocate memory for command queue", 172 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 173 return; 174 } 175 176 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 177 "%s channel %s to %s mode\n", cp->name, 178 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 179 "configured" : "wired", 180 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 181 "native-PCI" : "compatibility"); 182 183 /* 184 * with a CMD PCI64x, if we get here, the first channel is enabled: 185 * there's no way to disable the first channel without disabling 186 * the whole device 187 */ 188 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 189 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 190 "%s channel ignored (disabled)\n", cp->name); 191 cp->ata_channel.ch_flags |= ATACH_DISABLED; 192 return; 193 } 194 195 pciide_mapchan(pa, cp, interface, cmd_pci_intr); 196 } 197 198 static int 199 cmd_pci_intr(void *arg) 200 { 201 struct pciide_softc *sc = arg; 202 struct pciide_channel *cp; 203 struct ata_channel *wdc_cp; 204 int i, rv, crv; 205 u_int32_t priirq, secirq; 206 207 rv = 0; 208 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 209 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 210 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 211 cp = &sc->pciide_channels[i]; 212 wdc_cp = &cp->ata_channel; 213 /* If a compat channel skip. */ 214 if (cp->compat) 215 continue; 216 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 217 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 218 crv = wdcintr(wdc_cp); 219 if (crv == 0) { 220 aprint_error("%s:%d: bogus intr\n", 221 device_xname( 222 sc->sc_wdcdev.sc_atac.atac_dev), i); 223 sc->sc_wdcdev.irqack(wdc_cp); 224 } else 225 rv = 1; 226 } 227 } 228 return rv; 229 } 230 231 static void 232 cmd_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 233 { 234 int channel; 235 236 /* 237 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 238 * and base addresses registers can be disabled at 239 * hardware level. In this case, the device is wired 240 * in compat mode and its first channel is always enabled, 241 * but we can't rely on PCI_COMMAND_IO_ENABLE. 242 * In fact, it seems that the first channel of the CMD PCI0640 243 * can't be disabled. 244 */ 245 246 #ifdef PCIIDE_CMD064x_DISABLE 247 if (pciide_chipen(sc, pa) == 0) 248 return; 249 #endif 250 251 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 252 "hardware does not support DMA\n"); 253 sc->sc_dma_ok = 0; 254 255 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 256 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 257 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 258 sc->sc_wdcdev.wdc_maxdrives = 2; 259 260 wdc_allocate_regs(&sc->sc_wdcdev); 261 262 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 263 channel++) { 264 cmd_channel_map(pa, sc, channel); 265 } 266 } 267 268 static void 269 cmd0643_9_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 270 { 271 int channel; 272 pcireg_t rev = PCI_REVISION(pa->pa_class); 273 274 /* 275 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 276 * and base addresses registers can be disabled at 277 * hardware level. In this case, the device is wired 278 * in compat mode and its first channel is always enabled, 279 * but we can't rely on PCI_COMMAND_IO_ENABLE. 280 * In fact, it seems that the first channel of the CMD PCI0640 281 * can't be disabled. 282 */ 283 284 #ifdef PCIIDE_CMD064x_DISABLE 285 if (pciide_chipen(sc, pa) == 0) 286 return; 287 #endif 288 289 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 290 "bus-master DMA support present"); 291 pciide_mapreg_dma(sc, pa); 292 aprint_verbose("\n"); 293 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 294 if (sc->sc_dma_ok) { 295 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 296 switch (sc->sc_pp->ide_product) { 297 case PCI_PRODUCT_CMDTECH_649: 298 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 299 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 300 sc->sc_wdcdev.irqack = cmd646_9_irqack; 301 break; 302 case PCI_PRODUCT_CMDTECH_648: 303 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 304 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 305 sc->sc_wdcdev.irqack = cmd646_9_irqack; 306 break; 307 case PCI_PRODUCT_CMDTECH_646: 308 if (rev >= CMD0646U2_REV) { 309 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 310 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 311 } else if (rev >= CMD0646U_REV) { 312 /* 313 * Linux's driver claims that the 646U is broken 314 * with UDMA. Only enable it if we know what we're 315 * doing 316 */ 317 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 318 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 319 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 320 #endif 321 /* explicitly disable UDMA */ 322 pciide_pci_write(sc->sc_pc, sc->sc_tag, 323 CMD_UDMATIM(0), 0); 324 pciide_pci_write(sc->sc_pc, sc->sc_tag, 325 CMD_UDMATIM(1), 0); 326 } 327 sc->sc_wdcdev.irqack = cmd646_9_irqack; 328 break; 329 default: 330 sc->sc_wdcdev.irqack = pciide_irqack; 331 } 332 } 333 334 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 335 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 336 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 337 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 338 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel; 339 sc->sc_wdcdev.wdc_maxdrives = 2; 340 341 ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 342 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 343 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 344 DEBUG_PROBE); 345 346 wdc_allocate_regs(&sc->sc_wdcdev); 347 348 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 349 channel++) 350 cmd_channel_map(pa, sc, channel); 351 352 /* 353 * note - this also makes sure we clear the irq disable and reset 354 * bits 355 */ 356 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 357 ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 358 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 359 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 360 DEBUG_PROBE); 361 } 362 363 static void 364 cmd0643_9_setup_channel(struct ata_channel *chp) 365 { 366 struct ata_drive_datas *drvp; 367 u_int8_t tim; 368 u_int32_t idedma_ctl, udma_reg; 369 int drive, s; 370 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 371 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 372 373 idedma_ctl = 0; 374 /* setup DMA if needed */ 375 pciide_channel_dma_setup(cp); 376 377 for (drive = 0; drive < 2; drive++) { 378 drvp = &chp->ch_drive[drive]; 379 /* If no drive, skip */ 380 if (drvp->drive_type == ATA_DRIVET_NONE) 381 continue; 382 /* add timing values, setup DMA if needed */ 383 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 384 if (drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) { 385 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 386 /* UltraDMA on a 646U2, 0648 or 0649 */ 387 s = splbio(); 388 drvp->drive_flags &= ~ATA_DRIVE_DMA; 389 splx(s); 390 udma_reg = pciide_pci_read(sc->sc_pc, 391 sc->sc_tag, CMD_UDMATIM(chp->ch_channel)); 392 if (drvp->UDMA_mode > 2 && 393 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 394 CMD_BICSR) & 395 CMD_BICSR_80(chp->ch_channel)) == 0) 396 drvp->UDMA_mode = 2; 397 if (drvp->UDMA_mode > 2) 398 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 399 else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2) 400 udma_reg |= CMD_UDMATIM_UDMA33(drive); 401 udma_reg |= CMD_UDMATIM_UDMA(drive); 402 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 403 CMD_UDMATIM_TIM_OFF(drive)); 404 udma_reg |= 405 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 406 CMD_UDMATIM_TIM_OFF(drive)); 407 pciide_pci_write(sc->sc_pc, sc->sc_tag, 408 CMD_UDMATIM(chp->ch_channel), udma_reg); 409 } else { 410 /* 411 * use Multiword DMA. 412 * Timings will be used for both PIO and DMA, 413 * so adjust DMA mode if needed 414 * if we have a 0646U2/8/9, turn off UDMA 415 */ 416 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 417 udma_reg = pciide_pci_read(sc->sc_pc, 418 sc->sc_tag, 419 CMD_UDMATIM(chp->ch_channel)); 420 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 421 pciide_pci_write(sc->sc_pc, sc->sc_tag, 422 CMD_UDMATIM(chp->ch_channel), 423 udma_reg); 424 } 425 if (drvp->PIO_mode >= 3 && 426 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 427 drvp->DMA_mode = drvp->PIO_mode - 2; 428 } 429 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 430 } 431 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 432 } 433 pciide_pci_write(sc->sc_pc, sc->sc_tag, 434 CMD_DATA_TIM(chp->ch_channel, drive), tim); 435 } 436 if (idedma_ctl != 0) { 437 /* Add software bits in status register */ 438 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 439 idedma_ctl); 440 } 441 } 442 443 static void 444 cmd646_9_irqack(struct ata_channel *chp) 445 { 446 u_int32_t priirq, secirq; 447 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 448 449 if (chp->ch_channel == 0) { 450 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 451 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 452 } else { 453 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 454 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 455 } 456 pciide_irqack(chp); 457 } 458 459 static void 460 cmd680_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 461 { 462 int channel; 463 464 if (pciide_chipen(sc, pa) == 0) 465 return; 466 467 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 468 "bus-master DMA support present"); 469 pciide_mapreg_dma(sc, pa); 470 aprint_verbose("\n"); 471 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 472 if (sc->sc_dma_ok) { 473 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 474 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 475 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 476 sc->sc_wdcdev.irqack = pciide_irqack; 477 } 478 479 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 480 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 481 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 482 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 483 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel; 484 sc->sc_wdcdev.wdc_maxdrives = 2; 485 486 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 487 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 488 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 489 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 490 491 wdc_allocate_regs(&sc->sc_wdcdev); 492 493 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 494 channel++) 495 cmd680_channel_map(pa, sc, channel); 496 } 497 498 static void 499 cmd680_channel_map(const struct pci_attach_args *pa, struct pciide_softc *sc, 500 int channel) 501 { 502 struct pciide_channel *cp = &sc->pciide_channels[channel]; 503 int interface, i, reg; 504 static const u_int8_t init_val[] = 505 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 506 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 507 508 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 509 interface = PCIIDE_INTERFACE_SETTABLE(0) | 510 PCIIDE_INTERFACE_SETTABLE(1); 511 interface |= PCIIDE_INTERFACE_PCI(0) | 512 PCIIDE_INTERFACE_PCI(1); 513 } else { 514 interface = PCI_INTERFACE(pa->pa_class); 515 } 516 517 sc->wdc_chanarray[channel] = &cp->ata_channel; 518 cp->name = PCIIDE_CHANNEL_NAME(channel); 519 cp->ata_channel.ch_channel = channel; 520 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 521 522 cp->ata_channel.ch_queue = ata_queue_alloc(1); 523 if (cp->ata_channel.ch_queue == NULL) { 524 aprint_error("%s %s channel: " 525 "can't allocate memory for command queue", 526 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 527 return; 528 } 529 530 /* XXX */ 531 reg = 0xa2 + channel * 16; 532 for (i = 0; i < sizeof(init_val); i++) 533 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 534 535 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 536 "%s channel %s to %s mode\n", cp->name, 537 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 538 "configured" : "wired", 539 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 540 "native-PCI" : "compatibility"); 541 542 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 543 } 544 545 static void 546 cmd680_setup_channel(struct ata_channel *chp) 547 { 548 struct ata_drive_datas *drvp; 549 u_int8_t mode, off, scsc; 550 u_int16_t val; 551 u_int32_t idedma_ctl; 552 int drive, s; 553 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 554 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 555 pci_chipset_tag_t pc = sc->sc_pc; 556 pcitag_t pa = sc->sc_tag; 557 static const u_int8_t udma2_tbl[] = 558 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 559 static const u_int8_t udma_tbl[] = 560 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 561 static const u_int16_t dma_tbl[] = 562 { 0x2208, 0x10c2, 0x10c1 }; 563 static const u_int16_t pio_tbl[] = 564 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 565 566 idedma_ctl = 0; 567 pciide_channel_dma_setup(cp); 568 mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4); 569 570 for (drive = 0; drive < 2; drive++) { 571 drvp = &chp->ch_drive[drive]; 572 /* If no drive, skip */ 573 if (drvp->drive_type == ATA_DRIVET_NONE) 574 continue; 575 mode &= ~(0x03 << (drive * 4)); 576 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 577 s = splbio(); 578 drvp->drive_flags &= ~ATA_DRIVE_DMA; 579 splx(s); 580 off = 0xa0 + chp->ch_channel * 16; 581 if (drvp->UDMA_mode > 2 && 582 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 583 drvp->UDMA_mode = 2; 584 scsc = pciide_pci_read(pc, pa, 0x8a); 585 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 586 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 587 scsc = pciide_pci_read(pc, pa, 0x8a); 588 if ((scsc & 0x30) == 0) 589 drvp->UDMA_mode = 5; 590 } 591 mode |= 0x03 << (drive * 4); 592 off = 0xac + chp->ch_channel * 16 + drive * 2; 593 val = pciide_pci_read(pc, pa, off) & ~0x3f; 594 if (scsc & 0x30) 595 val |= udma2_tbl[drvp->UDMA_mode]; 596 else 597 val |= udma_tbl[drvp->UDMA_mode]; 598 pciide_pci_write(pc, pa, off, val); 599 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 600 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 601 mode |= 0x02 << (drive * 4); 602 off = 0xa8 + chp->ch_channel * 16 + drive * 2; 603 val = dma_tbl[drvp->DMA_mode]; 604 pciide_pci_write(pc, pa, off, val & 0xff); 605 pciide_pci_write(pc, pa, off+1, val >> 8); 606 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 607 } else { 608 mode |= 0x01 << (drive * 4); 609 off = 0xa4 + chp->ch_channel * 16 + drive * 2; 610 val = pio_tbl[drvp->PIO_mode]; 611 pciide_pci_write(pc, pa, off, val & 0xff); 612 pciide_pci_write(pc, pa, off+1, val >> 8); 613 } 614 } 615 616 pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode); 617 if (idedma_ctl != 0) { 618 /* Add software bits in status register */ 619 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 620 idedma_ctl); 621 } 622 } 623
Indexes created Wed Oct 01 19:09:53 GMT 2025