cmdide.c revision 1.4
1 /* $NetBSD: cmdide.c,v 1.4 2003/10/30 01:58:17 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pciidereg.h> 39 #include <dev/pci/pciidevar.h> 40 #include <dev/pci/pciide_cmd_reg.h> 41 #include <dev/pci/pciide_sii3112_reg.h> 42 43 44 static int cmdide_match(struct device *, struct cfdata *, void *); 45 static void cmdide_attach(struct device *, struct device *, void *); 46 47 CFATTACH_DECL(cmdide, sizeof(struct pciide_softc), 48 cmdide_match, cmdide_attach, NULL, NULL); 49 50 static void cmd_chip_map(struct pciide_softc*, struct pci_attach_args*); 51 static void cmd0643_9_chip_map(struct pciide_softc*, struct pci_attach_args*); 52 static void cmd0643_9_setup_channel(struct channel_softc*); 53 static void cmd_channel_map(struct pci_attach_args *, struct pciide_softc *, 54 int); 55 static int cmd_pci_intr(void *); 56 static void cmd646_9_irqack(struct channel_softc *); 57 static void cmd680_chip_map(struct pciide_softc*, struct pci_attach_args*); 58 static void cmd680_setup_channel(struct channel_softc*); 59 static void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *, 60 int); 61 62 static void cmd3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 63 static void cmd3112_setup_channel(struct channel_softc*); 64 65 static const struct pciide_product_desc pciide_cmd_products[] = { 66 { PCI_PRODUCT_CMDTECH_640, 67 0, 68 "CMD Technology PCI0640", 69 cmd_chip_map 70 }, 71 { PCI_PRODUCT_CMDTECH_643, 72 0, 73 "CMD Technology PCI0643", 74 cmd0643_9_chip_map, 75 }, 76 { PCI_PRODUCT_CMDTECH_646, 77 0, 78 "CMD Technology PCI0646", 79 cmd0643_9_chip_map, 80 }, 81 { PCI_PRODUCT_CMDTECH_648, 82 0, 83 "CMD Technology PCI0648", 84 cmd0643_9_chip_map, 85 }, 86 { PCI_PRODUCT_CMDTECH_649, 87 0, 88 "CMD Technology PCI0649", 89 cmd0643_9_chip_map, 90 }, 91 { PCI_PRODUCT_CMDTECH_680, 92 0, 93 "Silicon Image 0680", 94 cmd680_chip_map, 95 }, 96 { PCI_PRODUCT_CMDTECH_3112, 97 0, 98 "Silicon Image SATALink 3112", 99 cmd3112_chip_map, 100 }, 101 { 0, 102 0, 103 NULL, 104 NULL 105 } 106 }; 107 108 static int 109 cmdide_match(struct device *parent, struct cfdata *match, void *aux) 110 { 111 struct pci_attach_args *pa = aux; 112 113 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 114 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 115 return (2); 116 } 117 return (0); 118 } 119 120 static void 121 cmdide_attach(struct device *parent, struct device *self, void *aux) 122 { 123 struct pci_attach_args *pa = aux; 124 struct pciide_softc *sc = (struct pciide_softc *)self; 125 126 pciide_common_attach(sc, pa, 127 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 128 129 } 130 131 static void 132 cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 133 int channel) 134 { 135 struct pciide_channel *cp = &sc->pciide_channels[channel]; 136 bus_size_t cmdsize, ctlsize; 137 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 138 int interface, one_channel; 139 140 /* 141 * The 0648/0649 can be told to identify as a RAID controller. 142 * In this case, we have to fake interface 143 */ 144 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 145 interface = PCIIDE_INTERFACE_SETTABLE(0) | 146 PCIIDE_INTERFACE_SETTABLE(1); 147 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 148 CMD_CONF_DSA1) 149 interface |= PCIIDE_INTERFACE_PCI(0) | 150 PCIIDE_INTERFACE_PCI(1); 151 } else { 152 interface = PCI_INTERFACE(pa->pa_class); 153 } 154 155 sc->wdc_chanarray[channel] = &cp->wdc_channel; 156 cp->name = PCIIDE_CHANNEL_NAME(channel); 157 cp->wdc_channel.channel = channel; 158 cp->wdc_channel.wdc = &sc->sc_wdcdev; 159 160 /* 161 * Older CMD64X doesn't have independant channels 162 */ 163 switch (sc->sc_pp->ide_product) { 164 case PCI_PRODUCT_CMDTECH_649: 165 one_channel = 0; 166 break; 167 default: 168 one_channel = 1; 169 break; 170 } 171 172 if (channel > 0 && one_channel) { 173 cp->wdc_channel.ch_queue = 174 sc->pciide_channels[0].wdc_channel.ch_queue; 175 } else { 176 cp->wdc_channel.ch_queue = 177 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 178 } 179 if (cp->wdc_channel.ch_queue == NULL) { 180 aprint_error("%s %s channel: " 181 "can't allocate memory for command queue", 182 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 183 return; 184 } 185 186 aprint_normal("%s: %s channel %s to %s mode\n", 187 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 188 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 189 "configured" : "wired", 190 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 191 "native-PCI" : "compatibility"); 192 193 /* 194 * with a CMD PCI64x, if we get here, the first channel is enabled: 195 * there's no way to disable the first channel without disabling 196 * the whole device 197 */ 198 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 199 aprint_normal("%s: %s channel ignored (disabled)\n", 200 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 201 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 202 return; 203 } 204 205 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 206 } 207 208 static int 209 cmd_pci_intr(void *arg) 210 { 211 struct pciide_softc *sc = arg; 212 struct pciide_channel *cp; 213 struct channel_softc *wdc_cp; 214 int i, rv, crv; 215 u_int32_t priirq, secirq; 216 217 rv = 0; 218 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 219 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 220 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 221 cp = &sc->pciide_channels[i]; 222 wdc_cp = &cp->wdc_channel; 223 /* If a compat channel skip. */ 224 if (cp->compat) 225 continue; 226 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 227 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 228 crv = wdcintr(wdc_cp); 229 if (crv == 0) 230 printf("%s:%d: bogus intr\n", 231 sc->sc_wdcdev.sc_dev.dv_xname, i); 232 else 233 rv = 1; 234 } 235 } 236 return rv; 237 } 238 239 static void 240 cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 241 { 242 int channel; 243 244 /* 245 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 246 * and base adresses registers can be disabled at 247 * hardware level. In this case, the device is wired 248 * in compat mode and its first channel is always enabled, 249 * but we can't rely on PCI_COMMAND_IO_ENABLE. 250 * In fact, it seems that the first channel of the CMD PCI0640 251 * can't be disabled. 252 */ 253 254 #ifdef PCIIDE_CMD064x_DISABLE 255 if (pciide_chipen(sc, pa) == 0) 256 return; 257 #endif 258 259 aprint_normal("%s: hardware does not support DMA\n", 260 sc->sc_wdcdev.sc_dev.dv_xname); 261 sc->sc_dma_ok = 0; 262 263 sc->sc_wdcdev.channels = sc->wdc_chanarray; 264 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 265 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 266 267 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 268 cmd_channel_map(pa, sc, channel); 269 } 270 } 271 272 static void 273 cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 274 { 275 int channel; 276 pcireg_t rev = PCI_REVISION(pa->pa_class); 277 278 /* 279 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 280 * and base adresses registers can be disabled at 281 * hardware level. In this case, the device is wired 282 * in compat mode and its first channel is always enabled, 283 * but we can't rely on PCI_COMMAND_IO_ENABLE. 284 * In fact, it seems that the first channel of the CMD PCI0640 285 * can't be disabled. 286 */ 287 288 #ifdef PCIIDE_CMD064x_DISABLE 289 if (pciide_chipen(sc, pa) == 0) 290 return; 291 #endif 292 293 aprint_normal("%s: bus-master DMA support present", 294 sc->sc_wdcdev.sc_dev.dv_xname); 295 pciide_mapreg_dma(sc, pa); 296 aprint_normal("\n"); 297 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 298 WDC_CAPABILITY_MODE; 299 if (sc->sc_dma_ok) { 300 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 301 switch (sc->sc_pp->ide_product) { 302 case PCI_PRODUCT_CMDTECH_649: 303 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 304 sc->sc_wdcdev.UDMA_cap = 5; 305 sc->sc_wdcdev.irqack = cmd646_9_irqack; 306 break; 307 case PCI_PRODUCT_CMDTECH_648: 308 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 309 sc->sc_wdcdev.UDMA_cap = 4; 310 sc->sc_wdcdev.irqack = cmd646_9_irqack; 311 break; 312 case PCI_PRODUCT_CMDTECH_646: 313 if (rev >= CMD0646U2_REV) { 314 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 315 sc->sc_wdcdev.UDMA_cap = 2; 316 } else if (rev >= CMD0646U_REV) { 317 /* 318 * Linux's driver claims that the 646U is broken 319 * with UDMA. Only enable it if we know what we're 320 * doing 321 */ 322 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 323 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 324 sc->sc_wdcdev.UDMA_cap = 2; 325 #endif 326 /* explicitly disable UDMA */ 327 pciide_pci_write(sc->sc_pc, sc->sc_tag, 328 CMD_UDMATIM(0), 0); 329 pciide_pci_write(sc->sc_pc, sc->sc_tag, 330 CMD_UDMATIM(1), 0); 331 } 332 sc->sc_wdcdev.irqack = cmd646_9_irqack; 333 break; 334 default: 335 sc->sc_wdcdev.irqack = pciide_irqack; 336 } 337 } 338 339 sc->sc_wdcdev.channels = sc->wdc_chanarray; 340 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 341 sc->sc_wdcdev.PIO_cap = 4; 342 sc->sc_wdcdev.DMA_cap = 2; 343 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 344 345 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 346 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 347 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 348 DEBUG_PROBE); 349 350 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) 351 cmd_channel_map(pa, sc, channel); 352 353 /* 354 * note - this also makes sure we clear the irq disable and reset 355 * bits 356 */ 357 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 358 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 359 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 360 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 361 DEBUG_PROBE); 362 } 363 364 static void 365 cmd0643_9_setup_channel(struct channel_softc *chp) 366 { 367 struct ata_drive_datas *drvp; 368 u_int8_t tim; 369 u_int32_t idedma_ctl, udma_reg; 370 int drive; 371 struct pciide_channel *cp = (struct pciide_channel*)chp; 372 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 373 374 idedma_ctl = 0; 375 /* setup DMA if needed */ 376 pciide_channel_dma_setup(cp); 377 378 for (drive = 0; drive < 2; drive++) { 379 drvp = &chp->ch_drive[drive]; 380 /* If no drive, skip */ 381 if ((drvp->drive_flags & DRIVE) == 0) 382 continue; 383 /* add timing values, setup DMA if needed */ 384 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 385 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 386 if (drvp->drive_flags & DRIVE_UDMA) { 387 /* UltraDMA on a 646U2, 0648 or 0649 */ 388 drvp->drive_flags &= ~DRIVE_DMA; 389 udma_reg = pciide_pci_read(sc->sc_pc, 390 sc->sc_tag, CMD_UDMATIM(chp->channel)); 391 if (drvp->UDMA_mode > 2 && 392 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 393 CMD_BICSR) & 394 CMD_BICSR_80(chp->channel)) == 0) 395 drvp->UDMA_mode = 2; 396 if (drvp->UDMA_mode > 2) 397 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 398 else if (sc->sc_wdcdev.UDMA_cap > 2) 399 udma_reg |= CMD_UDMATIM_UDMA33(drive); 400 udma_reg |= CMD_UDMATIM_UDMA(drive); 401 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 402 CMD_UDMATIM_TIM_OFF(drive)); 403 udma_reg |= 404 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 405 CMD_UDMATIM_TIM_OFF(drive)); 406 pciide_pci_write(sc->sc_pc, sc->sc_tag, 407 CMD_UDMATIM(chp->channel), udma_reg); 408 } else { 409 /* 410 * use Multiword DMA. 411 * Timings will be used for both PIO and DMA, 412 * so adjust DMA mode if needed 413 * if we have a 0646U2/8/9, turn off UDMA 414 */ 415 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 416 udma_reg = pciide_pci_read(sc->sc_pc, 417 sc->sc_tag, 418 CMD_UDMATIM(chp->channel)); 419 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 420 pciide_pci_write(sc->sc_pc, sc->sc_tag, 421 CMD_UDMATIM(chp->channel), 422 udma_reg); 423 } 424 if (drvp->PIO_mode >= 3 && 425 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 426 drvp->DMA_mode = drvp->PIO_mode - 2; 427 } 428 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 429 } 430 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 431 } 432 pciide_pci_write(sc->sc_pc, sc->sc_tag, 433 CMD_DATA_TIM(chp->channel, drive), tim); 434 } 435 if (idedma_ctl != 0) { 436 /* Add software bits in status register */ 437 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 438 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 439 idedma_ctl); 440 } 441 } 442 443 static void 444 cmd646_9_irqack(struct channel_softc *chp) 445 { 446 u_int32_t priirq, secirq; 447 struct pciide_channel *cp = (struct pciide_channel*)chp; 448 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 449 450 if (chp->channel == 0) { 451 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 452 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 453 } else { 454 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 455 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 456 } 457 pciide_irqack(chp); 458 } 459 460 static void 461 cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 462 { 463 int channel; 464 465 if (pciide_chipen(sc, pa) == 0) 466 return; 467 468 aprint_normal("%s: bus-master DMA support present", 469 sc->sc_wdcdev.sc_dev.dv_xname); 470 pciide_mapreg_dma(sc, pa); 471 aprint_normal("\n"); 472 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 473 WDC_CAPABILITY_MODE; 474 if (sc->sc_dma_ok) { 475 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 476 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 477 sc->sc_wdcdev.UDMA_cap = 6; 478 sc->sc_wdcdev.irqack = pciide_irqack; 479 } 480 481 sc->sc_wdcdev.channels = sc->wdc_chanarray; 482 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 483 sc->sc_wdcdev.PIO_cap = 4; 484 sc->sc_wdcdev.DMA_cap = 2; 485 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 486 487 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 488 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 489 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 490 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 491 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) 492 cmd680_channel_map(pa, sc, channel); 493 } 494 495 static void 496 cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 497 int channel) 498 { 499 struct pciide_channel *cp = &sc->pciide_channels[channel]; 500 bus_size_t cmdsize, ctlsize; 501 int interface, i, reg; 502 static const u_int8_t init_val[] = 503 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 504 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 505 506 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 507 interface = PCIIDE_INTERFACE_SETTABLE(0) | 508 PCIIDE_INTERFACE_SETTABLE(1); 509 interface |= PCIIDE_INTERFACE_PCI(0) | 510 PCIIDE_INTERFACE_PCI(1); 511 } else { 512 interface = PCI_INTERFACE(pa->pa_class); 513 } 514 515 sc->wdc_chanarray[channel] = &cp->wdc_channel; 516 cp->name = PCIIDE_CHANNEL_NAME(channel); 517 cp->wdc_channel.channel = channel; 518 cp->wdc_channel.wdc = &sc->sc_wdcdev; 519 520 cp->wdc_channel.ch_queue = 521 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 522 if (cp->wdc_channel.ch_queue == NULL) { 523 aprint_error("%s %s channel: " 524 "can't allocate memory for command queue", 525 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 526 return; 527 } 528 529 /* XXX */ 530 reg = 0xa2 + channel * 16; 531 for (i = 0; i < sizeof(init_val); i++) 532 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 533 534 aprint_normal("%s: %s channel %s to %s mode\n", 535 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 536 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 537 "configured" : "wired", 538 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 539 "native-PCI" : "compatibility"); 540 541 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 542 } 543 544 static void 545 cmd680_setup_channel(struct channel_softc *chp) 546 { 547 struct ata_drive_datas *drvp; 548 u_int8_t mode, off, scsc; 549 u_int16_t val; 550 u_int32_t idedma_ctl; 551 int drive; 552 struct pciide_channel *cp = (struct pciide_channel*)chp; 553 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 554 pci_chipset_tag_t pc = sc->sc_pc; 555 pcitag_t pa = sc->sc_tag; 556 static const u_int8_t udma2_tbl[] = 557 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 558 static const u_int8_t udma_tbl[] = 559 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 560 static const u_int16_t dma_tbl[] = 561 { 0x2208, 0x10c2, 0x10c1 }; 562 static const u_int16_t pio_tbl[] = 563 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 564 565 idedma_ctl = 0; 566 pciide_channel_dma_setup(cp); 567 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 568 569 for (drive = 0; drive < 2; drive++) { 570 drvp = &chp->ch_drive[drive]; 571 /* If no drive, skip */ 572 if ((drvp->drive_flags & DRIVE) == 0) 573 continue; 574 mode &= ~(0x03 << (drive * 4)); 575 if (drvp->drive_flags & DRIVE_UDMA) { 576 drvp->drive_flags &= ~DRIVE_DMA; 577 off = 0xa0 + chp->channel * 16; 578 if (drvp->UDMA_mode > 2 && 579 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 580 drvp->UDMA_mode = 2; 581 scsc = pciide_pci_read(pc, pa, 0x8a); 582 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 583 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 584 scsc = pciide_pci_read(pc, pa, 0x8a); 585 if ((scsc & 0x30) == 0) 586 drvp->UDMA_mode = 5; 587 } 588 mode |= 0x03 << (drive * 4); 589 off = 0xac + chp->channel * 16 + drive * 2; 590 val = pciide_pci_read(pc, pa, off) & ~0x3f; 591 if (scsc & 0x30) 592 val |= udma2_tbl[drvp->UDMA_mode]; 593 else 594 val |= udma_tbl[drvp->UDMA_mode]; 595 pciide_pci_write(pc, pa, off, val); 596 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 597 } else if (drvp->drive_flags & DRIVE_DMA) { 598 mode |= 0x02 << (drive * 4); 599 off = 0xa8 + chp->channel * 16 + drive * 2; 600 val = dma_tbl[drvp->DMA_mode]; 601 pciide_pci_write(pc, pa, off, val & 0xff); 602 pciide_pci_write(pc, pa, off, val >> 8); 603 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 604 } else { 605 mode |= 0x01 << (drive * 4); 606 off = 0xa4 + chp->channel * 16 + drive * 2; 607 val = pio_tbl[drvp->PIO_mode]; 608 pciide_pci_write(pc, pa, off, val & 0xff); 609 pciide_pci_write(pc, pa, off, val >> 8); 610 } 611 } 612 613 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 614 if (idedma_ctl != 0) { 615 /* Add software bits in status register */ 616 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 617 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 618 idedma_ctl); 619 } 620 } 621 622 static void 623 cmd3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 624 { 625 struct pciide_channel *cp; 626 bus_size_t cmdsize, ctlsize; 627 pcireg_t interface; 628 int channel; 629 630 if (pciide_chipen(sc, pa) == 0) 631 return; 632 633 aprint_normal("%s: bus-master DMA support present", 634 sc->sc_wdcdev.sc_dev.dv_xname); 635 pciide_mapreg_dma(sc, pa); 636 aprint_normal("\n"); 637 638 /* 639 * Rev. <= 0x01 of the 3112 have a bug that can cause data 640 * corruption if DMA transfers cross an 8K boundary. This is 641 * apparently hard to tickle, but we'll go ahead and play it 642 * safe. 643 */ 644 if (PCI_REVISION(pa->pa_class) <= 0x01) { 645 sc->sc_dma_maxsegsz = 8192; 646 sc->sc_dma_boundary = 8192; 647 } 648 649 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 650 WDC_CAPABILITY_MODE; 651 sc->sc_wdcdev.PIO_cap = 4; 652 if (sc->sc_dma_ok) { 653 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 654 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 655 sc->sc_wdcdev.irqack = pciide_irqack; 656 sc->sc_wdcdev.DMA_cap = 2; 657 sc->sc_wdcdev.UDMA_cap = 6; 658 } 659 sc->sc_wdcdev.set_modes = cmd3112_setup_channel; 660 661 sc->sc_wdcdev.channels = sc->wdc_chanarray; 662 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 663 664 /* 665 * The 3112 can be told to identify as a RAID controller. 666 * In this case, we have to fake interface 667 */ 668 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 669 interface = PCI_INTERFACE(pa->pa_class); 670 } else { 671 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 672 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 673 } 674 675 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 676 cp = &sc->pciide_channels[channel]; 677 if (pciide_chansetup(sc, channel, interface) == 0) 678 continue; 679 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 680 pciide_pci_intr); 681 } 682 } 683 684 static void 685 cmd3112_setup_channel(struct channel_softc *chp) 686 { 687 struct ata_drive_datas *drvp; 688 int drive; 689 u_int32_t idedma_ctl, dtm; 690 struct pciide_channel *cp = (struct pciide_channel*)chp; 691 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 692 693 /* setup DMA if needed */ 694 pciide_channel_dma_setup(cp); 695 696 idedma_ctl = 0; 697 dtm = 0; 698 699 for (drive = 0; drive < 2; drive++) { 700 drvp = &chp->ch_drive[drive]; 701 /* If no drive, skip */ 702 if ((drvp->drive_flags & DRIVE) == 0) 703 continue; 704 if (drvp->drive_flags & DRIVE_UDMA) { 705 /* use Ultra/DMA */ 706 drvp->drive_flags &= ~DRIVE_DMA; 707 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 708 dtm |= DTM_IDEx_DMA; 709 } else if (drvp->drive_flags & DRIVE_DMA) { 710 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 711 dtm |= DTM_IDEx_DMA; 712 } else { 713 dtm |= DTM_IDEx_PIO; 714 } 715 } 716 717 /* 718 * Nothing to do to setup modes; it is meaningless in S-ATA 719 * (but many S-ATA drives still want to get the SET_FEATURE 720 * command). 721 */ 722 if (idedma_ctl != 0) { 723 /* Add software bits in status register */ 724 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 725 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 726 idedma_ctl); 727 } 728 pci_conf_write(sc->sc_pc, sc->sc_tag, 729 chp->channel == 0 ? SII3112_DTM_IDE0 : SII3112_DTM_IDE1, dtm); 730 } 731
Indexes created Tue Sep 23 14:10:03 GMT 2025