cmdide.c revision 1.42
1 /* $NetBSD: cmdide.c,v 1.42 2017/10/20 21:51:29 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: cmdide.c,v 1.42 2017/10/20 21:51:29 jdolecek Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_cmd_reg.h> 38 39 40 static int cmdide_match(device_t, cfdata_t, void *); 41 static void cmdide_attach(device_t, device_t, void *); 42 43 CFATTACH_DECL_NEW(cmdide, sizeof(struct pciide_softc), 44 cmdide_match, cmdide_attach, pciide_detach, NULL); 45 46 static void cmd_chip_map(struct pciide_softc*, const struct pci_attach_args*); 47 static void cmd0643_9_chip_map(struct pciide_softc*, 48 const struct pci_attach_args*); 49 static void cmd0643_9_setup_channel(struct ata_channel*); 50 static void cmd_channel_map(const struct pci_attach_args *, 51 struct pciide_softc *, int); 52 static int cmd_pci_intr(void *); 53 static void cmd646_9_irqack(struct ata_channel *); 54 static void cmd680_chip_map(struct pciide_softc*, 55 const struct pci_attach_args*); 56 static void cmd680_setup_channel(struct ata_channel*); 57 static void cmd680_channel_map(const struct pci_attach_args *, 58 struct pciide_softc *, int); 59 60 /* Older CMD64X doesn't have independent channels */ 61 static const struct pciide_product_desc pciide_cmd_products[] = { 62 { PCI_PRODUCT_CMDTECH_640, 63 IDE_SHARED_CHANNELS, 64 "CMD Technology PCI0640", 65 cmd_chip_map 66 }, 67 { PCI_PRODUCT_CMDTECH_643, 68 IDE_SHARED_CHANNELS, 69 "CMD Technology PCI0643", 70 cmd0643_9_chip_map, 71 }, 72 { PCI_PRODUCT_CMDTECH_646, 73 IDE_SHARED_CHANNELS, 74 "CMD Technology PCI0646", 75 cmd0643_9_chip_map, 76 }, 77 { PCI_PRODUCT_CMDTECH_648, 78 IDE_SHARED_CHANNELS, 79 "CMD Technology PCI0648", 80 cmd0643_9_chip_map, 81 }, 82 { PCI_PRODUCT_CMDTECH_649, 83 0, 84 "CMD Technology PCI0649", 85 cmd0643_9_chip_map, 86 }, 87 { PCI_PRODUCT_CMDTECH_680, 88 0, 89 "Silicon Image 0680", 90 cmd680_chip_map, 91 }, 92 { 0, 93 0, 94 NULL, 95 NULL 96 } 97 }; 98 99 static int 100 cmdide_match(device_t parent, cfdata_t match, void *aux) 101 { 102 struct pci_attach_args *pa = aux; 103 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 105 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 106 return (2); 107 } 108 return (0); 109 } 110 111 static void 112 cmdide_attach(device_t parent, device_t self, void *aux) 113 { 114 struct pci_attach_args *pa = aux; 115 struct pciide_softc *sc = device_private(self); 116 117 sc->sc_wdcdev.sc_atac.atac_dev = self; 118 119 pciide_common_attach(sc, pa, 120 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 121 122 } 123 124 static void 125 cmd_channel_map(const struct pci_attach_args *pa, struct pciide_softc *sc, 126 int channel) 127 { 128 struct pciide_channel *cp = &sc->pciide_channels[channel]; 129 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 130 int interface; 131 bool one_channel = ISSET(sc->sc_pp->ide_flags, IDE_SHARED_CHANNELS); 132 133 /* 134 * The 0648/0649 can be told to identify as a RAID controller. 135 * In this case, we have to fake interface 136 */ 137 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 138 interface = PCIIDE_INTERFACE_SETTABLE(0) | 139 PCIIDE_INTERFACE_SETTABLE(1); 140 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 141 CMD_CONF_DSA1) 142 interface |= PCIIDE_INTERFACE_PCI(0) | 143 PCIIDE_INTERFACE_PCI(1); 144 } else { 145 interface = PCI_INTERFACE(pa->pa_class); 146 } 147 148 sc->wdc_chanarray[channel] = &cp->ata_channel; 149 cp->name = PCIIDE_CHANNEL_NAME(channel); 150 cp->ata_channel.ch_channel = channel; 151 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 152 153 if (channel > 0 && one_channel) { 154 cp->ata_channel.ch_queue = 155 sc->pciide_channels[0].ata_channel.ch_queue; 156 } else { 157 /* XXX */ 158 cp->ata_channel.ch_queue = ata_queue_alloc(1); 159 } 160 161 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 162 "%s channel %s to %s mode%s\n", cp->name, 163 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 164 "configured" : "wired", 165 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 166 "native-PCI" : "compatibility", 167 one_channel ? ", channel non-independant" : ""); 168 169 /* 170 * with a CMD PCI64x, if we get here, the first channel is enabled: 171 * there's no way to disable the first channel without disabling 172 * the whole device 173 */ 174 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 175 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 176 "%s channel ignored (disabled)\n", cp->name); 177 cp->ata_channel.ch_flags |= ATACH_DISABLED; 178 return; 179 } 180 181 pciide_mapchan(pa, cp, interface, cmd_pci_intr); 182 } 183 184 static int 185 cmd_pci_intr(void *arg) 186 { 187 struct pciide_softc *sc = arg; 188 struct pciide_channel *cp; 189 struct ata_channel *wdc_cp; 190 int i, rv, crv; 191 u_int32_t priirq, secirq; 192 193 rv = 0; 194 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 195 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 196 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 197 cp = &sc->pciide_channels[i]; 198 wdc_cp = &cp->ata_channel; 199 /* If a compat channel skip. */ 200 if (cp->compat) 201 continue; 202 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 203 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 204 crv = wdcintr(wdc_cp); 205 if (crv == 0) { 206 aprint_error("%s:%d: bogus intr\n", 207 device_xname( 208 sc->sc_wdcdev.sc_atac.atac_dev), i); 209 sc->sc_wdcdev.irqack(wdc_cp); 210 } else 211 rv = 1; 212 } 213 } 214 return rv; 215 } 216 217 static void 218 cmd_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 219 { 220 int channel; 221 222 /* 223 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 224 * and base addresses registers can be disabled at 225 * hardware level. In this case, the device is wired 226 * in compat mode and its first channel is always enabled, 227 * but we can't rely on PCI_COMMAND_IO_ENABLE. 228 * In fact, it seems that the first channel of the CMD PCI0640 229 * can't be disabled. 230 */ 231 232 #ifdef PCIIDE_CMD064x_DISABLE 233 if (pciide_chipen(sc, pa) == 0) 234 return; 235 #endif 236 237 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 238 "hardware does not support DMA\n"); 239 sc->sc_dma_ok = 0; 240 241 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 242 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 243 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 244 sc->sc_wdcdev.wdc_maxdrives = 2; 245 246 wdc_allocate_regs(&sc->sc_wdcdev); 247 248 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 249 channel++) { 250 cmd_channel_map(pa, sc, channel); 251 } 252 } 253 254 static void 255 cmd0643_9_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 256 { 257 int channel; 258 pcireg_t rev = PCI_REVISION(pa->pa_class); 259 260 /* 261 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 262 * and base addresses registers can be disabled at 263 * hardware level. In this case, the device is wired 264 * in compat mode and its first channel is always enabled, 265 * but we can't rely on PCI_COMMAND_IO_ENABLE. 266 * In fact, it seems that the first channel of the CMD PCI0640 267 * can't be disabled. 268 */ 269 270 #ifdef PCIIDE_CMD064x_DISABLE 271 if (pciide_chipen(sc, pa) == 0) 272 return; 273 #endif 274 275 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 276 "bus-master DMA support present"); 277 pciide_mapreg_dma(sc, pa); 278 aprint_verbose("\n"); 279 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 280 if (sc->sc_dma_ok) { 281 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 282 switch (sc->sc_pp->ide_product) { 283 case PCI_PRODUCT_CMDTECH_649: 284 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 285 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 286 sc->sc_wdcdev.irqack = cmd646_9_irqack; 287 break; 288 case PCI_PRODUCT_CMDTECH_648: 289 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 290 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 291 sc->sc_wdcdev.irqack = cmd646_9_irqack; 292 break; 293 case PCI_PRODUCT_CMDTECH_646: 294 if (rev >= CMD0646U2_REV) { 295 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 296 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 297 } else if (rev >= CMD0646U_REV) { 298 /* 299 * Linux's driver claims that the 646U is broken 300 * with UDMA. Only enable it if we know what we're 301 * doing 302 */ 303 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 304 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 305 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 306 #endif 307 /* explicitly disable UDMA */ 308 pciide_pci_write(sc->sc_pc, sc->sc_tag, 309 CMD_UDMATIM(0), 0); 310 pciide_pci_write(sc->sc_pc, sc->sc_tag, 311 CMD_UDMATIM(1), 0); 312 } 313 sc->sc_wdcdev.irqack = cmd646_9_irqack; 314 break; 315 default: 316 sc->sc_wdcdev.irqack = pciide_irqack; 317 } 318 } 319 320 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 321 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 322 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 323 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 324 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel; 325 sc->sc_wdcdev.wdc_maxdrives = 2; 326 327 ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 328 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 329 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 330 DEBUG_PROBE); 331 332 wdc_allocate_regs(&sc->sc_wdcdev); 333 334 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 335 channel++) 336 cmd_channel_map(pa, sc, channel); 337 338 /* 339 * note - this also makes sure we clear the irq disable and reset 340 * bits 341 */ 342 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 343 ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 344 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 345 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 346 DEBUG_PROBE); 347 } 348 349 static void 350 cmd0643_9_setup_channel(struct ata_channel *chp) 351 { 352 struct ata_drive_datas *drvp; 353 u_int8_t tim; 354 u_int32_t idedma_ctl, udma_reg; 355 int drive, s; 356 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 357 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 358 359 idedma_ctl = 0; 360 /* setup DMA if needed */ 361 pciide_channel_dma_setup(cp); 362 363 for (drive = 0; drive < 2; drive++) { 364 drvp = &chp->ch_drive[drive]; 365 /* If no drive, skip */ 366 if (drvp->drive_type == ATA_DRIVET_NONE) 367 continue; 368 /* add timing values, setup DMA if needed */ 369 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 370 if (drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) { 371 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 372 /* UltraDMA on a 646U2, 0648 or 0649 */ 373 s = splbio(); 374 drvp->drive_flags &= ~ATA_DRIVE_DMA; 375 splx(s); 376 udma_reg = pciide_pci_read(sc->sc_pc, 377 sc->sc_tag, CMD_UDMATIM(chp->ch_channel)); 378 if (drvp->UDMA_mode > 2 && 379 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 380 CMD_BICSR) & 381 CMD_BICSR_80(chp->ch_channel)) == 0) 382 drvp->UDMA_mode = 2; 383 if (drvp->UDMA_mode > 2) 384 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 385 else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2) 386 udma_reg |= CMD_UDMATIM_UDMA33(drive); 387 udma_reg |= CMD_UDMATIM_UDMA(drive); 388 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 389 CMD_UDMATIM_TIM_OFF(drive)); 390 udma_reg |= 391 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 392 CMD_UDMATIM_TIM_OFF(drive)); 393 pciide_pci_write(sc->sc_pc, sc->sc_tag, 394 CMD_UDMATIM(chp->ch_channel), udma_reg); 395 } else { 396 /* 397 * use Multiword DMA. 398 * Timings will be used for both PIO and DMA, 399 * so adjust DMA mode if needed 400 * if we have a 0646U2/8/9, turn off UDMA 401 */ 402 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 403 udma_reg = pciide_pci_read(sc->sc_pc, 404 sc->sc_tag, 405 CMD_UDMATIM(chp->ch_channel)); 406 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 407 pciide_pci_write(sc->sc_pc, sc->sc_tag, 408 CMD_UDMATIM(chp->ch_channel), 409 udma_reg); 410 } 411 if (drvp->PIO_mode >= 3 && 412 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 413 drvp->DMA_mode = drvp->PIO_mode - 2; 414 } 415 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 416 } 417 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 418 } 419 pciide_pci_write(sc->sc_pc, sc->sc_tag, 420 CMD_DATA_TIM(chp->ch_channel, drive), tim); 421 } 422 if (idedma_ctl != 0) { 423 /* Add software bits in status register */ 424 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 425 idedma_ctl); 426 } 427 } 428 429 static void 430 cmd646_9_irqack(struct ata_channel *chp) 431 { 432 u_int32_t priirq, secirq; 433 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 434 435 if (chp->ch_channel == 0) { 436 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 437 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 438 } else { 439 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 440 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 441 } 442 pciide_irqack(chp); 443 } 444 445 static void 446 cmd680_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 447 { 448 int channel; 449 450 if (pciide_chipen(sc, pa) == 0) 451 return; 452 453 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 454 "bus-master DMA support present"); 455 pciide_mapreg_dma(sc, pa); 456 aprint_verbose("\n"); 457 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 458 if (sc->sc_dma_ok) { 459 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 460 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 461 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 462 sc->sc_wdcdev.irqack = pciide_irqack; 463 } 464 465 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 466 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 467 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 468 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 469 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel; 470 sc->sc_wdcdev.wdc_maxdrives = 2; 471 472 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 473 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 474 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 475 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 476 477 wdc_allocate_regs(&sc->sc_wdcdev); 478 479 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 480 channel++) 481 cmd680_channel_map(pa, sc, channel); 482 } 483 484 static void 485 cmd680_channel_map(const struct pci_attach_args *pa, struct pciide_softc *sc, 486 int channel) 487 { 488 struct pciide_channel *cp = &sc->pciide_channels[channel]; 489 int interface, i, reg; 490 static const u_int8_t init_val[] = 491 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 492 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 493 494 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 495 interface = PCIIDE_INTERFACE_SETTABLE(0) | 496 PCIIDE_INTERFACE_SETTABLE(1); 497 interface |= PCIIDE_INTERFACE_PCI(0) | 498 PCIIDE_INTERFACE_PCI(1); 499 } else { 500 interface = PCI_INTERFACE(pa->pa_class); 501 } 502 503 sc->wdc_chanarray[channel] = &cp->ata_channel; 504 cp->name = PCIIDE_CHANNEL_NAME(channel); 505 cp->ata_channel.ch_channel = channel; 506 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 507 508 /* XXX */ 509 reg = 0xa2 + channel * 16; 510 for (i = 0; i < sizeof(init_val); i++) 511 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 512 513 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 514 "%s channel %s to %s mode\n", cp->name, 515 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 516 "configured" : "wired", 517 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 518 "native-PCI" : "compatibility"); 519 520 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 521 } 522 523 static void 524 cmd680_setup_channel(struct ata_channel *chp) 525 { 526 struct ata_drive_datas *drvp; 527 u_int8_t mode, off, scsc; 528 u_int16_t val; 529 u_int32_t idedma_ctl; 530 int drive, s; 531 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 532 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 533 pci_chipset_tag_t pc = sc->sc_pc; 534 pcitag_t pa = sc->sc_tag; 535 static const u_int8_t udma2_tbl[] = 536 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 537 static const u_int8_t udma_tbl[] = 538 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 539 static const u_int16_t dma_tbl[] = 540 { 0x2208, 0x10c2, 0x10c1 }; 541 static const u_int16_t pio_tbl[] = 542 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 543 544 idedma_ctl = 0; 545 pciide_channel_dma_setup(cp); 546 mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4); 547 548 for (drive = 0; drive < 2; drive++) { 549 drvp = &chp->ch_drive[drive]; 550 /* If no drive, skip */ 551 if (drvp->drive_type == ATA_DRIVET_NONE) 552 continue; 553 mode &= ~(0x03 << (drive * 4)); 554 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 555 s = splbio(); 556 drvp->drive_flags &= ~ATA_DRIVE_DMA; 557 splx(s); 558 off = 0xa0 + chp->ch_channel * 16; 559 if (drvp->UDMA_mode > 2 && 560 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 561 drvp->UDMA_mode = 2; 562 scsc = pciide_pci_read(pc, pa, 0x8a); 563 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 564 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 565 scsc = pciide_pci_read(pc, pa, 0x8a); 566 if ((scsc & 0x30) == 0) 567 drvp->UDMA_mode = 5; 568 } 569 mode |= 0x03 << (drive * 4); 570 off = 0xac + chp->ch_channel * 16 + drive * 2; 571 val = pciide_pci_read(pc, pa, off) & ~0x3f; 572 if (scsc & 0x30) 573 val |= udma2_tbl[drvp->UDMA_mode]; 574 else 575 val |= udma_tbl[drvp->UDMA_mode]; 576 pciide_pci_write(pc, pa, off, val); 577 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 578 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 579 mode |= 0x02 << (drive * 4); 580 off = 0xa8 + chp->ch_channel * 16 + drive * 2; 581 val = dma_tbl[drvp->DMA_mode]; 582 pciide_pci_write(pc, pa, off, val & 0xff); 583 pciide_pci_write(pc, pa, off+1, val >> 8); 584 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 585 } else { 586 mode |= 0x01 << (drive * 4); 587 off = 0xa4 + chp->ch_channel * 16 + drive * 2; 588 val = pio_tbl[drvp->PIO_mode]; 589 pciide_pci_write(pc, pa, off, val & 0xff); 590 pciide_pci_write(pc, pa, off+1, val >> 8); 591 } 592 } 593 594 pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode); 595 if (idedma_ctl != 0) { 596 /* Add software bits in status register */ 597 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 598 idedma_ctl); 599 } 600 } 601
Indexes created Fri Sep 26 20:09:58 GMT 2025