cmdide.c revision 1.44
1 /* $NetBSD: cmdide.c,v 1.44 2020/07/01 15:10:01 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: cmdide.c,v 1.44 2020/07/01 15:10:01 jdolecek Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/atomic.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_cmd_reg.h> 39 40 #define CMDIDE_ACT_CHANNEL_NONE 0xff 41 42 static int cmdide_match(device_t, cfdata_t, void *); 43 static void cmdide_attach(device_t, device_t, void *); 44 45 CFATTACH_DECL_NEW(cmdide, sizeof(struct pciide_softc), 46 cmdide_match, cmdide_attach, pciide_detach, NULL); 47 48 static void cmd_chip_map(struct pciide_softc*, const struct pci_attach_args*); 49 static void cmd0643_9_chip_map(struct pciide_softc*, 50 const struct pci_attach_args*); 51 static void cmd0643_9_setup_channel(struct ata_channel*); 52 static void cmd_channel_map(const struct pci_attach_args *, 53 struct pciide_softc *, int); 54 static int cmd064x_claim_hw(struct ata_channel *, int); 55 static void cmd064x_free_hw(struct ata_channel *); 56 static int cmd_pci_intr(void *); 57 static void cmd646_9_irqack(struct ata_channel *); 58 static void cmd680_chip_map(struct pciide_softc*, 59 const struct pci_attach_args*); 60 static void cmd680_setup_channel(struct ata_channel*); 61 static void cmd680_channel_map(const struct pci_attach_args *, 62 struct pciide_softc *, int); 63 64 /* Older CMD64X doesn't have independent channels */ 65 static const struct pciide_product_desc pciide_cmd_products[] = { 66 { PCI_PRODUCT_CMDTECH_640, 67 IDE_SHARED_CHANNELS, 68 "CMD Technology PCI0640", 69 cmd_chip_map 70 }, 71 { PCI_PRODUCT_CMDTECH_643, 72 IDE_SHARED_CHANNELS, 73 "CMD Technology PCI0643", 74 cmd0643_9_chip_map, 75 }, 76 { PCI_PRODUCT_CMDTECH_646, 77 IDE_SHARED_CHANNELS, 78 "CMD Technology PCI0646", 79 cmd0643_9_chip_map, 80 }, 81 { PCI_PRODUCT_CMDTECH_648, 82 IDE_SHARED_CHANNELS, 83 "CMD Technology PCI0648", 84 cmd0643_9_chip_map, 85 }, 86 { PCI_PRODUCT_CMDTECH_649, 87 0, 88 "CMD Technology PCI0649", 89 cmd0643_9_chip_map, 90 }, 91 { PCI_PRODUCT_CMDTECH_680, 92 0, 93 "Silicon Image 0680", 94 cmd680_chip_map, 95 }, 96 { 0, 97 0, 98 NULL, 99 NULL 100 } 101 }; 102 103 static int 104 cmdide_match(device_t parent, cfdata_t match, void *aux) 105 { 106 struct pci_attach_args *pa = aux; 107 108 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 109 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 110 return (2); 111 } 112 return (0); 113 } 114 115 static void 116 cmdide_attach(device_t parent, device_t self, void *aux) 117 { 118 struct pci_attach_args *pa = aux; 119 struct pciide_softc *sc = device_private(self); 120 121 sc->sc_wdcdev.sc_atac.atac_dev = self; 122 123 pciide_common_attach(sc, pa, 124 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 125 126 } 127 128 static void 129 cmd_channel_map(const struct pci_attach_args *pa, struct pciide_softc *sc, 130 int channel) 131 { 132 struct pciide_channel *cp = &sc->pciide_channels[channel]; 133 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 134 int interface; 135 bool one_channel = ISSET(sc->sc_pp->ide_flags, IDE_SHARED_CHANNELS); 136 137 /* 138 * The 0648/0649 can be told to identify as a RAID controller. 139 * In this case, we have to fake interface 140 */ 141 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 142 interface = PCIIDE_INTERFACE_SETTABLE(0) | 143 PCIIDE_INTERFACE_SETTABLE(1); 144 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 145 CMD_CONF_DSA1) 146 interface |= PCIIDE_INTERFACE_PCI(0) | 147 PCIIDE_INTERFACE_PCI(1); 148 } else { 149 interface = PCI_INTERFACE(pa->pa_class); 150 } 151 152 sc->wdc_chanarray[channel] = &cp->ata_channel; 153 cp->name = PCIIDE_CHANNEL_NAME(channel); 154 cp->ata_channel.ch_channel = channel; 155 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 156 157 if (channel > 0 && one_channel) { 158 /* Channels are not independant, need synchronization */ 159 sc->sc_wdcdev.sc_atac.atac_claim_hw = cmd064x_claim_hw; 160 sc->sc_wdcdev.sc_atac.atac_free_hw = cmd064x_free_hw; 161 sc->sc_cmd_act_channel = CMDIDE_ACT_CHANNEL_NONE; 162 } 163 164 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 165 "%s channel %s to %s mode%s\n", cp->name, 166 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 167 "configured" : "wired", 168 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 169 "native-PCI" : "compatibility", 170 one_channel ? ", channel non-independant" : ""); 171 172 /* 173 * with a CMD PCI64x, if we get here, the first channel is enabled: 174 * there's no way to disable the first channel without disabling 175 * the whole device 176 */ 177 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 178 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 179 "%s channel ignored (disabled)\n", cp->name); 180 cp->ata_channel.ch_flags |= ATACH_DISABLED; 181 return; 182 } 183 184 pciide_mapchan(pa, cp, interface, cmd_pci_intr); 185 } 186 187 /* 188 * Check if we can execute next xfer on the channel. 189 * Called with chp channel lock held. 190 */ 191 static int 192 cmd064x_claim_hw(struct ata_channel *chp, int maysleep) 193 { 194 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 195 196 return atomic_cas_uint(&sc->sc_cmd_act_channel, 197 CMDIDE_ACT_CHANNEL_NONE, chp->ch_channel) 198 == CMDIDE_ACT_CHANNEL_NONE; 199 } 200 201 /* Allow another channel to run. Called with ochp channel lock held. */ 202 static void 203 cmd064x_free_hw(struct ata_channel *ochp) 204 { 205 struct pciide_softc *sc = CHAN_TO_PCIIDE(ochp); 206 uint oact = atomic_cas_uint(&sc->sc_cmd_act_channel, 207 ochp->ch_channel, CMDIDE_ACT_CHANNEL_NONE); 208 struct ata_channel *nchp; 209 210 KASSERT(oact == ochp->ch_channel); 211 212 /* Start the other channel(s) */ 213 for(uint i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 214 /* Skip the current channel */ 215 if (i == oact) 216 continue; 217 218 nchp = &sc->pciide_channels[i].ata_channel; 219 if (nchp->ch_ndrives == 0) 220 continue; 221 222 atastart(nchp); 223 } 224 } 225 226 static int 227 cmd_pci_intr(void *arg) 228 { 229 struct pciide_softc *sc = arg; 230 struct pciide_channel *cp; 231 struct ata_channel *wdc_cp; 232 int i, rv, crv; 233 u_int32_t priirq, secirq; 234 235 rv = 0; 236 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 237 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 238 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 239 cp = &sc->pciide_channels[i]; 240 wdc_cp = &cp->ata_channel; 241 242 /* If a compat channel skip. */ 243 if (cp->compat) 244 continue; 245 246 /* if this channel not waiting for intr, skip */ 247 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) 248 continue; 249 250 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 251 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 252 crv = wdcintr(wdc_cp); 253 if (crv == 0) { 254 aprint_error("%s:%d: bogus intr\n", 255 device_xname( 256 sc->sc_wdcdev.sc_atac.atac_dev), i); 257 sc->sc_wdcdev.irqack(wdc_cp); 258 } else 259 rv = 1; 260 } 261 } 262 return rv; 263 } 264 265 static void 266 cmd_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 267 { 268 int channel; 269 270 /* 271 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 272 * and base addresses registers can be disabled at 273 * hardware level. In this case, the device is wired 274 * in compat mode and its first channel is always enabled, 275 * but we can't rely on PCI_COMMAND_IO_ENABLE. 276 * In fact, it seems that the first channel of the CMD PCI0640 277 * can't be disabled. 278 */ 279 280 #ifdef PCIIDE_CMD064x_DISABLE 281 if (pciide_chipen(sc, pa) == 0) 282 return; 283 #endif 284 285 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 286 "hardware does not support DMA\n"); 287 sc->sc_dma_ok = 0; 288 289 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 290 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 291 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 292 sc->sc_wdcdev.wdc_maxdrives = 2; 293 294 wdc_allocate_regs(&sc->sc_wdcdev); 295 296 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 297 channel++) { 298 cmd_channel_map(pa, sc, channel); 299 } 300 } 301 302 static void 303 cmd0643_9_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 304 { 305 int channel; 306 pcireg_t rev = PCI_REVISION(pa->pa_class); 307 308 /* 309 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 310 * and base addresses registers can be disabled at 311 * hardware level. In this case, the device is wired 312 * in compat mode and its first channel is always enabled, 313 * but we can't rely on PCI_COMMAND_IO_ENABLE. 314 * In fact, it seems that the first channel of the CMD PCI0640 315 * can't be disabled. 316 */ 317 318 #ifdef PCIIDE_CMD064x_DISABLE 319 if (pciide_chipen(sc, pa) == 0) 320 return; 321 #endif 322 323 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 324 "bus-master DMA support present"); 325 pciide_mapreg_dma(sc, pa); 326 aprint_verbose("\n"); 327 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 328 if (sc->sc_dma_ok) { 329 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 330 switch (sc->sc_pp->ide_product) { 331 case PCI_PRODUCT_CMDTECH_649: 332 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 333 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 334 sc->sc_wdcdev.irqack = cmd646_9_irqack; 335 break; 336 case PCI_PRODUCT_CMDTECH_648: 337 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 338 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 339 sc->sc_wdcdev.irqack = cmd646_9_irqack; 340 break; 341 case PCI_PRODUCT_CMDTECH_646: 342 if (rev >= CMD0646U2_REV) { 343 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 344 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 345 } else if (rev >= CMD0646U_REV) { 346 /* 347 * Linux's driver claims that the 646U is broken 348 * with UDMA. Only enable it if we know what we're 349 * doing 350 */ 351 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 352 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 353 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 354 #endif 355 /* explicitly disable UDMA */ 356 pciide_pci_write(sc->sc_pc, sc->sc_tag, 357 CMD_UDMATIM(0), 0); 358 pciide_pci_write(sc->sc_pc, sc->sc_tag, 359 CMD_UDMATIM(1), 0); 360 } 361 sc->sc_wdcdev.irqack = cmd646_9_irqack; 362 break; 363 default: 364 sc->sc_wdcdev.irqack = pciide_irqack; 365 } 366 } 367 368 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 369 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 370 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 371 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 372 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel; 373 sc->sc_wdcdev.wdc_maxdrives = 2; 374 375 ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 376 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 377 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 378 DEBUG_PROBE); 379 380 wdc_allocate_regs(&sc->sc_wdcdev); 381 382 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 383 channel++) 384 cmd_channel_map(pa, sc, channel); 385 386 /* 387 * note - this also makes sure we clear the irq disable and reset 388 * bits 389 */ 390 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 391 ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 392 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 393 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 394 DEBUG_PROBE); 395 } 396 397 static void 398 cmd0643_9_setup_channel(struct ata_channel *chp) 399 { 400 struct ata_drive_datas *drvp; 401 u_int8_t tim; 402 u_int32_t idedma_ctl, udma_reg; 403 int drive, s; 404 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 405 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 406 407 idedma_ctl = 0; 408 /* setup DMA if needed */ 409 pciide_channel_dma_setup(cp); 410 411 for (drive = 0; drive < 2; drive++) { 412 drvp = &chp->ch_drive[drive]; 413 /* If no drive, skip */ 414 if (drvp->drive_type == ATA_DRIVET_NONE) 415 continue; 416 /* add timing values, setup DMA if needed */ 417 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 418 if (drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) { 419 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 420 /* UltraDMA on a 646U2, 0648 or 0649 */ 421 s = splbio(); 422 drvp->drive_flags &= ~ATA_DRIVE_DMA; 423 splx(s); 424 udma_reg = pciide_pci_read(sc->sc_pc, 425 sc->sc_tag, CMD_UDMATIM(chp->ch_channel)); 426 if (drvp->UDMA_mode > 2 && 427 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 428 CMD_BICSR) & 429 CMD_BICSR_80(chp->ch_channel)) == 0) 430 drvp->UDMA_mode = 2; 431 if (drvp->UDMA_mode > 2) 432 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 433 else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2) 434 udma_reg |= CMD_UDMATIM_UDMA33(drive); 435 udma_reg |= CMD_UDMATIM_UDMA(drive); 436 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 437 CMD_UDMATIM_TIM_OFF(drive)); 438 udma_reg |= 439 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 440 CMD_UDMATIM_TIM_OFF(drive)); 441 pciide_pci_write(sc->sc_pc, sc->sc_tag, 442 CMD_UDMATIM(chp->ch_channel), udma_reg); 443 } else { 444 /* 445 * use Multiword DMA. 446 * Timings will be used for both PIO and DMA, 447 * so adjust DMA mode if needed 448 * if we have a 0646U2/8/9, turn off UDMA 449 */ 450 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 451 udma_reg = pciide_pci_read(sc->sc_pc, 452 sc->sc_tag, 453 CMD_UDMATIM(chp->ch_channel)); 454 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 455 pciide_pci_write(sc->sc_pc, sc->sc_tag, 456 CMD_UDMATIM(chp->ch_channel), 457 udma_reg); 458 } 459 if (drvp->PIO_mode >= 3 && 460 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 461 drvp->DMA_mode = drvp->PIO_mode - 2; 462 } 463 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 464 } 465 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 466 } 467 pciide_pci_write(sc->sc_pc, sc->sc_tag, 468 CMD_DATA_TIM(chp->ch_channel, drive), tim); 469 } 470 if (idedma_ctl != 0) { 471 /* Add software bits in status register */ 472 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 473 idedma_ctl); 474 } 475 } 476 477 static void 478 cmd646_9_irqack(struct ata_channel *chp) 479 { 480 u_int32_t priirq, secirq; 481 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 482 483 if (chp->ch_channel == 0) { 484 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 485 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 486 } else { 487 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 488 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 489 } 490 pciide_irqack(chp); 491 } 492 493 static void 494 cmd680_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 495 { 496 int channel; 497 498 if (pciide_chipen(sc, pa) == 0) 499 return; 500 501 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 502 "bus-master DMA support present"); 503 pciide_mapreg_dma(sc, pa); 504 aprint_verbose("\n"); 505 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 506 if (sc->sc_dma_ok) { 507 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 508 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 509 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 510 sc->sc_wdcdev.irqack = pciide_irqack; 511 } 512 513 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 514 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 515 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 516 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 517 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel; 518 sc->sc_wdcdev.wdc_maxdrives = 2; 519 520 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 521 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 522 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 523 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 524 525 wdc_allocate_regs(&sc->sc_wdcdev); 526 527 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 528 channel++) 529 cmd680_channel_map(pa, sc, channel); 530 } 531 532 static void 533 cmd680_channel_map(const struct pci_attach_args *pa, struct pciide_softc *sc, 534 int channel) 535 { 536 struct pciide_channel *cp = &sc->pciide_channels[channel]; 537 int interface, i, reg; 538 static const u_int8_t init_val[] = 539 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 540 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 541 542 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 543 interface = PCIIDE_INTERFACE_SETTABLE(0) | 544 PCIIDE_INTERFACE_SETTABLE(1); 545 interface |= PCIIDE_INTERFACE_PCI(0) | 546 PCIIDE_INTERFACE_PCI(1); 547 } else { 548 interface = PCI_INTERFACE(pa->pa_class); 549 } 550 551 sc->wdc_chanarray[channel] = &cp->ata_channel; 552 cp->name = PCIIDE_CHANNEL_NAME(channel); 553 cp->ata_channel.ch_channel = channel; 554 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 555 556 /* XXX */ 557 reg = 0xa2 + channel * 16; 558 for (i = 0; i < sizeof(init_val); i++) 559 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 560 561 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 562 "%s channel %s to %s mode\n", cp->name, 563 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 564 "configured" : "wired", 565 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 566 "native-PCI" : "compatibility"); 567 568 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 569 } 570 571 static void 572 cmd680_setup_channel(struct ata_channel *chp) 573 { 574 struct ata_drive_datas *drvp; 575 u_int8_t mode, off, scsc; 576 u_int16_t val; 577 u_int32_t idedma_ctl; 578 int drive, s; 579 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 580 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 581 pci_chipset_tag_t pc = sc->sc_pc; 582 pcitag_t pa = sc->sc_tag; 583 static const u_int8_t udma2_tbl[] = 584 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 585 static const u_int8_t udma_tbl[] = 586 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 587 static const u_int16_t dma_tbl[] = 588 { 0x2208, 0x10c2, 0x10c1 }; 589 static const u_int16_t pio_tbl[] = 590 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 591 592 idedma_ctl = 0; 593 pciide_channel_dma_setup(cp); 594 mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4); 595 596 for (drive = 0; drive < 2; drive++) { 597 drvp = &chp->ch_drive[drive]; 598 /* If no drive, skip */ 599 if (drvp->drive_type == ATA_DRIVET_NONE) 600 continue; 601 mode &= ~(0x03 << (drive * 4)); 602 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 603 s = splbio(); 604 drvp->drive_flags &= ~ATA_DRIVE_DMA; 605 splx(s); 606 off = 0xa0 + chp->ch_channel * 16; 607 if (drvp->UDMA_mode > 2 && 608 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 609 drvp->UDMA_mode = 2; 610 scsc = pciide_pci_read(pc, pa, 0x8a); 611 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 612 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 613 scsc = pciide_pci_read(pc, pa, 0x8a); 614 if ((scsc & 0x30) == 0) 615 drvp->UDMA_mode = 5; 616 } 617 mode |= 0x03 << (drive * 4); 618 off = 0xac + chp->ch_channel * 16 + drive * 2; 619 val = pciide_pci_read(pc, pa, off) & ~0x3f; 620 if (scsc & 0x30) 621 val |= udma2_tbl[drvp->UDMA_mode]; 622 else 623 val |= udma_tbl[drvp->UDMA_mode]; 624 pciide_pci_write(pc, pa, off, val); 625 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 626 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 627 mode |= 0x02 << (drive * 4); 628 off = 0xa8 + chp->ch_channel * 16 + drive * 2; 629 val = dma_tbl[drvp->DMA_mode]; 630 pciide_pci_write(pc, pa, off, val & 0xff); 631 pciide_pci_write(pc, pa, off+1, val >> 8); 632 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 633 } else { 634 mode |= 0x01 << (drive * 4); 635 off = 0xa4 + chp->ch_channel * 16 + drive * 2; 636 val = pio_tbl[drvp->PIO_mode]; 637 pciide_pci_write(pc, pa, off, val & 0xff); 638 pciide_pci_write(pc, pa, off+1, val >> 8); 639 } 640 } 641 642 pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode); 643 if (idedma_ctl != 0) { 644 /* Add software bits in status register */ 645 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 646 idedma_ctl); 647 } 648 } 649
Indexes created Wed Oct 01 19:09:53 GMT 2025