cmdide.c revision 1.8
1 /* $NetBSD: cmdide.c,v 1.8 2004/01/01 17:18:53 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pciidereg.h> 39 #include <dev/pci/pciidevar.h> 40 #include <dev/pci/pciide_cmd_reg.h> 41 42 43 static int cmdide_match(struct device *, struct cfdata *, void *); 44 static void cmdide_attach(struct device *, struct device *, void *); 45 46 CFATTACH_DECL(cmdide, sizeof(struct pciide_softc), 47 cmdide_match, cmdide_attach, NULL, NULL); 48 49 static void cmd_chip_map(struct pciide_softc*, struct pci_attach_args*); 50 static void cmd0643_9_chip_map(struct pciide_softc*, struct pci_attach_args*); 51 static void cmd0643_9_setup_channel(struct channel_softc*); 52 static void cmd_channel_map(struct pci_attach_args *, struct pciide_softc *, 53 int); 54 static int cmd_pci_intr(void *); 55 static void cmd646_9_irqack(struct channel_softc *); 56 static void cmd680_chip_map(struct pciide_softc*, struct pci_attach_args*); 57 static void cmd680_setup_channel(struct channel_softc*); 58 static void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *, 59 int); 60 61 static const struct pciide_product_desc pciide_cmd_products[] = { 62 { PCI_PRODUCT_CMDTECH_640, 63 0, 64 "CMD Technology PCI0640", 65 cmd_chip_map 66 }, 67 { PCI_PRODUCT_CMDTECH_643, 68 0, 69 "CMD Technology PCI0643", 70 cmd0643_9_chip_map, 71 }, 72 { PCI_PRODUCT_CMDTECH_646, 73 0, 74 "CMD Technology PCI0646", 75 cmd0643_9_chip_map, 76 }, 77 { PCI_PRODUCT_CMDTECH_648, 78 0, 79 "CMD Technology PCI0648", 80 cmd0643_9_chip_map, 81 }, 82 { PCI_PRODUCT_CMDTECH_649, 83 0, 84 "CMD Technology PCI0649", 85 cmd0643_9_chip_map, 86 }, 87 { PCI_PRODUCT_CMDTECH_680, 88 0, 89 "Silicon Image 0680", 90 cmd680_chip_map, 91 }, 92 { 0, 93 0, 94 NULL, 95 NULL 96 } 97 }; 98 99 static int 100 cmdide_match(struct device *parent, struct cfdata *match, void *aux) 101 { 102 struct pci_attach_args *pa = aux; 103 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 105 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 106 return (2); 107 } 108 return (0); 109 } 110 111 static void 112 cmdide_attach(struct device *parent, struct device *self, void *aux) 113 { 114 struct pci_attach_args *pa = aux; 115 struct pciide_softc *sc = (struct pciide_softc *)self; 116 117 pciide_common_attach(sc, pa, 118 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 119 120 } 121 122 static void 123 cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 124 int channel) 125 { 126 struct pciide_channel *cp = &sc->pciide_channels[channel]; 127 bus_size_t cmdsize, ctlsize; 128 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 129 int interface, one_channel; 130 131 /* 132 * The 0648/0649 can be told to identify as a RAID controller. 133 * In this case, we have to fake interface 134 */ 135 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 136 interface = PCIIDE_INTERFACE_SETTABLE(0) | 137 PCIIDE_INTERFACE_SETTABLE(1); 138 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 139 CMD_CONF_DSA1) 140 interface |= PCIIDE_INTERFACE_PCI(0) | 141 PCIIDE_INTERFACE_PCI(1); 142 } else { 143 interface = PCI_INTERFACE(pa->pa_class); 144 } 145 146 sc->wdc_chanarray[channel] = &cp->wdc_channel; 147 cp->name = PCIIDE_CHANNEL_NAME(channel); 148 cp->wdc_channel.channel = channel; 149 cp->wdc_channel.wdc = &sc->sc_wdcdev; 150 151 /* 152 * Older CMD64X doesn't have independant channels 153 */ 154 switch (sc->sc_pp->ide_product) { 155 case PCI_PRODUCT_CMDTECH_649: 156 one_channel = 0; 157 break; 158 default: 159 one_channel = 1; 160 break; 161 } 162 163 if (channel > 0 && one_channel) { 164 cp->wdc_channel.ch_queue = 165 sc->pciide_channels[0].wdc_channel.ch_queue; 166 } else { 167 cp->wdc_channel.ch_queue = 168 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 169 } 170 if (cp->wdc_channel.ch_queue == NULL) { 171 aprint_error("%s %s channel: " 172 "can't allocate memory for command queue", 173 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 174 return; 175 } 176 177 aprint_normal("%s: %s channel %s to %s mode\n", 178 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 179 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 180 "configured" : "wired", 181 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 182 "native-PCI" : "compatibility"); 183 184 /* 185 * with a CMD PCI64x, if we get here, the first channel is enabled: 186 * there's no way to disable the first channel without disabling 187 * the whole device 188 */ 189 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 190 aprint_normal("%s: %s channel ignored (disabled)\n", 191 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 192 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 193 return; 194 } 195 196 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 197 } 198 199 static int 200 cmd_pci_intr(void *arg) 201 { 202 struct pciide_softc *sc = arg; 203 struct pciide_channel *cp; 204 struct channel_softc *wdc_cp; 205 int i, rv, crv; 206 u_int32_t priirq, secirq; 207 208 rv = 0; 209 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 210 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 211 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 212 cp = &sc->pciide_channels[i]; 213 wdc_cp = &cp->wdc_channel; 214 /* If a compat channel skip. */ 215 if (cp->compat) 216 continue; 217 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 218 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 219 crv = wdcintr(wdc_cp); 220 if (crv == 0) 221 printf("%s:%d: bogus intr\n", 222 sc->sc_wdcdev.sc_dev.dv_xname, i); 223 else 224 rv = 1; 225 } 226 } 227 return rv; 228 } 229 230 static void 231 cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 232 { 233 int channel; 234 235 /* 236 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 237 * and base addresses registers can be disabled at 238 * hardware level. In this case, the device is wired 239 * in compat mode and its first channel is always enabled, 240 * but we can't rely on PCI_COMMAND_IO_ENABLE. 241 * In fact, it seems that the first channel of the CMD PCI0640 242 * can't be disabled. 243 */ 244 245 #ifdef PCIIDE_CMD064x_DISABLE 246 if (pciide_chipen(sc, pa) == 0) 247 return; 248 #endif 249 250 aprint_normal("%s: hardware does not support DMA\n", 251 sc->sc_wdcdev.sc_dev.dv_xname); 252 sc->sc_dma_ok = 0; 253 254 sc->sc_wdcdev.channels = sc->wdc_chanarray; 255 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 256 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 257 258 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 259 cmd_channel_map(pa, sc, channel); 260 } 261 } 262 263 static void 264 cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 265 { 266 int channel; 267 pcireg_t rev = PCI_REVISION(pa->pa_class); 268 269 /* 270 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 271 * and base addresses registers can be disabled at 272 * hardware level. In this case, the device is wired 273 * in compat mode and its first channel is always enabled, 274 * but we can't rely on PCI_COMMAND_IO_ENABLE. 275 * In fact, it seems that the first channel of the CMD PCI0640 276 * can't be disabled. 277 */ 278 279 #ifdef PCIIDE_CMD064x_DISABLE 280 if (pciide_chipen(sc, pa) == 0) 281 return; 282 #endif 283 284 aprint_normal("%s: bus-master DMA support present", 285 sc->sc_wdcdev.sc_dev.dv_xname); 286 pciide_mapreg_dma(sc, pa); 287 aprint_normal("\n"); 288 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 289 WDC_CAPABILITY_MODE; 290 if (sc->sc_dma_ok) { 291 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 292 switch (sc->sc_pp->ide_product) { 293 case PCI_PRODUCT_CMDTECH_649: 294 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 295 sc->sc_wdcdev.UDMA_cap = 5; 296 sc->sc_wdcdev.irqack = cmd646_9_irqack; 297 break; 298 case PCI_PRODUCT_CMDTECH_648: 299 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 300 sc->sc_wdcdev.UDMA_cap = 4; 301 sc->sc_wdcdev.irqack = cmd646_9_irqack; 302 break; 303 case PCI_PRODUCT_CMDTECH_646: 304 if (rev >= CMD0646U2_REV) { 305 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 306 sc->sc_wdcdev.UDMA_cap = 2; 307 } else if (rev >= CMD0646U_REV) { 308 /* 309 * Linux's driver claims that the 646U is broken 310 * with UDMA. Only enable it if we know what we're 311 * doing 312 */ 313 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 314 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 315 sc->sc_wdcdev.UDMA_cap = 2; 316 #endif 317 /* explicitly disable UDMA */ 318 pciide_pci_write(sc->sc_pc, sc->sc_tag, 319 CMD_UDMATIM(0), 0); 320 pciide_pci_write(sc->sc_pc, sc->sc_tag, 321 CMD_UDMATIM(1), 0); 322 } 323 sc->sc_wdcdev.irqack = cmd646_9_irqack; 324 break; 325 default: 326 sc->sc_wdcdev.irqack = pciide_irqack; 327 } 328 } 329 330 sc->sc_wdcdev.channels = sc->wdc_chanarray; 331 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 332 sc->sc_wdcdev.PIO_cap = 4; 333 sc->sc_wdcdev.DMA_cap = 2; 334 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 335 336 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 337 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 338 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 339 DEBUG_PROBE); 340 341 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) 342 cmd_channel_map(pa, sc, channel); 343 344 /* 345 * note - this also makes sure we clear the irq disable and reset 346 * bits 347 */ 348 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 349 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 350 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 351 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 352 DEBUG_PROBE); 353 } 354 355 static void 356 cmd0643_9_setup_channel(struct channel_softc *chp) 357 { 358 struct ata_drive_datas *drvp; 359 u_int8_t tim; 360 u_int32_t idedma_ctl, udma_reg; 361 int drive; 362 struct pciide_channel *cp = (struct pciide_channel*)chp; 363 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 364 365 idedma_ctl = 0; 366 /* setup DMA if needed */ 367 pciide_channel_dma_setup(cp); 368 369 for (drive = 0; drive < 2; drive++) { 370 drvp = &chp->ch_drive[drive]; 371 /* If no drive, skip */ 372 if ((drvp->drive_flags & DRIVE) == 0) 373 continue; 374 /* add timing values, setup DMA if needed */ 375 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 376 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 377 if (drvp->drive_flags & DRIVE_UDMA) { 378 /* UltraDMA on a 646U2, 0648 or 0649 */ 379 drvp->drive_flags &= ~DRIVE_DMA; 380 udma_reg = pciide_pci_read(sc->sc_pc, 381 sc->sc_tag, CMD_UDMATIM(chp->channel)); 382 if (drvp->UDMA_mode > 2 && 383 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 384 CMD_BICSR) & 385 CMD_BICSR_80(chp->channel)) == 0) 386 drvp->UDMA_mode = 2; 387 if (drvp->UDMA_mode > 2) 388 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 389 else if (sc->sc_wdcdev.UDMA_cap > 2) 390 udma_reg |= CMD_UDMATIM_UDMA33(drive); 391 udma_reg |= CMD_UDMATIM_UDMA(drive); 392 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 393 CMD_UDMATIM_TIM_OFF(drive)); 394 udma_reg |= 395 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 396 CMD_UDMATIM_TIM_OFF(drive)); 397 pciide_pci_write(sc->sc_pc, sc->sc_tag, 398 CMD_UDMATIM(chp->channel), udma_reg); 399 } else { 400 /* 401 * use Multiword DMA. 402 * Timings will be used for both PIO and DMA, 403 * so adjust DMA mode if needed 404 * if we have a 0646U2/8/9, turn off UDMA 405 */ 406 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 407 udma_reg = pciide_pci_read(sc->sc_pc, 408 sc->sc_tag, 409 CMD_UDMATIM(chp->channel)); 410 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 411 pciide_pci_write(sc->sc_pc, sc->sc_tag, 412 CMD_UDMATIM(chp->channel), 413 udma_reg); 414 } 415 if (drvp->PIO_mode >= 3 && 416 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 417 drvp->DMA_mode = drvp->PIO_mode - 2; 418 } 419 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 420 } 421 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 422 } 423 pciide_pci_write(sc->sc_pc, sc->sc_tag, 424 CMD_DATA_TIM(chp->channel, drive), tim); 425 } 426 if (idedma_ctl != 0) { 427 /* Add software bits in status register */ 428 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 429 idedma_ctl); 430 } 431 } 432 433 static void 434 cmd646_9_irqack(struct channel_softc *chp) 435 { 436 u_int32_t priirq, secirq; 437 struct pciide_channel *cp = (struct pciide_channel*)chp; 438 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 439 440 if (chp->channel == 0) { 441 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 442 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 443 } else { 444 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 445 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 446 } 447 pciide_irqack(chp); 448 } 449 450 static void 451 cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 452 { 453 int channel; 454 455 if (pciide_chipen(sc, pa) == 0) 456 return; 457 458 aprint_normal("%s: bus-master DMA support present", 459 sc->sc_wdcdev.sc_dev.dv_xname); 460 pciide_mapreg_dma(sc, pa); 461 aprint_normal("\n"); 462 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 463 WDC_CAPABILITY_MODE; 464 if (sc->sc_dma_ok) { 465 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 466 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 467 sc->sc_wdcdev.UDMA_cap = 6; 468 sc->sc_wdcdev.irqack = pciide_irqack; 469 } 470 471 sc->sc_wdcdev.channels = sc->wdc_chanarray; 472 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 473 sc->sc_wdcdev.PIO_cap = 4; 474 sc->sc_wdcdev.DMA_cap = 2; 475 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 476 477 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 478 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 479 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 480 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 481 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) 482 cmd680_channel_map(pa, sc, channel); 483 } 484 485 static void 486 cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 487 int channel) 488 { 489 struct pciide_channel *cp = &sc->pciide_channels[channel]; 490 bus_size_t cmdsize, ctlsize; 491 int interface, i, reg; 492 static const u_int8_t init_val[] = 493 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 494 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 495 496 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 497 interface = PCIIDE_INTERFACE_SETTABLE(0) | 498 PCIIDE_INTERFACE_SETTABLE(1); 499 interface |= PCIIDE_INTERFACE_PCI(0) | 500 PCIIDE_INTERFACE_PCI(1); 501 } else { 502 interface = PCI_INTERFACE(pa->pa_class); 503 } 504 505 sc->wdc_chanarray[channel] = &cp->wdc_channel; 506 cp->name = PCIIDE_CHANNEL_NAME(channel); 507 cp->wdc_channel.channel = channel; 508 cp->wdc_channel.wdc = &sc->sc_wdcdev; 509 510 cp->wdc_channel.ch_queue = 511 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 512 if (cp->wdc_channel.ch_queue == NULL) { 513 aprint_error("%s %s channel: " 514 "can't allocate memory for command queue", 515 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 516 return; 517 } 518 519 /* XXX */ 520 reg = 0xa2 + channel * 16; 521 for (i = 0; i < sizeof(init_val); i++) 522 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 523 524 aprint_normal("%s: %s channel %s to %s mode\n", 525 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 526 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 527 "configured" : "wired", 528 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 529 "native-PCI" : "compatibility"); 530 531 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 532 } 533 534 static void 535 cmd680_setup_channel(struct channel_softc *chp) 536 { 537 struct ata_drive_datas *drvp; 538 u_int8_t mode, off, scsc; 539 u_int16_t val; 540 u_int32_t idedma_ctl; 541 int drive; 542 struct pciide_channel *cp = (struct pciide_channel*)chp; 543 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 544 pci_chipset_tag_t pc = sc->sc_pc; 545 pcitag_t pa = sc->sc_tag; 546 static const u_int8_t udma2_tbl[] = 547 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 548 static const u_int8_t udma_tbl[] = 549 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 550 static const u_int16_t dma_tbl[] = 551 { 0x2208, 0x10c2, 0x10c1 }; 552 static const u_int16_t pio_tbl[] = 553 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 554 555 idedma_ctl = 0; 556 pciide_channel_dma_setup(cp); 557 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 558 559 for (drive = 0; drive < 2; drive++) { 560 drvp = &chp->ch_drive[drive]; 561 /* If no drive, skip */ 562 if ((drvp->drive_flags & DRIVE) == 0) 563 continue; 564 mode &= ~(0x03 << (drive * 4)); 565 if (drvp->drive_flags & DRIVE_UDMA) { 566 drvp->drive_flags &= ~DRIVE_DMA; 567 off = 0xa0 + chp->channel * 16; 568 if (drvp->UDMA_mode > 2 && 569 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 570 drvp->UDMA_mode = 2; 571 scsc = pciide_pci_read(pc, pa, 0x8a); 572 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 573 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 574 scsc = pciide_pci_read(pc, pa, 0x8a); 575 if ((scsc & 0x30) == 0) 576 drvp->UDMA_mode = 5; 577 } 578 mode |= 0x03 << (drive * 4); 579 off = 0xac + chp->channel * 16 + drive * 2; 580 val = pciide_pci_read(pc, pa, off) & ~0x3f; 581 if (scsc & 0x30) 582 val |= udma2_tbl[drvp->UDMA_mode]; 583 else 584 val |= udma_tbl[drvp->UDMA_mode]; 585 pciide_pci_write(pc, pa, off, val); 586 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 587 } else if (drvp->drive_flags & DRIVE_DMA) { 588 mode |= 0x02 << (drive * 4); 589 off = 0xa8 + chp->channel * 16 + drive * 2; 590 val = dma_tbl[drvp->DMA_mode]; 591 pciide_pci_write(pc, pa, off, val & 0xff); 592 pciide_pci_write(pc, pa, off, val >> 8); 593 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 594 } else { 595 mode |= 0x01 << (drive * 4); 596 off = 0xa4 + chp->channel * 16 + drive * 2; 597 val = pio_tbl[drvp->PIO_mode]; 598 pciide_pci_write(pc, pa, off, val & 0xff); 599 pciide_pci_write(pc, pa, off, val >> 8); 600 } 601 } 602 603 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 604 if (idedma_ctl != 0) { 605 /* Add software bits in status register */ 606 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 607 idedma_ctl); 608 } 609 } 610
Indexes created Thu Sep 25 16:09:42 GMT 2025