cmpci.c revision 1.10 1 1.10 itohy /* $NetBSD: cmpci.c,v 1.10 2001/11/04 06:57:40 itohy Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.10 itohy * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.7 tshiozak * by Takuya SHIOZAKI <tshiozak (at) netbsd.org> .
9 1.1 augustss *
10 1.10 itohy * This code is derived from software contributed to The NetBSD Foundation
11 1.10 itohy * by ITOH Yasufumi.
12 1.10 itohy *
13 1.1 augustss * Redistribution and use in source and binary forms, with or without
14 1.1 augustss * modification, are permitted provided that the following conditions
15 1.1 augustss * are met:
16 1.1 augustss * 1. Redistributions of source code must retain the above copyright
17 1.1 augustss * notice, this list of conditions and the following disclaimer.
18 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
19 1.1 augustss * notice, this list of conditions and the following disclaimer in the
20 1.1 augustss * documentation and/or other materials provided with the distribution.
21 1.1 augustss *
22 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 1.1 augustss * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.1 augustss * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 augustss * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 1.1 augustss * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 1.1 augustss * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 1.1 augustss * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.1 augustss * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.1 augustss * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.1 augustss * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.1 augustss * SUCH DAMAGE.
33 1.1 augustss *
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * C-Media CMI8x38 Audio Chip Support.
38 1.1 augustss *
39 1.1 augustss * TODO:
40 1.10 itohy * - 4ch / 6ch support.
41 1.10 itohy * - Joystick support.
42 1.1 augustss *
43 1.1 augustss */
44 1.1 augustss
45 1.1 augustss #if defined(AUDIO_DEBUG) || defined(DEBUG)
46 1.7 tshiozak #define DPRINTF(x) if (cmpcidebug) printf x
47 1.7 tshiozak int cmpcidebug = 0;
48 1.1 augustss #else
49 1.1 augustss #define DPRINTF(x)
50 1.1 augustss #endif
51 1.1 augustss
52 1.8 itohy #include "mpu.h"
53 1.8 itohy
54 1.1 augustss #include <sys/param.h>
55 1.1 augustss #include <sys/systm.h>
56 1.1 augustss #include <sys/kernel.h>
57 1.1 augustss #include <sys/malloc.h>
58 1.1 augustss #include <sys/device.h>
59 1.1 augustss #include <sys/proc.h>
60 1.1 augustss
61 1.1 augustss #include <dev/pci/pcidevs.h>
62 1.1 augustss #include <dev/pci/pcivar.h>
63 1.1 augustss
64 1.1 augustss #include <sys/audioio.h>
65 1.1 augustss #include <dev/audio_if.h>
66 1.1 augustss #include <dev/midi_if.h>
67 1.1 augustss
68 1.1 augustss #include <dev/mulaw.h>
69 1.1 augustss #include <dev/auconv.h>
70 1.1 augustss #include <dev/pci/cmpcireg.h>
71 1.1 augustss #include <dev/pci/cmpcivar.h>
72 1.1 augustss
73 1.1 augustss #include <dev/ic/mpuvar.h>
74 1.1 augustss #include <machine/bus.h>
75 1.1 augustss #include <machine/intr.h>
76 1.1 augustss
77 1.1 augustss /*
78 1.1 augustss * Low-level HW interface
79 1.1 augustss */
80 1.1 augustss static __inline uint8_t cmpci_mixerreg_read __P((struct cmpci_softc *,
81 1.7 tshiozak uint8_t));
82 1.1 augustss static __inline void cmpci_mixerreg_write __P((struct cmpci_softc *,
83 1.7 tshiozak uint8_t, uint8_t));
84 1.10 itohy static __inline void cmpci_reg_partial_write_1 __P((struct cmpci_softc *,
85 1.10 itohy int, int,
86 1.10 itohy unsigned, unsigned));
87 1.1 augustss static __inline void cmpci_reg_partial_write_4 __P((struct cmpci_softc *,
88 1.7 tshiozak int, int,
89 1.7 tshiozak uint32_t, uint32_t));
90 1.7 tshiozak static __inline void cmpci_reg_set_1 __P((struct cmpci_softc *,
91 1.7 tshiozak int, uint8_t));
92 1.7 tshiozak static __inline void cmpci_reg_clear_1 __P((struct cmpci_softc *,
93 1.7 tshiozak int, uint8_t));
94 1.1 augustss static __inline void cmpci_reg_set_4 __P((struct cmpci_softc *,
95 1.7 tshiozak int, uint32_t));
96 1.1 augustss static __inline void cmpci_reg_clear_4 __P((struct cmpci_softc *,
97 1.7 tshiozak int, uint32_t));
98 1.1 augustss static int cmpci_rate_to_index __P((int));
99 1.1 augustss static __inline int cmpci_index_to_rate __P((int));
100 1.1 augustss static __inline int cmpci_index_to_divider __P((int));
101 1.1 augustss
102 1.1 augustss static int cmpci_adjust __P((int, int));
103 1.1 augustss static void cmpci_set_mixer_gain __P((struct cmpci_softc *, int));
104 1.7 tshiozak static void cmpci_set_out_ports __P((struct cmpci_softc *));
105 1.10 itohy static int cmpci_set_in_ports __P((struct cmpci_softc *));
106 1.1 augustss
107 1.1 augustss
108 1.1 augustss /*
109 1.1 augustss * autoconf interface
110 1.1 augustss */
111 1.1 augustss static int cmpci_match __P((struct device *, struct cfdata *, void *));
112 1.1 augustss static void cmpci_attach __P((struct device *, struct device *, void *));
113 1.1 augustss
114 1.1 augustss struct cfattach cmpci_ca = {
115 1.1 augustss sizeof (struct cmpci_softc), cmpci_match, cmpci_attach
116 1.1 augustss };
117 1.1 augustss
118 1.1 augustss /* interrupt */
119 1.1 augustss static int cmpci_intr __P((void *));
120 1.1 augustss
121 1.1 augustss
122 1.1 augustss /*
123 1.1 augustss * DMA stuffs
124 1.1 augustss */
125 1.1 augustss static int cmpci_alloc_dmamem __P((struct cmpci_softc *,
126 1.7 tshiozak size_t, int, int, caddr_t *));
127 1.1 augustss static int cmpci_free_dmamem __P((struct cmpci_softc *, caddr_t, int));
128 1.1 augustss static struct cmpci_dmanode * cmpci_find_dmamem __P((struct cmpci_softc *,
129 1.7 tshiozak caddr_t));
130 1.1 augustss
131 1.1 augustss
132 1.1 augustss /*
133 1.1 augustss * interface to machine independent layer
134 1.1 augustss */
135 1.1 augustss static int cmpci_open __P((void *, int));
136 1.1 augustss static void cmpci_close __P((void *));
137 1.1 augustss static int cmpci_query_encoding __P((void *, struct audio_encoding *));
138 1.1 augustss static int cmpci_set_params __P((void *, int, int,
139 1.7 tshiozak struct audio_params *,
140 1.7 tshiozak struct audio_params *));
141 1.1 augustss static int cmpci_round_blocksize __P((void *, int));
142 1.1 augustss static int cmpci_halt_output __P((void *));
143 1.1 augustss static int cmpci_halt_input __P((void *));
144 1.1 augustss static int cmpci_getdev __P((void *, struct audio_device *));
145 1.1 augustss static int cmpci_set_port __P((void *, mixer_ctrl_t *));
146 1.1 augustss static int cmpci_get_port __P((void *, mixer_ctrl_t *));
147 1.1 augustss static int cmpci_query_devinfo __P((void *, mixer_devinfo_t *));
148 1.1 augustss static void *cmpci_allocm __P((void *, int, size_t, int, int));
149 1.1 augustss static void cmpci_freem __P((void *, void *, int));
150 1.1 augustss static size_t cmpci_round_buffersize __P((void *, int, size_t));
151 1.4 simonb static paddr_t cmpci_mappage __P((void *, void *, off_t, int));
152 1.1 augustss static int cmpci_get_props __P((void *));
153 1.1 augustss static int cmpci_trigger_output __P((void *, void *, void *, int,
154 1.7 tshiozak void (*)(void *), void *,
155 1.7 tshiozak struct audio_params *));
156 1.1 augustss static int cmpci_trigger_input __P((void *, void *, void *, int,
157 1.7 tshiozak void (*)(void *), void *,
158 1.7 tshiozak struct audio_params *));
159 1.1 augustss
160 1.1 augustss static struct audio_hw_if cmpci_hw_if = {
161 1.3 gmcgarry cmpci_open, /* open */
162 1.3 gmcgarry cmpci_close, /* close */
163 1.1 augustss NULL, /* drain */
164 1.3 gmcgarry cmpci_query_encoding, /* query_encoding */
165 1.3 gmcgarry cmpci_set_params, /* set_params */
166 1.3 gmcgarry cmpci_round_blocksize, /* round_blocksize */
167 1.1 augustss NULL, /* commit_settings */
168 1.1 augustss NULL, /* init_output */
169 1.1 augustss NULL, /* init_input */
170 1.1 augustss NULL, /* start_output */
171 1.1 augustss NULL, /* start_input */
172 1.3 gmcgarry cmpci_halt_output, /* halt_output */
173 1.3 gmcgarry cmpci_halt_input, /* halt_input */
174 1.1 augustss NULL, /* speaker_ctl */
175 1.3 gmcgarry cmpci_getdev, /* getdev */
176 1.1 augustss NULL, /* setfd */
177 1.3 gmcgarry cmpci_set_port, /* set_port */
178 1.3 gmcgarry cmpci_get_port, /* get_port */
179 1.3 gmcgarry cmpci_query_devinfo, /* query_devinfo */
180 1.3 gmcgarry cmpci_allocm, /* allocm */
181 1.3 gmcgarry cmpci_freem, /* freem */
182 1.3 gmcgarry cmpci_round_buffersize,/* round_buffersize */
183 1.3 gmcgarry cmpci_mappage, /* mappage */
184 1.3 gmcgarry cmpci_get_props, /* get_props */
185 1.3 gmcgarry cmpci_trigger_output, /* trigger_output */
186 1.9 augustss cmpci_trigger_input, /* trigger_input */
187 1.9 augustss NULL, /* dev_ioctl */
188 1.1 augustss };
189 1.1 augustss
190 1.1 augustss
191 1.1 augustss /*
192 1.1 augustss * Low-level HW interface
193 1.1 augustss */
194 1.1 augustss
195 1.1 augustss /* mixer register read/write */
196 1.1 augustss static __inline uint8_t
197 1.1 augustss cmpci_mixerreg_read(sc, no)
198 1.1 augustss struct cmpci_softc *sc;
199 1.1 augustss uint8_t no;
200 1.1 augustss {
201 1.1 augustss uint8_t ret;
202 1.1 augustss
203 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no);
204 1.1 augustss delay(10);
205 1.1 augustss ret = bus_space_read_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA);
206 1.1 augustss delay(10);
207 1.1 augustss return ret;
208 1.1 augustss }
209 1.1 augustss
210 1.1 augustss static __inline void
211 1.1 augustss cmpci_mixerreg_write(sc, no, val)
212 1.1 augustss struct cmpci_softc *sc;
213 1.1 augustss uint8_t no, val;
214 1.1 augustss {
215 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no);
216 1.1 augustss delay(10);
217 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA, val);
218 1.1 augustss delay(10);
219 1.1 augustss }
220 1.1 augustss
221 1.1 augustss
222 1.1 augustss /* register partial write */
223 1.1 augustss static __inline void
224 1.10 itohy cmpci_reg_partial_write_1(sc, no, shift, mask, val)
225 1.10 itohy struct cmpci_softc *sc;
226 1.10 itohy int no, shift;
227 1.10 itohy unsigned mask, val;
228 1.10 itohy {
229 1.10 itohy bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
230 1.10 itohy (val<<shift) |
231 1.10 itohy (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));
232 1.10 itohy delay(10);
233 1.10 itohy }
234 1.10 itohy
235 1.10 itohy static __inline void
236 1.1 augustss cmpci_reg_partial_write_4(sc, no, shift, mask, val)
237 1.1 augustss struct cmpci_softc *sc;
238 1.1 augustss int no, shift;
239 1.1 augustss uint32_t mask, val;
240 1.1 augustss {
241 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
242 1.1 augustss (val<<shift) |
243 1.1 augustss (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));
244 1.1 augustss delay(10);
245 1.1 augustss }
246 1.1 augustss
247 1.1 augustss /* register set/clear bit */
248 1.1 augustss static __inline void
249 1.7 tshiozak cmpci_reg_set_1(sc, no, mask)
250 1.7 tshiozak struct cmpci_softc *sc;
251 1.7 tshiozak int no;
252 1.7 tshiozak uint8_t mask;
253 1.7 tshiozak {
254 1.7 tshiozak bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
255 1.7 tshiozak (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) | mask));
256 1.7 tshiozak delay(10);
257 1.7 tshiozak }
258 1.7 tshiozak
259 1.7 tshiozak static __inline void
260 1.7 tshiozak cmpci_reg_clear_1(sc, no, mask)
261 1.7 tshiozak struct cmpci_softc *sc;
262 1.7 tshiozak int no;
263 1.7 tshiozak uint8_t mask;
264 1.7 tshiozak {
265 1.7 tshiozak bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
266 1.7 tshiozak (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~mask));
267 1.7 tshiozak delay(10);
268 1.7 tshiozak }
269 1.7 tshiozak
270 1.7 tshiozak
271 1.7 tshiozak static __inline void
272 1.1 augustss cmpci_reg_set_4(sc, no, mask)
273 1.1 augustss struct cmpci_softc *sc;
274 1.1 augustss int no;
275 1.1 augustss uint32_t mask;
276 1.1 augustss {
277 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
278 1.7 tshiozak (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) | mask));
279 1.1 augustss delay(10);
280 1.1 augustss }
281 1.1 augustss
282 1.1 augustss static __inline void
283 1.1 augustss cmpci_reg_clear_4(sc, no, mask)
284 1.1 augustss struct cmpci_softc *sc;
285 1.1 augustss int no;
286 1.1 augustss uint32_t mask;
287 1.1 augustss {
288 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
289 1.7 tshiozak (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~mask));
290 1.1 augustss delay(10);
291 1.1 augustss }
292 1.1 augustss
293 1.1 augustss
294 1.1 augustss /* rate */
295 1.6 jdolecek static const struct {
296 1.1 augustss int rate;
297 1.1 augustss int divider;
298 1.1 augustss } cmpci_rate_table[CMPCI_REG_NUMRATE] = {
299 1.1 augustss #define _RATE(n) { n, CMPCI_REG_RATE_ ## n }
300 1.1 augustss _RATE(5512),
301 1.1 augustss _RATE(8000),
302 1.1 augustss _RATE(11025),
303 1.1 augustss _RATE(16000),
304 1.1 augustss _RATE(22050),
305 1.1 augustss _RATE(32000),
306 1.1 augustss _RATE(44100),
307 1.1 augustss _RATE(48000)
308 1.7 tshiozak #undef _RATE
309 1.1 augustss };
310 1.1 augustss
311 1.1 augustss static int
312 1.1 augustss cmpci_rate_to_index(rate)
313 1.1 augustss int rate;
314 1.1 augustss {
315 1.1 augustss int i;
316 1.1 augustss
317 1.1 augustss for (i = 0; i < CMPCI_REG_NUMRATE - 2; i++)
318 1.1 augustss if (rate <=
319 1.1 augustss (cmpci_rate_table[i].rate+cmpci_rate_table[i+1].rate) / 2)
320 1.1 augustss return i;
321 1.1 augustss return i; /* 48000 */
322 1.1 augustss }
323 1.1 augustss
324 1.1 augustss static __inline int
325 1.1 augustss cmpci_index_to_rate(index)
326 1.1 augustss int index;
327 1.1 augustss {
328 1.1 augustss return cmpci_rate_table[index].rate;
329 1.1 augustss }
330 1.1 augustss
331 1.1 augustss static __inline int
332 1.1 augustss cmpci_index_to_divider(index)
333 1.1 augustss int index;
334 1.1 augustss {
335 1.1 augustss return cmpci_rate_table[index].divider;
336 1.1 augustss }
337 1.1 augustss
338 1.1 augustss
339 1.1 augustss /*
340 1.1 augustss * interface to configure the device.
341 1.1 augustss */
342 1.1 augustss
343 1.1 augustss static int
344 1.1 augustss cmpci_match(parent, match, aux)
345 1.1 augustss struct device *parent;
346 1.1 augustss struct cfdata *match;
347 1.1 augustss void *aux;
348 1.1 augustss {
349 1.1 augustss struct pci_attach_args *pa = (struct pci_attach_args *)aux;
350 1.1 augustss
351 1.1 augustss if ( PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMEDIA &&
352 1.1 augustss (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338A ||
353 1.1 augustss PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338B ||
354 1.7 tshiozak PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738 ||
355 1.7 tshiozak PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738B) )
356 1.1 augustss return 1;
357 1.1 augustss
358 1.1 augustss return 0;
359 1.1 augustss }
360 1.1 augustss
361 1.1 augustss static void
362 1.1 augustss cmpci_attach(parent, self, aux)
363 1.1 augustss struct device *parent, *self;
364 1.1 augustss void *aux;
365 1.1 augustss {
366 1.1 augustss struct cmpci_softc *sc = (struct cmpci_softc *)self;
367 1.1 augustss struct pci_attach_args *pa = (struct pci_attach_args *)aux;
368 1.8 itohy struct audio_attach_args aa;
369 1.1 augustss pci_intr_handle_t ih;
370 1.1 augustss char const *strintr;
371 1.7 tshiozak char devinfo[256];
372 1.1 augustss int i, v;
373 1.1 augustss
374 1.7 tshiozak sc->sc_id = pa->pa_id;
375 1.7 tshiozak sc->sc_class = pa->pa_class;
376 1.7 tshiozak pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
377 1.7 tshiozak printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(sc->sc_class));
378 1.7 tshiozak switch (PCI_PRODUCT(sc->sc_id)) {
379 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338A:
380 1.7 tshiozak /*FALLTHROUGH*/
381 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338B:
382 1.7 tshiozak sc->sc_capable = CMPCI_CAP_CMI8338;
383 1.1 augustss break;
384 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8738:
385 1.7 tshiozak /*FALLTHROUGH*/
386 1.7 tshiozak case PCI_PRODUCT_CMEDIA_CMI8738B:
387 1.7 tshiozak sc->sc_capable = CMPCI_CAP_CMI8738;
388 1.1 augustss break;
389 1.1 augustss }
390 1.1 augustss
391 1.2 augustss /* map I/O space */
392 1.1 augustss if (pci_mapreg_map(pa, CMPCI_PCI_IOBASEREG, PCI_MAPREG_TYPE_IO, 0,
393 1.7 tshiozak &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) {
394 1.1 augustss printf("%s: failed to map I/O space\n", sc->sc_dev.dv_xname);
395 1.1 augustss return;
396 1.1 augustss }
397 1.1 augustss
398 1.2 augustss /* interrupt */
399 1.5 sommerfe if (pci_intr_map(pa, &ih)) {
400 1.1 augustss printf("%s: failed to map interrupt\n", sc->sc_dev.dv_xname);
401 1.1 augustss return;
402 1.1 augustss }
403 1.1 augustss strintr = pci_intr_string(pa->pa_pc, ih);
404 1.1 augustss sc->sc_ih=pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, cmpci_intr, sc);
405 1.1 augustss if (sc->sc_ih == NULL) {
406 1.1 augustss printf("%s: failed to establish interrupt",
407 1.1 augustss sc->sc_dev.dv_xname);
408 1.1 augustss if (strintr != NULL)
409 1.1 augustss printf(" at %s", strintr);
410 1.1 augustss printf("\n");
411 1.1 augustss return;
412 1.1 augustss }
413 1.3 gmcgarry printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, strintr);
414 1.1 augustss
415 1.1 augustss sc->sc_dmat = pa->pa_dmat;
416 1.1 augustss
417 1.1 augustss audio_attach_mi(&cmpci_hw_if, sc, &sc->sc_dev);
418 1.1 augustss
419 1.8 itohy /* attach OPL device */
420 1.8 itohy aa.type = AUDIODEV_TYPE_OPL;
421 1.8 itohy aa.hwif = NULL;
422 1.8 itohy aa.hdl = NULL;
423 1.8 itohy (void)config_found(&sc->sc_dev, &aa, audioprint);
424 1.8 itohy
425 1.8 itohy /* attach MPU-401 device */
426 1.8 itohy aa.type = AUDIODEV_TYPE_MPU;
427 1.8 itohy aa.hwif = NULL;
428 1.8 itohy aa.hdl = NULL;
429 1.8 itohy if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
430 1.8 itohy CMPCI_REG_MPU_BASE, CMPCI_REG_MPU_SIZE, &sc->sc_mpu_ioh) == 0)
431 1.8 itohy sc->sc_mpudev = config_found(&sc->sc_dev, &aa, audioprint);
432 1.8 itohy
433 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_RESET, 0);
434 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
435 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
436 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX,
437 1.1 augustss CMPCI_SB16_SW_CD|CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
438 1.1 augustss for (i = 0; i < CMPCI_NDEVS; i++) {
439 1.1 augustss switch(i) {
440 1.10 itohy /*
441 1.10 itohy * CMI8738 defaults are
442 1.10 itohy * master: 0xe0 (0x00 - 0xf8)
443 1.10 itohy * wave, DAC: 0xc0 (0x00 - 0xf8)
444 1.10 itohy * PC speaker: 0x80 (0x00 - 0xc0)
445 1.10 itohy * others: 0
446 1.10 itohy */
447 1.10 itohy /* volume */
448 1.8 itohy case CMPCI_MASTER_VOL:
449 1.10 itohy v = 128; /* 224 */
450 1.10 itohy break;
451 1.8 itohy case CMPCI_FM_VOL:
452 1.10 itohy case CMPCI_DAC_VOL:
453 1.10 itohy v = 192;
454 1.10 itohy break;
455 1.8 itohy case CMPCI_PCSPEAKER:
456 1.10 itohy v = 128;
457 1.1 augustss break;
458 1.8 itohy
459 1.8 itohy /* booleans, set to true */
460 1.10 itohy case CMPCI_CD_MUTE:
461 1.10 itohy case CMPCI_MIC_MUTE:
462 1.10 itohy case CMPCI_LINE_IN_MUTE:
463 1.10 itohy case CMPCI_AUX_IN_MUTE:
464 1.8 itohy v = 1;
465 1.1 augustss break;
466 1.10 itohy
467 1.10 itohy /* volume with inital value 0 */
468 1.10 itohy case CMPCI_CD_VOL:
469 1.10 itohy case CMPCI_LINE_IN_VOL:
470 1.10 itohy case CMPCI_AUX_IN_VOL:
471 1.10 itohy case CMPCI_MIC_VOL:
472 1.10 itohy case CMPCI_MIC_RECVOL:
473 1.10 itohy /* FALLTHROUGH */
474 1.10 itohy
475 1.8 itohy /* others are cleared */
476 1.10 itohy case CMPCI_MIC_PREAMP:
477 1.8 itohy case CMPCI_RECORD_SOURCE:
478 1.10 itohy case CMPCI_PLAYBACK_MODE:
479 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
480 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
481 1.7 tshiozak case CMPCI_SPDIF_LOOP:
482 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
483 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
484 1.10 itohy case CMPCI_MONITOR_DAC:
485 1.7 tshiozak case CMPCI_REAR:
486 1.7 tshiozak case CMPCI_INDIVIDUAL:
487 1.7 tshiozak case CMPCI_REVERSE:
488 1.7 tshiozak case CMPCI_SURROUND:
489 1.8 itohy default:
490 1.1 augustss v = 0;
491 1.1 augustss break;
492 1.1 augustss }
493 1.7 tshiozak sc->sc_gain[i][CMPCI_LEFT] = sc->sc_gain[i][CMPCI_RIGHT] = v;
494 1.1 augustss cmpci_set_mixer_gain(sc, i);
495 1.1 augustss }
496 1.1 augustss }
497 1.1 augustss
498 1.1 augustss
499 1.1 augustss static int
500 1.1 augustss cmpci_intr(handle)
501 1.1 augustss void *handle;
502 1.1 augustss {
503 1.1 augustss struct cmpci_softc *sc = handle;
504 1.1 augustss uint32_t intrstat;
505 1.1 augustss
506 1.1 augustss intrstat = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
507 1.1 augustss CMPCI_REG_INTR_STATUS);
508 1.1 augustss
509 1.1 augustss if (!(intrstat & CMPCI_REG_ANY_INTR))
510 1.1 augustss return 0;
511 1.1 augustss
512 1.8 itohy delay(10);
513 1.8 itohy
514 1.1 augustss /* disable and reset intr */
515 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR)
516 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL,
517 1.1 augustss CMPCI_REG_CH0_INTR_ENABLE);
518 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR)
519 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL,
520 1.1 augustss CMPCI_REG_CH1_INTR_ENABLE);
521 1.1 augustss
522 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR) {
523 1.1 augustss if (sc->sc_play.intr != NULL)
524 1.1 augustss (*sc->sc_play.intr)(sc->sc_play.intr_arg);
525 1.1 augustss }
526 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR) {
527 1.1 augustss if (sc->sc_rec.intr != NULL)
528 1.1 augustss (*sc->sc_rec.intr)(sc->sc_rec.intr_arg);
529 1.1 augustss }
530 1.1 augustss
531 1.1 augustss /* enable intr */
532 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR)
533 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL,
534 1.1 augustss CMPCI_REG_CH0_INTR_ENABLE);
535 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR)
536 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL,
537 1.1 augustss CMPCI_REG_CH1_INTR_ENABLE);
538 1.8 itohy
539 1.8 itohy #if NMPU > 0
540 1.8 itohy if (intrstat & CMPCI_REG_UART_INTR && sc->sc_mpudev != NULL)
541 1.8 itohy mpu_intr(sc->sc_mpudev);
542 1.8 itohy #endif
543 1.8 itohy
544 1.8 itohy return 1;
545 1.1 augustss }
546 1.1 augustss
547 1.1 augustss
548 1.1 augustss /* open/close */
549 1.1 augustss static int
550 1.1 augustss cmpci_open(handle, flags)
551 1.1 augustss void *handle;
552 1.1 augustss int flags;
553 1.1 augustss {
554 1.1 augustss return 0;
555 1.1 augustss }
556 1.1 augustss
557 1.1 augustss static void
558 1.1 augustss cmpci_close(handle)
559 1.1 augustss void *handle;
560 1.1 augustss {
561 1.1 augustss }
562 1.1 augustss
563 1.1 augustss static int
564 1.1 augustss cmpci_query_encoding(handle, fp)
565 1.1 augustss void *handle;
566 1.1 augustss struct audio_encoding *fp;
567 1.1 augustss {
568 1.1 augustss switch (fp->index) {
569 1.1 augustss case 0:
570 1.1 augustss strcpy(fp->name, AudioEulinear);
571 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR;
572 1.1 augustss fp->precision = 8;
573 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
574 1.1 augustss break;
575 1.1 augustss case 1:
576 1.1 augustss strcpy(fp->name, AudioEmulaw);
577 1.1 augustss fp->encoding = AUDIO_ENCODING_ULAW;
578 1.1 augustss fp->precision = 8;
579 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
580 1.1 augustss break;
581 1.1 augustss case 2:
582 1.1 augustss strcpy(fp->name, AudioEalaw);
583 1.1 augustss fp->encoding = AUDIO_ENCODING_ALAW;
584 1.1 augustss fp->precision = 8;
585 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
586 1.1 augustss break;
587 1.1 augustss case 3:
588 1.1 augustss strcpy(fp->name, AudioEslinear);
589 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR;
590 1.1 augustss fp->precision = 8;
591 1.1 augustss fp->flags = 0;
592 1.1 augustss break;
593 1.1 augustss case 4:
594 1.1 augustss strcpy(fp->name, AudioEslinear_le);
595 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR_LE;
596 1.1 augustss fp->precision = 16;
597 1.1 augustss fp->flags = 0;
598 1.1 augustss break;
599 1.1 augustss case 5:
600 1.1 augustss strcpy(fp->name, AudioEulinear_le);
601 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR_LE;
602 1.1 augustss fp->precision = 16;
603 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
604 1.1 augustss break;
605 1.1 augustss case 6:
606 1.1 augustss strcpy(fp->name, AudioEslinear_be);
607 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR_BE;
608 1.1 augustss fp->precision = 16;
609 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
610 1.1 augustss break;
611 1.1 augustss case 7:
612 1.1 augustss strcpy(fp->name, AudioEulinear_be);
613 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR_BE;
614 1.1 augustss fp->precision = 16;
615 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
616 1.1 augustss break;
617 1.1 augustss default:
618 1.1 augustss return EINVAL;
619 1.1 augustss }
620 1.1 augustss return 0;
621 1.1 augustss }
622 1.1 augustss
623 1.1 augustss
624 1.1 augustss static int
625 1.1 augustss cmpci_set_params(handle, setmode, usemode, play, rec)
626 1.1 augustss void *handle;
627 1.1 augustss int setmode, usemode;
628 1.1 augustss struct audio_params *play, *rec;
629 1.1 augustss {
630 1.1 augustss int i;
631 1.1 augustss struct cmpci_softc *sc = handle;
632 1.1 augustss
633 1.1 augustss for (i = 0; i < 2; i++) {
634 1.1 augustss int md_format;
635 1.1 augustss int md_divide;
636 1.1 augustss int md_index;
637 1.1 augustss int mode;
638 1.1 augustss struct audio_params *p;
639 1.10 itohy
640 1.1 augustss switch (i) {
641 1.1 augustss case 0:
642 1.1 augustss mode = AUMODE_PLAY;
643 1.1 augustss p = play;
644 1.1 augustss break;
645 1.1 augustss case 1:
646 1.1 augustss mode = AUMODE_RECORD;
647 1.1 augustss p = rec;
648 1.1 augustss break;
649 1.1 augustss }
650 1.10 itohy
651 1.1 augustss if (!(setmode & mode))
652 1.1 augustss continue;
653 1.1 augustss
654 1.1 augustss
655 1.1 augustss /* format */
656 1.1 augustss p->sw_code = NULL;
657 1.1 augustss switch ( p->channels ) {
658 1.1 augustss case 1:
659 1.1 augustss md_format = CMPCI_REG_FORMAT_MONO;
660 1.1 augustss break;
661 1.1 augustss case 2:
662 1.1 augustss md_format = CMPCI_REG_FORMAT_STEREO;
663 1.1 augustss break;
664 1.1 augustss default:
665 1.1 augustss return (EINVAL);
666 1.1 augustss }
667 1.1 augustss switch (p->encoding) {
668 1.1 augustss case AUDIO_ENCODING_ULAW:
669 1.1 augustss if (p->precision != 8)
670 1.1 augustss return (EINVAL);
671 1.1 augustss if (mode & AUMODE_PLAY) {
672 1.1 augustss p->factor = 2;
673 1.1 augustss p->sw_code = mulaw_to_slinear16_le;
674 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
675 1.1 augustss } else {
676 1.1 augustss p->sw_code = ulinear8_to_mulaw;
677 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
678 1.1 augustss }
679 1.1 augustss break;
680 1.1 augustss case AUDIO_ENCODING_ALAW:
681 1.1 augustss if (p->precision != 8)
682 1.1 augustss return (EINVAL);
683 1.1 augustss if (mode & AUMODE_PLAY) {
684 1.1 augustss p->factor = 2;
685 1.1 augustss p->sw_code = alaw_to_slinear16_le;
686 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
687 1.1 augustss } else {
688 1.1 augustss p->sw_code = ulinear8_to_alaw;
689 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
690 1.1 augustss }
691 1.1 augustss break;
692 1.1 augustss case AUDIO_ENCODING_SLINEAR_LE:
693 1.1 augustss switch (p->precision) {
694 1.1 augustss case 8:
695 1.1 augustss p->sw_code = change_sign8;
696 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
697 1.1 augustss break;
698 1.1 augustss case 16:
699 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
700 1.1 augustss break;
701 1.1 augustss default:
702 1.1 augustss return (EINVAL);
703 1.1 augustss }
704 1.1 augustss break;
705 1.1 augustss case AUDIO_ENCODING_SLINEAR_BE:
706 1.1 augustss switch (p->precision) {
707 1.1 augustss case 8:
708 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
709 1.1 augustss p->sw_code = change_sign8;
710 1.1 augustss break;
711 1.1 augustss case 16:
712 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
713 1.1 augustss p->sw_code = swap_bytes;
714 1.1 augustss break;
715 1.1 augustss default:
716 1.1 augustss return (EINVAL);
717 1.1 augustss }
718 1.1 augustss break;
719 1.1 augustss case AUDIO_ENCODING_ULINEAR_LE:
720 1.1 augustss switch (p->precision) {
721 1.1 augustss case 8:
722 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
723 1.1 augustss break;
724 1.1 augustss case 16:
725 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
726 1.1 augustss p->sw_code = change_sign16_le;
727 1.1 augustss break;
728 1.1 augustss default:
729 1.1 augustss return (EINVAL);
730 1.1 augustss }
731 1.1 augustss break;
732 1.1 augustss case AUDIO_ENCODING_ULINEAR_BE:
733 1.1 augustss switch (p->precision) {
734 1.1 augustss case 8:
735 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
736 1.1 augustss break;
737 1.1 augustss case 16:
738 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
739 1.1 augustss if (mode & AUMODE_PLAY)
740 1.7 tshiozak p->sw_code =
741 1.7 tshiozak swap_bytes_change_sign16_le;
742 1.1 augustss else
743 1.7 tshiozak p->sw_code =
744 1.7 tshiozak change_sign16_swap_bytes_le;
745 1.1 augustss break;
746 1.1 augustss default:
747 1.1 augustss return (EINVAL);
748 1.1 augustss }
749 1.1 augustss break;
750 1.1 augustss default:
751 1.1 augustss return (EINVAL);
752 1.1 augustss }
753 1.1 augustss if (mode & AUMODE_PLAY)
754 1.1 augustss cmpci_reg_partial_write_4(sc,
755 1.7 tshiozak CMPCI_REG_CHANNEL_FORMAT,
756 1.7 tshiozak CMPCI_REG_CH0_FORMAT_SHIFT,
757 1.7 tshiozak CMPCI_REG_CH0_FORMAT_MASK, md_format);
758 1.1 augustss else
759 1.1 augustss cmpci_reg_partial_write_4(sc,
760 1.7 tshiozak CMPCI_REG_CHANNEL_FORMAT,
761 1.7 tshiozak CMPCI_REG_CH1_FORMAT_SHIFT,
762 1.1 augustss CMPCI_REG_CH1_FORMAT_MASK, md_format);
763 1.1 augustss /* sample rate */
764 1.1 augustss md_index = cmpci_rate_to_index(p->sample_rate);
765 1.1 augustss md_divide = cmpci_index_to_divider(md_index);
766 1.1 augustss p->sample_rate = cmpci_index_to_rate(md_index);
767 1.1 augustss DPRINTF(("%s: sample:%d, divider=%d\n",
768 1.1 augustss sc->sc_dev.dv_xname, (int)p->sample_rate, md_divide));
769 1.1 augustss if (mode & AUMODE_PLAY) {
770 1.1 augustss cmpci_reg_partial_write_4(sc,
771 1.1 augustss CMPCI_REG_FUNC_1, CMPCI_REG_DAC_FS_SHIFT,
772 1.1 augustss CMPCI_REG_DAC_FS_MASK, md_divide);
773 1.7 tshiozak sc->sc_play.md_divide = md_divide;
774 1.1 augustss } else {
775 1.1 augustss cmpci_reg_partial_write_4(sc,
776 1.1 augustss CMPCI_REG_FUNC_1, CMPCI_REG_ADC_FS_SHIFT,
777 1.1 augustss CMPCI_REG_ADC_FS_MASK, md_divide);
778 1.7 tshiozak sc->sc_rec.md_divide = md_divide;
779 1.1 augustss }
780 1.10 itohy cmpci_set_out_ports(sc);
781 1.10 itohy cmpci_set_in_ports(sc);
782 1.1 augustss }
783 1.1 augustss return 0;
784 1.1 augustss }
785 1.1 augustss
786 1.1 augustss /* ARGSUSED */
787 1.1 augustss static int
788 1.1 augustss cmpci_round_blocksize(handle, block)
789 1.1 augustss void *handle;
790 1.1 augustss int block;
791 1.1 augustss {
792 1.1 augustss return (block & -4);
793 1.1 augustss }
794 1.1 augustss
795 1.1 augustss static int
796 1.1 augustss cmpci_halt_output(handle)
797 1.1 augustss void *handle;
798 1.1 augustss {
799 1.1 augustss struct cmpci_softc *sc = handle;
800 1.1 augustss int s;
801 1.1 augustss
802 1.1 augustss s = splaudio();
803 1.1 augustss sc->sc_play.intr = NULL;
804 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
805 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
806 1.1 augustss /* wait for reset DMA */
807 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
808 1.1 augustss delay(10);
809 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
810 1.1 augustss splx(s);
811 1.10 itohy
812 1.1 augustss return 0;
813 1.1 augustss }
814 1.1 augustss
815 1.1 augustss static int
816 1.1 augustss cmpci_halt_input(handle)
817 1.1 augustss void *handle;
818 1.1 augustss {
819 1.1 augustss struct cmpci_softc *sc = handle;
820 1.1 augustss int s;
821 1.10 itohy
822 1.1 augustss s = splaudio();
823 1.1 augustss sc->sc_rec.intr = NULL;
824 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
825 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
826 1.1 augustss /* wait for reset DMA */
827 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
828 1.1 augustss delay(10);
829 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
830 1.1 augustss splx(s);
831 1.10 itohy
832 1.1 augustss return 0;
833 1.1 augustss }
834 1.1 augustss
835 1.1 augustss
836 1.1 augustss /* get audio device information */
837 1.1 augustss static int
838 1.1 augustss cmpci_getdev(handle, ad)
839 1.7 tshiozak void *handle;
840 1.7 tshiozak struct audio_device *ad;
841 1.1 augustss {
842 1.1 augustss struct cmpci_softc *sc = handle;
843 1.1 augustss
844 1.1 augustss strncpy(ad->name, "CMI PCI Audio", sizeof(ad->name));
845 1.7 tshiozak snprintf(ad->version, sizeof(ad->version), "0x%02x",
846 1.7 tshiozak PCI_REVISION(sc->sc_class));
847 1.7 tshiozak switch (PCI_PRODUCT(sc->sc_id)) {
848 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338A:
849 1.1 augustss strncpy(ad->config, "CMI8338A", sizeof(ad->config));
850 1.1 augustss break;
851 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338B:
852 1.1 augustss strncpy(ad->config, "CMI8338B", sizeof(ad->config));
853 1.1 augustss break;
854 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8738:
855 1.1 augustss strncpy(ad->config, "CMI8738", sizeof(ad->config));
856 1.1 augustss break;
857 1.7 tshiozak case PCI_PRODUCT_CMEDIA_CMI8738B:
858 1.7 tshiozak strncpy(ad->config, "CMI8738B", sizeof(ad->config));
859 1.7 tshiozak break;
860 1.1 augustss default:
861 1.1 augustss strncpy(ad->config, "unknown", sizeof(ad->config));
862 1.1 augustss }
863 1.1 augustss
864 1.1 augustss return 0;
865 1.1 augustss }
866 1.1 augustss
867 1.1 augustss
868 1.1 augustss /* mixer device information */
869 1.1 augustss int
870 1.1 augustss cmpci_query_devinfo(handle, dip)
871 1.1 augustss void *handle;
872 1.1 augustss mixer_devinfo_t *dip;
873 1.1 augustss {
874 1.10 itohy static const char *const mixer_port_names[] = {
875 1.10 itohy AudioNdac, AudioNfmsynth, AudioNcd, AudioNline, AudioNaux,
876 1.10 itohy AudioNmicrophone
877 1.10 itohy };
878 1.10 itohy static const char *const mixer_classes[] = {
879 1.10 itohy AudioCinputs, AudioCoutputs, AudioCrecord, CmpciCplayback,
880 1.10 itohy CmpciCspdif
881 1.10 itohy };
882 1.10 itohy struct cmpci_softc *sc = handle;
883 1.10 itohy int i;
884 1.10 itohy
885 1.10 itohy dip->prev = dip->next = AUDIO_MIXER_LAST;
886 1.10 itohy
887 1.1 augustss switch (dip->index) {
888 1.10 itohy case CMPCI_INPUT_CLASS:
889 1.10 itohy case CMPCI_OUTPUT_CLASS:
890 1.10 itohy case CMPCI_RECORD_CLASS:
891 1.10 itohy case CMPCI_PLAYBACK_CLASS:
892 1.10 itohy case CMPCI_SPDIF_CLASS:
893 1.10 itohy dip->type = AUDIO_MIXER_CLASS;
894 1.10 itohy dip->mixer_class = dip->index;
895 1.10 itohy strcpy(dip->label.name,
896 1.10 itohy mixer_classes[dip->index - CMPCI_INPUT_CLASS]);
897 1.1 augustss return 0;
898 1.10 itohy
899 1.10 itohy case CMPCI_AUX_IN_VOL:
900 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_REG_AUX_VALBITS);
901 1.10 itohy goto vol1;
902 1.10 itohy case CMPCI_DAC_VOL:
903 1.1 augustss case CMPCI_FM_VOL:
904 1.10 itohy case CMPCI_CD_VOL:
905 1.10 itohy case CMPCI_LINE_IN_VOL:
906 1.10 itohy case CMPCI_MIC_VOL:
907 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS);
908 1.10 itohy vol1: dip->mixer_class = CMPCI_INPUT_CLASS;
909 1.10 itohy dip->next = dip->index + 6; /* CMPCI_xxx_MUTE */
910 1.10 itohy strcpy(dip->label.name, mixer_port_names[dip->index]);
911 1.10 itohy dip->un.v.num_channels = (dip->index == CMPCI_MIC_VOL ? 1 : 2);
912 1.10 itohy vol:
913 1.1 augustss dip->type = AUDIO_MIXER_VALUE;
914 1.1 augustss strcpy(dip->un.v.units.name, AudioNvolume);
915 1.1 augustss return 0;
916 1.10 itohy
917 1.10 itohy case CMPCI_MIC_MUTE:
918 1.10 itohy dip->next = CMPCI_MIC_PREAMP;
919 1.10 itohy /* FALLTHROUGH */
920 1.10 itohy case CMPCI_DAC_MUTE:
921 1.10 itohy case CMPCI_FM_MUTE:
922 1.10 itohy case CMPCI_CD_MUTE:
923 1.10 itohy case CMPCI_LINE_IN_MUTE:
924 1.10 itohy case CMPCI_AUX_IN_MUTE:
925 1.10 itohy dip->prev = dip->index - 6; /* CMPCI_xxx_VOL */
926 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
927 1.10 itohy strcpy(dip->label.name, AudioNmute);
928 1.10 itohy goto on_off;
929 1.10 itohy on_off:
930 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
931 1.10 itohy dip->un.e.num_mem = 2;
932 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNoff);
933 1.10 itohy dip->un.e.member[0].ord = 0;
934 1.10 itohy strcpy(dip->un.e.member[1].label.name, AudioNon);
935 1.10 itohy dip->un.e.member[1].ord = 1;
936 1.1 augustss return 0;
937 1.10 itohy
938 1.10 itohy case CMPCI_MIC_PREAMP:
939 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
940 1.10 itohy dip->prev = CMPCI_MIC_MUTE;
941 1.10 itohy strcpy(dip->label.name, AudioNpreamp);
942 1.10 itohy goto on_off;
943 1.10 itohy case CMPCI_PCSPEAKER:
944 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
945 1.10 itohy strcpy(dip->label.name, AudioNspeaker);
946 1.1 augustss dip->un.v.num_channels = 1;
947 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_SPEAKER_VALBITS);
948 1.10 itohy goto vol;
949 1.1 augustss case CMPCI_RECORD_SOURCE:
950 1.1 augustss dip->mixer_class = CMPCI_RECORD_CLASS;
951 1.1 augustss strcpy(dip->label.name, AudioNsource);
952 1.1 augustss dip->type = AUDIO_MIXER_SET;
953 1.10 itohy dip->un.s.num_mem = 7;
954 1.1 augustss strcpy(dip->un.s.member[0].label.name, AudioNmicrophone);
955 1.8 itohy dip->un.s.member[0].mask = CMPCI_RECORD_SOURCE_MIC;
956 1.1 augustss strcpy(dip->un.s.member[1].label.name, AudioNcd);
957 1.8 itohy dip->un.s.member[1].mask = CMPCI_RECORD_SOURCE_CD;
958 1.1 augustss strcpy(dip->un.s.member[2].label.name, AudioNline);
959 1.8 itohy dip->un.s.member[2].mask = CMPCI_RECORD_SOURCE_LINE_IN;
960 1.10 itohy strcpy(dip->un.s.member[3].label.name, AudioNaux);
961 1.10 itohy dip->un.s.member[3].mask = CMPCI_RECORD_SOURCE_AUX_IN;
962 1.10 itohy strcpy(dip->un.s.member[4].label.name, AudioNwave);
963 1.10 itohy dip->un.s.member[4].mask = CMPCI_RECORD_SOURCE_WAVE;
964 1.10 itohy strcpy(dip->un.s.member[5].label.name, AudioNfmsynth);
965 1.10 itohy dip->un.s.member[5].mask = CMPCI_RECORD_SOURCE_FM;
966 1.10 itohy strcpy(dip->un.s.member[6].label.name, CmpciNspdif);
967 1.10 itohy dip->un.s.member[6].mask = CMPCI_RECORD_SOURCE_SPDIF;
968 1.1 augustss return 0;
969 1.10 itohy case CMPCI_MIC_RECVOL:
970 1.1 augustss dip->mixer_class = CMPCI_RECORD_CLASS;
971 1.10 itohy strcpy(dip->label.name, AudioNmicrophone);
972 1.1 augustss dip->un.v.num_channels = 1;
973 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_REG_ADMIC_VALBITS);
974 1.10 itohy goto vol;
975 1.10 itohy
976 1.10 itohy case CMPCI_PLAYBACK_MODE:
977 1.10 itohy dip->mixer_class = CMPCI_PLAYBACK_CLASS;
978 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
979 1.10 itohy strcpy(dip->label.name, AudioNmode);
980 1.10 itohy dip->un.e.num_mem = 2;
981 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNdac);
982 1.10 itohy dip->un.e.member[0].ord = CMPCI_PLAYBACK_MODE_WAVE;
983 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdif);
984 1.10 itohy dip->un.e.member[1].ord = CMPCI_PLAYBACK_MODE_SPDIF;
985 1.1 augustss return 0;
986 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
987 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
988 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
989 1.10 itohy dip->next = CMPCI_SPDIF_IN_PHASE;
990 1.1 augustss strcpy(dip->label.name, AudioNinput);
991 1.10 itohy i = 0;
992 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdin1);
993 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN1;
994 1.10 itohy if (CMPCI_ISCAP(sc, 2ND_SPDIN)) {
995 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdin2);
996 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN2;
997 1.10 itohy }
998 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdout);
999 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDOUT;
1000 1.10 itohy dip->un.e.num_mem = i;
1001 1.10 itohy return 0;
1002 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
1003 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
1004 1.10 itohy dip->prev = CMPCI_SPDIF_IN_SELECT;
1005 1.10 itohy strcpy(dip->label.name, CmpciNphase);
1006 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
1007 1.10 itohy dip->un.e.num_mem = 2;
1008 1.10 itohy strcpy(dip->un.e.member[0].label.name, CmpciNpositive);
1009 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_IN_PHASE_POSITIVE;
1010 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNnegative);
1011 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_IN_PHASE_NEGATIVE;
1012 1.1 augustss return 0;
1013 1.10 itohy case CMPCI_SPDIF_LOOP:
1014 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
1015 1.10 itohy dip->next = CMPCI_SPDIF_OUT_PLAYBACK;
1016 1.1 augustss strcpy(dip->label.name, AudioNoutput);
1017 1.1 augustss dip->type = AUDIO_MIXER_ENUM;
1018 1.10 itohy dip->un.e.num_mem = 2;
1019 1.10 itohy strcpy(dip->un.e.member[0].label.name, CmpciNplayback);
1020 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_LOOP_OFF;
1021 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdin);
1022 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_LOOP_ON;
1023 1.7 tshiozak return 0;
1024 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1025 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
1026 1.10 itohy dip->prev = CMPCI_SPDIF_LOOP;
1027 1.10 itohy dip->next = CMPCI_SPDIF_OUT_VOLTAGE;
1028 1.10 itohy strcpy(dip->label.name, CmpciNplayback);
1029 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
1030 1.10 itohy dip->un.e.num_mem = 2;
1031 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNwave);
1032 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_PLAYBACK_WAVE;
1033 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNlegacy);
1034 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_PLAYBACK_LEGACY;
1035 1.7 tshiozak return 0;
1036 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1037 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
1038 1.10 itohy dip->prev = CMPCI_SPDIF_OUT_PLAYBACK;
1039 1.10 itohy strcpy(dip->label.name, CmpciNvoltage);
1040 1.7 tshiozak dip->type = AUDIO_MIXER_ENUM;
1041 1.7 tshiozak dip->un.e.num_mem = 2;
1042 1.7 tshiozak strcpy(dip->un.e.member[0].label.name, CmpciNlow_v);
1043 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_VOLTAGE_LOW;
1044 1.7 tshiozak strcpy(dip->un.e.member[1].label.name, CmpciNhigh_v);
1045 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_VOLTAGE_HIGH;
1046 1.7 tshiozak return 0;
1047 1.10 itohy case CMPCI_MONITOR_DAC:
1048 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
1049 1.10 itohy strcpy(dip->label.name, AudioNmonitor);
1050 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
1051 1.10 itohy dip->un.e.num_mem = 3;
1052 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNoff);
1053 1.10 itohy dip->un.e.member[0].ord = CMPCI_MONITOR_DAC_OFF;
1054 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdin);
1055 1.10 itohy dip->un.e.member[1].ord = CMPCI_MONITOR_DAC_SPDIN;
1056 1.10 itohy strcpy(dip->un.e.member[2].label.name, CmpciNspdout);
1057 1.10 itohy dip->un.e.member[2].ord = CMPCI_MONITOR_DAC_SPDOUT;
1058 1.10 itohy return 0;
1059 1.10 itohy
1060 1.10 itohy case CMPCI_MASTER_VOL:
1061 1.10 itohy dip->mixer_class = CMPCI_OUTPUT_CLASS;
1062 1.10 itohy strcpy(dip->label.name, AudioNmaster);
1063 1.10 itohy dip->un.v.num_channels = 2;
1064 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS);
1065 1.10 itohy goto vol;
1066 1.7 tshiozak case CMPCI_REAR:
1067 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1068 1.7 tshiozak dip->next = CMPCI_INDIVIDUAL;
1069 1.7 tshiozak strcpy(dip->label.name, CmpciNrear);
1070 1.7 tshiozak goto on_off;
1071 1.7 tshiozak case CMPCI_INDIVIDUAL:
1072 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1073 1.7 tshiozak dip->prev = CMPCI_REAR;
1074 1.7 tshiozak dip->next = CMPCI_REVERSE;
1075 1.7 tshiozak strcpy(dip->label.name, CmpciNindividual);
1076 1.7 tshiozak goto on_off;
1077 1.7 tshiozak case CMPCI_REVERSE:
1078 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1079 1.7 tshiozak dip->prev = CMPCI_INDIVIDUAL;
1080 1.7 tshiozak strcpy(dip->label.name, CmpciNreverse);
1081 1.10 itohy goto on_off;
1082 1.7 tshiozak case CMPCI_SURROUND:
1083 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1084 1.7 tshiozak strcpy(dip->label.name, CmpciNsurround);
1085 1.7 tshiozak goto on_off;
1086 1.10 itohy }
1087 1.7 tshiozak
1088 1.1 augustss return ENXIO;
1089 1.1 augustss }
1090 1.1 augustss
1091 1.1 augustss static int
1092 1.1 augustss cmpci_alloc_dmamem(sc, size, type, flags, r_addr)
1093 1.1 augustss struct cmpci_softc *sc;
1094 1.1 augustss size_t size;
1095 1.1 augustss int type, flags;
1096 1.1 augustss caddr_t *r_addr;
1097 1.1 augustss {
1098 1.1 augustss int error = 0;
1099 1.1 augustss struct cmpci_dmanode *n;
1100 1.1 augustss int w;
1101 1.1 augustss
1102 1.1 augustss n = malloc(sizeof(struct cmpci_dmanode), type, flags);
1103 1.1 augustss if (n == NULL) {
1104 1.1 augustss error = ENOMEM;
1105 1.1 augustss goto quit;
1106 1.1 augustss }
1107 1.1 augustss
1108 1.1 augustss w = (flags & M_NOWAIT) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK;
1109 1.1 augustss #define CMPCI_DMABUF_ALIGN 0x4
1110 1.1 augustss #define CMPCI_DMABUF_BOUNDARY 0x0
1111 1.1 augustss n->cd_tag = sc->sc_dmat;
1112 1.1 augustss n->cd_size = size;
1113 1.1 augustss error = bus_dmamem_alloc(n->cd_tag, n->cd_size,
1114 1.1 augustss CMPCI_DMABUF_ALIGN, CMPCI_DMABUF_BOUNDARY, n->cd_segs,
1115 1.7 tshiozak sizeof(n->cd_segs)/sizeof(n->cd_segs[0]), &n->cd_nsegs, w);
1116 1.1 augustss if (error)
1117 1.1 augustss goto mfree;
1118 1.1 augustss error = bus_dmamem_map(n->cd_tag, n->cd_segs, n->cd_nsegs, n->cd_size,
1119 1.1 augustss &n->cd_addr, w | BUS_DMA_COHERENT);
1120 1.1 augustss if (error)
1121 1.1 augustss goto dmafree;
1122 1.1 augustss error = bus_dmamap_create(n->cd_tag, n->cd_size, 1, n->cd_size, 0,
1123 1.1 augustss w, &n->cd_map);
1124 1.1 augustss if (error)
1125 1.1 augustss goto unmap;
1126 1.1 augustss error = bus_dmamap_load(n->cd_tag, n->cd_map, n->cd_addr, n->cd_size,
1127 1.1 augustss NULL, w);
1128 1.1 augustss if (error)
1129 1.1 augustss goto destroy;
1130 1.10 itohy
1131 1.1 augustss n->cd_next = sc->sc_dmap;
1132 1.1 augustss sc->sc_dmap = n;
1133 1.1 augustss *r_addr = KVADDR(n);
1134 1.1 augustss return 0;
1135 1.10 itohy
1136 1.1 augustss destroy:
1137 1.1 augustss bus_dmamap_destroy(n->cd_tag, n->cd_map);
1138 1.1 augustss unmap:
1139 1.1 augustss bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size);
1140 1.1 augustss dmafree:
1141 1.1 augustss bus_dmamem_free(n->cd_tag,
1142 1.1 augustss n->cd_segs, sizeof(n->cd_segs)/sizeof(n->cd_segs[0]));
1143 1.1 augustss mfree:
1144 1.1 augustss free(n, type);
1145 1.1 augustss quit:
1146 1.1 augustss return error;
1147 1.1 augustss }
1148 1.1 augustss
1149 1.1 augustss static int
1150 1.1 augustss cmpci_free_dmamem(sc, addr, type)
1151 1.1 augustss struct cmpci_softc *sc;
1152 1.1 augustss caddr_t addr;
1153 1.1 augustss int type;
1154 1.1 augustss {
1155 1.1 augustss struct cmpci_dmanode **nnp;
1156 1.10 itohy
1157 1.1 augustss for (nnp = &sc->sc_dmap; *nnp; nnp= &(*nnp)->cd_next) {
1158 1.1 augustss if ((*nnp)->cd_addr == addr) {
1159 1.1 augustss struct cmpci_dmanode *n = *nnp;
1160 1.1 augustss bus_dmamap_unload(n->cd_tag, n->cd_map);
1161 1.1 augustss bus_dmamap_destroy(n->cd_tag, n->cd_map);
1162 1.1 augustss bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size);
1163 1.1 augustss bus_dmamem_free(n->cd_tag, n->cd_segs,
1164 1.1 augustss sizeof(n->cd_segs)/sizeof(n->cd_segs[0]));
1165 1.1 augustss free(n, type);
1166 1.1 augustss return 0;
1167 1.1 augustss }
1168 1.1 augustss }
1169 1.1 augustss return -1;
1170 1.1 augustss }
1171 1.1 augustss
1172 1.1 augustss static struct cmpci_dmanode *
1173 1.1 augustss cmpci_find_dmamem(sc, addr)
1174 1.1 augustss struct cmpci_softc *sc;
1175 1.1 augustss caddr_t addr;
1176 1.1 augustss {
1177 1.1 augustss struct cmpci_dmanode *p;
1178 1.10 itohy
1179 1.1 augustss for (p=sc->sc_dmap; p; p=p->cd_next)
1180 1.1 augustss if ( KVADDR(p) == (void *)addr )
1181 1.1 augustss break;
1182 1.1 augustss return p;
1183 1.1 augustss }
1184 1.1 augustss
1185 1.1 augustss
1186 1.1 augustss #if 0
1187 1.1 augustss static void
1188 1.1 augustss cmpci_print_dmamem __P((struct cmpci_dmanode *p));
1189 1.1 augustss static void
1190 1.1 augustss cmpci_print_dmamem(p)
1191 1.1 augustss struct cmpci_dmanode *p;
1192 1.1 augustss {
1193 1.1 augustss DPRINTF(("DMA at virt:%p, dmaseg:%p, mapseg:%p, size:%p\n",
1194 1.1 augustss (void *)p->cd_addr, (void *)p->cd_segs[0].ds_addr,
1195 1.1 augustss (void *)DMAADDR(p), (void *)p->cd_size));
1196 1.1 augustss }
1197 1.1 augustss #endif /* DEBUG */
1198 1.1 augustss
1199 1.1 augustss
1200 1.1 augustss static void *
1201 1.1 augustss cmpci_allocm(handle, direction, size, type, flags)
1202 1.1 augustss void *handle;
1203 1.1 augustss int direction;
1204 1.1 augustss size_t size;
1205 1.1 augustss int type, flags;
1206 1.1 augustss {
1207 1.1 augustss struct cmpci_softc *sc = handle;
1208 1.1 augustss caddr_t addr;
1209 1.10 itohy
1210 1.1 augustss if (cmpci_alloc_dmamem(sc, size, type, flags, &addr))
1211 1.1 augustss return NULL;
1212 1.1 augustss return addr;
1213 1.1 augustss }
1214 1.1 augustss
1215 1.1 augustss static void
1216 1.1 augustss cmpci_freem(handle, addr, type)
1217 1.7 tshiozak void *handle;
1218 1.7 tshiozak void *addr;
1219 1.7 tshiozak int type;
1220 1.1 augustss {
1221 1.1 augustss struct cmpci_softc *sc = handle;
1222 1.10 itohy
1223 1.1 augustss cmpci_free_dmamem(sc, addr, type);
1224 1.1 augustss }
1225 1.1 augustss
1226 1.1 augustss
1227 1.1 augustss #define MAXVAL 256
1228 1.1 augustss static int
1229 1.1 augustss cmpci_adjust(val, mask)
1230 1.1 augustss int val, mask;
1231 1.1 augustss {
1232 1.1 augustss val += (MAXVAL - mask) >> 1;
1233 1.1 augustss if (val >= MAXVAL)
1234 1.1 augustss val = MAXVAL-1;
1235 1.1 augustss return val & mask;
1236 1.1 augustss }
1237 1.1 augustss
1238 1.1 augustss static void
1239 1.1 augustss cmpci_set_mixer_gain(sc, port)
1240 1.1 augustss struct cmpci_softc *sc;
1241 1.1 augustss int port;
1242 1.1 augustss {
1243 1.1 augustss int src;
1244 1.10 itohy int bits, mask;
1245 1.1 augustss
1246 1.1 augustss switch (port) {
1247 1.1 augustss case CMPCI_MIC_VOL:
1248 1.10 itohy cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_MIC,
1249 1.10 itohy CMPCI_ADJUST_MIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1250 1.1 augustss break;
1251 1.1 augustss case CMPCI_MASTER_VOL:
1252 1.1 augustss src = CMPCI_SB16_MIXER_MASTER_L;
1253 1.1 augustss break;
1254 1.1 augustss case CMPCI_LINE_IN_VOL:
1255 1.1 augustss src = CMPCI_SB16_MIXER_LINE_L;
1256 1.1 augustss break;
1257 1.10 itohy case CMPCI_AUX_IN_VOL:
1258 1.10 itohy bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MIXER_AUX,
1259 1.10 itohy CMPCI_ADJUST_AUX_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT],
1260 1.10 itohy sc->sc_gain[port][CMPCI_RIGHT]));
1261 1.10 itohy return;
1262 1.10 itohy case CMPCI_MIC_RECVOL:
1263 1.10 itohy cmpci_reg_partial_write_1(sc, CMPCI_REG_MIXER25,
1264 1.10 itohy CMPCI_REG_ADMIC_SHIFT, CMPCI_REG_ADMIC_MASK,
1265 1.10 itohy CMPCI_ADJUST_ADMIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1266 1.10 itohy return;
1267 1.10 itohy case CMPCI_DAC_VOL:
1268 1.1 augustss src = CMPCI_SB16_MIXER_VOICE_L;
1269 1.1 augustss break;
1270 1.1 augustss case CMPCI_FM_VOL:
1271 1.1 augustss src = CMPCI_SB16_MIXER_FM_L;
1272 1.1 augustss break;
1273 1.1 augustss case CMPCI_CD_VOL:
1274 1.1 augustss src = CMPCI_SB16_MIXER_CDDA_L;
1275 1.1 augustss break;
1276 1.1 augustss case CMPCI_PCSPEAKER:
1277 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_SPEAKER,
1278 1.10 itohy CMPCI_ADJUST_2_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1279 1.10 itohy return;
1280 1.10 itohy case CMPCI_MIC_PREAMP:
1281 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1282 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1283 1.10 itohy CMPCI_REG_MICGAINZ);
1284 1.10 itohy else
1285 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1286 1.10 itohy CMPCI_REG_MICGAINZ);
1287 1.7 tshiozak return;
1288 1.10 itohy
1289 1.10 itohy case CMPCI_DAC_MUTE:
1290 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1291 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1292 1.10 itohy CMPCI_REG_WSMUTE);
1293 1.10 itohy else
1294 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1295 1.10 itohy CMPCI_REG_WSMUTE);
1296 1.10 itohy return;
1297 1.10 itohy case CMPCI_FM_MUTE:
1298 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1299 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1300 1.10 itohy CMPCI_REG_FMMUTE);
1301 1.10 itohy else
1302 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1303 1.10 itohy CMPCI_REG_FMMUTE);
1304 1.10 itohy return;
1305 1.10 itohy case CMPCI_AUX_IN_MUTE:
1306 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1307 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1308 1.10 itohy CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM);
1309 1.10 itohy else
1310 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1311 1.10 itohy CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM);
1312 1.10 itohy return;
1313 1.10 itohy case CMPCI_CD_MUTE:
1314 1.10 itohy mask = CMPCI_SB16_SW_CD;
1315 1.10 itohy goto sbmute;
1316 1.10 itohy case CMPCI_MIC_MUTE:
1317 1.10 itohy mask = CMPCI_SB16_SW_MIC;
1318 1.10 itohy goto sbmute;
1319 1.10 itohy case CMPCI_LINE_IN_MUTE:
1320 1.10 itohy mask = CMPCI_SB16_SW_LINE;
1321 1.10 itohy sbmute:
1322 1.10 itohy bits = cmpci_mixerreg_read(sc, CMPCI_SB16_MIXER_OUTMIX);
1323 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1324 1.10 itohy bits = bits & ~mask;
1325 1.10 itohy else
1326 1.10 itohy bits = bits | mask;
1327 1.10 itohy cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX, bits);
1328 1.8 itohy return;
1329 1.10 itohy
1330 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1331 1.10 itohy case CMPCI_MONITOR_DAC:
1332 1.10 itohy case CMPCI_PLAYBACK_MODE:
1333 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1334 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1335 1.7 tshiozak cmpci_set_out_ports(sc);
1336 1.7 tshiozak return;
1337 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1338 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDOUT_VOLTAGE)) {
1339 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_OUT_VOLTAGE][CMPCI_LR]
1340 1.10 itohy == CMPCI_SPDIF_OUT_VOLTAGE_LOW)
1341 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_MISC,
1342 1.10 itohy CMPCI_REG_5V);
1343 1.10 itohy else
1344 1.7 tshiozak cmpci_reg_set_4(sc, CMPCI_REG_MISC,
1345 1.7 tshiozak CMPCI_REG_5V);
1346 1.7 tshiozak }
1347 1.7 tshiozak return;
1348 1.7 tshiozak case CMPCI_SURROUND:
1349 1.7 tshiozak if (CMPCI_ISCAP(sc, SURROUND)) {
1350 1.7 tshiozak if (sc->sc_gain[CMPCI_SURROUND][CMPCI_LR])
1351 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1352 1.7 tshiozak CMPCI_REG_SURROUND);
1353 1.7 tshiozak else
1354 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1355 1.7 tshiozak CMPCI_REG_SURROUND);
1356 1.7 tshiozak }
1357 1.7 tshiozak return;
1358 1.7 tshiozak case CMPCI_REAR:
1359 1.7 tshiozak if (CMPCI_ISCAP(sc, REAR)) {
1360 1.7 tshiozak if (sc->sc_gain[CMPCI_REAR][CMPCI_LR])
1361 1.7 tshiozak cmpci_reg_set_4(sc, CMPCI_REG_MISC,
1362 1.7 tshiozak CMPCI_REG_N4SPK3D);
1363 1.7 tshiozak else
1364 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_MISC,
1365 1.7 tshiozak CMPCI_REG_N4SPK3D);
1366 1.7 tshiozak }
1367 1.7 tshiozak return;
1368 1.7 tshiozak case CMPCI_INDIVIDUAL:
1369 1.7 tshiozak if (CMPCI_ISCAP(sc, INDIVIDUAL_REAR)) {
1370 1.7 tshiozak if (sc->sc_gain[CMPCI_REAR][CMPCI_LR])
1371 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1372 1.7 tshiozak CMPCI_REG_INDIVIDUAL);
1373 1.7 tshiozak else
1374 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1375 1.7 tshiozak CMPCI_REG_INDIVIDUAL);
1376 1.7 tshiozak }
1377 1.7 tshiozak return;
1378 1.7 tshiozak case CMPCI_REVERSE:
1379 1.7 tshiozak if (CMPCI_ISCAP(sc, REVERSE_FR)) {
1380 1.7 tshiozak if (sc->sc_gain[CMPCI_REVERSE][CMPCI_LR])
1381 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1382 1.7 tshiozak CMPCI_REG_REVERSE_FR);
1383 1.7 tshiozak else
1384 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1385 1.7 tshiozak CMPCI_REG_REVERSE_FR);
1386 1.7 tshiozak }
1387 1.7 tshiozak return;
1388 1.7 tshiozak case CMPCI_SPDIF_IN_PHASE:
1389 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDIN_PHASE)) {
1390 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_IN_PHASE][CMPCI_LR]
1391 1.10 itohy == CMPCI_SPDIF_IN_PHASE_POSITIVE)
1392 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_CHANNEL_FORMAT,
1393 1.10 itohy CMPCI_REG_SPDIN_PHASE);
1394 1.10 itohy else
1395 1.8 itohy cmpci_reg_set_1(sc, CMPCI_REG_CHANNEL_FORMAT,
1396 1.8 itohy CMPCI_REG_SPDIN_PHASE);
1397 1.7 tshiozak }
1398 1.1 augustss return;
1399 1.1 augustss default:
1400 1.1 augustss return;
1401 1.1 augustss }
1402 1.10 itohy
1403 1.10 itohy cmpci_mixerreg_write(sc, src,
1404 1.10 itohy CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT]));
1405 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_L_TO_R(src),
1406 1.10 itohy CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_RIGHT]));
1407 1.7 tshiozak }
1408 1.7 tshiozak
1409 1.7 tshiozak static void
1410 1.7 tshiozak cmpci_set_out_ports(sc)
1411 1.7 tshiozak struct cmpci_softc *sc;
1412 1.7 tshiozak {
1413 1.10 itohy u_int8_t v;
1414 1.10 itohy int enspdout = 0;
1415 1.10 itohy
1416 1.7 tshiozak if (!CMPCI_ISCAP(sc, SPDLOOP))
1417 1.7 tshiozak return;
1418 1.10 itohy
1419 1.10 itohy /* SPDIF/out select */
1420 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_LOOP][CMPCI_LR] == CMPCI_SPDIF_LOOP_OFF) {
1421 1.10 itohy /* playback */
1422 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
1423 1.10 itohy } else {
1424 1.10 itohy /* monitor SPDIF/in */
1425 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
1426 1.10 itohy }
1427 1.10 itohy
1428 1.10 itohy /* SPDIF in select */
1429 1.10 itohy v = sc->sc_gain[CMPCI_SPDIF_IN_SELECT][CMPCI_LR];
1430 1.10 itohy if (v & CMPCI_SPDIFIN_SPDIFIN2)
1431 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_MISC, CMPCI_REG_2ND_SPDIFIN);
1432 1.10 itohy else
1433 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_MISC, CMPCI_REG_2ND_SPDIFIN);
1434 1.10 itohy if (v & CMPCI_SPDIFIN_SPDIFOUT)
1435 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_MISC, CMPCI_REG_SPDFLOOPI);
1436 1.10 itohy else
1437 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_MISC, CMPCI_REG_SPDFLOOPI);
1438 1.10 itohy
1439 1.10 itohy /* playback to ... */
1440 1.10 itohy if (CMPCI_ISCAP(sc, SPDOUT) &&
1441 1.10 itohy sc->sc_gain[CMPCI_PLAYBACK_MODE][CMPCI_LR]
1442 1.10 itohy == CMPCI_PLAYBACK_MODE_SPDIF &&
1443 1.10 itohy (sc->sc_play.md_divide == CMPCI_REG_RATE_44100 ||
1444 1.10 itohy (CMPCI_ISCAP(sc, SPDOUT_48K) &&
1445 1.10 itohy sc->sc_play.md_divide==CMPCI_REG_RATE_48000))) {
1446 1.10 itohy /* playback to SPDIF */
1447 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF0_ENABLE);
1448 1.10 itohy enspdout = 1;
1449 1.10 itohy if (sc->sc_play.md_divide==CMPCI_REG_RATE_48000)
1450 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_MISC,
1451 1.10 itohy CMPCI_REG_SPDIF_48K);
1452 1.10 itohy else
1453 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_MISC,
1454 1.10 itohy CMPCI_REG_SPDIF_48K);
1455 1.10 itohy } else {
1456 1.10 itohy /* playback to DAC */
1457 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1,
1458 1.10 itohy CMPCI_REG_SPDIF0_ENABLE);
1459 1.10 itohy if (CMPCI_ISCAP(sc, SPDOUT_48K))
1460 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_MISC,
1461 1.10 itohy CMPCI_REG_SPDIF_48K);
1462 1.10 itohy }
1463 1.10 itohy
1464 1.10 itohy /* legacy to SPDIF/out or not */
1465 1.10 itohy if (CMPCI_ISCAP(sc, SPDLEGACY)) {
1466 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_OUT_PLAYBACK][CMPCI_LR]
1467 1.10 itohy == CMPCI_SPDIF_OUT_PLAYBACK_WAVE)
1468 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL,
1469 1.10 itohy CMPCI_REG_LEGACY_SPDIF_ENABLE);
1470 1.10 itohy else {
1471 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL,
1472 1.10 itohy CMPCI_REG_LEGACY_SPDIF_ENABLE);
1473 1.10 itohy enspdout = 1;
1474 1.10 itohy }
1475 1.10 itohy }
1476 1.10 itohy
1477 1.10 itohy /* enable/disable SPDIF/out */
1478 1.10 itohy if (CMPCI_ISCAP(sc, XSPDOUT) && enspdout)
1479 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL,
1480 1.10 itohy CMPCI_REG_XSPDIF_ENABLE);
1481 1.10 itohy else
1482 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL,
1483 1.10 itohy CMPCI_REG_XSPDIF_ENABLE);
1484 1.10 itohy
1485 1.10 itohy /* SPDIF monitor (digital to alalog output) */
1486 1.10 itohy if (CMPCI_ISCAP(sc, SPDIN_MONITOR)) {
1487 1.10 itohy v = sc->sc_gain[CMPCI_MONITOR_DAC][CMPCI_LR];
1488 1.10 itohy if (!(v & CMPCI_MONDAC_ENABLE))
1489 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1490 1.10 itohy CMPCI_REG_SPDIN_MONITOR);
1491 1.10 itohy if (v & CMPCI_MONDAC_SPDOUT)
1492 1.7 tshiozak cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1,
1493 1.10 itohy CMPCI_REG_SPDIFOUT_DAC);
1494 1.10 itohy else
1495 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1,
1496 1.10 itohy CMPCI_REG_SPDIFOUT_DAC);
1497 1.10 itohy if (v & CMPCI_MONDAC_ENABLE)
1498 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1499 1.10 itohy CMPCI_REG_SPDIN_MONITOR);
1500 1.7 tshiozak }
1501 1.1 augustss }
1502 1.1 augustss
1503 1.1 augustss static int
1504 1.10 itohy cmpci_set_in_ports(sc)
1505 1.1 augustss struct cmpci_softc *sc;
1506 1.10 itohy {
1507 1.1 augustss int mask;
1508 1.1 augustss int bitsl, bitsr;
1509 1.1 augustss
1510 1.10 itohy mask = sc->sc_in_mask;
1511 1.10 itohy
1512 1.10 itohy /*
1513 1.10 itohy * Note CMPCI_RECORD_SOURCE_CD, CMPCI_RECORD_SOURCE_LINE_IN and
1514 1.10 itohy * CMPCI_RECORD_SOURCE_FM are defined to the corresponding bit
1515 1.10 itohy * of the mixer register.
1516 1.10 itohy */
1517 1.10 itohy bitsr = mask & (CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |
1518 1.10 itohy CMPCI_RECORD_SOURCE_FM);
1519 1.10 itohy
1520 1.1 augustss bitsl = CMPCI_SB16_MIXER_SRC_R_TO_L(bitsr);
1521 1.8 itohy if (mask & CMPCI_RECORD_SOURCE_MIC) {
1522 1.1 augustss bitsl |= CMPCI_SB16_MIXER_MIC_SRC;
1523 1.1 augustss bitsr |= CMPCI_SB16_MIXER_MIC_SRC;
1524 1.1 augustss }
1525 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, bitsl);
1526 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, bitsr);
1527 1.10 itohy
1528 1.10 itohy if (mask & CMPCI_RECORD_SOURCE_AUX_IN)
1529 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1530 1.10 itohy CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN);
1531 1.10 itohy else
1532 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1533 1.10 itohy CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN);
1534 1.10 itohy
1535 1.10 itohy if (mask & CMPCI_RECORD_SOURCE_WAVE)
1536 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1537 1.10 itohy CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR);
1538 1.10 itohy else
1539 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1540 1.10 itohy CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR);
1541 1.10 itohy
1542 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDIN) &&
1543 1.10 itohy (sc->sc_rec.md_divide == CMPCI_REG_RATE_44100 ||
1544 1.10 itohy (CMPCI_ISCAP(sc, SPDOUT_48K) &&
1545 1.10 itohy sc->sc_rec.md_divide == CMPCI_REG_RATE_48000/* XXX? */))) {
1546 1.8 itohy if (mask & CMPCI_RECORD_SOURCE_SPDIF) {
1547 1.7 tshiozak /* enable SPDIF/in */
1548 1.7 tshiozak cmpci_reg_set_4(sc,
1549 1.7 tshiozak CMPCI_REG_FUNC_1,
1550 1.7 tshiozak CMPCI_REG_SPDIF1_ENABLE);
1551 1.7 tshiozak } else {
1552 1.7 tshiozak cmpci_reg_clear_4(sc,
1553 1.7 tshiozak CMPCI_REG_FUNC_1,
1554 1.7 tshiozak CMPCI_REG_SPDIF1_ENABLE);
1555 1.7 tshiozak }
1556 1.7 tshiozak }
1557 1.1 augustss
1558 1.1 augustss return 0;
1559 1.1 augustss }
1560 1.1 augustss
1561 1.1 augustss static int
1562 1.1 augustss cmpci_set_port(handle, cp)
1563 1.1 augustss void *handle;
1564 1.1 augustss mixer_ctrl_t *cp;
1565 1.1 augustss {
1566 1.1 augustss struct cmpci_softc *sc = handle;
1567 1.1 augustss int lgain, rgain;
1568 1.10 itohy
1569 1.1 augustss switch (cp->dev) {
1570 1.10 itohy case CMPCI_MIC_VOL:
1571 1.1 augustss case CMPCI_PCSPEAKER:
1572 1.10 itohy case CMPCI_MIC_RECVOL:
1573 1.10 itohy if (cp->un.value.num_channels != 1)
1574 1.10 itohy return EINVAL;
1575 1.10 itohy /* FALLTHROUGH */
1576 1.10 itohy case CMPCI_DAC_VOL:
1577 1.1 augustss case CMPCI_FM_VOL:
1578 1.1 augustss case CMPCI_CD_VOL:
1579 1.10 itohy case CMPCI_LINE_IN_VOL:
1580 1.10 itohy case CMPCI_AUX_IN_VOL:
1581 1.1 augustss case CMPCI_MASTER_VOL:
1582 1.1 augustss if (cp->type != AUDIO_MIXER_VALUE)
1583 1.1 augustss return EINVAL;
1584 1.10 itohy switch (cp->un.value.num_channels) {
1585 1.10 itohy case 1:
1586 1.1 augustss lgain = rgain =
1587 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_MONO];
1588 1.1 augustss break;
1589 1.10 itohy case 2:
1590 1.10 itohy lgain = cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT];
1591 1.10 itohy rgain = cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT];
1592 1.1 augustss break;
1593 1.1 augustss default:
1594 1.10 itohy return EINVAL;
1595 1.1 augustss }
1596 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT] = lgain;
1597 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_RIGHT] = rgain;
1598 1.1 augustss
1599 1.1 augustss cmpci_set_mixer_gain(sc, cp->dev);
1600 1.1 augustss break;
1601 1.1 augustss
1602 1.1 augustss case CMPCI_RECORD_SOURCE:
1603 1.1 augustss if (cp->type != AUDIO_MIXER_SET)
1604 1.1 augustss return EINVAL;
1605 1.8 itohy
1606 1.10 itohy if (cp->un.mask & ~(CMPCI_RECORD_SOURCE_MIC |
1607 1.10 itohy CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |
1608 1.10 itohy CMPCI_RECORD_SOURCE_AUX_IN | CMPCI_RECORD_SOURCE_WAVE |
1609 1.10 itohy CMPCI_RECORD_SOURCE_FM | CMPCI_RECORD_SOURCE_SPDIF))
1610 1.10 itohy return EINVAL;
1611 1.10 itohy
1612 1.8 itohy if (cp->un.mask & CMPCI_RECORD_SOURCE_SPDIF)
1613 1.8 itohy cp->un.mask = CMPCI_RECORD_SOURCE_SPDIF;
1614 1.8 itohy
1615 1.10 itohy sc->sc_in_mask = cp->un.mask;
1616 1.10 itohy return cmpci_set_in_ports(sc);
1617 1.1 augustss
1618 1.10 itohy /* boolean */
1619 1.10 itohy case CMPCI_DAC_MUTE:
1620 1.10 itohy case CMPCI_FM_MUTE:
1621 1.10 itohy case CMPCI_CD_MUTE:
1622 1.10 itohy case CMPCI_LINE_IN_MUTE:
1623 1.10 itohy case CMPCI_AUX_IN_MUTE:
1624 1.10 itohy case CMPCI_MIC_MUTE:
1625 1.10 itohy case CMPCI_MIC_PREAMP:
1626 1.10 itohy case CMPCI_PLAYBACK_MODE:
1627 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
1628 1.10 itohy case CMPCI_SPDIF_LOOP:
1629 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1630 1.10 itohy case CMPCI_SPDIF_OUT_VOLTAGE:
1631 1.10 itohy case CMPCI_REAR:
1632 1.10 itohy case CMPCI_INDIVIDUAL:
1633 1.10 itohy case CMPCI_REVERSE:
1634 1.10 itohy case CMPCI_SURROUND:
1635 1.1 augustss if (cp->type != AUDIO_MIXER_ENUM)
1636 1.1 augustss return EINVAL;
1637 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord != 0;
1638 1.10 itohy cmpci_set_mixer_gain(sc, cp->dev);
1639 1.1 augustss break;
1640 1.1 augustss
1641 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1642 1.10 itohy switch (cp->un.ord) {
1643 1.10 itohy case CMPCI_SPDIF_IN_SPDIN1:
1644 1.10 itohy case CMPCI_SPDIF_IN_SPDIN2:
1645 1.10 itohy case CMPCI_SPDIF_IN_SPDOUT:
1646 1.10 itohy break;
1647 1.10 itohy default:
1648 1.1 augustss return EINVAL;
1649 1.1 augustss }
1650 1.10 itohy goto xenum;
1651 1.10 itohy case CMPCI_MONITOR_DAC:
1652 1.10 itohy switch (cp->un.ord) {
1653 1.10 itohy case CMPCI_MONITOR_DAC_OFF:
1654 1.10 itohy case CMPCI_MONITOR_DAC_SPDIN:
1655 1.10 itohy case CMPCI_MONITOR_DAC_SPDOUT:
1656 1.10 itohy break;
1657 1.10 itohy default:
1658 1.10 itohy return EINVAL;
1659 1.1 augustss }
1660 1.10 itohy xenum:
1661 1.10 itohy if (cp->type != AUDIO_MIXER_ENUM)
1662 1.10 itohy return EINVAL;
1663 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord;
1664 1.10 itohy cmpci_set_mixer_gain(sc, cp->dev);
1665 1.7 tshiozak break;
1666 1.10 itohy
1667 1.1 augustss default:
1668 1.1 augustss return EINVAL;
1669 1.1 augustss }
1670 1.10 itohy
1671 1.1 augustss return 0;
1672 1.1 augustss }
1673 1.1 augustss
1674 1.1 augustss static int
1675 1.1 augustss cmpci_get_port(handle, cp)
1676 1.1 augustss void *handle;
1677 1.1 augustss mixer_ctrl_t *cp;
1678 1.1 augustss {
1679 1.1 augustss struct cmpci_softc *sc = handle;
1680 1.10 itohy
1681 1.1 augustss switch (cp->dev) {
1682 1.1 augustss case CMPCI_MIC_VOL:
1683 1.10 itohy case CMPCI_PCSPEAKER:
1684 1.10 itohy case CMPCI_MIC_RECVOL:
1685 1.1 augustss if (cp->un.value.num_channels != 1)
1686 1.1 augustss return EINVAL;
1687 1.1 augustss /* fall into */
1688 1.10 itohy case CMPCI_DAC_VOL:
1689 1.1 augustss case CMPCI_FM_VOL:
1690 1.1 augustss case CMPCI_CD_VOL:
1691 1.10 itohy case CMPCI_LINE_IN_VOL:
1692 1.10 itohy case CMPCI_AUX_IN_VOL:
1693 1.1 augustss case CMPCI_MASTER_VOL:
1694 1.1 augustss switch (cp->un.value.num_channels) {
1695 1.1 augustss case 1:
1696 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
1697 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT];
1698 1.1 augustss break;
1699 1.1 augustss case 2:
1700 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
1701 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT];
1702 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
1703 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_RIGHT];
1704 1.1 augustss break;
1705 1.1 augustss default:
1706 1.1 augustss return EINVAL;
1707 1.1 augustss }
1708 1.1 augustss break;
1709 1.10 itohy
1710 1.1 augustss case CMPCI_RECORD_SOURCE:
1711 1.7 tshiozak cp->un.mask = sc->sc_in_mask;
1712 1.1 augustss break;
1713 1.1 augustss
1714 1.10 itohy case CMPCI_DAC_MUTE:
1715 1.10 itohy case CMPCI_FM_MUTE:
1716 1.10 itohy case CMPCI_CD_MUTE:
1717 1.1 augustss case CMPCI_LINE_IN_MUTE:
1718 1.10 itohy case CMPCI_AUX_IN_MUTE:
1719 1.10 itohy case CMPCI_MIC_MUTE:
1720 1.10 itohy case CMPCI_MIC_PREAMP:
1721 1.10 itohy case CMPCI_PLAYBACK_MODE:
1722 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1723 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
1724 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1725 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1726 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1727 1.10 itohy case CMPCI_MONITOR_DAC:
1728 1.7 tshiozak case CMPCI_REAR:
1729 1.7 tshiozak case CMPCI_INDIVIDUAL:
1730 1.7 tshiozak case CMPCI_REVERSE:
1731 1.7 tshiozak case CMPCI_SURROUND:
1732 1.7 tshiozak cp->un.ord = sc->sc_gain[cp->dev][CMPCI_LR];
1733 1.1 augustss break;
1734 1.1 augustss
1735 1.1 augustss default:
1736 1.1 augustss return EINVAL;
1737 1.1 augustss }
1738 1.1 augustss
1739 1.1 augustss return 0;
1740 1.1 augustss }
1741 1.1 augustss
1742 1.1 augustss /* ARGSUSED */
1743 1.1 augustss static size_t
1744 1.1 augustss cmpci_round_buffersize(handle, direction, bufsize)
1745 1.1 augustss void *handle;
1746 1.1 augustss int direction;
1747 1.1 augustss size_t bufsize;
1748 1.1 augustss {
1749 1.1 augustss if (bufsize > 0x10000)
1750 1.1 augustss bufsize = 0x10000;
1751 1.10 itohy
1752 1.1 augustss return bufsize;
1753 1.1 augustss }
1754 1.1 augustss
1755 1.1 augustss
1756 1.4 simonb static paddr_t
1757 1.1 augustss cmpci_mappage(handle, addr, offset, prot)
1758 1.1 augustss void *handle;
1759 1.1 augustss void *addr;
1760 1.4 simonb off_t offset;
1761 1.4 simonb int prot;
1762 1.1 augustss {
1763 1.1 augustss struct cmpci_softc *sc = handle;
1764 1.1 augustss struct cmpci_dmanode *p;
1765 1.10 itohy
1766 1.1 augustss if (offset < 0 || NULL == (p = cmpci_find_dmamem(sc, addr)))
1767 1.1 augustss return -1;
1768 1.1 augustss
1769 1.1 augustss return bus_dmamem_mmap(p->cd_tag, p->cd_segs,
1770 1.7 tshiozak sizeof(p->cd_segs)/sizeof(p->cd_segs[0]),
1771 1.7 tshiozak offset, prot, BUS_DMA_WAITOK);
1772 1.1 augustss }
1773 1.1 augustss
1774 1.1 augustss
1775 1.1 augustss /* ARGSUSED */
1776 1.1 augustss static int
1777 1.1 augustss cmpci_get_props(handle)
1778 1.1 augustss void *handle;
1779 1.1 augustss {
1780 1.1 augustss return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
1781 1.1 augustss }
1782 1.1 augustss
1783 1.1 augustss
1784 1.1 augustss static int
1785 1.1 augustss cmpci_trigger_output(handle, start, end, blksize, intr, arg, param)
1786 1.7 tshiozak void *handle;
1787 1.7 tshiozak void *start, *end;
1788 1.7 tshiozak int blksize;
1789 1.7 tshiozak void (*intr) __P((void *));
1790 1.7 tshiozak void *arg;
1791 1.7 tshiozak struct audio_params *param;
1792 1.1 augustss {
1793 1.1 augustss struct cmpci_softc *sc = handle;
1794 1.1 augustss struct cmpci_dmanode *p;
1795 1.1 augustss int bps;
1796 1.1 augustss
1797 1.1 augustss sc->sc_play.intr = intr;
1798 1.1 augustss sc->sc_play.intr_arg = arg;
1799 1.1 augustss bps = param->channels*param->precision*param->factor / 8;
1800 1.1 augustss if (!bps)
1801 1.1 augustss return EINVAL;
1802 1.1 augustss
1803 1.1 augustss /* set DMA frame */
1804 1.1 augustss if (!(p = cmpci_find_dmamem(sc, start)))
1805 1.1 augustss return EINVAL;
1806 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BASE,
1807 1.1 augustss DMAADDR(p));
1808 1.1 augustss delay(10);
1809 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BYTES,
1810 1.7 tshiozak ((caddr_t)end - (caddr_t)start + 1) / bps - 1);
1811 1.1 augustss delay(10);
1812 1.1 augustss
1813 1.1 augustss /* set interrupt count */
1814 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_SAMPLES,
1815 1.1 augustss (blksize + bps - 1) / bps - 1);
1816 1.1 augustss delay(10);
1817 1.1 augustss
1818 1.1 augustss /* start DMA */
1819 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); /* PLAY */
1820 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
1821 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
1822 1.10 itohy
1823 1.1 augustss return 0;
1824 1.1 augustss }
1825 1.1 augustss
1826 1.1 augustss static int
1827 1.1 augustss cmpci_trigger_input(handle, start, end, blksize, intr, arg, param)
1828 1.7 tshiozak void *handle;
1829 1.7 tshiozak void *start, *end;
1830 1.7 tshiozak int blksize;
1831 1.7 tshiozak void (*intr) __P((void *));
1832 1.7 tshiozak void *arg;
1833 1.7 tshiozak struct audio_params *param;
1834 1.1 augustss {
1835 1.1 augustss struct cmpci_softc *sc = handle;
1836 1.1 augustss struct cmpci_dmanode *p;
1837 1.1 augustss int bps;
1838 1.1 augustss
1839 1.1 augustss sc->sc_rec.intr = intr;
1840 1.1 augustss sc->sc_rec.intr_arg = arg;
1841 1.1 augustss bps = param->channels*param->precision*param->factor/8;
1842 1.1 augustss if (!bps)
1843 1.1 augustss return EINVAL;
1844 1.1 augustss
1845 1.1 augustss /* set DMA frame */
1846 1.1 augustss if (!(p=cmpci_find_dmamem(sc, start)))
1847 1.1 augustss return EINVAL;
1848 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BASE,
1849 1.1 augustss DMAADDR(p));
1850 1.1 augustss delay(10);
1851 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BYTES,
1852 1.7 tshiozak ((caddr_t)end - (caddr_t)start + 1) / bps - 1);
1853 1.1 augustss delay(10);
1854 1.1 augustss
1855 1.1 augustss /* set interrupt count */
1856 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_SAMPLES,
1857 1.7 tshiozak (blksize + bps - 1) / bps - 1);
1858 1.1 augustss delay(10);
1859 1.1 augustss
1860 1.1 augustss /* start DMA */
1861 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); /* REC */
1862 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
1863 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
1864 1.10 itohy
1865 1.1 augustss return 0;
1866 1.1 augustss }
1867 1.1 augustss
1868 1.1 augustss
1869 1.1 augustss /* end of file */
1870