cmpci.c revision 1.21 1 1.21 itohy /* $NetBSD: cmpci.c,v 1.21 2003/11/22 16:48:14 itohy Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.10 itohy * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.7 tshiozak * by Takuya SHIOZAKI <tshiozak (at) netbsd.org> .
9 1.1 augustss *
10 1.10 itohy * This code is derived from software contributed to The NetBSD Foundation
11 1.10 itohy * by ITOH Yasufumi.
12 1.10 itohy *
13 1.1 augustss * Redistribution and use in source and binary forms, with or without
14 1.1 augustss * modification, are permitted provided that the following conditions
15 1.1 augustss * are met:
16 1.1 augustss * 1. Redistributions of source code must retain the above copyright
17 1.1 augustss * notice, this list of conditions and the following disclaimer.
18 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
19 1.1 augustss * notice, this list of conditions and the following disclaimer in the
20 1.1 augustss * documentation and/or other materials provided with the distribution.
21 1.1 augustss *
22 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 1.1 augustss * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.1 augustss * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 augustss * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 1.1 augustss * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 1.1 augustss * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 1.1 augustss * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.1 augustss * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.1 augustss * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.1 augustss * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.1 augustss * SUCH DAMAGE.
33 1.1 augustss *
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * C-Media CMI8x38 Audio Chip Support.
38 1.1 augustss *
39 1.1 augustss * TODO:
40 1.10 itohy * - 4ch / 6ch support.
41 1.10 itohy * - Joystick support.
42 1.1 augustss *
43 1.1 augustss */
44 1.11 lukem
45 1.11 lukem #include <sys/cdefs.h>
46 1.21 itohy __KERNEL_RCSID(0, "$NetBSD: cmpci.c,v 1.21 2003/11/22 16:48:14 itohy Exp $");
47 1.1 augustss
48 1.1 augustss #if defined(AUDIO_DEBUG) || defined(DEBUG)
49 1.7 tshiozak #define DPRINTF(x) if (cmpcidebug) printf x
50 1.7 tshiozak int cmpcidebug = 0;
51 1.1 augustss #else
52 1.1 augustss #define DPRINTF(x)
53 1.1 augustss #endif
54 1.1 augustss
55 1.8 itohy #include "mpu.h"
56 1.8 itohy
57 1.1 augustss #include <sys/param.h>
58 1.1 augustss #include <sys/systm.h>
59 1.1 augustss #include <sys/kernel.h>
60 1.1 augustss #include <sys/malloc.h>
61 1.1 augustss #include <sys/device.h>
62 1.1 augustss #include <sys/proc.h>
63 1.1 augustss
64 1.1 augustss #include <dev/pci/pcidevs.h>
65 1.1 augustss #include <dev/pci/pcivar.h>
66 1.1 augustss
67 1.1 augustss #include <sys/audioio.h>
68 1.1 augustss #include <dev/audio_if.h>
69 1.1 augustss #include <dev/midi_if.h>
70 1.1 augustss
71 1.1 augustss #include <dev/mulaw.h>
72 1.1 augustss #include <dev/auconv.h>
73 1.1 augustss #include <dev/pci/cmpcireg.h>
74 1.1 augustss #include <dev/pci/cmpcivar.h>
75 1.1 augustss
76 1.1 augustss #include <dev/ic/mpuvar.h>
77 1.1 augustss #include <machine/bus.h>
78 1.1 augustss #include <machine/intr.h>
79 1.1 augustss
80 1.1 augustss /*
81 1.1 augustss * Low-level HW interface
82 1.1 augustss */
83 1.1 augustss static __inline uint8_t cmpci_mixerreg_read __P((struct cmpci_softc *,
84 1.7 tshiozak uint8_t));
85 1.1 augustss static __inline void cmpci_mixerreg_write __P((struct cmpci_softc *,
86 1.7 tshiozak uint8_t, uint8_t));
87 1.10 itohy static __inline void cmpci_reg_partial_write_1 __P((struct cmpci_softc *,
88 1.10 itohy int, int,
89 1.10 itohy unsigned, unsigned));
90 1.1 augustss static __inline void cmpci_reg_partial_write_4 __P((struct cmpci_softc *,
91 1.7 tshiozak int, int,
92 1.7 tshiozak uint32_t, uint32_t));
93 1.7 tshiozak static __inline void cmpci_reg_set_1 __P((struct cmpci_softc *,
94 1.7 tshiozak int, uint8_t));
95 1.7 tshiozak static __inline void cmpci_reg_clear_1 __P((struct cmpci_softc *,
96 1.7 tshiozak int, uint8_t));
97 1.1 augustss static __inline void cmpci_reg_set_4 __P((struct cmpci_softc *,
98 1.7 tshiozak int, uint32_t));
99 1.1 augustss static __inline void cmpci_reg_clear_4 __P((struct cmpci_softc *,
100 1.7 tshiozak int, uint32_t));
101 1.21 itohy static __inline void cmpci_reg_set_reg_misc __P((struct cmpci_softc *,
102 1.21 itohy uint32_t));
103 1.21 itohy static __inline void cmpci_reg_clear_reg_misc __P((struct cmpci_softc *,
104 1.21 itohy uint32_t));
105 1.1 augustss static int cmpci_rate_to_index __P((int));
106 1.1 augustss static __inline int cmpci_index_to_rate __P((int));
107 1.1 augustss static __inline int cmpci_index_to_divider __P((int));
108 1.1 augustss
109 1.1 augustss static int cmpci_adjust __P((int, int));
110 1.1 augustss static void cmpci_set_mixer_gain __P((struct cmpci_softc *, int));
111 1.7 tshiozak static void cmpci_set_out_ports __P((struct cmpci_softc *));
112 1.10 itohy static int cmpci_set_in_ports __P((struct cmpci_softc *));
113 1.1 augustss
114 1.1 augustss
115 1.1 augustss /*
116 1.1 augustss * autoconf interface
117 1.1 augustss */
118 1.1 augustss static int cmpci_match __P((struct device *, struct cfdata *, void *));
119 1.1 augustss static void cmpci_attach __P((struct device *, struct device *, void *));
120 1.1 augustss
121 1.15 thorpej CFATTACH_DECL(cmpci, sizeof (struct cmpci_softc),
122 1.16 thorpej cmpci_match, cmpci_attach, NULL, NULL);
123 1.1 augustss
124 1.1 augustss /* interrupt */
125 1.1 augustss static int cmpci_intr __P((void *));
126 1.1 augustss
127 1.1 augustss
128 1.1 augustss /*
129 1.1 augustss * DMA stuffs
130 1.1 augustss */
131 1.1 augustss static int cmpci_alloc_dmamem __P((struct cmpci_softc *,
132 1.18 thorpej size_t, struct malloc_type *,
133 1.18 thorpej int, caddr_t *));
134 1.18 thorpej static int cmpci_free_dmamem __P((struct cmpci_softc *, caddr_t,
135 1.18 thorpej struct malloc_type *));
136 1.1 augustss static struct cmpci_dmanode * cmpci_find_dmamem __P((struct cmpci_softc *,
137 1.7 tshiozak caddr_t));
138 1.1 augustss
139 1.1 augustss
140 1.1 augustss /*
141 1.1 augustss * interface to machine independent layer
142 1.1 augustss */
143 1.1 augustss static int cmpci_open __P((void *, int));
144 1.1 augustss static void cmpci_close __P((void *));
145 1.1 augustss static int cmpci_query_encoding __P((void *, struct audio_encoding *));
146 1.1 augustss static int cmpci_set_params __P((void *, int, int,
147 1.7 tshiozak struct audio_params *,
148 1.7 tshiozak struct audio_params *));
149 1.1 augustss static int cmpci_round_blocksize __P((void *, int));
150 1.1 augustss static int cmpci_halt_output __P((void *));
151 1.1 augustss static int cmpci_halt_input __P((void *));
152 1.1 augustss static int cmpci_getdev __P((void *, struct audio_device *));
153 1.1 augustss static int cmpci_set_port __P((void *, mixer_ctrl_t *));
154 1.1 augustss static int cmpci_get_port __P((void *, mixer_ctrl_t *));
155 1.1 augustss static int cmpci_query_devinfo __P((void *, mixer_devinfo_t *));
156 1.18 thorpej static void *cmpci_allocm __P((void *, int, size_t, struct malloc_type *, int));
157 1.18 thorpej static void cmpci_freem __P((void *, void *, struct malloc_type *));
158 1.1 augustss static size_t cmpci_round_buffersize __P((void *, int, size_t));
159 1.4 simonb static paddr_t cmpci_mappage __P((void *, void *, off_t, int));
160 1.1 augustss static int cmpci_get_props __P((void *));
161 1.1 augustss static int cmpci_trigger_output __P((void *, void *, void *, int,
162 1.7 tshiozak void (*)(void *), void *,
163 1.7 tshiozak struct audio_params *));
164 1.1 augustss static int cmpci_trigger_input __P((void *, void *, void *, int,
165 1.7 tshiozak void (*)(void *), void *,
166 1.7 tshiozak struct audio_params *));
167 1.1 augustss
168 1.1 augustss static struct audio_hw_if cmpci_hw_if = {
169 1.3 gmcgarry cmpci_open, /* open */
170 1.3 gmcgarry cmpci_close, /* close */
171 1.1 augustss NULL, /* drain */
172 1.3 gmcgarry cmpci_query_encoding, /* query_encoding */
173 1.3 gmcgarry cmpci_set_params, /* set_params */
174 1.3 gmcgarry cmpci_round_blocksize, /* round_blocksize */
175 1.1 augustss NULL, /* commit_settings */
176 1.1 augustss NULL, /* init_output */
177 1.1 augustss NULL, /* init_input */
178 1.1 augustss NULL, /* start_output */
179 1.1 augustss NULL, /* start_input */
180 1.3 gmcgarry cmpci_halt_output, /* halt_output */
181 1.3 gmcgarry cmpci_halt_input, /* halt_input */
182 1.1 augustss NULL, /* speaker_ctl */
183 1.3 gmcgarry cmpci_getdev, /* getdev */
184 1.1 augustss NULL, /* setfd */
185 1.3 gmcgarry cmpci_set_port, /* set_port */
186 1.3 gmcgarry cmpci_get_port, /* get_port */
187 1.3 gmcgarry cmpci_query_devinfo, /* query_devinfo */
188 1.3 gmcgarry cmpci_allocm, /* allocm */
189 1.3 gmcgarry cmpci_freem, /* freem */
190 1.3 gmcgarry cmpci_round_buffersize,/* round_buffersize */
191 1.3 gmcgarry cmpci_mappage, /* mappage */
192 1.3 gmcgarry cmpci_get_props, /* get_props */
193 1.3 gmcgarry cmpci_trigger_output, /* trigger_output */
194 1.9 augustss cmpci_trigger_input, /* trigger_input */
195 1.9 augustss NULL, /* dev_ioctl */
196 1.1 augustss };
197 1.1 augustss
198 1.1 augustss
199 1.1 augustss /*
200 1.1 augustss * Low-level HW interface
201 1.1 augustss */
202 1.1 augustss
203 1.1 augustss /* mixer register read/write */
204 1.1 augustss static __inline uint8_t
205 1.1 augustss cmpci_mixerreg_read(sc, no)
206 1.1 augustss struct cmpci_softc *sc;
207 1.1 augustss uint8_t no;
208 1.1 augustss {
209 1.1 augustss uint8_t ret;
210 1.1 augustss
211 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no);
212 1.1 augustss delay(10);
213 1.1 augustss ret = bus_space_read_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA);
214 1.1 augustss delay(10);
215 1.1 augustss return ret;
216 1.1 augustss }
217 1.1 augustss
218 1.1 augustss static __inline void
219 1.1 augustss cmpci_mixerreg_write(sc, no, val)
220 1.1 augustss struct cmpci_softc *sc;
221 1.1 augustss uint8_t no, val;
222 1.1 augustss {
223 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no);
224 1.1 augustss delay(10);
225 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA, val);
226 1.1 augustss delay(10);
227 1.1 augustss }
228 1.1 augustss
229 1.1 augustss
230 1.1 augustss /* register partial write */
231 1.1 augustss static __inline void
232 1.10 itohy cmpci_reg_partial_write_1(sc, no, shift, mask, val)
233 1.10 itohy struct cmpci_softc *sc;
234 1.10 itohy int no, shift;
235 1.10 itohy unsigned mask, val;
236 1.10 itohy {
237 1.10 itohy bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
238 1.10 itohy (val<<shift) |
239 1.10 itohy (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));
240 1.10 itohy delay(10);
241 1.10 itohy }
242 1.10 itohy
243 1.10 itohy static __inline void
244 1.1 augustss cmpci_reg_partial_write_4(sc, no, shift, mask, val)
245 1.1 augustss struct cmpci_softc *sc;
246 1.1 augustss int no, shift;
247 1.1 augustss uint32_t mask, val;
248 1.1 augustss {
249 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
250 1.1 augustss (val<<shift) |
251 1.1 augustss (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));
252 1.1 augustss delay(10);
253 1.1 augustss }
254 1.1 augustss
255 1.1 augustss /* register set/clear bit */
256 1.1 augustss static __inline void
257 1.7 tshiozak cmpci_reg_set_1(sc, no, mask)
258 1.7 tshiozak struct cmpci_softc *sc;
259 1.7 tshiozak int no;
260 1.7 tshiozak uint8_t mask;
261 1.7 tshiozak {
262 1.7 tshiozak bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
263 1.7 tshiozak (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) | mask));
264 1.7 tshiozak delay(10);
265 1.7 tshiozak }
266 1.7 tshiozak
267 1.7 tshiozak static __inline void
268 1.7 tshiozak cmpci_reg_clear_1(sc, no, mask)
269 1.7 tshiozak struct cmpci_softc *sc;
270 1.7 tshiozak int no;
271 1.7 tshiozak uint8_t mask;
272 1.7 tshiozak {
273 1.7 tshiozak bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
274 1.7 tshiozak (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~mask));
275 1.7 tshiozak delay(10);
276 1.7 tshiozak }
277 1.7 tshiozak
278 1.7 tshiozak
279 1.7 tshiozak static __inline void
280 1.1 augustss cmpci_reg_set_4(sc, no, mask)
281 1.1 augustss struct cmpci_softc *sc;
282 1.1 augustss int no;
283 1.1 augustss uint32_t mask;
284 1.1 augustss {
285 1.21 itohy /* use cmpci_reg_set_reg_misc() for CMPCI_REG_MISC */
286 1.21 itohy KDASSERT(no != CMPCI_REG_MISC);
287 1.21 itohy
288 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
289 1.7 tshiozak (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) | mask));
290 1.1 augustss delay(10);
291 1.1 augustss }
292 1.1 augustss
293 1.1 augustss static __inline void
294 1.1 augustss cmpci_reg_clear_4(sc, no, mask)
295 1.1 augustss struct cmpci_softc *sc;
296 1.1 augustss int no;
297 1.1 augustss uint32_t mask;
298 1.1 augustss {
299 1.21 itohy /* use cmpci_reg_clear_reg_misc() for CMPCI_REG_MISC */
300 1.21 itohy KDASSERT(no != CMPCI_REG_MISC);
301 1.21 itohy
302 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
303 1.7 tshiozak (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~mask));
304 1.1 augustss delay(10);
305 1.1 augustss }
306 1.1 augustss
307 1.1 augustss
308 1.21 itohy /*
309 1.21 itohy * The CMPCI_REG_MISC register needs special handling, since one of
310 1.21 itohy * its bits has different read/write values.
311 1.21 itohy */
312 1.21 itohy static __inline void
313 1.21 itohy cmpci_reg_set_reg_misc(sc, mask)
314 1.21 itohy struct cmpci_softc *sc;
315 1.21 itohy uint32_t mask;
316 1.21 itohy {
317 1.21 itohy sc->sc_reg_misc |= mask;
318 1.21 itohy bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MISC,
319 1.21 itohy sc->sc_reg_misc);
320 1.21 itohy delay(10);
321 1.21 itohy }
322 1.21 itohy
323 1.21 itohy static __inline void
324 1.21 itohy cmpci_reg_clear_reg_misc(sc, mask)
325 1.21 itohy struct cmpci_softc *sc;
326 1.21 itohy uint32_t mask;
327 1.21 itohy {
328 1.21 itohy sc->sc_reg_misc &= ~mask;
329 1.21 itohy bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MISC,
330 1.21 itohy sc->sc_reg_misc);
331 1.21 itohy delay(10);
332 1.21 itohy }
333 1.21 itohy
334 1.21 itohy
335 1.1 augustss /* rate */
336 1.6 jdolecek static const struct {
337 1.1 augustss int rate;
338 1.1 augustss int divider;
339 1.1 augustss } cmpci_rate_table[CMPCI_REG_NUMRATE] = {
340 1.1 augustss #define _RATE(n) { n, CMPCI_REG_RATE_ ## n }
341 1.1 augustss _RATE(5512),
342 1.1 augustss _RATE(8000),
343 1.1 augustss _RATE(11025),
344 1.1 augustss _RATE(16000),
345 1.1 augustss _RATE(22050),
346 1.1 augustss _RATE(32000),
347 1.1 augustss _RATE(44100),
348 1.1 augustss _RATE(48000)
349 1.7 tshiozak #undef _RATE
350 1.1 augustss };
351 1.1 augustss
352 1.1 augustss static int
353 1.1 augustss cmpci_rate_to_index(rate)
354 1.1 augustss int rate;
355 1.1 augustss {
356 1.1 augustss int i;
357 1.1 augustss
358 1.13 augustss for (i = 0; i < CMPCI_REG_NUMRATE - 1; i++)
359 1.1 augustss if (rate <=
360 1.1 augustss (cmpci_rate_table[i].rate+cmpci_rate_table[i+1].rate) / 2)
361 1.1 augustss return i;
362 1.1 augustss return i; /* 48000 */
363 1.1 augustss }
364 1.1 augustss
365 1.1 augustss static __inline int
366 1.1 augustss cmpci_index_to_rate(index)
367 1.1 augustss int index;
368 1.1 augustss {
369 1.1 augustss return cmpci_rate_table[index].rate;
370 1.1 augustss }
371 1.1 augustss
372 1.1 augustss static __inline int
373 1.1 augustss cmpci_index_to_divider(index)
374 1.1 augustss int index;
375 1.1 augustss {
376 1.1 augustss return cmpci_rate_table[index].divider;
377 1.1 augustss }
378 1.1 augustss
379 1.1 augustss
380 1.1 augustss /*
381 1.1 augustss * interface to configure the device.
382 1.1 augustss */
383 1.1 augustss
384 1.1 augustss static int
385 1.1 augustss cmpci_match(parent, match, aux)
386 1.1 augustss struct device *parent;
387 1.1 augustss struct cfdata *match;
388 1.1 augustss void *aux;
389 1.1 augustss {
390 1.1 augustss struct pci_attach_args *pa = (struct pci_attach_args *)aux;
391 1.1 augustss
392 1.1 augustss if ( PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMEDIA &&
393 1.1 augustss (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338A ||
394 1.1 augustss PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338B ||
395 1.7 tshiozak PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738 ||
396 1.7 tshiozak PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738B) )
397 1.1 augustss return 1;
398 1.1 augustss
399 1.1 augustss return 0;
400 1.1 augustss }
401 1.1 augustss
402 1.1 augustss static void
403 1.1 augustss cmpci_attach(parent, self, aux)
404 1.1 augustss struct device *parent, *self;
405 1.1 augustss void *aux;
406 1.1 augustss {
407 1.1 augustss struct cmpci_softc *sc = (struct cmpci_softc *)self;
408 1.1 augustss struct pci_attach_args *pa = (struct pci_attach_args *)aux;
409 1.8 itohy struct audio_attach_args aa;
410 1.1 augustss pci_intr_handle_t ih;
411 1.1 augustss char const *strintr;
412 1.7 tshiozak char devinfo[256];
413 1.1 augustss int i, v;
414 1.1 augustss
415 1.17 thorpej aprint_naive(": Audio controller\n");
416 1.17 thorpej
417 1.7 tshiozak sc->sc_id = pa->pa_id;
418 1.7 tshiozak sc->sc_class = pa->pa_class;
419 1.7 tshiozak pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
420 1.17 thorpej aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
421 1.17 thorpej PCI_REVISION(sc->sc_class));
422 1.7 tshiozak switch (PCI_PRODUCT(sc->sc_id)) {
423 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338A:
424 1.7 tshiozak /*FALLTHROUGH*/
425 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338B:
426 1.7 tshiozak sc->sc_capable = CMPCI_CAP_CMI8338;
427 1.1 augustss break;
428 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8738:
429 1.7 tshiozak /*FALLTHROUGH*/
430 1.7 tshiozak case PCI_PRODUCT_CMEDIA_CMI8738B:
431 1.7 tshiozak sc->sc_capable = CMPCI_CAP_CMI8738;
432 1.1 augustss break;
433 1.1 augustss }
434 1.1 augustss
435 1.2 augustss /* map I/O space */
436 1.1 augustss if (pci_mapreg_map(pa, CMPCI_PCI_IOBASEREG, PCI_MAPREG_TYPE_IO, 0,
437 1.7 tshiozak &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) {
438 1.17 thorpej aprint_error("%s: failed to map I/O space\n",
439 1.17 thorpej sc->sc_dev.dv_xname);
440 1.1 augustss return;
441 1.1 augustss }
442 1.1 augustss
443 1.2 augustss /* interrupt */
444 1.5 sommerfe if (pci_intr_map(pa, &ih)) {
445 1.17 thorpej aprint_error("%s: failed to map interrupt\n",
446 1.17 thorpej sc->sc_dev.dv_xname);
447 1.1 augustss return;
448 1.1 augustss }
449 1.1 augustss strintr = pci_intr_string(pa->pa_pc, ih);
450 1.1 augustss sc->sc_ih=pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, cmpci_intr, sc);
451 1.1 augustss if (sc->sc_ih == NULL) {
452 1.17 thorpej aprint_error("%s: failed to establish interrupt",
453 1.1 augustss sc->sc_dev.dv_xname);
454 1.1 augustss if (strintr != NULL)
455 1.17 thorpej aprint_normal(" at %s", strintr);
456 1.17 thorpej aprint_normal("\n");
457 1.1 augustss return;
458 1.1 augustss }
459 1.17 thorpej aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, strintr);
460 1.1 augustss
461 1.1 augustss sc->sc_dmat = pa->pa_dmat;
462 1.1 augustss
463 1.1 augustss audio_attach_mi(&cmpci_hw_if, sc, &sc->sc_dev);
464 1.1 augustss
465 1.8 itohy /* attach OPL device */
466 1.8 itohy aa.type = AUDIODEV_TYPE_OPL;
467 1.8 itohy aa.hwif = NULL;
468 1.8 itohy aa.hdl = NULL;
469 1.8 itohy (void)config_found(&sc->sc_dev, &aa, audioprint);
470 1.8 itohy
471 1.8 itohy /* attach MPU-401 device */
472 1.8 itohy aa.type = AUDIODEV_TYPE_MPU;
473 1.8 itohy aa.hwif = NULL;
474 1.8 itohy aa.hdl = NULL;
475 1.8 itohy if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
476 1.8 itohy CMPCI_REG_MPU_BASE, CMPCI_REG_MPU_SIZE, &sc->sc_mpu_ioh) == 0)
477 1.8 itohy sc->sc_mpudev = config_found(&sc->sc_dev, &aa, audioprint);
478 1.8 itohy
479 1.21 itohy /* get initial value (this is 0 and may be omitted but just in case) */
480 1.21 itohy sc->sc_reg_misc = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
481 1.21 itohy CMPCI_REG_MISC) & ~CMPCI_REG_SPDIF48K;
482 1.21 itohy
483 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_RESET, 0);
484 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
485 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
486 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX,
487 1.1 augustss CMPCI_SB16_SW_CD|CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
488 1.1 augustss for (i = 0; i < CMPCI_NDEVS; i++) {
489 1.1 augustss switch(i) {
490 1.10 itohy /*
491 1.10 itohy * CMI8738 defaults are
492 1.10 itohy * master: 0xe0 (0x00 - 0xf8)
493 1.12 itohy * FM, DAC: 0xc0 (0x00 - 0xf8)
494 1.10 itohy * PC speaker: 0x80 (0x00 - 0xc0)
495 1.10 itohy * others: 0
496 1.10 itohy */
497 1.10 itohy /* volume */
498 1.8 itohy case CMPCI_MASTER_VOL:
499 1.10 itohy v = 128; /* 224 */
500 1.10 itohy break;
501 1.8 itohy case CMPCI_FM_VOL:
502 1.10 itohy case CMPCI_DAC_VOL:
503 1.10 itohy v = 192;
504 1.10 itohy break;
505 1.8 itohy case CMPCI_PCSPEAKER:
506 1.10 itohy v = 128;
507 1.1 augustss break;
508 1.8 itohy
509 1.8 itohy /* booleans, set to true */
510 1.10 itohy case CMPCI_CD_MUTE:
511 1.10 itohy case CMPCI_MIC_MUTE:
512 1.10 itohy case CMPCI_LINE_IN_MUTE:
513 1.10 itohy case CMPCI_AUX_IN_MUTE:
514 1.8 itohy v = 1;
515 1.1 augustss break;
516 1.10 itohy
517 1.10 itohy /* volume with inital value 0 */
518 1.10 itohy case CMPCI_CD_VOL:
519 1.10 itohy case CMPCI_LINE_IN_VOL:
520 1.10 itohy case CMPCI_AUX_IN_VOL:
521 1.10 itohy case CMPCI_MIC_VOL:
522 1.10 itohy case CMPCI_MIC_RECVOL:
523 1.10 itohy /* FALLTHROUGH */
524 1.10 itohy
525 1.8 itohy /* others are cleared */
526 1.10 itohy case CMPCI_MIC_PREAMP:
527 1.8 itohy case CMPCI_RECORD_SOURCE:
528 1.10 itohy case CMPCI_PLAYBACK_MODE:
529 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
530 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
531 1.7 tshiozak case CMPCI_SPDIF_LOOP:
532 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
533 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
534 1.10 itohy case CMPCI_MONITOR_DAC:
535 1.7 tshiozak case CMPCI_REAR:
536 1.7 tshiozak case CMPCI_INDIVIDUAL:
537 1.7 tshiozak case CMPCI_REVERSE:
538 1.7 tshiozak case CMPCI_SURROUND:
539 1.8 itohy default:
540 1.1 augustss v = 0;
541 1.1 augustss break;
542 1.1 augustss }
543 1.7 tshiozak sc->sc_gain[i][CMPCI_LEFT] = sc->sc_gain[i][CMPCI_RIGHT] = v;
544 1.1 augustss cmpci_set_mixer_gain(sc, i);
545 1.1 augustss }
546 1.1 augustss }
547 1.1 augustss
548 1.1 augustss
549 1.1 augustss static int
550 1.1 augustss cmpci_intr(handle)
551 1.1 augustss void *handle;
552 1.1 augustss {
553 1.1 augustss struct cmpci_softc *sc = handle;
554 1.1 augustss uint32_t intrstat;
555 1.1 augustss
556 1.1 augustss intrstat = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
557 1.1 augustss CMPCI_REG_INTR_STATUS);
558 1.1 augustss
559 1.1 augustss if (!(intrstat & CMPCI_REG_ANY_INTR))
560 1.1 augustss return 0;
561 1.1 augustss
562 1.8 itohy delay(10);
563 1.8 itohy
564 1.1 augustss /* disable and reset intr */
565 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR)
566 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL,
567 1.1 augustss CMPCI_REG_CH0_INTR_ENABLE);
568 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR)
569 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL,
570 1.1 augustss CMPCI_REG_CH1_INTR_ENABLE);
571 1.1 augustss
572 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR) {
573 1.1 augustss if (sc->sc_play.intr != NULL)
574 1.1 augustss (*sc->sc_play.intr)(sc->sc_play.intr_arg);
575 1.1 augustss }
576 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR) {
577 1.1 augustss if (sc->sc_rec.intr != NULL)
578 1.1 augustss (*sc->sc_rec.intr)(sc->sc_rec.intr_arg);
579 1.1 augustss }
580 1.1 augustss
581 1.1 augustss /* enable intr */
582 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR)
583 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL,
584 1.1 augustss CMPCI_REG_CH0_INTR_ENABLE);
585 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR)
586 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL,
587 1.1 augustss CMPCI_REG_CH1_INTR_ENABLE);
588 1.8 itohy
589 1.8 itohy #if NMPU > 0
590 1.8 itohy if (intrstat & CMPCI_REG_UART_INTR && sc->sc_mpudev != NULL)
591 1.8 itohy mpu_intr(sc->sc_mpudev);
592 1.8 itohy #endif
593 1.8 itohy
594 1.8 itohy return 1;
595 1.1 augustss }
596 1.1 augustss
597 1.1 augustss
598 1.1 augustss /* open/close */
599 1.1 augustss static int
600 1.1 augustss cmpci_open(handle, flags)
601 1.1 augustss void *handle;
602 1.1 augustss int flags;
603 1.1 augustss {
604 1.1 augustss return 0;
605 1.1 augustss }
606 1.1 augustss
607 1.1 augustss static void
608 1.1 augustss cmpci_close(handle)
609 1.1 augustss void *handle;
610 1.1 augustss {
611 1.1 augustss }
612 1.1 augustss
613 1.1 augustss static int
614 1.1 augustss cmpci_query_encoding(handle, fp)
615 1.1 augustss void *handle;
616 1.1 augustss struct audio_encoding *fp;
617 1.1 augustss {
618 1.1 augustss switch (fp->index) {
619 1.1 augustss case 0:
620 1.1 augustss strcpy(fp->name, AudioEulinear);
621 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR;
622 1.1 augustss fp->precision = 8;
623 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
624 1.1 augustss break;
625 1.1 augustss case 1:
626 1.1 augustss strcpy(fp->name, AudioEmulaw);
627 1.1 augustss fp->encoding = AUDIO_ENCODING_ULAW;
628 1.1 augustss fp->precision = 8;
629 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
630 1.1 augustss break;
631 1.1 augustss case 2:
632 1.1 augustss strcpy(fp->name, AudioEalaw);
633 1.1 augustss fp->encoding = AUDIO_ENCODING_ALAW;
634 1.1 augustss fp->precision = 8;
635 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
636 1.1 augustss break;
637 1.1 augustss case 3:
638 1.1 augustss strcpy(fp->name, AudioEslinear);
639 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR;
640 1.1 augustss fp->precision = 8;
641 1.1 augustss fp->flags = 0;
642 1.1 augustss break;
643 1.1 augustss case 4:
644 1.1 augustss strcpy(fp->name, AudioEslinear_le);
645 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR_LE;
646 1.1 augustss fp->precision = 16;
647 1.1 augustss fp->flags = 0;
648 1.1 augustss break;
649 1.1 augustss case 5:
650 1.1 augustss strcpy(fp->name, AudioEulinear_le);
651 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR_LE;
652 1.1 augustss fp->precision = 16;
653 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
654 1.1 augustss break;
655 1.1 augustss case 6:
656 1.1 augustss strcpy(fp->name, AudioEslinear_be);
657 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR_BE;
658 1.1 augustss fp->precision = 16;
659 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
660 1.1 augustss break;
661 1.1 augustss case 7:
662 1.1 augustss strcpy(fp->name, AudioEulinear_be);
663 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR_BE;
664 1.1 augustss fp->precision = 16;
665 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
666 1.1 augustss break;
667 1.1 augustss default:
668 1.1 augustss return EINVAL;
669 1.1 augustss }
670 1.1 augustss return 0;
671 1.1 augustss }
672 1.1 augustss
673 1.1 augustss
674 1.1 augustss static int
675 1.1 augustss cmpci_set_params(handle, setmode, usemode, play, rec)
676 1.1 augustss void *handle;
677 1.1 augustss int setmode, usemode;
678 1.1 augustss struct audio_params *play, *rec;
679 1.1 augustss {
680 1.1 augustss int i;
681 1.1 augustss struct cmpci_softc *sc = handle;
682 1.1 augustss
683 1.1 augustss for (i = 0; i < 2; i++) {
684 1.1 augustss int md_format;
685 1.1 augustss int md_divide;
686 1.1 augustss int md_index;
687 1.1 augustss int mode;
688 1.1 augustss struct audio_params *p;
689 1.10 itohy
690 1.1 augustss switch (i) {
691 1.1 augustss case 0:
692 1.1 augustss mode = AUMODE_PLAY;
693 1.1 augustss p = play;
694 1.1 augustss break;
695 1.1 augustss case 1:
696 1.1 augustss mode = AUMODE_RECORD;
697 1.1 augustss p = rec;
698 1.1 augustss break;
699 1.19 christos default:
700 1.19 christos return EINVAL;
701 1.1 augustss }
702 1.10 itohy
703 1.1 augustss if (!(setmode & mode))
704 1.1 augustss continue;
705 1.1 augustss
706 1.1 augustss
707 1.1 augustss /* format */
708 1.1 augustss p->sw_code = NULL;
709 1.1 augustss switch ( p->channels ) {
710 1.1 augustss case 1:
711 1.1 augustss md_format = CMPCI_REG_FORMAT_MONO;
712 1.1 augustss break;
713 1.1 augustss case 2:
714 1.1 augustss md_format = CMPCI_REG_FORMAT_STEREO;
715 1.1 augustss break;
716 1.1 augustss default:
717 1.1 augustss return (EINVAL);
718 1.1 augustss }
719 1.1 augustss switch (p->encoding) {
720 1.1 augustss case AUDIO_ENCODING_ULAW:
721 1.1 augustss if (p->precision != 8)
722 1.1 augustss return (EINVAL);
723 1.1 augustss if (mode & AUMODE_PLAY) {
724 1.1 augustss p->factor = 2;
725 1.1 augustss p->sw_code = mulaw_to_slinear16_le;
726 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
727 1.1 augustss } else {
728 1.1 augustss p->sw_code = ulinear8_to_mulaw;
729 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
730 1.1 augustss }
731 1.1 augustss break;
732 1.1 augustss case AUDIO_ENCODING_ALAW:
733 1.1 augustss if (p->precision != 8)
734 1.1 augustss return (EINVAL);
735 1.1 augustss if (mode & AUMODE_PLAY) {
736 1.1 augustss p->factor = 2;
737 1.1 augustss p->sw_code = alaw_to_slinear16_le;
738 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
739 1.1 augustss } else {
740 1.1 augustss p->sw_code = ulinear8_to_alaw;
741 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
742 1.1 augustss }
743 1.1 augustss break;
744 1.1 augustss case AUDIO_ENCODING_SLINEAR_LE:
745 1.1 augustss switch (p->precision) {
746 1.1 augustss case 8:
747 1.1 augustss p->sw_code = change_sign8;
748 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
749 1.1 augustss break;
750 1.1 augustss case 16:
751 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
752 1.1 augustss break;
753 1.1 augustss default:
754 1.1 augustss return (EINVAL);
755 1.1 augustss }
756 1.1 augustss break;
757 1.1 augustss case AUDIO_ENCODING_SLINEAR_BE:
758 1.1 augustss switch (p->precision) {
759 1.1 augustss case 8:
760 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
761 1.1 augustss p->sw_code = change_sign8;
762 1.1 augustss break;
763 1.1 augustss case 16:
764 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
765 1.1 augustss p->sw_code = swap_bytes;
766 1.1 augustss break;
767 1.1 augustss default:
768 1.1 augustss return (EINVAL);
769 1.1 augustss }
770 1.1 augustss break;
771 1.1 augustss case AUDIO_ENCODING_ULINEAR_LE:
772 1.1 augustss switch (p->precision) {
773 1.1 augustss case 8:
774 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
775 1.1 augustss break;
776 1.1 augustss case 16:
777 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
778 1.1 augustss p->sw_code = change_sign16_le;
779 1.1 augustss break;
780 1.1 augustss default:
781 1.1 augustss return (EINVAL);
782 1.1 augustss }
783 1.1 augustss break;
784 1.1 augustss case AUDIO_ENCODING_ULINEAR_BE:
785 1.1 augustss switch (p->precision) {
786 1.1 augustss case 8:
787 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
788 1.1 augustss break;
789 1.1 augustss case 16:
790 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
791 1.1 augustss if (mode & AUMODE_PLAY)
792 1.7 tshiozak p->sw_code =
793 1.7 tshiozak swap_bytes_change_sign16_le;
794 1.1 augustss else
795 1.7 tshiozak p->sw_code =
796 1.7 tshiozak change_sign16_swap_bytes_le;
797 1.1 augustss break;
798 1.1 augustss default:
799 1.1 augustss return (EINVAL);
800 1.1 augustss }
801 1.1 augustss break;
802 1.1 augustss default:
803 1.1 augustss return (EINVAL);
804 1.1 augustss }
805 1.1 augustss if (mode & AUMODE_PLAY)
806 1.1 augustss cmpci_reg_partial_write_4(sc,
807 1.7 tshiozak CMPCI_REG_CHANNEL_FORMAT,
808 1.7 tshiozak CMPCI_REG_CH0_FORMAT_SHIFT,
809 1.7 tshiozak CMPCI_REG_CH0_FORMAT_MASK, md_format);
810 1.1 augustss else
811 1.1 augustss cmpci_reg_partial_write_4(sc,
812 1.7 tshiozak CMPCI_REG_CHANNEL_FORMAT,
813 1.7 tshiozak CMPCI_REG_CH1_FORMAT_SHIFT,
814 1.1 augustss CMPCI_REG_CH1_FORMAT_MASK, md_format);
815 1.1 augustss /* sample rate */
816 1.1 augustss md_index = cmpci_rate_to_index(p->sample_rate);
817 1.1 augustss md_divide = cmpci_index_to_divider(md_index);
818 1.1 augustss p->sample_rate = cmpci_index_to_rate(md_index);
819 1.1 augustss DPRINTF(("%s: sample:%d, divider=%d\n",
820 1.1 augustss sc->sc_dev.dv_xname, (int)p->sample_rate, md_divide));
821 1.1 augustss if (mode & AUMODE_PLAY) {
822 1.1 augustss cmpci_reg_partial_write_4(sc,
823 1.1 augustss CMPCI_REG_FUNC_1, CMPCI_REG_DAC_FS_SHIFT,
824 1.1 augustss CMPCI_REG_DAC_FS_MASK, md_divide);
825 1.7 tshiozak sc->sc_play.md_divide = md_divide;
826 1.1 augustss } else {
827 1.1 augustss cmpci_reg_partial_write_4(sc,
828 1.1 augustss CMPCI_REG_FUNC_1, CMPCI_REG_ADC_FS_SHIFT,
829 1.1 augustss CMPCI_REG_ADC_FS_MASK, md_divide);
830 1.7 tshiozak sc->sc_rec.md_divide = md_divide;
831 1.1 augustss }
832 1.10 itohy cmpci_set_out_ports(sc);
833 1.10 itohy cmpci_set_in_ports(sc);
834 1.1 augustss }
835 1.1 augustss return 0;
836 1.1 augustss }
837 1.1 augustss
838 1.1 augustss /* ARGSUSED */
839 1.1 augustss static int
840 1.1 augustss cmpci_round_blocksize(handle, block)
841 1.1 augustss void *handle;
842 1.1 augustss int block;
843 1.1 augustss {
844 1.1 augustss return (block & -4);
845 1.1 augustss }
846 1.1 augustss
847 1.1 augustss static int
848 1.1 augustss cmpci_halt_output(handle)
849 1.1 augustss void *handle;
850 1.1 augustss {
851 1.1 augustss struct cmpci_softc *sc = handle;
852 1.1 augustss int s;
853 1.1 augustss
854 1.1 augustss s = splaudio();
855 1.1 augustss sc->sc_play.intr = NULL;
856 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
857 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
858 1.1 augustss /* wait for reset DMA */
859 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
860 1.1 augustss delay(10);
861 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
862 1.1 augustss splx(s);
863 1.10 itohy
864 1.1 augustss return 0;
865 1.1 augustss }
866 1.1 augustss
867 1.1 augustss static int
868 1.1 augustss cmpci_halt_input(handle)
869 1.1 augustss void *handle;
870 1.1 augustss {
871 1.1 augustss struct cmpci_softc *sc = handle;
872 1.1 augustss int s;
873 1.10 itohy
874 1.1 augustss s = splaudio();
875 1.1 augustss sc->sc_rec.intr = NULL;
876 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
877 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
878 1.1 augustss /* wait for reset DMA */
879 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
880 1.1 augustss delay(10);
881 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
882 1.1 augustss splx(s);
883 1.10 itohy
884 1.1 augustss return 0;
885 1.1 augustss }
886 1.1 augustss
887 1.1 augustss
888 1.1 augustss /* get audio device information */
889 1.1 augustss static int
890 1.1 augustss cmpci_getdev(handle, ad)
891 1.7 tshiozak void *handle;
892 1.7 tshiozak struct audio_device *ad;
893 1.1 augustss {
894 1.1 augustss struct cmpci_softc *sc = handle;
895 1.1 augustss
896 1.1 augustss strncpy(ad->name, "CMI PCI Audio", sizeof(ad->name));
897 1.7 tshiozak snprintf(ad->version, sizeof(ad->version), "0x%02x",
898 1.7 tshiozak PCI_REVISION(sc->sc_class));
899 1.7 tshiozak switch (PCI_PRODUCT(sc->sc_id)) {
900 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338A:
901 1.1 augustss strncpy(ad->config, "CMI8338A", sizeof(ad->config));
902 1.1 augustss break;
903 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338B:
904 1.1 augustss strncpy(ad->config, "CMI8338B", sizeof(ad->config));
905 1.1 augustss break;
906 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8738:
907 1.1 augustss strncpy(ad->config, "CMI8738", sizeof(ad->config));
908 1.1 augustss break;
909 1.7 tshiozak case PCI_PRODUCT_CMEDIA_CMI8738B:
910 1.7 tshiozak strncpy(ad->config, "CMI8738B", sizeof(ad->config));
911 1.7 tshiozak break;
912 1.1 augustss default:
913 1.1 augustss strncpy(ad->config, "unknown", sizeof(ad->config));
914 1.1 augustss }
915 1.1 augustss
916 1.1 augustss return 0;
917 1.1 augustss }
918 1.1 augustss
919 1.1 augustss
920 1.1 augustss /* mixer device information */
921 1.1 augustss int
922 1.1 augustss cmpci_query_devinfo(handle, dip)
923 1.1 augustss void *handle;
924 1.1 augustss mixer_devinfo_t *dip;
925 1.1 augustss {
926 1.10 itohy static const char *const mixer_port_names[] = {
927 1.10 itohy AudioNdac, AudioNfmsynth, AudioNcd, AudioNline, AudioNaux,
928 1.10 itohy AudioNmicrophone
929 1.10 itohy };
930 1.10 itohy static const char *const mixer_classes[] = {
931 1.10 itohy AudioCinputs, AudioCoutputs, AudioCrecord, CmpciCplayback,
932 1.10 itohy CmpciCspdif
933 1.10 itohy };
934 1.10 itohy struct cmpci_softc *sc = handle;
935 1.10 itohy int i;
936 1.10 itohy
937 1.10 itohy dip->prev = dip->next = AUDIO_MIXER_LAST;
938 1.10 itohy
939 1.1 augustss switch (dip->index) {
940 1.10 itohy case CMPCI_INPUT_CLASS:
941 1.10 itohy case CMPCI_OUTPUT_CLASS:
942 1.10 itohy case CMPCI_RECORD_CLASS:
943 1.10 itohy case CMPCI_PLAYBACK_CLASS:
944 1.10 itohy case CMPCI_SPDIF_CLASS:
945 1.10 itohy dip->type = AUDIO_MIXER_CLASS;
946 1.10 itohy dip->mixer_class = dip->index;
947 1.10 itohy strcpy(dip->label.name,
948 1.10 itohy mixer_classes[dip->index - CMPCI_INPUT_CLASS]);
949 1.1 augustss return 0;
950 1.10 itohy
951 1.10 itohy case CMPCI_AUX_IN_VOL:
952 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_REG_AUX_VALBITS);
953 1.10 itohy goto vol1;
954 1.10 itohy case CMPCI_DAC_VOL:
955 1.1 augustss case CMPCI_FM_VOL:
956 1.10 itohy case CMPCI_CD_VOL:
957 1.10 itohy case CMPCI_LINE_IN_VOL:
958 1.10 itohy case CMPCI_MIC_VOL:
959 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS);
960 1.10 itohy vol1: dip->mixer_class = CMPCI_INPUT_CLASS;
961 1.10 itohy dip->next = dip->index + 6; /* CMPCI_xxx_MUTE */
962 1.10 itohy strcpy(dip->label.name, mixer_port_names[dip->index]);
963 1.10 itohy dip->un.v.num_channels = (dip->index == CMPCI_MIC_VOL ? 1 : 2);
964 1.10 itohy vol:
965 1.1 augustss dip->type = AUDIO_MIXER_VALUE;
966 1.1 augustss strcpy(dip->un.v.units.name, AudioNvolume);
967 1.1 augustss return 0;
968 1.10 itohy
969 1.10 itohy case CMPCI_MIC_MUTE:
970 1.10 itohy dip->next = CMPCI_MIC_PREAMP;
971 1.10 itohy /* FALLTHROUGH */
972 1.10 itohy case CMPCI_DAC_MUTE:
973 1.10 itohy case CMPCI_FM_MUTE:
974 1.10 itohy case CMPCI_CD_MUTE:
975 1.10 itohy case CMPCI_LINE_IN_MUTE:
976 1.10 itohy case CMPCI_AUX_IN_MUTE:
977 1.10 itohy dip->prev = dip->index - 6; /* CMPCI_xxx_VOL */
978 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
979 1.10 itohy strcpy(dip->label.name, AudioNmute);
980 1.10 itohy goto on_off;
981 1.10 itohy on_off:
982 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
983 1.10 itohy dip->un.e.num_mem = 2;
984 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNoff);
985 1.10 itohy dip->un.e.member[0].ord = 0;
986 1.10 itohy strcpy(dip->un.e.member[1].label.name, AudioNon);
987 1.10 itohy dip->un.e.member[1].ord = 1;
988 1.1 augustss return 0;
989 1.10 itohy
990 1.10 itohy case CMPCI_MIC_PREAMP:
991 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
992 1.10 itohy dip->prev = CMPCI_MIC_MUTE;
993 1.10 itohy strcpy(dip->label.name, AudioNpreamp);
994 1.10 itohy goto on_off;
995 1.10 itohy case CMPCI_PCSPEAKER:
996 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
997 1.10 itohy strcpy(dip->label.name, AudioNspeaker);
998 1.1 augustss dip->un.v.num_channels = 1;
999 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_SPEAKER_VALBITS);
1000 1.10 itohy goto vol;
1001 1.1 augustss case CMPCI_RECORD_SOURCE:
1002 1.1 augustss dip->mixer_class = CMPCI_RECORD_CLASS;
1003 1.1 augustss strcpy(dip->label.name, AudioNsource);
1004 1.1 augustss dip->type = AUDIO_MIXER_SET;
1005 1.10 itohy dip->un.s.num_mem = 7;
1006 1.1 augustss strcpy(dip->un.s.member[0].label.name, AudioNmicrophone);
1007 1.8 itohy dip->un.s.member[0].mask = CMPCI_RECORD_SOURCE_MIC;
1008 1.1 augustss strcpy(dip->un.s.member[1].label.name, AudioNcd);
1009 1.8 itohy dip->un.s.member[1].mask = CMPCI_RECORD_SOURCE_CD;
1010 1.1 augustss strcpy(dip->un.s.member[2].label.name, AudioNline);
1011 1.8 itohy dip->un.s.member[2].mask = CMPCI_RECORD_SOURCE_LINE_IN;
1012 1.10 itohy strcpy(dip->un.s.member[3].label.name, AudioNaux);
1013 1.10 itohy dip->un.s.member[3].mask = CMPCI_RECORD_SOURCE_AUX_IN;
1014 1.10 itohy strcpy(dip->un.s.member[4].label.name, AudioNwave);
1015 1.10 itohy dip->un.s.member[4].mask = CMPCI_RECORD_SOURCE_WAVE;
1016 1.10 itohy strcpy(dip->un.s.member[5].label.name, AudioNfmsynth);
1017 1.10 itohy dip->un.s.member[5].mask = CMPCI_RECORD_SOURCE_FM;
1018 1.10 itohy strcpy(dip->un.s.member[6].label.name, CmpciNspdif);
1019 1.10 itohy dip->un.s.member[6].mask = CMPCI_RECORD_SOURCE_SPDIF;
1020 1.1 augustss return 0;
1021 1.10 itohy case CMPCI_MIC_RECVOL:
1022 1.1 augustss dip->mixer_class = CMPCI_RECORD_CLASS;
1023 1.10 itohy strcpy(dip->label.name, AudioNmicrophone);
1024 1.1 augustss dip->un.v.num_channels = 1;
1025 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_REG_ADMIC_VALBITS);
1026 1.10 itohy goto vol;
1027 1.10 itohy
1028 1.10 itohy case CMPCI_PLAYBACK_MODE:
1029 1.10 itohy dip->mixer_class = CMPCI_PLAYBACK_CLASS;
1030 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
1031 1.10 itohy strcpy(dip->label.name, AudioNmode);
1032 1.10 itohy dip->un.e.num_mem = 2;
1033 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNdac);
1034 1.10 itohy dip->un.e.member[0].ord = CMPCI_PLAYBACK_MODE_WAVE;
1035 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdif);
1036 1.10 itohy dip->un.e.member[1].ord = CMPCI_PLAYBACK_MODE_SPDIF;
1037 1.1 augustss return 0;
1038 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1039 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
1040 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
1041 1.10 itohy dip->next = CMPCI_SPDIF_IN_PHASE;
1042 1.1 augustss strcpy(dip->label.name, AudioNinput);
1043 1.10 itohy i = 0;
1044 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdin1);
1045 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN1;
1046 1.10 itohy if (CMPCI_ISCAP(sc, 2ND_SPDIN)) {
1047 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdin2);
1048 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN2;
1049 1.10 itohy }
1050 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdout);
1051 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDOUT;
1052 1.10 itohy dip->un.e.num_mem = i;
1053 1.10 itohy return 0;
1054 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
1055 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
1056 1.10 itohy dip->prev = CMPCI_SPDIF_IN_SELECT;
1057 1.10 itohy strcpy(dip->label.name, CmpciNphase);
1058 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
1059 1.10 itohy dip->un.e.num_mem = 2;
1060 1.10 itohy strcpy(dip->un.e.member[0].label.name, CmpciNpositive);
1061 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_IN_PHASE_POSITIVE;
1062 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNnegative);
1063 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_IN_PHASE_NEGATIVE;
1064 1.1 augustss return 0;
1065 1.10 itohy case CMPCI_SPDIF_LOOP:
1066 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
1067 1.10 itohy dip->next = CMPCI_SPDIF_OUT_PLAYBACK;
1068 1.1 augustss strcpy(dip->label.name, AudioNoutput);
1069 1.1 augustss dip->type = AUDIO_MIXER_ENUM;
1070 1.10 itohy dip->un.e.num_mem = 2;
1071 1.10 itohy strcpy(dip->un.e.member[0].label.name, CmpciNplayback);
1072 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_LOOP_OFF;
1073 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdin);
1074 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_LOOP_ON;
1075 1.7 tshiozak return 0;
1076 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1077 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
1078 1.10 itohy dip->prev = CMPCI_SPDIF_LOOP;
1079 1.10 itohy dip->next = CMPCI_SPDIF_OUT_VOLTAGE;
1080 1.10 itohy strcpy(dip->label.name, CmpciNplayback);
1081 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
1082 1.10 itohy dip->un.e.num_mem = 2;
1083 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNwave);
1084 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_PLAYBACK_WAVE;
1085 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNlegacy);
1086 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_PLAYBACK_LEGACY;
1087 1.7 tshiozak return 0;
1088 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1089 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
1090 1.10 itohy dip->prev = CMPCI_SPDIF_OUT_PLAYBACK;
1091 1.10 itohy strcpy(dip->label.name, CmpciNvoltage);
1092 1.7 tshiozak dip->type = AUDIO_MIXER_ENUM;
1093 1.7 tshiozak dip->un.e.num_mem = 2;
1094 1.21 itohy strcpy(dip->un.e.member[0].label.name, CmpciNhigh_v);
1095 1.21 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_VOLTAGE_HIGH;
1096 1.21 itohy strcpy(dip->un.e.member[1].label.name, CmpciNlow_v);
1097 1.21 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_VOLTAGE_LOW;
1098 1.7 tshiozak return 0;
1099 1.10 itohy case CMPCI_MONITOR_DAC:
1100 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
1101 1.10 itohy strcpy(dip->label.name, AudioNmonitor);
1102 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
1103 1.10 itohy dip->un.e.num_mem = 3;
1104 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNoff);
1105 1.10 itohy dip->un.e.member[0].ord = CMPCI_MONITOR_DAC_OFF;
1106 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdin);
1107 1.10 itohy dip->un.e.member[1].ord = CMPCI_MONITOR_DAC_SPDIN;
1108 1.10 itohy strcpy(dip->un.e.member[2].label.name, CmpciNspdout);
1109 1.10 itohy dip->un.e.member[2].ord = CMPCI_MONITOR_DAC_SPDOUT;
1110 1.10 itohy return 0;
1111 1.10 itohy
1112 1.10 itohy case CMPCI_MASTER_VOL:
1113 1.10 itohy dip->mixer_class = CMPCI_OUTPUT_CLASS;
1114 1.10 itohy strcpy(dip->label.name, AudioNmaster);
1115 1.10 itohy dip->un.v.num_channels = 2;
1116 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS);
1117 1.10 itohy goto vol;
1118 1.7 tshiozak case CMPCI_REAR:
1119 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1120 1.7 tshiozak dip->next = CMPCI_INDIVIDUAL;
1121 1.7 tshiozak strcpy(dip->label.name, CmpciNrear);
1122 1.7 tshiozak goto on_off;
1123 1.7 tshiozak case CMPCI_INDIVIDUAL:
1124 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1125 1.7 tshiozak dip->prev = CMPCI_REAR;
1126 1.7 tshiozak dip->next = CMPCI_REVERSE;
1127 1.7 tshiozak strcpy(dip->label.name, CmpciNindividual);
1128 1.7 tshiozak goto on_off;
1129 1.7 tshiozak case CMPCI_REVERSE:
1130 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1131 1.7 tshiozak dip->prev = CMPCI_INDIVIDUAL;
1132 1.7 tshiozak strcpy(dip->label.name, CmpciNreverse);
1133 1.10 itohy goto on_off;
1134 1.7 tshiozak case CMPCI_SURROUND:
1135 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1136 1.7 tshiozak strcpy(dip->label.name, CmpciNsurround);
1137 1.7 tshiozak goto on_off;
1138 1.10 itohy }
1139 1.7 tshiozak
1140 1.1 augustss return ENXIO;
1141 1.1 augustss }
1142 1.1 augustss
1143 1.1 augustss static int
1144 1.1 augustss cmpci_alloc_dmamem(sc, size, type, flags, r_addr)
1145 1.1 augustss struct cmpci_softc *sc;
1146 1.1 augustss size_t size;
1147 1.18 thorpej struct malloc_type *type;
1148 1.18 thorpej int flags;
1149 1.1 augustss caddr_t *r_addr;
1150 1.1 augustss {
1151 1.1 augustss int error = 0;
1152 1.1 augustss struct cmpci_dmanode *n;
1153 1.1 augustss int w;
1154 1.1 augustss
1155 1.1 augustss n = malloc(sizeof(struct cmpci_dmanode), type, flags);
1156 1.1 augustss if (n == NULL) {
1157 1.1 augustss error = ENOMEM;
1158 1.1 augustss goto quit;
1159 1.1 augustss }
1160 1.1 augustss
1161 1.1 augustss w = (flags & M_NOWAIT) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK;
1162 1.1 augustss #define CMPCI_DMABUF_ALIGN 0x4
1163 1.1 augustss #define CMPCI_DMABUF_BOUNDARY 0x0
1164 1.1 augustss n->cd_tag = sc->sc_dmat;
1165 1.1 augustss n->cd_size = size;
1166 1.1 augustss error = bus_dmamem_alloc(n->cd_tag, n->cd_size,
1167 1.1 augustss CMPCI_DMABUF_ALIGN, CMPCI_DMABUF_BOUNDARY, n->cd_segs,
1168 1.7 tshiozak sizeof(n->cd_segs)/sizeof(n->cd_segs[0]), &n->cd_nsegs, w);
1169 1.1 augustss if (error)
1170 1.1 augustss goto mfree;
1171 1.1 augustss error = bus_dmamem_map(n->cd_tag, n->cd_segs, n->cd_nsegs, n->cd_size,
1172 1.1 augustss &n->cd_addr, w | BUS_DMA_COHERENT);
1173 1.1 augustss if (error)
1174 1.1 augustss goto dmafree;
1175 1.1 augustss error = bus_dmamap_create(n->cd_tag, n->cd_size, 1, n->cd_size, 0,
1176 1.1 augustss w, &n->cd_map);
1177 1.1 augustss if (error)
1178 1.1 augustss goto unmap;
1179 1.1 augustss error = bus_dmamap_load(n->cd_tag, n->cd_map, n->cd_addr, n->cd_size,
1180 1.1 augustss NULL, w);
1181 1.1 augustss if (error)
1182 1.1 augustss goto destroy;
1183 1.10 itohy
1184 1.1 augustss n->cd_next = sc->sc_dmap;
1185 1.1 augustss sc->sc_dmap = n;
1186 1.1 augustss *r_addr = KVADDR(n);
1187 1.1 augustss return 0;
1188 1.10 itohy
1189 1.1 augustss destroy:
1190 1.1 augustss bus_dmamap_destroy(n->cd_tag, n->cd_map);
1191 1.1 augustss unmap:
1192 1.1 augustss bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size);
1193 1.1 augustss dmafree:
1194 1.1 augustss bus_dmamem_free(n->cd_tag,
1195 1.1 augustss n->cd_segs, sizeof(n->cd_segs)/sizeof(n->cd_segs[0]));
1196 1.1 augustss mfree:
1197 1.1 augustss free(n, type);
1198 1.1 augustss quit:
1199 1.1 augustss return error;
1200 1.1 augustss }
1201 1.1 augustss
1202 1.1 augustss static int
1203 1.1 augustss cmpci_free_dmamem(sc, addr, type)
1204 1.1 augustss struct cmpci_softc *sc;
1205 1.1 augustss caddr_t addr;
1206 1.18 thorpej struct malloc_type *type;
1207 1.1 augustss {
1208 1.1 augustss struct cmpci_dmanode **nnp;
1209 1.10 itohy
1210 1.1 augustss for (nnp = &sc->sc_dmap; *nnp; nnp= &(*nnp)->cd_next) {
1211 1.1 augustss if ((*nnp)->cd_addr == addr) {
1212 1.1 augustss struct cmpci_dmanode *n = *nnp;
1213 1.1 augustss bus_dmamap_unload(n->cd_tag, n->cd_map);
1214 1.1 augustss bus_dmamap_destroy(n->cd_tag, n->cd_map);
1215 1.1 augustss bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size);
1216 1.1 augustss bus_dmamem_free(n->cd_tag, n->cd_segs,
1217 1.1 augustss sizeof(n->cd_segs)/sizeof(n->cd_segs[0]));
1218 1.1 augustss free(n, type);
1219 1.1 augustss return 0;
1220 1.1 augustss }
1221 1.1 augustss }
1222 1.1 augustss return -1;
1223 1.1 augustss }
1224 1.1 augustss
1225 1.1 augustss static struct cmpci_dmanode *
1226 1.1 augustss cmpci_find_dmamem(sc, addr)
1227 1.1 augustss struct cmpci_softc *sc;
1228 1.1 augustss caddr_t addr;
1229 1.1 augustss {
1230 1.1 augustss struct cmpci_dmanode *p;
1231 1.10 itohy
1232 1.1 augustss for (p=sc->sc_dmap; p; p=p->cd_next)
1233 1.1 augustss if ( KVADDR(p) == (void *)addr )
1234 1.1 augustss break;
1235 1.1 augustss return p;
1236 1.1 augustss }
1237 1.1 augustss
1238 1.1 augustss
1239 1.1 augustss #if 0
1240 1.1 augustss static void
1241 1.1 augustss cmpci_print_dmamem __P((struct cmpci_dmanode *p));
1242 1.1 augustss static void
1243 1.1 augustss cmpci_print_dmamem(p)
1244 1.1 augustss struct cmpci_dmanode *p;
1245 1.1 augustss {
1246 1.1 augustss DPRINTF(("DMA at virt:%p, dmaseg:%p, mapseg:%p, size:%p\n",
1247 1.1 augustss (void *)p->cd_addr, (void *)p->cd_segs[0].ds_addr,
1248 1.1 augustss (void *)DMAADDR(p), (void *)p->cd_size));
1249 1.1 augustss }
1250 1.1 augustss #endif /* DEBUG */
1251 1.1 augustss
1252 1.1 augustss
1253 1.1 augustss static void *
1254 1.1 augustss cmpci_allocm(handle, direction, size, type, flags)
1255 1.1 augustss void *handle;
1256 1.1 augustss int direction;
1257 1.1 augustss size_t size;
1258 1.18 thorpej struct malloc_type *type;
1259 1.18 thorpej int flags;
1260 1.1 augustss {
1261 1.1 augustss struct cmpci_softc *sc = handle;
1262 1.1 augustss caddr_t addr;
1263 1.10 itohy
1264 1.1 augustss if (cmpci_alloc_dmamem(sc, size, type, flags, &addr))
1265 1.1 augustss return NULL;
1266 1.1 augustss return addr;
1267 1.1 augustss }
1268 1.1 augustss
1269 1.1 augustss static void
1270 1.1 augustss cmpci_freem(handle, addr, type)
1271 1.7 tshiozak void *handle;
1272 1.7 tshiozak void *addr;
1273 1.18 thorpej struct malloc_type *type;
1274 1.1 augustss {
1275 1.1 augustss struct cmpci_softc *sc = handle;
1276 1.10 itohy
1277 1.1 augustss cmpci_free_dmamem(sc, addr, type);
1278 1.1 augustss }
1279 1.1 augustss
1280 1.1 augustss
1281 1.1 augustss #define MAXVAL 256
1282 1.1 augustss static int
1283 1.1 augustss cmpci_adjust(val, mask)
1284 1.1 augustss int val, mask;
1285 1.1 augustss {
1286 1.1 augustss val += (MAXVAL - mask) >> 1;
1287 1.1 augustss if (val >= MAXVAL)
1288 1.1 augustss val = MAXVAL-1;
1289 1.1 augustss return val & mask;
1290 1.1 augustss }
1291 1.1 augustss
1292 1.1 augustss static void
1293 1.1 augustss cmpci_set_mixer_gain(sc, port)
1294 1.1 augustss struct cmpci_softc *sc;
1295 1.1 augustss int port;
1296 1.1 augustss {
1297 1.20 christos int src = 0; /* XXX: gcc */
1298 1.10 itohy int bits, mask;
1299 1.1 augustss
1300 1.1 augustss switch (port) {
1301 1.1 augustss case CMPCI_MIC_VOL:
1302 1.10 itohy cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_MIC,
1303 1.10 itohy CMPCI_ADJUST_MIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1304 1.1 augustss break;
1305 1.1 augustss case CMPCI_MASTER_VOL:
1306 1.1 augustss src = CMPCI_SB16_MIXER_MASTER_L;
1307 1.1 augustss break;
1308 1.1 augustss case CMPCI_LINE_IN_VOL:
1309 1.1 augustss src = CMPCI_SB16_MIXER_LINE_L;
1310 1.1 augustss break;
1311 1.10 itohy case CMPCI_AUX_IN_VOL:
1312 1.10 itohy bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MIXER_AUX,
1313 1.10 itohy CMPCI_ADJUST_AUX_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT],
1314 1.10 itohy sc->sc_gain[port][CMPCI_RIGHT]));
1315 1.10 itohy return;
1316 1.10 itohy case CMPCI_MIC_RECVOL:
1317 1.10 itohy cmpci_reg_partial_write_1(sc, CMPCI_REG_MIXER25,
1318 1.10 itohy CMPCI_REG_ADMIC_SHIFT, CMPCI_REG_ADMIC_MASK,
1319 1.10 itohy CMPCI_ADJUST_ADMIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1320 1.10 itohy return;
1321 1.10 itohy case CMPCI_DAC_VOL:
1322 1.1 augustss src = CMPCI_SB16_MIXER_VOICE_L;
1323 1.1 augustss break;
1324 1.1 augustss case CMPCI_FM_VOL:
1325 1.1 augustss src = CMPCI_SB16_MIXER_FM_L;
1326 1.1 augustss break;
1327 1.1 augustss case CMPCI_CD_VOL:
1328 1.1 augustss src = CMPCI_SB16_MIXER_CDDA_L;
1329 1.1 augustss break;
1330 1.1 augustss case CMPCI_PCSPEAKER:
1331 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_SPEAKER,
1332 1.10 itohy CMPCI_ADJUST_2_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1333 1.10 itohy return;
1334 1.10 itohy case CMPCI_MIC_PREAMP:
1335 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1336 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1337 1.10 itohy CMPCI_REG_MICGAINZ);
1338 1.10 itohy else
1339 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1340 1.10 itohy CMPCI_REG_MICGAINZ);
1341 1.7 tshiozak return;
1342 1.10 itohy
1343 1.10 itohy case CMPCI_DAC_MUTE:
1344 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1345 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1346 1.10 itohy CMPCI_REG_WSMUTE);
1347 1.10 itohy else
1348 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1349 1.10 itohy CMPCI_REG_WSMUTE);
1350 1.10 itohy return;
1351 1.10 itohy case CMPCI_FM_MUTE:
1352 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1353 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1354 1.10 itohy CMPCI_REG_FMMUTE);
1355 1.10 itohy else
1356 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1357 1.10 itohy CMPCI_REG_FMMUTE);
1358 1.10 itohy return;
1359 1.10 itohy case CMPCI_AUX_IN_MUTE:
1360 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1361 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1362 1.10 itohy CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM);
1363 1.10 itohy else
1364 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1365 1.10 itohy CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM);
1366 1.10 itohy return;
1367 1.10 itohy case CMPCI_CD_MUTE:
1368 1.10 itohy mask = CMPCI_SB16_SW_CD;
1369 1.10 itohy goto sbmute;
1370 1.10 itohy case CMPCI_MIC_MUTE:
1371 1.10 itohy mask = CMPCI_SB16_SW_MIC;
1372 1.10 itohy goto sbmute;
1373 1.10 itohy case CMPCI_LINE_IN_MUTE:
1374 1.10 itohy mask = CMPCI_SB16_SW_LINE;
1375 1.10 itohy sbmute:
1376 1.10 itohy bits = cmpci_mixerreg_read(sc, CMPCI_SB16_MIXER_OUTMIX);
1377 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1378 1.10 itohy bits = bits & ~mask;
1379 1.10 itohy else
1380 1.10 itohy bits = bits | mask;
1381 1.10 itohy cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX, bits);
1382 1.8 itohy return;
1383 1.10 itohy
1384 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1385 1.10 itohy case CMPCI_MONITOR_DAC:
1386 1.10 itohy case CMPCI_PLAYBACK_MODE:
1387 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1388 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1389 1.7 tshiozak cmpci_set_out_ports(sc);
1390 1.7 tshiozak return;
1391 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1392 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDOUT_VOLTAGE)) {
1393 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_OUT_VOLTAGE][CMPCI_LR]
1394 1.21 itohy == CMPCI_SPDIF_OUT_VOLTAGE_HIGH)
1395 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_5V);
1396 1.10 itohy else
1397 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_5V);
1398 1.7 tshiozak }
1399 1.7 tshiozak return;
1400 1.7 tshiozak case CMPCI_SURROUND:
1401 1.7 tshiozak if (CMPCI_ISCAP(sc, SURROUND)) {
1402 1.7 tshiozak if (sc->sc_gain[CMPCI_SURROUND][CMPCI_LR])
1403 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1404 1.7 tshiozak CMPCI_REG_SURROUND);
1405 1.7 tshiozak else
1406 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1407 1.7 tshiozak CMPCI_REG_SURROUND);
1408 1.7 tshiozak }
1409 1.7 tshiozak return;
1410 1.7 tshiozak case CMPCI_REAR:
1411 1.7 tshiozak if (CMPCI_ISCAP(sc, REAR)) {
1412 1.7 tshiozak if (sc->sc_gain[CMPCI_REAR][CMPCI_LR])
1413 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_N4SPK3D);
1414 1.7 tshiozak else
1415 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_N4SPK3D);
1416 1.7 tshiozak }
1417 1.7 tshiozak return;
1418 1.7 tshiozak case CMPCI_INDIVIDUAL:
1419 1.7 tshiozak if (CMPCI_ISCAP(sc, INDIVIDUAL_REAR)) {
1420 1.7 tshiozak if (sc->sc_gain[CMPCI_REAR][CMPCI_LR])
1421 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1422 1.7 tshiozak CMPCI_REG_INDIVIDUAL);
1423 1.7 tshiozak else
1424 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1425 1.7 tshiozak CMPCI_REG_INDIVIDUAL);
1426 1.7 tshiozak }
1427 1.7 tshiozak return;
1428 1.7 tshiozak case CMPCI_REVERSE:
1429 1.7 tshiozak if (CMPCI_ISCAP(sc, REVERSE_FR)) {
1430 1.7 tshiozak if (sc->sc_gain[CMPCI_REVERSE][CMPCI_LR])
1431 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1432 1.7 tshiozak CMPCI_REG_REVERSE_FR);
1433 1.7 tshiozak else
1434 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1435 1.7 tshiozak CMPCI_REG_REVERSE_FR);
1436 1.7 tshiozak }
1437 1.7 tshiozak return;
1438 1.7 tshiozak case CMPCI_SPDIF_IN_PHASE:
1439 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDIN_PHASE)) {
1440 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_IN_PHASE][CMPCI_LR]
1441 1.10 itohy == CMPCI_SPDIF_IN_PHASE_POSITIVE)
1442 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_CHANNEL_FORMAT,
1443 1.10 itohy CMPCI_REG_SPDIN_PHASE);
1444 1.10 itohy else
1445 1.8 itohy cmpci_reg_set_1(sc, CMPCI_REG_CHANNEL_FORMAT,
1446 1.8 itohy CMPCI_REG_SPDIN_PHASE);
1447 1.7 tshiozak }
1448 1.1 augustss return;
1449 1.1 augustss default:
1450 1.1 augustss return;
1451 1.1 augustss }
1452 1.10 itohy
1453 1.10 itohy cmpci_mixerreg_write(sc, src,
1454 1.10 itohy CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT]));
1455 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_L_TO_R(src),
1456 1.10 itohy CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_RIGHT]));
1457 1.7 tshiozak }
1458 1.7 tshiozak
1459 1.7 tshiozak static void
1460 1.7 tshiozak cmpci_set_out_ports(sc)
1461 1.7 tshiozak struct cmpci_softc *sc;
1462 1.7 tshiozak {
1463 1.10 itohy u_int8_t v;
1464 1.10 itohy int enspdout = 0;
1465 1.10 itohy
1466 1.7 tshiozak if (!CMPCI_ISCAP(sc, SPDLOOP))
1467 1.7 tshiozak return;
1468 1.10 itohy
1469 1.10 itohy /* SPDIF/out select */
1470 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_LOOP][CMPCI_LR] == CMPCI_SPDIF_LOOP_OFF) {
1471 1.10 itohy /* playback */
1472 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
1473 1.10 itohy } else {
1474 1.10 itohy /* monitor SPDIF/in */
1475 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
1476 1.10 itohy }
1477 1.10 itohy
1478 1.10 itohy /* SPDIF in select */
1479 1.10 itohy v = sc->sc_gain[CMPCI_SPDIF_IN_SELECT][CMPCI_LR];
1480 1.10 itohy if (v & CMPCI_SPDIFIN_SPDIFIN2)
1481 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_2ND_SPDIFIN);
1482 1.10 itohy else
1483 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_2ND_SPDIFIN);
1484 1.10 itohy if (v & CMPCI_SPDIFIN_SPDIFOUT)
1485 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_SPDFLOOPI);
1486 1.10 itohy else
1487 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_SPDFLOOPI);
1488 1.10 itohy
1489 1.10 itohy /* playback to ... */
1490 1.10 itohy if (CMPCI_ISCAP(sc, SPDOUT) &&
1491 1.10 itohy sc->sc_gain[CMPCI_PLAYBACK_MODE][CMPCI_LR]
1492 1.10 itohy == CMPCI_PLAYBACK_MODE_SPDIF &&
1493 1.10 itohy (sc->sc_play.md_divide == CMPCI_REG_RATE_44100 ||
1494 1.10 itohy (CMPCI_ISCAP(sc, SPDOUT_48K) &&
1495 1.10 itohy sc->sc_play.md_divide==CMPCI_REG_RATE_48000))) {
1496 1.10 itohy /* playback to SPDIF */
1497 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF0_ENABLE);
1498 1.10 itohy enspdout = 1;
1499 1.10 itohy if (sc->sc_play.md_divide==CMPCI_REG_RATE_48000)
1500 1.21 itohy cmpci_reg_set_reg_misc(sc,
1501 1.21 itohy CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K);
1502 1.10 itohy else
1503 1.21 itohy cmpci_reg_clear_reg_misc(sc,
1504 1.21 itohy CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K);
1505 1.10 itohy } else {
1506 1.10 itohy /* playback to DAC */
1507 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1,
1508 1.10 itohy CMPCI_REG_SPDIF0_ENABLE);
1509 1.10 itohy if (CMPCI_ISCAP(sc, SPDOUT_48K))
1510 1.21 itohy cmpci_reg_clear_reg_misc(sc,
1511 1.21 itohy CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K);
1512 1.10 itohy }
1513 1.10 itohy
1514 1.10 itohy /* legacy to SPDIF/out or not */
1515 1.10 itohy if (CMPCI_ISCAP(sc, SPDLEGACY)) {
1516 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_OUT_PLAYBACK][CMPCI_LR]
1517 1.10 itohy == CMPCI_SPDIF_OUT_PLAYBACK_WAVE)
1518 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL,
1519 1.10 itohy CMPCI_REG_LEGACY_SPDIF_ENABLE);
1520 1.10 itohy else {
1521 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL,
1522 1.10 itohy CMPCI_REG_LEGACY_SPDIF_ENABLE);
1523 1.10 itohy enspdout = 1;
1524 1.10 itohy }
1525 1.10 itohy }
1526 1.10 itohy
1527 1.10 itohy /* enable/disable SPDIF/out */
1528 1.10 itohy if (CMPCI_ISCAP(sc, XSPDOUT) && enspdout)
1529 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL,
1530 1.10 itohy CMPCI_REG_XSPDIF_ENABLE);
1531 1.10 itohy else
1532 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL,
1533 1.10 itohy CMPCI_REG_XSPDIF_ENABLE);
1534 1.10 itohy
1535 1.10 itohy /* SPDIF monitor (digital to alalog output) */
1536 1.10 itohy if (CMPCI_ISCAP(sc, SPDIN_MONITOR)) {
1537 1.10 itohy v = sc->sc_gain[CMPCI_MONITOR_DAC][CMPCI_LR];
1538 1.10 itohy if (!(v & CMPCI_MONDAC_ENABLE))
1539 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1540 1.10 itohy CMPCI_REG_SPDIN_MONITOR);
1541 1.10 itohy if (v & CMPCI_MONDAC_SPDOUT)
1542 1.7 tshiozak cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1,
1543 1.10 itohy CMPCI_REG_SPDIFOUT_DAC);
1544 1.10 itohy else
1545 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1,
1546 1.10 itohy CMPCI_REG_SPDIFOUT_DAC);
1547 1.10 itohy if (v & CMPCI_MONDAC_ENABLE)
1548 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1549 1.10 itohy CMPCI_REG_SPDIN_MONITOR);
1550 1.7 tshiozak }
1551 1.1 augustss }
1552 1.1 augustss
1553 1.1 augustss static int
1554 1.10 itohy cmpci_set_in_ports(sc)
1555 1.1 augustss struct cmpci_softc *sc;
1556 1.10 itohy {
1557 1.1 augustss int mask;
1558 1.1 augustss int bitsl, bitsr;
1559 1.1 augustss
1560 1.10 itohy mask = sc->sc_in_mask;
1561 1.10 itohy
1562 1.10 itohy /*
1563 1.10 itohy * Note CMPCI_RECORD_SOURCE_CD, CMPCI_RECORD_SOURCE_LINE_IN and
1564 1.10 itohy * CMPCI_RECORD_SOURCE_FM are defined to the corresponding bit
1565 1.10 itohy * of the mixer register.
1566 1.10 itohy */
1567 1.10 itohy bitsr = mask & (CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |
1568 1.10 itohy CMPCI_RECORD_SOURCE_FM);
1569 1.10 itohy
1570 1.1 augustss bitsl = CMPCI_SB16_MIXER_SRC_R_TO_L(bitsr);
1571 1.8 itohy if (mask & CMPCI_RECORD_SOURCE_MIC) {
1572 1.1 augustss bitsl |= CMPCI_SB16_MIXER_MIC_SRC;
1573 1.1 augustss bitsr |= CMPCI_SB16_MIXER_MIC_SRC;
1574 1.1 augustss }
1575 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, bitsl);
1576 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, bitsr);
1577 1.10 itohy
1578 1.10 itohy if (mask & CMPCI_RECORD_SOURCE_AUX_IN)
1579 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1580 1.10 itohy CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN);
1581 1.10 itohy else
1582 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1583 1.10 itohy CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN);
1584 1.10 itohy
1585 1.10 itohy if (mask & CMPCI_RECORD_SOURCE_WAVE)
1586 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1587 1.10 itohy CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR);
1588 1.10 itohy else
1589 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1590 1.10 itohy CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR);
1591 1.10 itohy
1592 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDIN) &&
1593 1.10 itohy (sc->sc_rec.md_divide == CMPCI_REG_RATE_44100 ||
1594 1.10 itohy (CMPCI_ISCAP(sc, SPDOUT_48K) &&
1595 1.10 itohy sc->sc_rec.md_divide == CMPCI_REG_RATE_48000/* XXX? */))) {
1596 1.8 itohy if (mask & CMPCI_RECORD_SOURCE_SPDIF) {
1597 1.7 tshiozak /* enable SPDIF/in */
1598 1.7 tshiozak cmpci_reg_set_4(sc,
1599 1.7 tshiozak CMPCI_REG_FUNC_1,
1600 1.7 tshiozak CMPCI_REG_SPDIF1_ENABLE);
1601 1.7 tshiozak } else {
1602 1.7 tshiozak cmpci_reg_clear_4(sc,
1603 1.7 tshiozak CMPCI_REG_FUNC_1,
1604 1.7 tshiozak CMPCI_REG_SPDIF1_ENABLE);
1605 1.7 tshiozak }
1606 1.7 tshiozak }
1607 1.1 augustss
1608 1.1 augustss return 0;
1609 1.1 augustss }
1610 1.1 augustss
1611 1.1 augustss static int
1612 1.1 augustss cmpci_set_port(handle, cp)
1613 1.1 augustss void *handle;
1614 1.1 augustss mixer_ctrl_t *cp;
1615 1.1 augustss {
1616 1.1 augustss struct cmpci_softc *sc = handle;
1617 1.1 augustss int lgain, rgain;
1618 1.10 itohy
1619 1.1 augustss switch (cp->dev) {
1620 1.10 itohy case CMPCI_MIC_VOL:
1621 1.1 augustss case CMPCI_PCSPEAKER:
1622 1.10 itohy case CMPCI_MIC_RECVOL:
1623 1.10 itohy if (cp->un.value.num_channels != 1)
1624 1.10 itohy return EINVAL;
1625 1.10 itohy /* FALLTHROUGH */
1626 1.10 itohy case CMPCI_DAC_VOL:
1627 1.1 augustss case CMPCI_FM_VOL:
1628 1.1 augustss case CMPCI_CD_VOL:
1629 1.10 itohy case CMPCI_LINE_IN_VOL:
1630 1.10 itohy case CMPCI_AUX_IN_VOL:
1631 1.1 augustss case CMPCI_MASTER_VOL:
1632 1.1 augustss if (cp->type != AUDIO_MIXER_VALUE)
1633 1.1 augustss return EINVAL;
1634 1.10 itohy switch (cp->un.value.num_channels) {
1635 1.10 itohy case 1:
1636 1.1 augustss lgain = rgain =
1637 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_MONO];
1638 1.1 augustss break;
1639 1.10 itohy case 2:
1640 1.10 itohy lgain = cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT];
1641 1.10 itohy rgain = cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT];
1642 1.1 augustss break;
1643 1.1 augustss default:
1644 1.10 itohy return EINVAL;
1645 1.1 augustss }
1646 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT] = lgain;
1647 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_RIGHT] = rgain;
1648 1.1 augustss
1649 1.1 augustss cmpci_set_mixer_gain(sc, cp->dev);
1650 1.1 augustss break;
1651 1.1 augustss
1652 1.1 augustss case CMPCI_RECORD_SOURCE:
1653 1.1 augustss if (cp->type != AUDIO_MIXER_SET)
1654 1.1 augustss return EINVAL;
1655 1.8 itohy
1656 1.10 itohy if (cp->un.mask & ~(CMPCI_RECORD_SOURCE_MIC |
1657 1.10 itohy CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |
1658 1.10 itohy CMPCI_RECORD_SOURCE_AUX_IN | CMPCI_RECORD_SOURCE_WAVE |
1659 1.10 itohy CMPCI_RECORD_SOURCE_FM | CMPCI_RECORD_SOURCE_SPDIF))
1660 1.10 itohy return EINVAL;
1661 1.10 itohy
1662 1.8 itohy if (cp->un.mask & CMPCI_RECORD_SOURCE_SPDIF)
1663 1.8 itohy cp->un.mask = CMPCI_RECORD_SOURCE_SPDIF;
1664 1.8 itohy
1665 1.10 itohy sc->sc_in_mask = cp->un.mask;
1666 1.10 itohy return cmpci_set_in_ports(sc);
1667 1.1 augustss
1668 1.10 itohy /* boolean */
1669 1.10 itohy case CMPCI_DAC_MUTE:
1670 1.10 itohy case CMPCI_FM_MUTE:
1671 1.10 itohy case CMPCI_CD_MUTE:
1672 1.10 itohy case CMPCI_LINE_IN_MUTE:
1673 1.10 itohy case CMPCI_AUX_IN_MUTE:
1674 1.10 itohy case CMPCI_MIC_MUTE:
1675 1.10 itohy case CMPCI_MIC_PREAMP:
1676 1.10 itohy case CMPCI_PLAYBACK_MODE:
1677 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
1678 1.10 itohy case CMPCI_SPDIF_LOOP:
1679 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1680 1.10 itohy case CMPCI_SPDIF_OUT_VOLTAGE:
1681 1.10 itohy case CMPCI_REAR:
1682 1.10 itohy case CMPCI_INDIVIDUAL:
1683 1.10 itohy case CMPCI_REVERSE:
1684 1.10 itohy case CMPCI_SURROUND:
1685 1.1 augustss if (cp->type != AUDIO_MIXER_ENUM)
1686 1.1 augustss return EINVAL;
1687 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord != 0;
1688 1.10 itohy cmpci_set_mixer_gain(sc, cp->dev);
1689 1.1 augustss break;
1690 1.1 augustss
1691 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1692 1.10 itohy switch (cp->un.ord) {
1693 1.10 itohy case CMPCI_SPDIF_IN_SPDIN1:
1694 1.10 itohy case CMPCI_SPDIF_IN_SPDIN2:
1695 1.10 itohy case CMPCI_SPDIF_IN_SPDOUT:
1696 1.10 itohy break;
1697 1.10 itohy default:
1698 1.1 augustss return EINVAL;
1699 1.1 augustss }
1700 1.10 itohy goto xenum;
1701 1.10 itohy case CMPCI_MONITOR_DAC:
1702 1.10 itohy switch (cp->un.ord) {
1703 1.10 itohy case CMPCI_MONITOR_DAC_OFF:
1704 1.10 itohy case CMPCI_MONITOR_DAC_SPDIN:
1705 1.10 itohy case CMPCI_MONITOR_DAC_SPDOUT:
1706 1.10 itohy break;
1707 1.10 itohy default:
1708 1.10 itohy return EINVAL;
1709 1.1 augustss }
1710 1.10 itohy xenum:
1711 1.10 itohy if (cp->type != AUDIO_MIXER_ENUM)
1712 1.10 itohy return EINVAL;
1713 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord;
1714 1.10 itohy cmpci_set_mixer_gain(sc, cp->dev);
1715 1.7 tshiozak break;
1716 1.10 itohy
1717 1.1 augustss default:
1718 1.1 augustss return EINVAL;
1719 1.1 augustss }
1720 1.10 itohy
1721 1.1 augustss return 0;
1722 1.1 augustss }
1723 1.1 augustss
1724 1.1 augustss static int
1725 1.1 augustss cmpci_get_port(handle, cp)
1726 1.1 augustss void *handle;
1727 1.1 augustss mixer_ctrl_t *cp;
1728 1.1 augustss {
1729 1.1 augustss struct cmpci_softc *sc = handle;
1730 1.10 itohy
1731 1.1 augustss switch (cp->dev) {
1732 1.1 augustss case CMPCI_MIC_VOL:
1733 1.10 itohy case CMPCI_PCSPEAKER:
1734 1.10 itohy case CMPCI_MIC_RECVOL:
1735 1.1 augustss if (cp->un.value.num_channels != 1)
1736 1.1 augustss return EINVAL;
1737 1.12 itohy /*FALLTHROUGH*/
1738 1.10 itohy case CMPCI_DAC_VOL:
1739 1.1 augustss case CMPCI_FM_VOL:
1740 1.1 augustss case CMPCI_CD_VOL:
1741 1.10 itohy case CMPCI_LINE_IN_VOL:
1742 1.10 itohy case CMPCI_AUX_IN_VOL:
1743 1.1 augustss case CMPCI_MASTER_VOL:
1744 1.1 augustss switch (cp->un.value.num_channels) {
1745 1.1 augustss case 1:
1746 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
1747 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT];
1748 1.1 augustss break;
1749 1.1 augustss case 2:
1750 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
1751 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT];
1752 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
1753 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_RIGHT];
1754 1.1 augustss break;
1755 1.1 augustss default:
1756 1.1 augustss return EINVAL;
1757 1.1 augustss }
1758 1.1 augustss break;
1759 1.10 itohy
1760 1.1 augustss case CMPCI_RECORD_SOURCE:
1761 1.7 tshiozak cp->un.mask = sc->sc_in_mask;
1762 1.1 augustss break;
1763 1.1 augustss
1764 1.10 itohy case CMPCI_DAC_MUTE:
1765 1.10 itohy case CMPCI_FM_MUTE:
1766 1.10 itohy case CMPCI_CD_MUTE:
1767 1.1 augustss case CMPCI_LINE_IN_MUTE:
1768 1.10 itohy case CMPCI_AUX_IN_MUTE:
1769 1.10 itohy case CMPCI_MIC_MUTE:
1770 1.10 itohy case CMPCI_MIC_PREAMP:
1771 1.10 itohy case CMPCI_PLAYBACK_MODE:
1772 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1773 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
1774 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1775 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1776 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1777 1.10 itohy case CMPCI_MONITOR_DAC:
1778 1.7 tshiozak case CMPCI_REAR:
1779 1.7 tshiozak case CMPCI_INDIVIDUAL:
1780 1.7 tshiozak case CMPCI_REVERSE:
1781 1.7 tshiozak case CMPCI_SURROUND:
1782 1.7 tshiozak cp->un.ord = sc->sc_gain[cp->dev][CMPCI_LR];
1783 1.1 augustss break;
1784 1.1 augustss
1785 1.1 augustss default:
1786 1.1 augustss return EINVAL;
1787 1.1 augustss }
1788 1.1 augustss
1789 1.1 augustss return 0;
1790 1.1 augustss }
1791 1.1 augustss
1792 1.1 augustss /* ARGSUSED */
1793 1.1 augustss static size_t
1794 1.1 augustss cmpci_round_buffersize(handle, direction, bufsize)
1795 1.1 augustss void *handle;
1796 1.1 augustss int direction;
1797 1.1 augustss size_t bufsize;
1798 1.1 augustss {
1799 1.1 augustss if (bufsize > 0x10000)
1800 1.1 augustss bufsize = 0x10000;
1801 1.10 itohy
1802 1.1 augustss return bufsize;
1803 1.1 augustss }
1804 1.1 augustss
1805 1.1 augustss
1806 1.4 simonb static paddr_t
1807 1.1 augustss cmpci_mappage(handle, addr, offset, prot)
1808 1.1 augustss void *handle;
1809 1.1 augustss void *addr;
1810 1.4 simonb off_t offset;
1811 1.4 simonb int prot;
1812 1.1 augustss {
1813 1.1 augustss struct cmpci_softc *sc = handle;
1814 1.1 augustss struct cmpci_dmanode *p;
1815 1.10 itohy
1816 1.1 augustss if (offset < 0 || NULL == (p = cmpci_find_dmamem(sc, addr)))
1817 1.1 augustss return -1;
1818 1.1 augustss
1819 1.1 augustss return bus_dmamem_mmap(p->cd_tag, p->cd_segs,
1820 1.7 tshiozak sizeof(p->cd_segs)/sizeof(p->cd_segs[0]),
1821 1.7 tshiozak offset, prot, BUS_DMA_WAITOK);
1822 1.1 augustss }
1823 1.1 augustss
1824 1.1 augustss
1825 1.1 augustss /* ARGSUSED */
1826 1.1 augustss static int
1827 1.1 augustss cmpci_get_props(handle)
1828 1.1 augustss void *handle;
1829 1.1 augustss {
1830 1.1 augustss return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
1831 1.1 augustss }
1832 1.1 augustss
1833 1.1 augustss
1834 1.1 augustss static int
1835 1.1 augustss cmpci_trigger_output(handle, start, end, blksize, intr, arg, param)
1836 1.7 tshiozak void *handle;
1837 1.7 tshiozak void *start, *end;
1838 1.7 tshiozak int blksize;
1839 1.7 tshiozak void (*intr) __P((void *));
1840 1.7 tshiozak void *arg;
1841 1.7 tshiozak struct audio_params *param;
1842 1.1 augustss {
1843 1.1 augustss struct cmpci_softc *sc = handle;
1844 1.1 augustss struct cmpci_dmanode *p;
1845 1.1 augustss int bps;
1846 1.1 augustss
1847 1.1 augustss sc->sc_play.intr = intr;
1848 1.1 augustss sc->sc_play.intr_arg = arg;
1849 1.1 augustss bps = param->channels*param->precision*param->factor / 8;
1850 1.1 augustss if (!bps)
1851 1.1 augustss return EINVAL;
1852 1.1 augustss
1853 1.1 augustss /* set DMA frame */
1854 1.1 augustss if (!(p = cmpci_find_dmamem(sc, start)))
1855 1.1 augustss return EINVAL;
1856 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BASE,
1857 1.1 augustss DMAADDR(p));
1858 1.1 augustss delay(10);
1859 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BYTES,
1860 1.7 tshiozak ((caddr_t)end - (caddr_t)start + 1) / bps - 1);
1861 1.1 augustss delay(10);
1862 1.1 augustss
1863 1.1 augustss /* set interrupt count */
1864 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_SAMPLES,
1865 1.1 augustss (blksize + bps - 1) / bps - 1);
1866 1.1 augustss delay(10);
1867 1.1 augustss
1868 1.1 augustss /* start DMA */
1869 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); /* PLAY */
1870 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
1871 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
1872 1.10 itohy
1873 1.1 augustss return 0;
1874 1.1 augustss }
1875 1.1 augustss
1876 1.1 augustss static int
1877 1.1 augustss cmpci_trigger_input(handle, start, end, blksize, intr, arg, param)
1878 1.7 tshiozak void *handle;
1879 1.7 tshiozak void *start, *end;
1880 1.7 tshiozak int blksize;
1881 1.7 tshiozak void (*intr) __P((void *));
1882 1.7 tshiozak void *arg;
1883 1.7 tshiozak struct audio_params *param;
1884 1.1 augustss {
1885 1.1 augustss struct cmpci_softc *sc = handle;
1886 1.1 augustss struct cmpci_dmanode *p;
1887 1.1 augustss int bps;
1888 1.1 augustss
1889 1.1 augustss sc->sc_rec.intr = intr;
1890 1.1 augustss sc->sc_rec.intr_arg = arg;
1891 1.1 augustss bps = param->channels*param->precision*param->factor/8;
1892 1.1 augustss if (!bps)
1893 1.1 augustss return EINVAL;
1894 1.1 augustss
1895 1.1 augustss /* set DMA frame */
1896 1.1 augustss if (!(p=cmpci_find_dmamem(sc, start)))
1897 1.1 augustss return EINVAL;
1898 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BASE,
1899 1.1 augustss DMAADDR(p));
1900 1.1 augustss delay(10);
1901 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BYTES,
1902 1.7 tshiozak ((caddr_t)end - (caddr_t)start + 1) / bps - 1);
1903 1.1 augustss delay(10);
1904 1.1 augustss
1905 1.1 augustss /* set interrupt count */
1906 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_SAMPLES,
1907 1.7 tshiozak (blksize + bps - 1) / bps - 1);
1908 1.1 augustss delay(10);
1909 1.1 augustss
1910 1.1 augustss /* start DMA */
1911 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); /* REC */
1912 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
1913 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
1914 1.10 itohy
1915 1.1 augustss return 0;
1916 1.1 augustss }
1917 1.1 augustss
1918 1.1 augustss
1919 1.1 augustss /* end of file */
1920