cmpci.c revision 1.52 1 1.52 isaki /* $NetBSD: cmpci.c,v 1.52 2019/03/16 12:09:58 isaki Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.43 jmcneill * Copyright (c) 2000, 2001, 2008 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.22 keihan * by Takuya SHIOZAKI <tshiozak (at) NetBSD.org> .
9 1.1 augustss *
10 1.10 itohy * This code is derived from software contributed to The NetBSD Foundation
11 1.10 itohy * by ITOH Yasufumi.
12 1.10 itohy *
13 1.1 augustss * Redistribution and use in source and binary forms, with or without
14 1.1 augustss * modification, are permitted provided that the following conditions
15 1.1 augustss * are met:
16 1.1 augustss * 1. Redistributions of source code must retain the above copyright
17 1.1 augustss * notice, this list of conditions and the following disclaimer.
18 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
19 1.1 augustss * notice, this list of conditions and the following disclaimer in the
20 1.1 augustss * documentation and/or other materials provided with the distribution.
21 1.1 augustss *
22 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 1.1 augustss * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.1 augustss * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 augustss * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 1.1 augustss * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 1.1 augustss * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 1.1 augustss * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.1 augustss * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.1 augustss * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.1 augustss * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.1 augustss * SUCH DAMAGE.
33 1.1 augustss *
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * C-Media CMI8x38 Audio Chip Support.
38 1.1 augustss *
39 1.1 augustss * TODO:
40 1.10 itohy * - 4ch / 6ch support.
41 1.10 itohy * - Joystick support.
42 1.1 augustss *
43 1.1 augustss */
44 1.11 lukem
45 1.11 lukem #include <sys/cdefs.h>
46 1.52 isaki __KERNEL_RCSID(0, "$NetBSD: cmpci.c,v 1.52 2019/03/16 12:09:58 isaki Exp $");
47 1.1 augustss
48 1.1 augustss #if defined(AUDIO_DEBUG) || defined(DEBUG)
49 1.7 tshiozak #define DPRINTF(x) if (cmpcidebug) printf x
50 1.7 tshiozak int cmpcidebug = 0;
51 1.1 augustss #else
52 1.1 augustss #define DPRINTF(x)
53 1.1 augustss #endif
54 1.1 augustss
55 1.8 itohy #include "mpu.h"
56 1.8 itohy
57 1.1 augustss #include <sys/param.h>
58 1.1 augustss #include <sys/systm.h>
59 1.1 augustss #include <sys/kernel.h>
60 1.43 jmcneill #include <sys/kmem.h>
61 1.1 augustss #include <sys/device.h>
62 1.1 augustss #include <sys/proc.h>
63 1.1 augustss
64 1.1 augustss #include <dev/pci/pcidevs.h>
65 1.1 augustss #include <dev/pci/pcivar.h>
66 1.1 augustss
67 1.1 augustss #include <sys/audioio.h>
68 1.1 augustss #include <dev/audio_if.h>
69 1.1 augustss #include <dev/midi_if.h>
70 1.1 augustss
71 1.1 augustss #include <dev/mulaw.h>
72 1.1 augustss #include <dev/auconv.h>
73 1.1 augustss #include <dev/pci/cmpcireg.h>
74 1.1 augustss #include <dev/pci/cmpcivar.h>
75 1.1 augustss
76 1.1 augustss #include <dev/ic/mpuvar.h>
77 1.36 ad #include <sys/bus.h>
78 1.36 ad #include <sys/intr.h>
79 1.1 augustss
80 1.1 augustss /*
81 1.1 augustss * Low-level HW interface
82 1.1 augustss */
83 1.30 perry static inline uint8_t cmpci_mixerreg_read(struct cmpci_softc *, uint8_t);
84 1.30 perry static inline void cmpci_mixerreg_write(struct cmpci_softc *,
85 1.28 kent uint8_t, uint8_t);
86 1.30 perry static inline void cmpci_reg_partial_write_1(struct cmpci_softc *, int, int,
87 1.28 kent unsigned, unsigned);
88 1.30 perry static inline void cmpci_reg_partial_write_4(struct cmpci_softc *, int, int,
89 1.28 kent uint32_t, uint32_t);
90 1.30 perry static inline void cmpci_reg_set_1(struct cmpci_softc *, int, uint8_t);
91 1.30 perry static inline void cmpci_reg_clear_1(struct cmpci_softc *, int, uint8_t);
92 1.30 perry static inline void cmpci_reg_set_4(struct cmpci_softc *, int, uint32_t);
93 1.30 perry static inline void cmpci_reg_clear_4(struct cmpci_softc *, int, uint32_t);
94 1.30 perry static inline void cmpci_reg_set_reg_misc(struct cmpci_softc *, uint32_t);
95 1.30 perry static inline void cmpci_reg_clear_reg_misc(struct cmpci_softc *, uint32_t);
96 1.28 kent static int cmpci_rate_to_index(int);
97 1.30 perry static inline int cmpci_index_to_rate(int);
98 1.30 perry static inline int cmpci_index_to_divider(int);
99 1.28 kent
100 1.28 kent static int cmpci_adjust(int, int);
101 1.28 kent static void cmpci_set_mixer_gain(struct cmpci_softc *, int);
102 1.28 kent static void cmpci_set_out_ports(struct cmpci_softc *);
103 1.28 kent static int cmpci_set_in_ports(struct cmpci_softc *);
104 1.1 augustss
105 1.1 augustss
106 1.1 augustss /*
107 1.1 augustss * autoconf interface
108 1.1 augustss */
109 1.40 cegger static int cmpci_match(device_t, cfdata_t, void *);
110 1.40 cegger static void cmpci_attach(device_t, device_t, void *);
111 1.1 augustss
112 1.46 chs CFATTACH_DECL_NEW(cmpci, sizeof (struct cmpci_softc),
113 1.16 thorpej cmpci_match, cmpci_attach, NULL, NULL);
114 1.1 augustss
115 1.1 augustss /* interrupt */
116 1.28 kent static int cmpci_intr(void *);
117 1.1 augustss
118 1.1 augustss
119 1.1 augustss /*
120 1.1 augustss * DMA stuffs
121 1.1 augustss */
122 1.43 jmcneill static int cmpci_alloc_dmamem(struct cmpci_softc *, size_t, void **);
123 1.43 jmcneill static int cmpci_free_dmamem(struct cmpci_softc *, void *, size_t);
124 1.28 kent static struct cmpci_dmanode * cmpci_find_dmamem(struct cmpci_softc *,
125 1.35 christos void *);
126 1.1 augustss
127 1.1 augustss
128 1.1 augustss /*
129 1.1 augustss * interface to machine independent layer
130 1.1 augustss */
131 1.28 kent static int cmpci_query_encoding(void *, struct audio_encoding *);
132 1.28 kent static int cmpci_set_params(void *, int, int, audio_params_t *,
133 1.28 kent audio_params_t *, stream_filter_list_t *, stream_filter_list_t *);
134 1.28 kent static int cmpci_round_blocksize(void *, int, int, const audio_params_t *);
135 1.28 kent static int cmpci_halt_output(void *);
136 1.28 kent static int cmpci_halt_input(void *);
137 1.28 kent static int cmpci_getdev(void *, struct audio_device *);
138 1.28 kent static int cmpci_set_port(void *, mixer_ctrl_t *);
139 1.28 kent static int cmpci_get_port(void *, mixer_ctrl_t *);
140 1.28 kent static int cmpci_query_devinfo(void *, mixer_devinfo_t *);
141 1.43 jmcneill static void *cmpci_allocm(void *, int, size_t);
142 1.43 jmcneill static void cmpci_freem(void *, void *, size_t);
143 1.28 kent static size_t cmpci_round_buffersize(void *, int, size_t);
144 1.28 kent static paddr_t cmpci_mappage(void *, void *, off_t, int);
145 1.28 kent static int cmpci_get_props(void *);
146 1.28 kent static int cmpci_trigger_output(void *, void *, void *, int,
147 1.28 kent void (*)(void *), void *, const audio_params_t *);
148 1.28 kent static int cmpci_trigger_input(void *, void *, void *, int,
149 1.28 kent void (*)(void *), void *, const audio_params_t *);
150 1.43 jmcneill static void cmpci_get_locks(void *, kmutex_t **, kmutex_t **);
151 1.1 augustss
152 1.26 yamt static const struct audio_hw_if cmpci_hw_if = {
153 1.52 isaki .query_encoding = cmpci_query_encoding,
154 1.52 isaki .set_params = cmpci_set_params,
155 1.52 isaki .round_blocksize = cmpci_round_blocksize,
156 1.52 isaki .halt_output = cmpci_halt_output,
157 1.52 isaki .halt_input = cmpci_halt_input,
158 1.52 isaki .getdev = cmpci_getdev,
159 1.52 isaki .set_port = cmpci_set_port,
160 1.52 isaki .get_port = cmpci_get_port,
161 1.52 isaki .query_devinfo = cmpci_query_devinfo,
162 1.52 isaki .allocm = cmpci_allocm,
163 1.52 isaki .freem = cmpci_freem,
164 1.52 isaki .round_buffersize = cmpci_round_buffersize,
165 1.52 isaki .mappage = cmpci_mappage,
166 1.52 isaki .get_props = cmpci_get_props,
167 1.52 isaki .trigger_output = cmpci_trigger_output,
168 1.52 isaki .trigger_input = cmpci_trigger_input,
169 1.52 isaki .get_locks = cmpci_get_locks,
170 1.1 augustss };
171 1.1 augustss
172 1.27 kent #define CMPCI_NFORMATS 4
173 1.27 kent static const struct audio_format cmpci_formats[CMPCI_NFORMATS] = {
174 1.27 kent {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
175 1.27 kent 2, AUFMT_STEREO, 0, {5512, 48000}},
176 1.27 kent {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
177 1.27 kent 1, AUFMT_MONAURAL, 0, {5512, 48000}},
178 1.27 kent {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR_LE, 8, 8,
179 1.27 kent 2, AUFMT_STEREO, 0, {5512, 48000}},
180 1.27 kent {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR_LE, 8, 8,
181 1.27 kent 1, AUFMT_MONAURAL, 0, {5512, 48000}},
182 1.27 kent };
183 1.27 kent
184 1.1 augustss
185 1.1 augustss /*
186 1.1 augustss * Low-level HW interface
187 1.1 augustss */
188 1.1 augustss
189 1.1 augustss /* mixer register read/write */
190 1.30 perry static inline uint8_t
191 1.28 kent cmpci_mixerreg_read(struct cmpci_softc *sc, uint8_t no)
192 1.1 augustss {
193 1.1 augustss uint8_t ret;
194 1.1 augustss
195 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no);
196 1.1 augustss delay(10);
197 1.1 augustss ret = bus_space_read_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA);
198 1.1 augustss delay(10);
199 1.1 augustss return ret;
200 1.1 augustss }
201 1.1 augustss
202 1.30 perry static inline void
203 1.28 kent cmpci_mixerreg_write(struct cmpci_softc *sc, uint8_t no, uint8_t val)
204 1.1 augustss {
205 1.28 kent
206 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no);
207 1.1 augustss delay(10);
208 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA, val);
209 1.1 augustss delay(10);
210 1.1 augustss }
211 1.1 augustss
212 1.1 augustss
213 1.1 augustss /* register partial write */
214 1.30 perry static inline void
215 1.28 kent cmpci_reg_partial_write_1(struct cmpci_softc *sc, int no, int shift,
216 1.28 kent unsigned mask, unsigned val)
217 1.10 itohy {
218 1.28 kent
219 1.10 itohy bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
220 1.10 itohy (val<<shift) |
221 1.10 itohy (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));
222 1.10 itohy delay(10);
223 1.10 itohy }
224 1.10 itohy
225 1.30 perry static inline void
226 1.28 kent cmpci_reg_partial_write_4(struct cmpci_softc *sc, int no, int shift,
227 1.28 kent uint32_t mask, uint32_t val)
228 1.1 augustss {
229 1.28 kent
230 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
231 1.1 augustss (val<<shift) |
232 1.1 augustss (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));
233 1.1 augustss delay(10);
234 1.1 augustss }
235 1.1 augustss
236 1.1 augustss /* register set/clear bit */
237 1.30 perry static inline void
238 1.28 kent cmpci_reg_set_1(struct cmpci_softc *sc, int no, uint8_t mask)
239 1.7 tshiozak {
240 1.28 kent
241 1.7 tshiozak bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
242 1.7 tshiozak (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) | mask));
243 1.7 tshiozak delay(10);
244 1.7 tshiozak }
245 1.7 tshiozak
246 1.30 perry static inline void
247 1.28 kent cmpci_reg_clear_1(struct cmpci_softc *sc, int no, uint8_t mask)
248 1.7 tshiozak {
249 1.28 kent
250 1.7 tshiozak bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
251 1.7 tshiozak (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~mask));
252 1.7 tshiozak delay(10);
253 1.7 tshiozak }
254 1.7 tshiozak
255 1.30 perry static inline void
256 1.28 kent cmpci_reg_set_4(struct cmpci_softc *sc, int no, uint32_t mask)
257 1.1 augustss {
258 1.28 kent
259 1.21 itohy /* use cmpci_reg_set_reg_misc() for CMPCI_REG_MISC */
260 1.21 itohy KDASSERT(no != CMPCI_REG_MISC);
261 1.21 itohy
262 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
263 1.7 tshiozak (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) | mask));
264 1.1 augustss delay(10);
265 1.1 augustss }
266 1.1 augustss
267 1.30 perry static inline void
268 1.28 kent cmpci_reg_clear_4(struct cmpci_softc *sc, int no, uint32_t mask)
269 1.1 augustss {
270 1.28 kent
271 1.21 itohy /* use cmpci_reg_clear_reg_misc() for CMPCI_REG_MISC */
272 1.21 itohy KDASSERT(no != CMPCI_REG_MISC);
273 1.21 itohy
274 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
275 1.7 tshiozak (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~mask));
276 1.1 augustss delay(10);
277 1.1 augustss }
278 1.1 augustss
279 1.21 itohy /*
280 1.21 itohy * The CMPCI_REG_MISC register needs special handling, since one of
281 1.21 itohy * its bits has different read/write values.
282 1.21 itohy */
283 1.30 perry static inline void
284 1.28 kent cmpci_reg_set_reg_misc(struct cmpci_softc *sc, uint32_t mask)
285 1.21 itohy {
286 1.28 kent
287 1.21 itohy sc->sc_reg_misc |= mask;
288 1.21 itohy bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MISC,
289 1.21 itohy sc->sc_reg_misc);
290 1.21 itohy delay(10);
291 1.21 itohy }
292 1.21 itohy
293 1.30 perry static inline void
294 1.28 kent cmpci_reg_clear_reg_misc(struct cmpci_softc *sc, uint32_t mask)
295 1.21 itohy {
296 1.28 kent
297 1.21 itohy sc->sc_reg_misc &= ~mask;
298 1.21 itohy bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MISC,
299 1.21 itohy sc->sc_reg_misc);
300 1.21 itohy delay(10);
301 1.21 itohy }
302 1.21 itohy
303 1.1 augustss /* rate */
304 1.6 jdolecek static const struct {
305 1.1 augustss int rate;
306 1.1 augustss int divider;
307 1.1 augustss } cmpci_rate_table[CMPCI_REG_NUMRATE] = {
308 1.1 augustss #define _RATE(n) { n, CMPCI_REG_RATE_ ## n }
309 1.1 augustss _RATE(5512),
310 1.1 augustss _RATE(8000),
311 1.1 augustss _RATE(11025),
312 1.1 augustss _RATE(16000),
313 1.1 augustss _RATE(22050),
314 1.1 augustss _RATE(32000),
315 1.1 augustss _RATE(44100),
316 1.1 augustss _RATE(48000)
317 1.7 tshiozak #undef _RATE
318 1.1 augustss };
319 1.1 augustss
320 1.1 augustss static int
321 1.28 kent cmpci_rate_to_index(int rate)
322 1.1 augustss {
323 1.1 augustss int i;
324 1.1 augustss
325 1.13 augustss for (i = 0; i < CMPCI_REG_NUMRATE - 1; i++)
326 1.1 augustss if (rate <=
327 1.1 augustss (cmpci_rate_table[i].rate+cmpci_rate_table[i+1].rate) / 2)
328 1.1 augustss return i;
329 1.1 augustss return i; /* 48000 */
330 1.1 augustss }
331 1.1 augustss
332 1.30 perry static inline int
333 1.28 kent cmpci_index_to_rate(int index)
334 1.1 augustss {
335 1.28 kent
336 1.1 augustss return cmpci_rate_table[index].rate;
337 1.1 augustss }
338 1.1 augustss
339 1.30 perry static inline int
340 1.28 kent cmpci_index_to_divider(int index)
341 1.1 augustss {
342 1.28 kent
343 1.1 augustss return cmpci_rate_table[index].divider;
344 1.1 augustss }
345 1.1 augustss
346 1.1 augustss /*
347 1.1 augustss * interface to configure the device.
348 1.1 augustss */
349 1.1 augustss static int
350 1.40 cegger cmpci_match(device_t parent, cfdata_t match, void *aux)
351 1.1 augustss {
352 1.28 kent struct pci_attach_args *pa;
353 1.1 augustss
354 1.28 kent pa = (struct pci_attach_args *)aux;
355 1.1 augustss if ( PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMEDIA &&
356 1.1 augustss (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338A ||
357 1.1 augustss PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338B ||
358 1.7 tshiozak PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738 ||
359 1.7 tshiozak PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738B) )
360 1.1 augustss return 1;
361 1.1 augustss
362 1.1 augustss return 0;
363 1.1 augustss }
364 1.1 augustss
365 1.1 augustss static void
366 1.40 cegger cmpci_attach(device_t parent, device_t self, void *aux)
367 1.1 augustss {
368 1.28 kent struct cmpci_softc *sc;
369 1.28 kent struct pci_attach_args *pa;
370 1.8 itohy struct audio_attach_args aa;
371 1.1 augustss pci_intr_handle_t ih;
372 1.1 augustss char const *strintr;
373 1.1 augustss int i, v;
374 1.47 christos char intrbuf[PCI_INTRSTR_LEN];
375 1.1 augustss
376 1.41 cegger sc = device_private(self);
377 1.46 chs sc->sc_dev = self;
378 1.28 kent pa = (struct pci_attach_args *)aux;
379 1.17 thorpej
380 1.7 tshiozak sc->sc_id = pa->pa_id;
381 1.7 tshiozak sc->sc_class = pa->pa_class;
382 1.45 drochner pci_aprint_devinfo(pa, "Audio controller");
383 1.7 tshiozak switch (PCI_PRODUCT(sc->sc_id)) {
384 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338A:
385 1.7 tshiozak /*FALLTHROUGH*/
386 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338B:
387 1.7 tshiozak sc->sc_capable = CMPCI_CAP_CMI8338;
388 1.1 augustss break;
389 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8738:
390 1.7 tshiozak /*FALLTHROUGH*/
391 1.7 tshiozak case PCI_PRODUCT_CMEDIA_CMI8738B:
392 1.7 tshiozak sc->sc_capable = CMPCI_CAP_CMI8738;
393 1.1 augustss break;
394 1.1 augustss }
395 1.1 augustss
396 1.2 augustss /* map I/O space */
397 1.1 augustss if (pci_mapreg_map(pa, CMPCI_PCI_IOBASEREG, PCI_MAPREG_TYPE_IO, 0,
398 1.7 tshiozak &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) {
399 1.46 chs aprint_error_dev(sc->sc_dev, "failed to map I/O space\n");
400 1.1 augustss return;
401 1.1 augustss }
402 1.1 augustss
403 1.43 jmcneill mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
404 1.44 mrg mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO);
405 1.43 jmcneill
406 1.2 augustss /* interrupt */
407 1.5 sommerfe if (pci_intr_map(pa, &ih)) {
408 1.46 chs aprint_error_dev(sc->sc_dev, "failed to map interrupt\n");
409 1.1 augustss return;
410 1.1 augustss }
411 1.47 christos strintr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
412 1.51 jdolecek sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_AUDIO,
413 1.51 jdolecek cmpci_intr, sc, device_xname(self));
414 1.1 augustss if (sc->sc_ih == NULL) {
415 1.46 chs aprint_error_dev(sc->sc_dev, "failed to establish interrupt");
416 1.1 augustss if (strintr != NULL)
417 1.42 njoly aprint_error(" at %s", strintr);
418 1.42 njoly aprint_error("\n");
419 1.43 jmcneill mutex_destroy(&sc->sc_lock);
420 1.43 jmcneill mutex_destroy(&sc->sc_intr_lock);
421 1.1 augustss return;
422 1.1 augustss }
423 1.46 chs aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", strintr);
424 1.1 augustss
425 1.1 augustss sc->sc_dmat = pa->pa_dmat;
426 1.1 augustss
427 1.46 chs audio_attach_mi(&cmpci_hw_if, sc, sc->sc_dev);
428 1.1 augustss
429 1.8 itohy /* attach OPL device */
430 1.8 itohy aa.type = AUDIODEV_TYPE_OPL;
431 1.8 itohy aa.hwif = NULL;
432 1.8 itohy aa.hdl = NULL;
433 1.46 chs (void)config_found(sc->sc_dev, &aa, audioprint);
434 1.8 itohy
435 1.8 itohy /* attach MPU-401 device */
436 1.8 itohy aa.type = AUDIODEV_TYPE_MPU;
437 1.8 itohy aa.hwif = NULL;
438 1.8 itohy aa.hdl = NULL;
439 1.8 itohy if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
440 1.8 itohy CMPCI_REG_MPU_BASE, CMPCI_REG_MPU_SIZE, &sc->sc_mpu_ioh) == 0)
441 1.46 chs sc->sc_mpudev = config_found(sc->sc_dev, &aa, audioprint);
442 1.8 itohy
443 1.21 itohy /* get initial value (this is 0 and may be omitted but just in case) */
444 1.21 itohy sc->sc_reg_misc = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
445 1.21 itohy CMPCI_REG_MISC) & ~CMPCI_REG_SPDIF48K;
446 1.21 itohy
447 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_RESET, 0);
448 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
449 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
450 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX,
451 1.1 augustss CMPCI_SB16_SW_CD|CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
452 1.1 augustss for (i = 0; i < CMPCI_NDEVS; i++) {
453 1.48 msaitoh switch (i) {
454 1.10 itohy /*
455 1.10 itohy * CMI8738 defaults are
456 1.10 itohy * master: 0xe0 (0x00 - 0xf8)
457 1.12 itohy * FM, DAC: 0xc0 (0x00 - 0xf8)
458 1.10 itohy * PC speaker: 0x80 (0x00 - 0xc0)
459 1.10 itohy * others: 0
460 1.10 itohy */
461 1.10 itohy /* volume */
462 1.8 itohy case CMPCI_MASTER_VOL:
463 1.10 itohy v = 128; /* 224 */
464 1.10 itohy break;
465 1.8 itohy case CMPCI_FM_VOL:
466 1.10 itohy case CMPCI_DAC_VOL:
467 1.10 itohy v = 192;
468 1.10 itohy break;
469 1.8 itohy case CMPCI_PCSPEAKER:
470 1.10 itohy v = 128;
471 1.1 augustss break;
472 1.8 itohy
473 1.8 itohy /* booleans, set to true */
474 1.10 itohy case CMPCI_CD_MUTE:
475 1.10 itohy case CMPCI_MIC_MUTE:
476 1.10 itohy case CMPCI_LINE_IN_MUTE:
477 1.10 itohy case CMPCI_AUX_IN_MUTE:
478 1.8 itohy v = 1;
479 1.1 augustss break;
480 1.10 itohy
481 1.10 itohy /* volume with inital value 0 */
482 1.10 itohy case CMPCI_CD_VOL:
483 1.10 itohy case CMPCI_LINE_IN_VOL:
484 1.10 itohy case CMPCI_AUX_IN_VOL:
485 1.10 itohy case CMPCI_MIC_VOL:
486 1.10 itohy case CMPCI_MIC_RECVOL:
487 1.10 itohy /* FALLTHROUGH */
488 1.10 itohy
489 1.8 itohy /* others are cleared */
490 1.10 itohy case CMPCI_MIC_PREAMP:
491 1.8 itohy case CMPCI_RECORD_SOURCE:
492 1.10 itohy case CMPCI_PLAYBACK_MODE:
493 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
494 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
495 1.7 tshiozak case CMPCI_SPDIF_LOOP:
496 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
497 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
498 1.10 itohy case CMPCI_MONITOR_DAC:
499 1.7 tshiozak case CMPCI_REAR:
500 1.7 tshiozak case CMPCI_INDIVIDUAL:
501 1.7 tshiozak case CMPCI_REVERSE:
502 1.7 tshiozak case CMPCI_SURROUND:
503 1.8 itohy default:
504 1.1 augustss v = 0;
505 1.1 augustss break;
506 1.1 augustss }
507 1.7 tshiozak sc->sc_gain[i][CMPCI_LEFT] = sc->sc_gain[i][CMPCI_RIGHT] = v;
508 1.1 augustss cmpci_set_mixer_gain(sc, i);
509 1.1 augustss }
510 1.1 augustss }
511 1.1 augustss
512 1.1 augustss static int
513 1.28 kent cmpci_intr(void *handle)
514 1.1 augustss {
515 1.37 xtraeme struct cmpci_softc *sc = handle;
516 1.37 xtraeme #if NMPU > 0
517 1.37 xtraeme struct mpu_softc *sc_mpu = device_private(sc->sc_mpudev);
518 1.37 xtraeme #endif
519 1.1 augustss uint32_t intrstat;
520 1.1 augustss
521 1.43 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
522 1.43 jmcneill
523 1.1 augustss intrstat = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
524 1.1 augustss CMPCI_REG_INTR_STATUS);
525 1.1 augustss
526 1.43 jmcneill if (!(intrstat & CMPCI_REG_ANY_INTR)) {
527 1.43 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
528 1.1 augustss return 0;
529 1.43 jmcneill }
530 1.1 augustss
531 1.8 itohy delay(10);
532 1.8 itohy
533 1.1 augustss /* disable and reset intr */
534 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR)
535 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL,
536 1.1 augustss CMPCI_REG_CH0_INTR_ENABLE);
537 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR)
538 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL,
539 1.1 augustss CMPCI_REG_CH1_INTR_ENABLE);
540 1.1 augustss
541 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR) {
542 1.1 augustss if (sc->sc_play.intr != NULL)
543 1.1 augustss (*sc->sc_play.intr)(sc->sc_play.intr_arg);
544 1.1 augustss }
545 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR) {
546 1.1 augustss if (sc->sc_rec.intr != NULL)
547 1.1 augustss (*sc->sc_rec.intr)(sc->sc_rec.intr_arg);
548 1.1 augustss }
549 1.1 augustss
550 1.1 augustss /* enable intr */
551 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR)
552 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL,
553 1.1 augustss CMPCI_REG_CH0_INTR_ENABLE);
554 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR)
555 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL,
556 1.1 augustss CMPCI_REG_CH1_INTR_ENABLE);
557 1.8 itohy
558 1.8 itohy #if NMPU > 0
559 1.37 xtraeme if (intrstat & CMPCI_REG_UART_INTR && sc_mpu != NULL)
560 1.37 xtraeme mpu_intr(sc_mpu);
561 1.8 itohy #endif
562 1.8 itohy
563 1.43 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
564 1.8 itohy return 1;
565 1.1 augustss }
566 1.1 augustss
567 1.1 augustss static int
568 1.34 christos cmpci_query_encoding(void *handle, struct audio_encoding *fp)
569 1.1 augustss {
570 1.28 kent
571 1.1 augustss switch (fp->index) {
572 1.1 augustss case 0:
573 1.1 augustss strcpy(fp->name, AudioEulinear);
574 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR;
575 1.1 augustss fp->precision = 8;
576 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
577 1.1 augustss break;
578 1.1 augustss case 1:
579 1.1 augustss strcpy(fp->name, AudioEmulaw);
580 1.1 augustss fp->encoding = AUDIO_ENCODING_ULAW;
581 1.1 augustss fp->precision = 8;
582 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
583 1.1 augustss break;
584 1.1 augustss case 2:
585 1.1 augustss strcpy(fp->name, AudioEalaw);
586 1.1 augustss fp->encoding = AUDIO_ENCODING_ALAW;
587 1.1 augustss fp->precision = 8;
588 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
589 1.1 augustss break;
590 1.1 augustss case 3:
591 1.1 augustss strcpy(fp->name, AudioEslinear);
592 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR;
593 1.1 augustss fp->precision = 8;
594 1.1 augustss fp->flags = 0;
595 1.1 augustss break;
596 1.1 augustss case 4:
597 1.1 augustss strcpy(fp->name, AudioEslinear_le);
598 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR_LE;
599 1.1 augustss fp->precision = 16;
600 1.1 augustss fp->flags = 0;
601 1.1 augustss break;
602 1.1 augustss case 5:
603 1.1 augustss strcpy(fp->name, AudioEulinear_le);
604 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR_LE;
605 1.1 augustss fp->precision = 16;
606 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
607 1.1 augustss break;
608 1.1 augustss case 6:
609 1.1 augustss strcpy(fp->name, AudioEslinear_be);
610 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR_BE;
611 1.1 augustss fp->precision = 16;
612 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
613 1.1 augustss break;
614 1.1 augustss case 7:
615 1.1 augustss strcpy(fp->name, AudioEulinear_be);
616 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR_BE;
617 1.1 augustss fp->precision = 16;
618 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
619 1.1 augustss break;
620 1.1 augustss default:
621 1.1 augustss return EINVAL;
622 1.1 augustss }
623 1.1 augustss return 0;
624 1.1 augustss }
625 1.1 augustss
626 1.1 augustss
627 1.1 augustss static int
628 1.34 christos cmpci_set_params(void *handle, int setmode, int usemode,
629 1.33 christos audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil,
630 1.33 christos stream_filter_list_t *rfil)
631 1.1 augustss {
632 1.1 augustss int i;
633 1.28 kent struct cmpci_softc *sc;
634 1.1 augustss
635 1.28 kent sc = handle;
636 1.1 augustss for (i = 0; i < 2; i++) {
637 1.1 augustss int md_format;
638 1.1 augustss int md_divide;
639 1.1 augustss int md_index;
640 1.1 augustss int mode;
641 1.27 kent audio_params_t *p;
642 1.27 kent stream_filter_list_t *fil;
643 1.27 kent int ind;
644 1.10 itohy
645 1.1 augustss switch (i) {
646 1.1 augustss case 0:
647 1.1 augustss mode = AUMODE_PLAY;
648 1.1 augustss p = play;
649 1.27 kent fil = pfil;
650 1.1 augustss break;
651 1.1 augustss case 1:
652 1.1 augustss mode = AUMODE_RECORD;
653 1.1 augustss p = rec;
654 1.27 kent fil = rfil;
655 1.1 augustss break;
656 1.19 christos default:
657 1.19 christos return EINVAL;
658 1.1 augustss }
659 1.10 itohy
660 1.1 augustss if (!(setmode & mode))
661 1.1 augustss continue;
662 1.1 augustss
663 1.27 kent md_index = cmpci_rate_to_index(p->sample_rate);
664 1.27 kent md_divide = cmpci_index_to_divider(md_index);
665 1.27 kent p->sample_rate = cmpci_index_to_rate(md_index);
666 1.27 kent DPRINTF(("%s: sample:%u, divider=%d\n",
667 1.46 chs device_xname(sc->sc_dev), p->sample_rate, md_divide));
668 1.27 kent
669 1.27 kent ind = auconv_set_converter(cmpci_formats, CMPCI_NFORMATS,
670 1.27 kent mode, p, FALSE, fil);
671 1.27 kent if (ind < 0)
672 1.27 kent return EINVAL;
673 1.27 kent if (fil->req_size > 0)
674 1.27 kent p = &fil->filters[0].param;
675 1.1 augustss
676 1.1 augustss /* format */
677 1.27 kent md_format = p->channels == 1
678 1.27 kent ? CMPCI_REG_FORMAT_MONO : CMPCI_REG_FORMAT_STEREO;
679 1.27 kent md_format |= p->precision == 16
680 1.27 kent ? CMPCI_REG_FORMAT_16BIT : CMPCI_REG_FORMAT_8BIT;
681 1.27 kent if (mode & AUMODE_PLAY) {
682 1.1 augustss cmpci_reg_partial_write_4(sc,
683 1.7 tshiozak CMPCI_REG_CHANNEL_FORMAT,
684 1.7 tshiozak CMPCI_REG_CH0_FORMAT_SHIFT,
685 1.7 tshiozak CMPCI_REG_CH0_FORMAT_MASK, md_format);
686 1.1 augustss cmpci_reg_partial_write_4(sc,
687 1.1 augustss CMPCI_REG_FUNC_1, CMPCI_REG_DAC_FS_SHIFT,
688 1.1 augustss CMPCI_REG_DAC_FS_MASK, md_divide);
689 1.7 tshiozak sc->sc_play.md_divide = md_divide;
690 1.1 augustss } else {
691 1.1 augustss cmpci_reg_partial_write_4(sc,
692 1.27 kent CMPCI_REG_CHANNEL_FORMAT,
693 1.27 kent CMPCI_REG_CH1_FORMAT_SHIFT,
694 1.27 kent CMPCI_REG_CH1_FORMAT_MASK, md_format);
695 1.27 kent cmpci_reg_partial_write_4(sc,
696 1.1 augustss CMPCI_REG_FUNC_1, CMPCI_REG_ADC_FS_SHIFT,
697 1.1 augustss CMPCI_REG_ADC_FS_MASK, md_divide);
698 1.7 tshiozak sc->sc_rec.md_divide = md_divide;
699 1.1 augustss }
700 1.10 itohy cmpci_set_out_ports(sc);
701 1.10 itohy cmpci_set_in_ports(sc);
702 1.1 augustss }
703 1.1 augustss return 0;
704 1.1 augustss }
705 1.1 augustss
706 1.1 augustss /* ARGSUSED */
707 1.1 augustss static int
708 1.34 christos cmpci_round_blocksize(void *handle, int block,
709 1.34 christos int mode, const audio_params_t *param)
710 1.1 augustss {
711 1.28 kent
712 1.28 kent return block & -4;
713 1.1 augustss }
714 1.1 augustss
715 1.1 augustss static int
716 1.28 kent cmpci_halt_output(void *handle)
717 1.1 augustss {
718 1.28 kent struct cmpci_softc *sc;
719 1.1 augustss
720 1.28 kent sc = handle;
721 1.1 augustss sc->sc_play.intr = NULL;
722 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
723 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
724 1.1 augustss /* wait for reset DMA */
725 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
726 1.1 augustss delay(10);
727 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
728 1.10 itohy
729 1.1 augustss return 0;
730 1.1 augustss }
731 1.1 augustss
732 1.1 augustss static int
733 1.28 kent cmpci_halt_input(void *handle)
734 1.1 augustss {
735 1.28 kent struct cmpci_softc *sc;
736 1.10 itohy
737 1.28 kent sc = handle;
738 1.1 augustss sc->sc_rec.intr = NULL;
739 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
740 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
741 1.1 augustss /* wait for reset DMA */
742 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
743 1.1 augustss delay(10);
744 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
745 1.10 itohy
746 1.1 augustss return 0;
747 1.1 augustss }
748 1.1 augustss
749 1.1 augustss /* get audio device information */
750 1.1 augustss static int
751 1.28 kent cmpci_getdev(void *handle, struct audio_device *ad)
752 1.1 augustss {
753 1.28 kent struct cmpci_softc *sc;
754 1.1 augustss
755 1.28 kent sc = handle;
756 1.1 augustss strncpy(ad->name, "CMI PCI Audio", sizeof(ad->name));
757 1.7 tshiozak snprintf(ad->version, sizeof(ad->version), "0x%02x",
758 1.7 tshiozak PCI_REVISION(sc->sc_class));
759 1.7 tshiozak switch (PCI_PRODUCT(sc->sc_id)) {
760 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338A:
761 1.1 augustss strncpy(ad->config, "CMI8338A", sizeof(ad->config));
762 1.1 augustss break;
763 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338B:
764 1.1 augustss strncpy(ad->config, "CMI8338B", sizeof(ad->config));
765 1.1 augustss break;
766 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8738:
767 1.1 augustss strncpy(ad->config, "CMI8738", sizeof(ad->config));
768 1.1 augustss break;
769 1.7 tshiozak case PCI_PRODUCT_CMEDIA_CMI8738B:
770 1.7 tshiozak strncpy(ad->config, "CMI8738B", sizeof(ad->config));
771 1.7 tshiozak break;
772 1.1 augustss default:
773 1.1 augustss strncpy(ad->config, "unknown", sizeof(ad->config));
774 1.1 augustss }
775 1.1 augustss
776 1.1 augustss return 0;
777 1.1 augustss }
778 1.1 augustss
779 1.1 augustss /* mixer device information */
780 1.1 augustss int
781 1.28 kent cmpci_query_devinfo(void *handle, mixer_devinfo_t *dip)
782 1.1 augustss {
783 1.10 itohy static const char *const mixer_port_names[] = {
784 1.10 itohy AudioNdac, AudioNfmsynth, AudioNcd, AudioNline, AudioNaux,
785 1.10 itohy AudioNmicrophone
786 1.10 itohy };
787 1.10 itohy static const char *const mixer_classes[] = {
788 1.10 itohy AudioCinputs, AudioCoutputs, AudioCrecord, CmpciCplayback,
789 1.10 itohy CmpciCspdif
790 1.10 itohy };
791 1.28 kent struct cmpci_softc *sc;
792 1.10 itohy int i;
793 1.10 itohy
794 1.28 kent sc = handle;
795 1.10 itohy dip->prev = dip->next = AUDIO_MIXER_LAST;
796 1.10 itohy
797 1.1 augustss switch (dip->index) {
798 1.10 itohy case CMPCI_INPUT_CLASS:
799 1.10 itohy case CMPCI_OUTPUT_CLASS:
800 1.10 itohy case CMPCI_RECORD_CLASS:
801 1.10 itohy case CMPCI_PLAYBACK_CLASS:
802 1.10 itohy case CMPCI_SPDIF_CLASS:
803 1.10 itohy dip->type = AUDIO_MIXER_CLASS;
804 1.10 itohy dip->mixer_class = dip->index;
805 1.10 itohy strcpy(dip->label.name,
806 1.10 itohy mixer_classes[dip->index - CMPCI_INPUT_CLASS]);
807 1.1 augustss return 0;
808 1.10 itohy
809 1.10 itohy case CMPCI_AUX_IN_VOL:
810 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_REG_AUX_VALBITS);
811 1.10 itohy goto vol1;
812 1.10 itohy case CMPCI_DAC_VOL:
813 1.1 augustss case CMPCI_FM_VOL:
814 1.10 itohy case CMPCI_CD_VOL:
815 1.10 itohy case CMPCI_LINE_IN_VOL:
816 1.10 itohy case CMPCI_MIC_VOL:
817 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS);
818 1.10 itohy vol1: dip->mixer_class = CMPCI_INPUT_CLASS;
819 1.10 itohy dip->next = dip->index + 6; /* CMPCI_xxx_MUTE */
820 1.10 itohy strcpy(dip->label.name, mixer_port_names[dip->index]);
821 1.10 itohy dip->un.v.num_channels = (dip->index == CMPCI_MIC_VOL ? 1 : 2);
822 1.10 itohy vol:
823 1.1 augustss dip->type = AUDIO_MIXER_VALUE;
824 1.1 augustss strcpy(dip->un.v.units.name, AudioNvolume);
825 1.1 augustss return 0;
826 1.10 itohy
827 1.10 itohy case CMPCI_MIC_MUTE:
828 1.10 itohy dip->next = CMPCI_MIC_PREAMP;
829 1.10 itohy /* FALLTHROUGH */
830 1.10 itohy case CMPCI_DAC_MUTE:
831 1.10 itohy case CMPCI_FM_MUTE:
832 1.10 itohy case CMPCI_CD_MUTE:
833 1.10 itohy case CMPCI_LINE_IN_MUTE:
834 1.10 itohy case CMPCI_AUX_IN_MUTE:
835 1.10 itohy dip->prev = dip->index - 6; /* CMPCI_xxx_VOL */
836 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
837 1.10 itohy strcpy(dip->label.name, AudioNmute);
838 1.10 itohy goto on_off;
839 1.10 itohy on_off:
840 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
841 1.10 itohy dip->un.e.num_mem = 2;
842 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNoff);
843 1.10 itohy dip->un.e.member[0].ord = 0;
844 1.10 itohy strcpy(dip->un.e.member[1].label.name, AudioNon);
845 1.10 itohy dip->un.e.member[1].ord = 1;
846 1.1 augustss return 0;
847 1.10 itohy
848 1.10 itohy case CMPCI_MIC_PREAMP:
849 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
850 1.10 itohy dip->prev = CMPCI_MIC_MUTE;
851 1.10 itohy strcpy(dip->label.name, AudioNpreamp);
852 1.10 itohy goto on_off;
853 1.10 itohy case CMPCI_PCSPEAKER:
854 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
855 1.10 itohy strcpy(dip->label.name, AudioNspeaker);
856 1.1 augustss dip->un.v.num_channels = 1;
857 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_SPEAKER_VALBITS);
858 1.10 itohy goto vol;
859 1.1 augustss case CMPCI_RECORD_SOURCE:
860 1.1 augustss dip->mixer_class = CMPCI_RECORD_CLASS;
861 1.1 augustss strcpy(dip->label.name, AudioNsource);
862 1.1 augustss dip->type = AUDIO_MIXER_SET;
863 1.10 itohy dip->un.s.num_mem = 7;
864 1.1 augustss strcpy(dip->un.s.member[0].label.name, AudioNmicrophone);
865 1.8 itohy dip->un.s.member[0].mask = CMPCI_RECORD_SOURCE_MIC;
866 1.1 augustss strcpy(dip->un.s.member[1].label.name, AudioNcd);
867 1.8 itohy dip->un.s.member[1].mask = CMPCI_RECORD_SOURCE_CD;
868 1.1 augustss strcpy(dip->un.s.member[2].label.name, AudioNline);
869 1.8 itohy dip->un.s.member[2].mask = CMPCI_RECORD_SOURCE_LINE_IN;
870 1.10 itohy strcpy(dip->un.s.member[3].label.name, AudioNaux);
871 1.10 itohy dip->un.s.member[3].mask = CMPCI_RECORD_SOURCE_AUX_IN;
872 1.10 itohy strcpy(dip->un.s.member[4].label.name, AudioNwave);
873 1.10 itohy dip->un.s.member[4].mask = CMPCI_RECORD_SOURCE_WAVE;
874 1.10 itohy strcpy(dip->un.s.member[5].label.name, AudioNfmsynth);
875 1.10 itohy dip->un.s.member[5].mask = CMPCI_RECORD_SOURCE_FM;
876 1.10 itohy strcpy(dip->un.s.member[6].label.name, CmpciNspdif);
877 1.10 itohy dip->un.s.member[6].mask = CMPCI_RECORD_SOURCE_SPDIF;
878 1.1 augustss return 0;
879 1.10 itohy case CMPCI_MIC_RECVOL:
880 1.1 augustss dip->mixer_class = CMPCI_RECORD_CLASS;
881 1.10 itohy strcpy(dip->label.name, AudioNmicrophone);
882 1.1 augustss dip->un.v.num_channels = 1;
883 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_REG_ADMIC_VALBITS);
884 1.10 itohy goto vol;
885 1.10 itohy
886 1.10 itohy case CMPCI_PLAYBACK_MODE:
887 1.10 itohy dip->mixer_class = CMPCI_PLAYBACK_CLASS;
888 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
889 1.10 itohy strcpy(dip->label.name, AudioNmode);
890 1.10 itohy dip->un.e.num_mem = 2;
891 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNdac);
892 1.10 itohy dip->un.e.member[0].ord = CMPCI_PLAYBACK_MODE_WAVE;
893 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdif);
894 1.10 itohy dip->un.e.member[1].ord = CMPCI_PLAYBACK_MODE_SPDIF;
895 1.1 augustss return 0;
896 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
897 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
898 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
899 1.10 itohy dip->next = CMPCI_SPDIF_IN_PHASE;
900 1.1 augustss strcpy(dip->label.name, AudioNinput);
901 1.10 itohy i = 0;
902 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdin1);
903 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN1;
904 1.10 itohy if (CMPCI_ISCAP(sc, 2ND_SPDIN)) {
905 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdin2);
906 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN2;
907 1.10 itohy }
908 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdout);
909 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDOUT;
910 1.10 itohy dip->un.e.num_mem = i;
911 1.10 itohy return 0;
912 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
913 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
914 1.10 itohy dip->prev = CMPCI_SPDIF_IN_SELECT;
915 1.10 itohy strcpy(dip->label.name, CmpciNphase);
916 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
917 1.10 itohy dip->un.e.num_mem = 2;
918 1.10 itohy strcpy(dip->un.e.member[0].label.name, CmpciNpositive);
919 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_IN_PHASE_POSITIVE;
920 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNnegative);
921 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_IN_PHASE_NEGATIVE;
922 1.1 augustss return 0;
923 1.10 itohy case CMPCI_SPDIF_LOOP:
924 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
925 1.10 itohy dip->next = CMPCI_SPDIF_OUT_PLAYBACK;
926 1.1 augustss strcpy(dip->label.name, AudioNoutput);
927 1.1 augustss dip->type = AUDIO_MIXER_ENUM;
928 1.10 itohy dip->un.e.num_mem = 2;
929 1.10 itohy strcpy(dip->un.e.member[0].label.name, CmpciNplayback);
930 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_LOOP_OFF;
931 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdin);
932 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_LOOP_ON;
933 1.7 tshiozak return 0;
934 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
935 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
936 1.10 itohy dip->prev = CMPCI_SPDIF_LOOP;
937 1.10 itohy dip->next = CMPCI_SPDIF_OUT_VOLTAGE;
938 1.10 itohy strcpy(dip->label.name, CmpciNplayback);
939 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
940 1.10 itohy dip->un.e.num_mem = 2;
941 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNwave);
942 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_PLAYBACK_WAVE;
943 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNlegacy);
944 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_PLAYBACK_LEGACY;
945 1.7 tshiozak return 0;
946 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
947 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
948 1.10 itohy dip->prev = CMPCI_SPDIF_OUT_PLAYBACK;
949 1.10 itohy strcpy(dip->label.name, CmpciNvoltage);
950 1.7 tshiozak dip->type = AUDIO_MIXER_ENUM;
951 1.7 tshiozak dip->un.e.num_mem = 2;
952 1.21 itohy strcpy(dip->un.e.member[0].label.name, CmpciNhigh_v);
953 1.21 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_VOLTAGE_HIGH;
954 1.21 itohy strcpy(dip->un.e.member[1].label.name, CmpciNlow_v);
955 1.21 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_VOLTAGE_LOW;
956 1.7 tshiozak return 0;
957 1.10 itohy case CMPCI_MONITOR_DAC:
958 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
959 1.10 itohy strcpy(dip->label.name, AudioNmonitor);
960 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
961 1.10 itohy dip->un.e.num_mem = 3;
962 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNoff);
963 1.10 itohy dip->un.e.member[0].ord = CMPCI_MONITOR_DAC_OFF;
964 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdin);
965 1.10 itohy dip->un.e.member[1].ord = CMPCI_MONITOR_DAC_SPDIN;
966 1.10 itohy strcpy(dip->un.e.member[2].label.name, CmpciNspdout);
967 1.10 itohy dip->un.e.member[2].ord = CMPCI_MONITOR_DAC_SPDOUT;
968 1.10 itohy return 0;
969 1.10 itohy
970 1.10 itohy case CMPCI_MASTER_VOL:
971 1.10 itohy dip->mixer_class = CMPCI_OUTPUT_CLASS;
972 1.10 itohy strcpy(dip->label.name, AudioNmaster);
973 1.10 itohy dip->un.v.num_channels = 2;
974 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS);
975 1.10 itohy goto vol;
976 1.7 tshiozak case CMPCI_REAR:
977 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
978 1.7 tshiozak dip->next = CMPCI_INDIVIDUAL;
979 1.7 tshiozak strcpy(dip->label.name, CmpciNrear);
980 1.7 tshiozak goto on_off;
981 1.7 tshiozak case CMPCI_INDIVIDUAL:
982 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
983 1.7 tshiozak dip->prev = CMPCI_REAR;
984 1.7 tshiozak dip->next = CMPCI_REVERSE;
985 1.7 tshiozak strcpy(dip->label.name, CmpciNindividual);
986 1.7 tshiozak goto on_off;
987 1.7 tshiozak case CMPCI_REVERSE:
988 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
989 1.7 tshiozak dip->prev = CMPCI_INDIVIDUAL;
990 1.7 tshiozak strcpy(dip->label.name, CmpciNreverse);
991 1.10 itohy goto on_off;
992 1.7 tshiozak case CMPCI_SURROUND:
993 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
994 1.7 tshiozak strcpy(dip->label.name, CmpciNsurround);
995 1.7 tshiozak goto on_off;
996 1.10 itohy }
997 1.7 tshiozak
998 1.1 augustss return ENXIO;
999 1.1 augustss }
1000 1.1 augustss
1001 1.1 augustss static int
1002 1.43 jmcneill cmpci_alloc_dmamem(struct cmpci_softc *sc, size_t size, void **r_addr)
1003 1.1 augustss {
1004 1.28 kent int error;
1005 1.1 augustss struct cmpci_dmanode *n;
1006 1.1 augustss
1007 1.28 kent error = 0;
1008 1.49 maxv n = kmem_alloc(sizeof(*n), KM_SLEEP);
1009 1.1 augustss
1010 1.1 augustss #define CMPCI_DMABUF_ALIGN 0x4
1011 1.1 augustss #define CMPCI_DMABUF_BOUNDARY 0x0
1012 1.1 augustss n->cd_tag = sc->sc_dmat;
1013 1.1 augustss n->cd_size = size;
1014 1.1 augustss error = bus_dmamem_alloc(n->cd_tag, n->cd_size,
1015 1.1 augustss CMPCI_DMABUF_ALIGN, CMPCI_DMABUF_BOUNDARY, n->cd_segs,
1016 1.43 jmcneill sizeof(n->cd_segs)/sizeof(n->cd_segs[0]), &n->cd_nsegs,
1017 1.43 jmcneill BUS_DMA_WAITOK);
1018 1.1 augustss if (error)
1019 1.1 augustss goto mfree;
1020 1.1 augustss error = bus_dmamem_map(n->cd_tag, n->cd_segs, n->cd_nsegs, n->cd_size,
1021 1.43 jmcneill &n->cd_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
1022 1.1 augustss if (error)
1023 1.1 augustss goto dmafree;
1024 1.1 augustss error = bus_dmamap_create(n->cd_tag, n->cd_size, 1, n->cd_size, 0,
1025 1.43 jmcneill BUS_DMA_WAITOK, &n->cd_map);
1026 1.1 augustss if (error)
1027 1.1 augustss goto unmap;
1028 1.1 augustss error = bus_dmamap_load(n->cd_tag, n->cd_map, n->cd_addr, n->cd_size,
1029 1.43 jmcneill NULL, BUS_DMA_WAITOK);
1030 1.1 augustss if (error)
1031 1.1 augustss goto destroy;
1032 1.10 itohy
1033 1.1 augustss n->cd_next = sc->sc_dmap;
1034 1.1 augustss sc->sc_dmap = n;
1035 1.1 augustss *r_addr = KVADDR(n);
1036 1.1 augustss return 0;
1037 1.10 itohy
1038 1.1 augustss destroy:
1039 1.1 augustss bus_dmamap_destroy(n->cd_tag, n->cd_map);
1040 1.1 augustss unmap:
1041 1.1 augustss bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size);
1042 1.1 augustss dmafree:
1043 1.1 augustss bus_dmamem_free(n->cd_tag,
1044 1.1 augustss n->cd_segs, sizeof(n->cd_segs)/sizeof(n->cd_segs[0]));
1045 1.1 augustss mfree:
1046 1.43 jmcneill kmem_free(n, sizeof(*n));
1047 1.1 augustss return error;
1048 1.1 augustss }
1049 1.1 augustss
1050 1.1 augustss static int
1051 1.43 jmcneill cmpci_free_dmamem(struct cmpci_softc *sc, void *addr, size_t size)
1052 1.1 augustss {
1053 1.1 augustss struct cmpci_dmanode **nnp;
1054 1.10 itohy
1055 1.1 augustss for (nnp = &sc->sc_dmap; *nnp; nnp= &(*nnp)->cd_next) {
1056 1.1 augustss if ((*nnp)->cd_addr == addr) {
1057 1.1 augustss struct cmpci_dmanode *n = *nnp;
1058 1.1 augustss bus_dmamap_unload(n->cd_tag, n->cd_map);
1059 1.1 augustss bus_dmamap_destroy(n->cd_tag, n->cd_map);
1060 1.1 augustss bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size);
1061 1.1 augustss bus_dmamem_free(n->cd_tag, n->cd_segs,
1062 1.1 augustss sizeof(n->cd_segs)/sizeof(n->cd_segs[0]));
1063 1.43 jmcneill kmem_free(n, sizeof(*n));
1064 1.1 augustss return 0;
1065 1.1 augustss }
1066 1.1 augustss }
1067 1.1 augustss return -1;
1068 1.1 augustss }
1069 1.1 augustss
1070 1.1 augustss static struct cmpci_dmanode *
1071 1.35 christos cmpci_find_dmamem(struct cmpci_softc *sc, void *addr)
1072 1.1 augustss {
1073 1.1 augustss struct cmpci_dmanode *p;
1074 1.10 itohy
1075 1.28 kent for (p = sc->sc_dmap; p; p = p->cd_next)
1076 1.28 kent if (KVADDR(p) == (void *)addr)
1077 1.1 augustss break;
1078 1.1 augustss return p;
1079 1.1 augustss }
1080 1.1 augustss
1081 1.1 augustss #if 0
1082 1.1 augustss static void
1083 1.28 kent cmpci_print_dmamem(struct cmpci_dmanode *);
1084 1.1 augustss static void
1085 1.28 kent cmpci_print_dmamem(struct cmpci_dmanode *p)
1086 1.1 augustss {
1087 1.28 kent
1088 1.1 augustss DPRINTF(("DMA at virt:%p, dmaseg:%p, mapseg:%p, size:%p\n",
1089 1.1 augustss (void *)p->cd_addr, (void *)p->cd_segs[0].ds_addr,
1090 1.1 augustss (void *)DMAADDR(p), (void *)p->cd_size));
1091 1.1 augustss }
1092 1.1 augustss #endif /* DEBUG */
1093 1.1 augustss
1094 1.1 augustss static void *
1095 1.43 jmcneill cmpci_allocm(void *handle, int direction, size_t size)
1096 1.1 augustss {
1097 1.35 christos void *addr;
1098 1.10 itohy
1099 1.31 mrg addr = NULL; /* XXX gcc */
1100 1.31 mrg
1101 1.43 jmcneill if (cmpci_alloc_dmamem(handle, size, &addr))
1102 1.1 augustss return NULL;
1103 1.1 augustss return addr;
1104 1.1 augustss }
1105 1.1 augustss
1106 1.1 augustss static void
1107 1.43 jmcneill cmpci_freem(void *handle, void *addr, size_t size)
1108 1.1 augustss {
1109 1.10 itohy
1110 1.43 jmcneill cmpci_free_dmamem(handle, addr, size);
1111 1.1 augustss }
1112 1.1 augustss
1113 1.1 augustss #define MAXVAL 256
1114 1.1 augustss static int
1115 1.28 kent cmpci_adjust(int val, int mask)
1116 1.1 augustss {
1117 1.28 kent
1118 1.1 augustss val += (MAXVAL - mask) >> 1;
1119 1.1 augustss if (val >= MAXVAL)
1120 1.1 augustss val = MAXVAL-1;
1121 1.1 augustss return val & mask;
1122 1.1 augustss }
1123 1.1 augustss
1124 1.1 augustss static void
1125 1.28 kent cmpci_set_mixer_gain(struct cmpci_softc *sc, int port)
1126 1.1 augustss {
1127 1.23 itohy int src;
1128 1.10 itohy int bits, mask;
1129 1.1 augustss
1130 1.1 augustss switch (port) {
1131 1.1 augustss case CMPCI_MIC_VOL:
1132 1.10 itohy cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_MIC,
1133 1.10 itohy CMPCI_ADJUST_MIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1134 1.23 itohy return;
1135 1.1 augustss case CMPCI_MASTER_VOL:
1136 1.1 augustss src = CMPCI_SB16_MIXER_MASTER_L;
1137 1.1 augustss break;
1138 1.1 augustss case CMPCI_LINE_IN_VOL:
1139 1.1 augustss src = CMPCI_SB16_MIXER_LINE_L;
1140 1.1 augustss break;
1141 1.10 itohy case CMPCI_AUX_IN_VOL:
1142 1.10 itohy bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MIXER_AUX,
1143 1.10 itohy CMPCI_ADJUST_AUX_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT],
1144 1.10 itohy sc->sc_gain[port][CMPCI_RIGHT]));
1145 1.10 itohy return;
1146 1.10 itohy case CMPCI_MIC_RECVOL:
1147 1.10 itohy cmpci_reg_partial_write_1(sc, CMPCI_REG_MIXER25,
1148 1.10 itohy CMPCI_REG_ADMIC_SHIFT, CMPCI_REG_ADMIC_MASK,
1149 1.10 itohy CMPCI_ADJUST_ADMIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1150 1.10 itohy return;
1151 1.10 itohy case CMPCI_DAC_VOL:
1152 1.1 augustss src = CMPCI_SB16_MIXER_VOICE_L;
1153 1.1 augustss break;
1154 1.1 augustss case CMPCI_FM_VOL:
1155 1.1 augustss src = CMPCI_SB16_MIXER_FM_L;
1156 1.1 augustss break;
1157 1.1 augustss case CMPCI_CD_VOL:
1158 1.1 augustss src = CMPCI_SB16_MIXER_CDDA_L;
1159 1.1 augustss break;
1160 1.1 augustss case CMPCI_PCSPEAKER:
1161 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_SPEAKER,
1162 1.10 itohy CMPCI_ADJUST_2_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1163 1.10 itohy return;
1164 1.10 itohy case CMPCI_MIC_PREAMP:
1165 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1166 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1167 1.10 itohy CMPCI_REG_MICGAINZ);
1168 1.10 itohy else
1169 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1170 1.10 itohy CMPCI_REG_MICGAINZ);
1171 1.7 tshiozak return;
1172 1.10 itohy
1173 1.10 itohy case CMPCI_DAC_MUTE:
1174 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1175 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1176 1.10 itohy CMPCI_REG_WSMUTE);
1177 1.10 itohy else
1178 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1179 1.10 itohy CMPCI_REG_WSMUTE);
1180 1.10 itohy return;
1181 1.10 itohy case CMPCI_FM_MUTE:
1182 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1183 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1184 1.10 itohy CMPCI_REG_FMMUTE);
1185 1.10 itohy else
1186 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1187 1.10 itohy CMPCI_REG_FMMUTE);
1188 1.10 itohy return;
1189 1.10 itohy case CMPCI_AUX_IN_MUTE:
1190 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1191 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1192 1.10 itohy CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM);
1193 1.10 itohy else
1194 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1195 1.10 itohy CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM);
1196 1.10 itohy return;
1197 1.10 itohy case CMPCI_CD_MUTE:
1198 1.10 itohy mask = CMPCI_SB16_SW_CD;
1199 1.10 itohy goto sbmute;
1200 1.10 itohy case CMPCI_MIC_MUTE:
1201 1.10 itohy mask = CMPCI_SB16_SW_MIC;
1202 1.10 itohy goto sbmute;
1203 1.10 itohy case CMPCI_LINE_IN_MUTE:
1204 1.10 itohy mask = CMPCI_SB16_SW_LINE;
1205 1.10 itohy sbmute:
1206 1.10 itohy bits = cmpci_mixerreg_read(sc, CMPCI_SB16_MIXER_OUTMIX);
1207 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1208 1.10 itohy bits = bits & ~mask;
1209 1.10 itohy else
1210 1.10 itohy bits = bits | mask;
1211 1.10 itohy cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX, bits);
1212 1.8 itohy return;
1213 1.10 itohy
1214 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1215 1.10 itohy case CMPCI_MONITOR_DAC:
1216 1.10 itohy case CMPCI_PLAYBACK_MODE:
1217 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1218 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1219 1.7 tshiozak cmpci_set_out_ports(sc);
1220 1.7 tshiozak return;
1221 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1222 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDOUT_VOLTAGE)) {
1223 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_OUT_VOLTAGE][CMPCI_LR]
1224 1.21 itohy == CMPCI_SPDIF_OUT_VOLTAGE_HIGH)
1225 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_5V);
1226 1.10 itohy else
1227 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_5V);
1228 1.7 tshiozak }
1229 1.7 tshiozak return;
1230 1.7 tshiozak case CMPCI_SURROUND:
1231 1.7 tshiozak if (CMPCI_ISCAP(sc, SURROUND)) {
1232 1.7 tshiozak if (sc->sc_gain[CMPCI_SURROUND][CMPCI_LR])
1233 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1234 1.7 tshiozak CMPCI_REG_SURROUND);
1235 1.7 tshiozak else
1236 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1237 1.7 tshiozak CMPCI_REG_SURROUND);
1238 1.7 tshiozak }
1239 1.7 tshiozak return;
1240 1.7 tshiozak case CMPCI_REAR:
1241 1.7 tshiozak if (CMPCI_ISCAP(sc, REAR)) {
1242 1.7 tshiozak if (sc->sc_gain[CMPCI_REAR][CMPCI_LR])
1243 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_N4SPK3D);
1244 1.7 tshiozak else
1245 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_N4SPK3D);
1246 1.7 tshiozak }
1247 1.7 tshiozak return;
1248 1.7 tshiozak case CMPCI_INDIVIDUAL:
1249 1.7 tshiozak if (CMPCI_ISCAP(sc, INDIVIDUAL_REAR)) {
1250 1.7 tshiozak if (sc->sc_gain[CMPCI_REAR][CMPCI_LR])
1251 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1252 1.7 tshiozak CMPCI_REG_INDIVIDUAL);
1253 1.7 tshiozak else
1254 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1255 1.7 tshiozak CMPCI_REG_INDIVIDUAL);
1256 1.7 tshiozak }
1257 1.7 tshiozak return;
1258 1.7 tshiozak case CMPCI_REVERSE:
1259 1.7 tshiozak if (CMPCI_ISCAP(sc, REVERSE_FR)) {
1260 1.7 tshiozak if (sc->sc_gain[CMPCI_REVERSE][CMPCI_LR])
1261 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1262 1.7 tshiozak CMPCI_REG_REVERSE_FR);
1263 1.7 tshiozak else
1264 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1265 1.7 tshiozak CMPCI_REG_REVERSE_FR);
1266 1.7 tshiozak }
1267 1.7 tshiozak return;
1268 1.7 tshiozak case CMPCI_SPDIF_IN_PHASE:
1269 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDIN_PHASE)) {
1270 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_IN_PHASE][CMPCI_LR]
1271 1.10 itohy == CMPCI_SPDIF_IN_PHASE_POSITIVE)
1272 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_CHANNEL_FORMAT,
1273 1.10 itohy CMPCI_REG_SPDIN_PHASE);
1274 1.10 itohy else
1275 1.8 itohy cmpci_reg_set_1(sc, CMPCI_REG_CHANNEL_FORMAT,
1276 1.8 itohy CMPCI_REG_SPDIN_PHASE);
1277 1.7 tshiozak }
1278 1.1 augustss return;
1279 1.1 augustss default:
1280 1.1 augustss return;
1281 1.1 augustss }
1282 1.10 itohy
1283 1.10 itohy cmpci_mixerreg_write(sc, src,
1284 1.10 itohy CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT]));
1285 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_L_TO_R(src),
1286 1.10 itohy CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_RIGHT]));
1287 1.7 tshiozak }
1288 1.7 tshiozak
1289 1.7 tshiozak static void
1290 1.28 kent cmpci_set_out_ports(struct cmpci_softc *sc)
1291 1.7 tshiozak {
1292 1.28 kent uint8_t v;
1293 1.28 kent int enspdout;
1294 1.10 itohy
1295 1.7 tshiozak if (!CMPCI_ISCAP(sc, SPDLOOP))
1296 1.7 tshiozak return;
1297 1.10 itohy
1298 1.10 itohy /* SPDIF/out select */
1299 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_LOOP][CMPCI_LR] == CMPCI_SPDIF_LOOP_OFF) {
1300 1.10 itohy /* playback */
1301 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
1302 1.10 itohy } else {
1303 1.10 itohy /* monitor SPDIF/in */
1304 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
1305 1.10 itohy }
1306 1.10 itohy
1307 1.10 itohy /* SPDIF in select */
1308 1.10 itohy v = sc->sc_gain[CMPCI_SPDIF_IN_SELECT][CMPCI_LR];
1309 1.10 itohy if (v & CMPCI_SPDIFIN_SPDIFIN2)
1310 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_2ND_SPDIFIN);
1311 1.10 itohy else
1312 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_2ND_SPDIFIN);
1313 1.10 itohy if (v & CMPCI_SPDIFIN_SPDIFOUT)
1314 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_SPDFLOOPI);
1315 1.10 itohy else
1316 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_SPDFLOOPI);
1317 1.10 itohy
1318 1.28 kent enspdout = 0;
1319 1.10 itohy /* playback to ... */
1320 1.10 itohy if (CMPCI_ISCAP(sc, SPDOUT) &&
1321 1.10 itohy sc->sc_gain[CMPCI_PLAYBACK_MODE][CMPCI_LR]
1322 1.10 itohy == CMPCI_PLAYBACK_MODE_SPDIF &&
1323 1.10 itohy (sc->sc_play.md_divide == CMPCI_REG_RATE_44100 ||
1324 1.10 itohy (CMPCI_ISCAP(sc, SPDOUT_48K) &&
1325 1.10 itohy sc->sc_play.md_divide==CMPCI_REG_RATE_48000))) {
1326 1.10 itohy /* playback to SPDIF */
1327 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF0_ENABLE);
1328 1.10 itohy enspdout = 1;
1329 1.10 itohy if (sc->sc_play.md_divide==CMPCI_REG_RATE_48000)
1330 1.21 itohy cmpci_reg_set_reg_misc(sc,
1331 1.21 itohy CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K);
1332 1.10 itohy else
1333 1.21 itohy cmpci_reg_clear_reg_misc(sc,
1334 1.21 itohy CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K);
1335 1.10 itohy } else {
1336 1.10 itohy /* playback to DAC */
1337 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1,
1338 1.10 itohy CMPCI_REG_SPDIF0_ENABLE);
1339 1.10 itohy if (CMPCI_ISCAP(sc, SPDOUT_48K))
1340 1.21 itohy cmpci_reg_clear_reg_misc(sc,
1341 1.21 itohy CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K);
1342 1.10 itohy }
1343 1.10 itohy
1344 1.10 itohy /* legacy to SPDIF/out or not */
1345 1.10 itohy if (CMPCI_ISCAP(sc, SPDLEGACY)) {
1346 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_OUT_PLAYBACK][CMPCI_LR]
1347 1.10 itohy == CMPCI_SPDIF_OUT_PLAYBACK_WAVE)
1348 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL,
1349 1.10 itohy CMPCI_REG_LEGACY_SPDIF_ENABLE);
1350 1.10 itohy else {
1351 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL,
1352 1.10 itohy CMPCI_REG_LEGACY_SPDIF_ENABLE);
1353 1.10 itohy enspdout = 1;
1354 1.10 itohy }
1355 1.10 itohy }
1356 1.10 itohy
1357 1.10 itohy /* enable/disable SPDIF/out */
1358 1.10 itohy if (CMPCI_ISCAP(sc, XSPDOUT) && enspdout)
1359 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL,
1360 1.10 itohy CMPCI_REG_XSPDIF_ENABLE);
1361 1.10 itohy else
1362 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL,
1363 1.10 itohy CMPCI_REG_XSPDIF_ENABLE);
1364 1.10 itohy
1365 1.25 xtraeme /* SPDIF monitor (digital to analog output) */
1366 1.10 itohy if (CMPCI_ISCAP(sc, SPDIN_MONITOR)) {
1367 1.10 itohy v = sc->sc_gain[CMPCI_MONITOR_DAC][CMPCI_LR];
1368 1.10 itohy if (!(v & CMPCI_MONDAC_ENABLE))
1369 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1370 1.10 itohy CMPCI_REG_SPDIN_MONITOR);
1371 1.10 itohy if (v & CMPCI_MONDAC_SPDOUT)
1372 1.7 tshiozak cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1,
1373 1.10 itohy CMPCI_REG_SPDIFOUT_DAC);
1374 1.10 itohy else
1375 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1,
1376 1.10 itohy CMPCI_REG_SPDIFOUT_DAC);
1377 1.10 itohy if (v & CMPCI_MONDAC_ENABLE)
1378 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1379 1.10 itohy CMPCI_REG_SPDIN_MONITOR);
1380 1.7 tshiozak }
1381 1.1 augustss }
1382 1.1 augustss
1383 1.1 augustss static int
1384 1.28 kent cmpci_set_in_ports(struct cmpci_softc *sc)
1385 1.10 itohy {
1386 1.1 augustss int mask;
1387 1.1 augustss int bitsl, bitsr;
1388 1.1 augustss
1389 1.10 itohy mask = sc->sc_in_mask;
1390 1.10 itohy
1391 1.10 itohy /*
1392 1.10 itohy * Note CMPCI_RECORD_SOURCE_CD, CMPCI_RECORD_SOURCE_LINE_IN and
1393 1.10 itohy * CMPCI_RECORD_SOURCE_FM are defined to the corresponding bit
1394 1.10 itohy * of the mixer register.
1395 1.10 itohy */
1396 1.10 itohy bitsr = mask & (CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |
1397 1.10 itohy CMPCI_RECORD_SOURCE_FM);
1398 1.10 itohy
1399 1.1 augustss bitsl = CMPCI_SB16_MIXER_SRC_R_TO_L(bitsr);
1400 1.8 itohy if (mask & CMPCI_RECORD_SOURCE_MIC) {
1401 1.1 augustss bitsl |= CMPCI_SB16_MIXER_MIC_SRC;
1402 1.1 augustss bitsr |= CMPCI_SB16_MIXER_MIC_SRC;
1403 1.1 augustss }
1404 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, bitsl);
1405 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, bitsr);
1406 1.10 itohy
1407 1.10 itohy if (mask & CMPCI_RECORD_SOURCE_AUX_IN)
1408 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1409 1.10 itohy CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN);
1410 1.10 itohy else
1411 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1412 1.10 itohy CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN);
1413 1.10 itohy
1414 1.10 itohy if (mask & CMPCI_RECORD_SOURCE_WAVE)
1415 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1416 1.10 itohy CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR);
1417 1.10 itohy else
1418 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1419 1.10 itohy CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR);
1420 1.10 itohy
1421 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDIN) &&
1422 1.10 itohy (sc->sc_rec.md_divide == CMPCI_REG_RATE_44100 ||
1423 1.10 itohy (CMPCI_ISCAP(sc, SPDOUT_48K) &&
1424 1.10 itohy sc->sc_rec.md_divide == CMPCI_REG_RATE_48000/* XXX? */))) {
1425 1.8 itohy if (mask & CMPCI_RECORD_SOURCE_SPDIF) {
1426 1.7 tshiozak /* enable SPDIF/in */
1427 1.7 tshiozak cmpci_reg_set_4(sc,
1428 1.7 tshiozak CMPCI_REG_FUNC_1,
1429 1.7 tshiozak CMPCI_REG_SPDIF1_ENABLE);
1430 1.7 tshiozak } else {
1431 1.7 tshiozak cmpci_reg_clear_4(sc,
1432 1.7 tshiozak CMPCI_REG_FUNC_1,
1433 1.7 tshiozak CMPCI_REG_SPDIF1_ENABLE);
1434 1.7 tshiozak }
1435 1.7 tshiozak }
1436 1.1 augustss
1437 1.1 augustss return 0;
1438 1.1 augustss }
1439 1.1 augustss
1440 1.1 augustss static int
1441 1.28 kent cmpci_set_port(void *handle, mixer_ctrl_t *cp)
1442 1.1 augustss {
1443 1.28 kent struct cmpci_softc *sc;
1444 1.1 augustss int lgain, rgain;
1445 1.10 itohy
1446 1.28 kent sc = handle;
1447 1.1 augustss switch (cp->dev) {
1448 1.10 itohy case CMPCI_MIC_VOL:
1449 1.1 augustss case CMPCI_PCSPEAKER:
1450 1.10 itohy case CMPCI_MIC_RECVOL:
1451 1.10 itohy if (cp->un.value.num_channels != 1)
1452 1.10 itohy return EINVAL;
1453 1.10 itohy /* FALLTHROUGH */
1454 1.10 itohy case CMPCI_DAC_VOL:
1455 1.1 augustss case CMPCI_FM_VOL:
1456 1.1 augustss case CMPCI_CD_VOL:
1457 1.10 itohy case CMPCI_LINE_IN_VOL:
1458 1.10 itohy case CMPCI_AUX_IN_VOL:
1459 1.1 augustss case CMPCI_MASTER_VOL:
1460 1.1 augustss if (cp->type != AUDIO_MIXER_VALUE)
1461 1.1 augustss return EINVAL;
1462 1.10 itohy switch (cp->un.value.num_channels) {
1463 1.10 itohy case 1:
1464 1.1 augustss lgain = rgain =
1465 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_MONO];
1466 1.1 augustss break;
1467 1.10 itohy case 2:
1468 1.10 itohy lgain = cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT];
1469 1.10 itohy rgain = cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT];
1470 1.1 augustss break;
1471 1.1 augustss default:
1472 1.10 itohy return EINVAL;
1473 1.1 augustss }
1474 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT] = lgain;
1475 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_RIGHT] = rgain;
1476 1.1 augustss
1477 1.1 augustss cmpci_set_mixer_gain(sc, cp->dev);
1478 1.1 augustss break;
1479 1.1 augustss
1480 1.1 augustss case CMPCI_RECORD_SOURCE:
1481 1.1 augustss if (cp->type != AUDIO_MIXER_SET)
1482 1.1 augustss return EINVAL;
1483 1.8 itohy
1484 1.10 itohy if (cp->un.mask & ~(CMPCI_RECORD_SOURCE_MIC |
1485 1.10 itohy CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |
1486 1.10 itohy CMPCI_RECORD_SOURCE_AUX_IN | CMPCI_RECORD_SOURCE_WAVE |
1487 1.10 itohy CMPCI_RECORD_SOURCE_FM | CMPCI_RECORD_SOURCE_SPDIF))
1488 1.10 itohy return EINVAL;
1489 1.10 itohy
1490 1.8 itohy if (cp->un.mask & CMPCI_RECORD_SOURCE_SPDIF)
1491 1.8 itohy cp->un.mask = CMPCI_RECORD_SOURCE_SPDIF;
1492 1.8 itohy
1493 1.10 itohy sc->sc_in_mask = cp->un.mask;
1494 1.10 itohy return cmpci_set_in_ports(sc);
1495 1.1 augustss
1496 1.10 itohy /* boolean */
1497 1.10 itohy case CMPCI_DAC_MUTE:
1498 1.10 itohy case CMPCI_FM_MUTE:
1499 1.10 itohy case CMPCI_CD_MUTE:
1500 1.10 itohy case CMPCI_LINE_IN_MUTE:
1501 1.10 itohy case CMPCI_AUX_IN_MUTE:
1502 1.10 itohy case CMPCI_MIC_MUTE:
1503 1.10 itohy case CMPCI_MIC_PREAMP:
1504 1.10 itohy case CMPCI_PLAYBACK_MODE:
1505 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
1506 1.10 itohy case CMPCI_SPDIF_LOOP:
1507 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1508 1.10 itohy case CMPCI_SPDIF_OUT_VOLTAGE:
1509 1.10 itohy case CMPCI_REAR:
1510 1.10 itohy case CMPCI_INDIVIDUAL:
1511 1.10 itohy case CMPCI_REVERSE:
1512 1.10 itohy case CMPCI_SURROUND:
1513 1.1 augustss if (cp->type != AUDIO_MIXER_ENUM)
1514 1.1 augustss return EINVAL;
1515 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord != 0;
1516 1.10 itohy cmpci_set_mixer_gain(sc, cp->dev);
1517 1.1 augustss break;
1518 1.1 augustss
1519 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1520 1.10 itohy switch (cp->un.ord) {
1521 1.10 itohy case CMPCI_SPDIF_IN_SPDIN1:
1522 1.10 itohy case CMPCI_SPDIF_IN_SPDIN2:
1523 1.10 itohy case CMPCI_SPDIF_IN_SPDOUT:
1524 1.10 itohy break;
1525 1.10 itohy default:
1526 1.1 augustss return EINVAL;
1527 1.1 augustss }
1528 1.10 itohy goto xenum;
1529 1.10 itohy case CMPCI_MONITOR_DAC:
1530 1.10 itohy switch (cp->un.ord) {
1531 1.10 itohy case CMPCI_MONITOR_DAC_OFF:
1532 1.10 itohy case CMPCI_MONITOR_DAC_SPDIN:
1533 1.10 itohy case CMPCI_MONITOR_DAC_SPDOUT:
1534 1.10 itohy break;
1535 1.10 itohy default:
1536 1.10 itohy return EINVAL;
1537 1.1 augustss }
1538 1.10 itohy xenum:
1539 1.10 itohy if (cp->type != AUDIO_MIXER_ENUM)
1540 1.10 itohy return EINVAL;
1541 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord;
1542 1.10 itohy cmpci_set_mixer_gain(sc, cp->dev);
1543 1.7 tshiozak break;
1544 1.10 itohy
1545 1.1 augustss default:
1546 1.1 augustss return EINVAL;
1547 1.1 augustss }
1548 1.10 itohy
1549 1.1 augustss return 0;
1550 1.1 augustss }
1551 1.1 augustss
1552 1.1 augustss static int
1553 1.28 kent cmpci_get_port(void *handle, mixer_ctrl_t *cp)
1554 1.1 augustss {
1555 1.28 kent struct cmpci_softc *sc;
1556 1.10 itohy
1557 1.28 kent sc = handle;
1558 1.1 augustss switch (cp->dev) {
1559 1.1 augustss case CMPCI_MIC_VOL:
1560 1.10 itohy case CMPCI_PCSPEAKER:
1561 1.10 itohy case CMPCI_MIC_RECVOL:
1562 1.1 augustss if (cp->un.value.num_channels != 1)
1563 1.1 augustss return EINVAL;
1564 1.12 itohy /*FALLTHROUGH*/
1565 1.10 itohy case CMPCI_DAC_VOL:
1566 1.1 augustss case CMPCI_FM_VOL:
1567 1.1 augustss case CMPCI_CD_VOL:
1568 1.10 itohy case CMPCI_LINE_IN_VOL:
1569 1.10 itohy case CMPCI_AUX_IN_VOL:
1570 1.1 augustss case CMPCI_MASTER_VOL:
1571 1.1 augustss switch (cp->un.value.num_channels) {
1572 1.1 augustss case 1:
1573 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
1574 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT];
1575 1.1 augustss break;
1576 1.1 augustss case 2:
1577 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
1578 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT];
1579 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
1580 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_RIGHT];
1581 1.1 augustss break;
1582 1.1 augustss default:
1583 1.1 augustss return EINVAL;
1584 1.1 augustss }
1585 1.1 augustss break;
1586 1.10 itohy
1587 1.1 augustss case CMPCI_RECORD_SOURCE:
1588 1.7 tshiozak cp->un.mask = sc->sc_in_mask;
1589 1.1 augustss break;
1590 1.1 augustss
1591 1.10 itohy case CMPCI_DAC_MUTE:
1592 1.10 itohy case CMPCI_FM_MUTE:
1593 1.10 itohy case CMPCI_CD_MUTE:
1594 1.1 augustss case CMPCI_LINE_IN_MUTE:
1595 1.10 itohy case CMPCI_AUX_IN_MUTE:
1596 1.10 itohy case CMPCI_MIC_MUTE:
1597 1.10 itohy case CMPCI_MIC_PREAMP:
1598 1.10 itohy case CMPCI_PLAYBACK_MODE:
1599 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1600 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
1601 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1602 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1603 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1604 1.10 itohy case CMPCI_MONITOR_DAC:
1605 1.7 tshiozak case CMPCI_REAR:
1606 1.7 tshiozak case CMPCI_INDIVIDUAL:
1607 1.7 tshiozak case CMPCI_REVERSE:
1608 1.7 tshiozak case CMPCI_SURROUND:
1609 1.7 tshiozak cp->un.ord = sc->sc_gain[cp->dev][CMPCI_LR];
1610 1.1 augustss break;
1611 1.1 augustss
1612 1.1 augustss default:
1613 1.1 augustss return EINVAL;
1614 1.1 augustss }
1615 1.1 augustss
1616 1.1 augustss return 0;
1617 1.1 augustss }
1618 1.1 augustss
1619 1.1 augustss /* ARGSUSED */
1620 1.1 augustss static size_t
1621 1.34 christos cmpci_round_buffersize(void *handle, int direction,
1622 1.33 christos size_t bufsize)
1623 1.1 augustss {
1624 1.28 kent
1625 1.1 augustss if (bufsize > 0x10000)
1626 1.1 augustss bufsize = 0x10000;
1627 1.10 itohy
1628 1.1 augustss return bufsize;
1629 1.1 augustss }
1630 1.1 augustss
1631 1.4 simonb static paddr_t
1632 1.28 kent cmpci_mappage(void *handle, void *addr, off_t offset, int prot)
1633 1.1 augustss {
1634 1.1 augustss struct cmpci_dmanode *p;
1635 1.10 itohy
1636 1.28 kent if (offset < 0 || NULL == (p = cmpci_find_dmamem(handle, addr)))
1637 1.1 augustss return -1;
1638 1.1 augustss
1639 1.1 augustss return bus_dmamem_mmap(p->cd_tag, p->cd_segs,
1640 1.7 tshiozak sizeof(p->cd_segs)/sizeof(p->cd_segs[0]),
1641 1.7 tshiozak offset, prot, BUS_DMA_WAITOK);
1642 1.1 augustss }
1643 1.1 augustss
1644 1.1 augustss /* ARGSUSED */
1645 1.1 augustss static int
1646 1.34 christos cmpci_get_props(void *handle)
1647 1.1 augustss {
1648 1.28 kent
1649 1.1 augustss return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
1650 1.1 augustss }
1651 1.1 augustss
1652 1.1 augustss static int
1653 1.28 kent cmpci_trigger_output(void *handle, void *start, void *end, int blksize,
1654 1.28 kent void (*intr)(void *), void *arg,
1655 1.28 kent const audio_params_t *param)
1656 1.1 augustss {
1657 1.28 kent struct cmpci_softc *sc;
1658 1.1 augustss struct cmpci_dmanode *p;
1659 1.1 augustss int bps;
1660 1.1 augustss
1661 1.28 kent sc = handle;
1662 1.1 augustss sc->sc_play.intr = intr;
1663 1.1 augustss sc->sc_play.intr_arg = arg;
1664 1.27 kent bps = param->channels * param->precision / 8;
1665 1.1 augustss if (!bps)
1666 1.1 augustss return EINVAL;
1667 1.1 augustss
1668 1.1 augustss /* set DMA frame */
1669 1.1 augustss if (!(p = cmpci_find_dmamem(sc, start)))
1670 1.1 augustss return EINVAL;
1671 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BASE,
1672 1.1 augustss DMAADDR(p));
1673 1.1 augustss delay(10);
1674 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BYTES,
1675 1.35 christos ((char *)end - (char *)start + 1) / bps - 1);
1676 1.1 augustss delay(10);
1677 1.1 augustss
1678 1.1 augustss /* set interrupt count */
1679 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_SAMPLES,
1680 1.1 augustss (blksize + bps - 1) / bps - 1);
1681 1.1 augustss delay(10);
1682 1.1 augustss
1683 1.1 augustss /* start DMA */
1684 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); /* PLAY */
1685 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
1686 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
1687 1.10 itohy
1688 1.1 augustss return 0;
1689 1.1 augustss }
1690 1.1 augustss
1691 1.1 augustss static int
1692 1.28 kent cmpci_trigger_input(void *handle, void *start, void *end, int blksize,
1693 1.28 kent void (*intr)(void *), void *arg,
1694 1.28 kent const audio_params_t *param)
1695 1.1 augustss {
1696 1.28 kent struct cmpci_softc *sc;
1697 1.1 augustss struct cmpci_dmanode *p;
1698 1.1 augustss int bps;
1699 1.1 augustss
1700 1.28 kent sc = handle;
1701 1.1 augustss sc->sc_rec.intr = intr;
1702 1.1 augustss sc->sc_rec.intr_arg = arg;
1703 1.27 kent bps = param->channels * param->precision / 8;
1704 1.1 augustss if (!bps)
1705 1.1 augustss return EINVAL;
1706 1.1 augustss
1707 1.1 augustss /* set DMA frame */
1708 1.1 augustss if (!(p=cmpci_find_dmamem(sc, start)))
1709 1.1 augustss return EINVAL;
1710 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BASE,
1711 1.1 augustss DMAADDR(p));
1712 1.1 augustss delay(10);
1713 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BYTES,
1714 1.35 christos ((char *)end - (char *)start + 1) / bps - 1);
1715 1.1 augustss delay(10);
1716 1.1 augustss
1717 1.1 augustss /* set interrupt count */
1718 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_SAMPLES,
1719 1.7 tshiozak (blksize + bps - 1) / bps - 1);
1720 1.1 augustss delay(10);
1721 1.1 augustss
1722 1.1 augustss /* start DMA */
1723 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); /* REC */
1724 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
1725 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
1726 1.10 itohy
1727 1.1 augustss return 0;
1728 1.1 augustss }
1729 1.1 augustss
1730 1.43 jmcneill static void
1731 1.43 jmcneill cmpci_get_locks(void *addr, kmutex_t **intr, kmutex_t **thread)
1732 1.43 jmcneill {
1733 1.43 jmcneill struct cmpci_softc *sc;
1734 1.43 jmcneill
1735 1.43 jmcneill sc = addr;
1736 1.43 jmcneill *intr = &sc->sc_intr_lock;
1737 1.43 jmcneill *thread = &sc->sc_lock;
1738 1.43 jmcneill }
1739 1.43 jmcneill
1740 1.1 augustss /* end of file */
1741