cmpci.c revision 1.53.2.1 1 1.53.2.1 isaki /* $NetBSD: cmpci.c,v 1.53.2.1 2019/04/21 05:11:22 isaki Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.43 jmcneill * Copyright (c) 2000, 2001, 2008 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.22 keihan * by Takuya SHIOZAKI <tshiozak (at) NetBSD.org> .
9 1.1 augustss *
10 1.10 itohy * This code is derived from software contributed to The NetBSD Foundation
11 1.10 itohy * by ITOH Yasufumi.
12 1.10 itohy *
13 1.1 augustss * Redistribution and use in source and binary forms, with or without
14 1.1 augustss * modification, are permitted provided that the following conditions
15 1.1 augustss * are met:
16 1.1 augustss * 1. Redistributions of source code must retain the above copyright
17 1.1 augustss * notice, this list of conditions and the following disclaimer.
18 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
19 1.1 augustss * notice, this list of conditions and the following disclaimer in the
20 1.1 augustss * documentation and/or other materials provided with the distribution.
21 1.1 augustss *
22 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 1.1 augustss * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.1 augustss * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 augustss * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 1.1 augustss * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 1.1 augustss * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 1.1 augustss * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.1 augustss * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.1 augustss * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.1 augustss * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.1 augustss * SUCH DAMAGE.
33 1.1 augustss *
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * C-Media CMI8x38 Audio Chip Support.
38 1.1 augustss *
39 1.1 augustss * TODO:
40 1.10 itohy * - 4ch / 6ch support.
41 1.10 itohy * - Joystick support.
42 1.1 augustss *
43 1.1 augustss */
44 1.11 lukem
45 1.11 lukem #include <sys/cdefs.h>
46 1.53.2.1 isaki __KERNEL_RCSID(0, "$NetBSD: cmpci.c,v 1.53.2.1 2019/04/21 05:11:22 isaki Exp $");
47 1.1 augustss
48 1.1 augustss #if defined(AUDIO_DEBUG) || defined(DEBUG)
49 1.7 tshiozak #define DPRINTF(x) if (cmpcidebug) printf x
50 1.7 tshiozak int cmpcidebug = 0;
51 1.1 augustss #else
52 1.1 augustss #define DPRINTF(x)
53 1.1 augustss #endif
54 1.1 augustss
55 1.8 itohy #include "mpu.h"
56 1.8 itohy
57 1.1 augustss #include <sys/param.h>
58 1.1 augustss #include <sys/systm.h>
59 1.1 augustss #include <sys/kernel.h>
60 1.43 jmcneill #include <sys/kmem.h>
61 1.1 augustss #include <sys/device.h>
62 1.1 augustss #include <sys/proc.h>
63 1.1 augustss
64 1.1 augustss #include <dev/pci/pcidevs.h>
65 1.1 augustss #include <dev/pci/pcivar.h>
66 1.1 augustss
67 1.1 augustss #include <sys/audioio.h>
68 1.1 augustss #include <dev/audio_if.h>
69 1.1 augustss #include <dev/midi_if.h>
70 1.1 augustss
71 1.1 augustss #include <dev/mulaw.h>
72 1.1 augustss #include <dev/auconv.h>
73 1.1 augustss #include <dev/pci/cmpcireg.h>
74 1.1 augustss #include <dev/pci/cmpcivar.h>
75 1.1 augustss
76 1.1 augustss #include <dev/ic/mpuvar.h>
77 1.36 ad #include <sys/bus.h>
78 1.36 ad #include <sys/intr.h>
79 1.1 augustss
80 1.1 augustss /*
81 1.1 augustss * Low-level HW interface
82 1.1 augustss */
83 1.30 perry static inline uint8_t cmpci_mixerreg_read(struct cmpci_softc *, uint8_t);
84 1.30 perry static inline void cmpci_mixerreg_write(struct cmpci_softc *,
85 1.28 kent uint8_t, uint8_t);
86 1.30 perry static inline void cmpci_reg_partial_write_1(struct cmpci_softc *, int, int,
87 1.28 kent unsigned, unsigned);
88 1.30 perry static inline void cmpci_reg_partial_write_4(struct cmpci_softc *, int, int,
89 1.28 kent uint32_t, uint32_t);
90 1.30 perry static inline void cmpci_reg_set_1(struct cmpci_softc *, int, uint8_t);
91 1.30 perry static inline void cmpci_reg_clear_1(struct cmpci_softc *, int, uint8_t);
92 1.30 perry static inline void cmpci_reg_set_4(struct cmpci_softc *, int, uint32_t);
93 1.30 perry static inline void cmpci_reg_clear_4(struct cmpci_softc *, int, uint32_t);
94 1.30 perry static inline void cmpci_reg_set_reg_misc(struct cmpci_softc *, uint32_t);
95 1.30 perry static inline void cmpci_reg_clear_reg_misc(struct cmpci_softc *, uint32_t);
96 1.28 kent static int cmpci_rate_to_index(int);
97 1.30 perry static inline int cmpci_index_to_rate(int);
98 1.30 perry static inline int cmpci_index_to_divider(int);
99 1.28 kent
100 1.28 kent static int cmpci_adjust(int, int);
101 1.28 kent static void cmpci_set_mixer_gain(struct cmpci_softc *, int);
102 1.28 kent static void cmpci_set_out_ports(struct cmpci_softc *);
103 1.28 kent static int cmpci_set_in_ports(struct cmpci_softc *);
104 1.1 augustss
105 1.1 augustss
106 1.1 augustss /*
107 1.1 augustss * autoconf interface
108 1.1 augustss */
109 1.40 cegger static int cmpci_match(device_t, cfdata_t, void *);
110 1.40 cegger static void cmpci_attach(device_t, device_t, void *);
111 1.1 augustss
112 1.46 chs CFATTACH_DECL_NEW(cmpci, sizeof (struct cmpci_softc),
113 1.16 thorpej cmpci_match, cmpci_attach, NULL, NULL);
114 1.1 augustss
115 1.1 augustss /* interrupt */
116 1.28 kent static int cmpci_intr(void *);
117 1.1 augustss
118 1.1 augustss
119 1.1 augustss /*
120 1.1 augustss * DMA stuffs
121 1.1 augustss */
122 1.43 jmcneill static int cmpci_alloc_dmamem(struct cmpci_softc *, size_t, void **);
123 1.43 jmcneill static int cmpci_free_dmamem(struct cmpci_softc *, void *, size_t);
124 1.28 kent static struct cmpci_dmanode * cmpci_find_dmamem(struct cmpci_softc *,
125 1.35 christos void *);
126 1.1 augustss
127 1.1 augustss
128 1.1 augustss /*
129 1.1 augustss * interface to machine independent layer
130 1.1 augustss */
131 1.28 kent static int cmpci_query_encoding(void *, struct audio_encoding *);
132 1.28 kent static int cmpci_set_params(void *, int, int, audio_params_t *,
133 1.28 kent audio_params_t *, stream_filter_list_t *, stream_filter_list_t *);
134 1.28 kent static int cmpci_round_blocksize(void *, int, int, const audio_params_t *);
135 1.28 kent static int cmpci_halt_output(void *);
136 1.28 kent static int cmpci_halt_input(void *);
137 1.28 kent static int cmpci_getdev(void *, struct audio_device *);
138 1.28 kent static int cmpci_set_port(void *, mixer_ctrl_t *);
139 1.28 kent static int cmpci_get_port(void *, mixer_ctrl_t *);
140 1.28 kent static int cmpci_query_devinfo(void *, mixer_devinfo_t *);
141 1.43 jmcneill static void *cmpci_allocm(void *, int, size_t);
142 1.43 jmcneill static void cmpci_freem(void *, void *, size_t);
143 1.28 kent static size_t cmpci_round_buffersize(void *, int, size_t);
144 1.28 kent static paddr_t cmpci_mappage(void *, void *, off_t, int);
145 1.28 kent static int cmpci_get_props(void *);
146 1.28 kent static int cmpci_trigger_output(void *, void *, void *, int,
147 1.28 kent void (*)(void *), void *, const audio_params_t *);
148 1.28 kent static int cmpci_trigger_input(void *, void *, void *, int,
149 1.28 kent void (*)(void *), void *, const audio_params_t *);
150 1.43 jmcneill static void cmpci_get_locks(void *, kmutex_t **, kmutex_t **);
151 1.1 augustss
152 1.26 yamt static const struct audio_hw_if cmpci_hw_if = {
153 1.52 isaki .query_encoding = cmpci_query_encoding,
154 1.52 isaki .set_params = cmpci_set_params,
155 1.52 isaki .round_blocksize = cmpci_round_blocksize,
156 1.52 isaki .halt_output = cmpci_halt_output,
157 1.52 isaki .halt_input = cmpci_halt_input,
158 1.53 isaki .getdev = cmpci_getdev,
159 1.52 isaki .set_port = cmpci_set_port,
160 1.52 isaki .get_port = cmpci_get_port,
161 1.52 isaki .query_devinfo = cmpci_query_devinfo,
162 1.53 isaki .allocm = cmpci_allocm,
163 1.52 isaki .freem = cmpci_freem,
164 1.52 isaki .round_buffersize = cmpci_round_buffersize,
165 1.52 isaki .mappage = cmpci_mappage,
166 1.52 isaki .get_props = cmpci_get_props,
167 1.52 isaki .trigger_output = cmpci_trigger_output,
168 1.52 isaki .trigger_input = cmpci_trigger_input,
169 1.52 isaki .get_locks = cmpci_get_locks,
170 1.1 augustss };
171 1.1 augustss
172 1.27 kent #define CMPCI_NFORMATS 4
173 1.53.2.1 isaki #define CMPCI_FORMAT(enc, prec, ch, chmask) \
174 1.53.2.1 isaki { \
175 1.53.2.1 isaki .mode = AUMODE_PLAY | AUMODE_RECORD, \
176 1.53.2.1 isaki .encoding = (enc), \
177 1.53.2.1 isaki .validbits = (prec), \
178 1.53.2.1 isaki .precision = (prec), \
179 1.53.2.1 isaki .channels = (ch), \
180 1.53.2.1 isaki .channel_mask = (chmask), \
181 1.53.2.1 isaki .frequency_type = 0, \
182 1.53.2.1 isaki .frequency = { 5512, 48000 }, \
183 1.53.2.1 isaki }
184 1.27 kent static const struct audio_format cmpci_formats[CMPCI_NFORMATS] = {
185 1.53.2.1 isaki CMPCI_FORMAT(AUDIO_ENCODING_SLINEAR_LE, 16, 2, AUFMT_STEREO),
186 1.53.2.1 isaki CMPCI_FORMAT(AUDIO_ENCODING_SLINEAR_LE, 16, 1, AUFMT_MONAURAL),
187 1.53.2.1 isaki CMPCI_FORMAT(AUDIO_ENCODING_ULINEAR_LE, 8, 2, AUFMT_STEREO),
188 1.53.2.1 isaki CMPCI_FORMAT(AUDIO_ENCODING_ULINEAR_LE, 8, 1, AUFMT_MONAURAL),
189 1.27 kent };
190 1.27 kent
191 1.1 augustss
192 1.1 augustss /*
193 1.1 augustss * Low-level HW interface
194 1.1 augustss */
195 1.1 augustss
196 1.1 augustss /* mixer register read/write */
197 1.30 perry static inline uint8_t
198 1.28 kent cmpci_mixerreg_read(struct cmpci_softc *sc, uint8_t no)
199 1.1 augustss {
200 1.1 augustss uint8_t ret;
201 1.1 augustss
202 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no);
203 1.1 augustss delay(10);
204 1.1 augustss ret = bus_space_read_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA);
205 1.1 augustss delay(10);
206 1.1 augustss return ret;
207 1.1 augustss }
208 1.1 augustss
209 1.30 perry static inline void
210 1.28 kent cmpci_mixerreg_write(struct cmpci_softc *sc, uint8_t no, uint8_t val)
211 1.1 augustss {
212 1.28 kent
213 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no);
214 1.1 augustss delay(10);
215 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA, val);
216 1.1 augustss delay(10);
217 1.1 augustss }
218 1.1 augustss
219 1.1 augustss
220 1.1 augustss /* register partial write */
221 1.30 perry static inline void
222 1.28 kent cmpci_reg_partial_write_1(struct cmpci_softc *sc, int no, int shift,
223 1.28 kent unsigned mask, unsigned val)
224 1.10 itohy {
225 1.28 kent
226 1.10 itohy bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
227 1.10 itohy (val<<shift) |
228 1.10 itohy (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));
229 1.10 itohy delay(10);
230 1.10 itohy }
231 1.10 itohy
232 1.30 perry static inline void
233 1.28 kent cmpci_reg_partial_write_4(struct cmpci_softc *sc, int no, int shift,
234 1.28 kent uint32_t mask, uint32_t val)
235 1.1 augustss {
236 1.28 kent
237 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
238 1.1 augustss (val<<shift) |
239 1.1 augustss (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));
240 1.1 augustss delay(10);
241 1.1 augustss }
242 1.1 augustss
243 1.1 augustss /* register set/clear bit */
244 1.30 perry static inline void
245 1.28 kent cmpci_reg_set_1(struct cmpci_softc *sc, int no, uint8_t mask)
246 1.7 tshiozak {
247 1.28 kent
248 1.7 tshiozak bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
249 1.7 tshiozak (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) | mask));
250 1.7 tshiozak delay(10);
251 1.7 tshiozak }
252 1.7 tshiozak
253 1.30 perry static inline void
254 1.28 kent cmpci_reg_clear_1(struct cmpci_softc *sc, int no, uint8_t mask)
255 1.7 tshiozak {
256 1.28 kent
257 1.7 tshiozak bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
258 1.7 tshiozak (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~mask));
259 1.7 tshiozak delay(10);
260 1.7 tshiozak }
261 1.7 tshiozak
262 1.30 perry static inline void
263 1.28 kent cmpci_reg_set_4(struct cmpci_softc *sc, int no, uint32_t mask)
264 1.1 augustss {
265 1.28 kent
266 1.21 itohy /* use cmpci_reg_set_reg_misc() for CMPCI_REG_MISC */
267 1.21 itohy KDASSERT(no != CMPCI_REG_MISC);
268 1.21 itohy
269 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
270 1.7 tshiozak (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) | mask));
271 1.1 augustss delay(10);
272 1.1 augustss }
273 1.1 augustss
274 1.30 perry static inline void
275 1.28 kent cmpci_reg_clear_4(struct cmpci_softc *sc, int no, uint32_t mask)
276 1.1 augustss {
277 1.28 kent
278 1.21 itohy /* use cmpci_reg_clear_reg_misc() for CMPCI_REG_MISC */
279 1.21 itohy KDASSERT(no != CMPCI_REG_MISC);
280 1.21 itohy
281 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
282 1.7 tshiozak (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~mask));
283 1.1 augustss delay(10);
284 1.1 augustss }
285 1.1 augustss
286 1.21 itohy /*
287 1.21 itohy * The CMPCI_REG_MISC register needs special handling, since one of
288 1.21 itohy * its bits has different read/write values.
289 1.21 itohy */
290 1.30 perry static inline void
291 1.28 kent cmpci_reg_set_reg_misc(struct cmpci_softc *sc, uint32_t mask)
292 1.21 itohy {
293 1.28 kent
294 1.21 itohy sc->sc_reg_misc |= mask;
295 1.21 itohy bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MISC,
296 1.21 itohy sc->sc_reg_misc);
297 1.21 itohy delay(10);
298 1.21 itohy }
299 1.21 itohy
300 1.30 perry static inline void
301 1.28 kent cmpci_reg_clear_reg_misc(struct cmpci_softc *sc, uint32_t mask)
302 1.21 itohy {
303 1.28 kent
304 1.21 itohy sc->sc_reg_misc &= ~mask;
305 1.21 itohy bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MISC,
306 1.21 itohy sc->sc_reg_misc);
307 1.21 itohy delay(10);
308 1.21 itohy }
309 1.21 itohy
310 1.1 augustss /* rate */
311 1.6 jdolecek static const struct {
312 1.1 augustss int rate;
313 1.1 augustss int divider;
314 1.1 augustss } cmpci_rate_table[CMPCI_REG_NUMRATE] = {
315 1.1 augustss #define _RATE(n) { n, CMPCI_REG_RATE_ ## n }
316 1.1 augustss _RATE(5512),
317 1.1 augustss _RATE(8000),
318 1.1 augustss _RATE(11025),
319 1.1 augustss _RATE(16000),
320 1.1 augustss _RATE(22050),
321 1.1 augustss _RATE(32000),
322 1.1 augustss _RATE(44100),
323 1.1 augustss _RATE(48000)
324 1.7 tshiozak #undef _RATE
325 1.1 augustss };
326 1.1 augustss
327 1.1 augustss static int
328 1.28 kent cmpci_rate_to_index(int rate)
329 1.1 augustss {
330 1.1 augustss int i;
331 1.1 augustss
332 1.13 augustss for (i = 0; i < CMPCI_REG_NUMRATE - 1; i++)
333 1.1 augustss if (rate <=
334 1.1 augustss (cmpci_rate_table[i].rate+cmpci_rate_table[i+1].rate) / 2)
335 1.1 augustss return i;
336 1.1 augustss return i; /* 48000 */
337 1.1 augustss }
338 1.1 augustss
339 1.30 perry static inline int
340 1.28 kent cmpci_index_to_rate(int index)
341 1.1 augustss {
342 1.28 kent
343 1.1 augustss return cmpci_rate_table[index].rate;
344 1.1 augustss }
345 1.1 augustss
346 1.30 perry static inline int
347 1.28 kent cmpci_index_to_divider(int index)
348 1.1 augustss {
349 1.28 kent
350 1.1 augustss return cmpci_rate_table[index].divider;
351 1.1 augustss }
352 1.1 augustss
353 1.1 augustss /*
354 1.1 augustss * interface to configure the device.
355 1.1 augustss */
356 1.1 augustss static int
357 1.40 cegger cmpci_match(device_t parent, cfdata_t match, void *aux)
358 1.1 augustss {
359 1.28 kent struct pci_attach_args *pa;
360 1.1 augustss
361 1.28 kent pa = (struct pci_attach_args *)aux;
362 1.1 augustss if ( PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMEDIA &&
363 1.1 augustss (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338A ||
364 1.1 augustss PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338B ||
365 1.7 tshiozak PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738 ||
366 1.7 tshiozak PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738B) )
367 1.1 augustss return 1;
368 1.1 augustss
369 1.1 augustss return 0;
370 1.1 augustss }
371 1.1 augustss
372 1.1 augustss static void
373 1.40 cegger cmpci_attach(device_t parent, device_t self, void *aux)
374 1.1 augustss {
375 1.28 kent struct cmpci_softc *sc;
376 1.28 kent struct pci_attach_args *pa;
377 1.8 itohy struct audio_attach_args aa;
378 1.1 augustss pci_intr_handle_t ih;
379 1.1 augustss char const *strintr;
380 1.1 augustss int i, v;
381 1.47 christos char intrbuf[PCI_INTRSTR_LEN];
382 1.1 augustss
383 1.41 cegger sc = device_private(self);
384 1.46 chs sc->sc_dev = self;
385 1.28 kent pa = (struct pci_attach_args *)aux;
386 1.17 thorpej
387 1.7 tshiozak sc->sc_id = pa->pa_id;
388 1.7 tshiozak sc->sc_class = pa->pa_class;
389 1.45 drochner pci_aprint_devinfo(pa, "Audio controller");
390 1.7 tshiozak switch (PCI_PRODUCT(sc->sc_id)) {
391 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338A:
392 1.7 tshiozak /*FALLTHROUGH*/
393 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338B:
394 1.7 tshiozak sc->sc_capable = CMPCI_CAP_CMI8338;
395 1.1 augustss break;
396 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8738:
397 1.7 tshiozak /*FALLTHROUGH*/
398 1.7 tshiozak case PCI_PRODUCT_CMEDIA_CMI8738B:
399 1.7 tshiozak sc->sc_capable = CMPCI_CAP_CMI8738;
400 1.1 augustss break;
401 1.1 augustss }
402 1.1 augustss
403 1.2 augustss /* map I/O space */
404 1.1 augustss if (pci_mapreg_map(pa, CMPCI_PCI_IOBASEREG, PCI_MAPREG_TYPE_IO, 0,
405 1.7 tshiozak &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) {
406 1.46 chs aprint_error_dev(sc->sc_dev, "failed to map I/O space\n");
407 1.1 augustss return;
408 1.1 augustss }
409 1.1 augustss
410 1.43 jmcneill mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
411 1.44 mrg mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO);
412 1.43 jmcneill
413 1.2 augustss /* interrupt */
414 1.5 sommerfe if (pci_intr_map(pa, &ih)) {
415 1.46 chs aprint_error_dev(sc->sc_dev, "failed to map interrupt\n");
416 1.1 augustss return;
417 1.1 augustss }
418 1.47 christos strintr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
419 1.51 jdolecek sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_AUDIO,
420 1.51 jdolecek cmpci_intr, sc, device_xname(self));
421 1.1 augustss if (sc->sc_ih == NULL) {
422 1.46 chs aprint_error_dev(sc->sc_dev, "failed to establish interrupt");
423 1.1 augustss if (strintr != NULL)
424 1.42 njoly aprint_error(" at %s", strintr);
425 1.42 njoly aprint_error("\n");
426 1.43 jmcneill mutex_destroy(&sc->sc_lock);
427 1.43 jmcneill mutex_destroy(&sc->sc_intr_lock);
428 1.1 augustss return;
429 1.1 augustss }
430 1.46 chs aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", strintr);
431 1.1 augustss
432 1.1 augustss sc->sc_dmat = pa->pa_dmat;
433 1.1 augustss
434 1.46 chs audio_attach_mi(&cmpci_hw_if, sc, sc->sc_dev);
435 1.1 augustss
436 1.8 itohy /* attach OPL device */
437 1.8 itohy aa.type = AUDIODEV_TYPE_OPL;
438 1.8 itohy aa.hwif = NULL;
439 1.8 itohy aa.hdl = NULL;
440 1.46 chs (void)config_found(sc->sc_dev, &aa, audioprint);
441 1.8 itohy
442 1.8 itohy /* attach MPU-401 device */
443 1.8 itohy aa.type = AUDIODEV_TYPE_MPU;
444 1.8 itohy aa.hwif = NULL;
445 1.8 itohy aa.hdl = NULL;
446 1.8 itohy if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
447 1.8 itohy CMPCI_REG_MPU_BASE, CMPCI_REG_MPU_SIZE, &sc->sc_mpu_ioh) == 0)
448 1.46 chs sc->sc_mpudev = config_found(sc->sc_dev, &aa, audioprint);
449 1.8 itohy
450 1.21 itohy /* get initial value (this is 0 and may be omitted but just in case) */
451 1.21 itohy sc->sc_reg_misc = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
452 1.21 itohy CMPCI_REG_MISC) & ~CMPCI_REG_SPDIF48K;
453 1.21 itohy
454 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_RESET, 0);
455 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
456 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
457 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX,
458 1.1 augustss CMPCI_SB16_SW_CD|CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
459 1.1 augustss for (i = 0; i < CMPCI_NDEVS; i++) {
460 1.48 msaitoh switch (i) {
461 1.10 itohy /*
462 1.10 itohy * CMI8738 defaults are
463 1.10 itohy * master: 0xe0 (0x00 - 0xf8)
464 1.12 itohy * FM, DAC: 0xc0 (0x00 - 0xf8)
465 1.10 itohy * PC speaker: 0x80 (0x00 - 0xc0)
466 1.10 itohy * others: 0
467 1.10 itohy */
468 1.10 itohy /* volume */
469 1.8 itohy case CMPCI_MASTER_VOL:
470 1.10 itohy v = 128; /* 224 */
471 1.10 itohy break;
472 1.8 itohy case CMPCI_FM_VOL:
473 1.10 itohy case CMPCI_DAC_VOL:
474 1.10 itohy v = 192;
475 1.10 itohy break;
476 1.8 itohy case CMPCI_PCSPEAKER:
477 1.10 itohy v = 128;
478 1.1 augustss break;
479 1.8 itohy
480 1.8 itohy /* booleans, set to true */
481 1.10 itohy case CMPCI_CD_MUTE:
482 1.10 itohy case CMPCI_MIC_MUTE:
483 1.10 itohy case CMPCI_LINE_IN_MUTE:
484 1.10 itohy case CMPCI_AUX_IN_MUTE:
485 1.8 itohy v = 1;
486 1.1 augustss break;
487 1.10 itohy
488 1.10 itohy /* volume with inital value 0 */
489 1.10 itohy case CMPCI_CD_VOL:
490 1.10 itohy case CMPCI_LINE_IN_VOL:
491 1.10 itohy case CMPCI_AUX_IN_VOL:
492 1.10 itohy case CMPCI_MIC_VOL:
493 1.10 itohy case CMPCI_MIC_RECVOL:
494 1.10 itohy /* FALLTHROUGH */
495 1.10 itohy
496 1.8 itohy /* others are cleared */
497 1.10 itohy case CMPCI_MIC_PREAMP:
498 1.8 itohy case CMPCI_RECORD_SOURCE:
499 1.10 itohy case CMPCI_PLAYBACK_MODE:
500 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
501 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
502 1.7 tshiozak case CMPCI_SPDIF_LOOP:
503 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
504 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
505 1.10 itohy case CMPCI_MONITOR_DAC:
506 1.7 tshiozak case CMPCI_REAR:
507 1.7 tshiozak case CMPCI_INDIVIDUAL:
508 1.7 tshiozak case CMPCI_REVERSE:
509 1.7 tshiozak case CMPCI_SURROUND:
510 1.8 itohy default:
511 1.1 augustss v = 0;
512 1.1 augustss break;
513 1.1 augustss }
514 1.7 tshiozak sc->sc_gain[i][CMPCI_LEFT] = sc->sc_gain[i][CMPCI_RIGHT] = v;
515 1.1 augustss cmpci_set_mixer_gain(sc, i);
516 1.1 augustss }
517 1.1 augustss }
518 1.1 augustss
519 1.1 augustss static int
520 1.28 kent cmpci_intr(void *handle)
521 1.1 augustss {
522 1.37 xtraeme struct cmpci_softc *sc = handle;
523 1.37 xtraeme #if NMPU > 0
524 1.37 xtraeme struct mpu_softc *sc_mpu = device_private(sc->sc_mpudev);
525 1.37 xtraeme #endif
526 1.1 augustss uint32_t intrstat;
527 1.1 augustss
528 1.43 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
529 1.43 jmcneill
530 1.1 augustss intrstat = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
531 1.1 augustss CMPCI_REG_INTR_STATUS);
532 1.1 augustss
533 1.43 jmcneill if (!(intrstat & CMPCI_REG_ANY_INTR)) {
534 1.43 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
535 1.1 augustss return 0;
536 1.43 jmcneill }
537 1.1 augustss
538 1.8 itohy delay(10);
539 1.8 itohy
540 1.1 augustss /* disable and reset intr */
541 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR)
542 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL,
543 1.1 augustss CMPCI_REG_CH0_INTR_ENABLE);
544 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR)
545 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL,
546 1.1 augustss CMPCI_REG_CH1_INTR_ENABLE);
547 1.1 augustss
548 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR) {
549 1.1 augustss if (sc->sc_play.intr != NULL)
550 1.1 augustss (*sc->sc_play.intr)(sc->sc_play.intr_arg);
551 1.1 augustss }
552 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR) {
553 1.1 augustss if (sc->sc_rec.intr != NULL)
554 1.1 augustss (*sc->sc_rec.intr)(sc->sc_rec.intr_arg);
555 1.1 augustss }
556 1.1 augustss
557 1.1 augustss /* enable intr */
558 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR)
559 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL,
560 1.1 augustss CMPCI_REG_CH0_INTR_ENABLE);
561 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR)
562 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL,
563 1.1 augustss CMPCI_REG_CH1_INTR_ENABLE);
564 1.8 itohy
565 1.8 itohy #if NMPU > 0
566 1.37 xtraeme if (intrstat & CMPCI_REG_UART_INTR && sc_mpu != NULL)
567 1.37 xtraeme mpu_intr(sc_mpu);
568 1.8 itohy #endif
569 1.8 itohy
570 1.43 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
571 1.8 itohy return 1;
572 1.1 augustss }
573 1.1 augustss
574 1.1 augustss static int
575 1.34 christos cmpci_query_encoding(void *handle, struct audio_encoding *fp)
576 1.1 augustss {
577 1.28 kent
578 1.1 augustss switch (fp->index) {
579 1.1 augustss case 0:
580 1.1 augustss strcpy(fp->name, AudioEulinear);
581 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR;
582 1.1 augustss fp->precision = 8;
583 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
584 1.1 augustss break;
585 1.1 augustss case 1:
586 1.1 augustss strcpy(fp->name, AudioEmulaw);
587 1.1 augustss fp->encoding = AUDIO_ENCODING_ULAW;
588 1.1 augustss fp->precision = 8;
589 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
590 1.1 augustss break;
591 1.1 augustss case 2:
592 1.1 augustss strcpy(fp->name, AudioEalaw);
593 1.1 augustss fp->encoding = AUDIO_ENCODING_ALAW;
594 1.1 augustss fp->precision = 8;
595 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
596 1.1 augustss break;
597 1.1 augustss case 3:
598 1.1 augustss strcpy(fp->name, AudioEslinear);
599 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR;
600 1.1 augustss fp->precision = 8;
601 1.1 augustss fp->flags = 0;
602 1.1 augustss break;
603 1.1 augustss case 4:
604 1.1 augustss strcpy(fp->name, AudioEslinear_le);
605 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR_LE;
606 1.1 augustss fp->precision = 16;
607 1.1 augustss fp->flags = 0;
608 1.1 augustss break;
609 1.1 augustss case 5:
610 1.1 augustss strcpy(fp->name, AudioEulinear_le);
611 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR_LE;
612 1.1 augustss fp->precision = 16;
613 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
614 1.1 augustss break;
615 1.1 augustss case 6:
616 1.1 augustss strcpy(fp->name, AudioEslinear_be);
617 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR_BE;
618 1.1 augustss fp->precision = 16;
619 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
620 1.1 augustss break;
621 1.1 augustss case 7:
622 1.1 augustss strcpy(fp->name, AudioEulinear_be);
623 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR_BE;
624 1.1 augustss fp->precision = 16;
625 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
626 1.1 augustss break;
627 1.1 augustss default:
628 1.1 augustss return EINVAL;
629 1.1 augustss }
630 1.1 augustss return 0;
631 1.1 augustss }
632 1.1 augustss
633 1.1 augustss
634 1.1 augustss static int
635 1.34 christos cmpci_set_params(void *handle, int setmode, int usemode,
636 1.33 christos audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil,
637 1.33 christos stream_filter_list_t *rfil)
638 1.1 augustss {
639 1.1 augustss int i;
640 1.28 kent struct cmpci_softc *sc;
641 1.1 augustss
642 1.28 kent sc = handle;
643 1.1 augustss for (i = 0; i < 2; i++) {
644 1.1 augustss int md_format;
645 1.1 augustss int md_divide;
646 1.1 augustss int md_index;
647 1.1 augustss int mode;
648 1.27 kent audio_params_t *p;
649 1.27 kent stream_filter_list_t *fil;
650 1.27 kent int ind;
651 1.10 itohy
652 1.1 augustss switch (i) {
653 1.1 augustss case 0:
654 1.1 augustss mode = AUMODE_PLAY;
655 1.1 augustss p = play;
656 1.27 kent fil = pfil;
657 1.1 augustss break;
658 1.1 augustss case 1:
659 1.1 augustss mode = AUMODE_RECORD;
660 1.1 augustss p = rec;
661 1.27 kent fil = rfil;
662 1.1 augustss break;
663 1.19 christos default:
664 1.19 christos return EINVAL;
665 1.1 augustss }
666 1.10 itohy
667 1.1 augustss if (!(setmode & mode))
668 1.1 augustss continue;
669 1.1 augustss
670 1.27 kent md_index = cmpci_rate_to_index(p->sample_rate);
671 1.27 kent md_divide = cmpci_index_to_divider(md_index);
672 1.27 kent p->sample_rate = cmpci_index_to_rate(md_index);
673 1.27 kent DPRINTF(("%s: sample:%u, divider=%d\n",
674 1.46 chs device_xname(sc->sc_dev), p->sample_rate, md_divide));
675 1.27 kent
676 1.27 kent ind = auconv_set_converter(cmpci_formats, CMPCI_NFORMATS,
677 1.27 kent mode, p, FALSE, fil);
678 1.27 kent if (ind < 0)
679 1.27 kent return EINVAL;
680 1.27 kent if (fil->req_size > 0)
681 1.27 kent p = &fil->filters[0].param;
682 1.1 augustss
683 1.1 augustss /* format */
684 1.27 kent md_format = p->channels == 1
685 1.27 kent ? CMPCI_REG_FORMAT_MONO : CMPCI_REG_FORMAT_STEREO;
686 1.27 kent md_format |= p->precision == 16
687 1.27 kent ? CMPCI_REG_FORMAT_16BIT : CMPCI_REG_FORMAT_8BIT;
688 1.27 kent if (mode & AUMODE_PLAY) {
689 1.1 augustss cmpci_reg_partial_write_4(sc,
690 1.7 tshiozak CMPCI_REG_CHANNEL_FORMAT,
691 1.7 tshiozak CMPCI_REG_CH0_FORMAT_SHIFT,
692 1.7 tshiozak CMPCI_REG_CH0_FORMAT_MASK, md_format);
693 1.1 augustss cmpci_reg_partial_write_4(sc,
694 1.1 augustss CMPCI_REG_FUNC_1, CMPCI_REG_DAC_FS_SHIFT,
695 1.1 augustss CMPCI_REG_DAC_FS_MASK, md_divide);
696 1.7 tshiozak sc->sc_play.md_divide = md_divide;
697 1.1 augustss } else {
698 1.1 augustss cmpci_reg_partial_write_4(sc,
699 1.27 kent CMPCI_REG_CHANNEL_FORMAT,
700 1.27 kent CMPCI_REG_CH1_FORMAT_SHIFT,
701 1.27 kent CMPCI_REG_CH1_FORMAT_MASK, md_format);
702 1.27 kent cmpci_reg_partial_write_4(sc,
703 1.1 augustss CMPCI_REG_FUNC_1, CMPCI_REG_ADC_FS_SHIFT,
704 1.1 augustss CMPCI_REG_ADC_FS_MASK, md_divide);
705 1.7 tshiozak sc->sc_rec.md_divide = md_divide;
706 1.1 augustss }
707 1.10 itohy cmpci_set_out_ports(sc);
708 1.10 itohy cmpci_set_in_ports(sc);
709 1.1 augustss }
710 1.1 augustss return 0;
711 1.1 augustss }
712 1.1 augustss
713 1.1 augustss /* ARGSUSED */
714 1.1 augustss static int
715 1.34 christos cmpci_round_blocksize(void *handle, int block,
716 1.34 christos int mode, const audio_params_t *param)
717 1.1 augustss {
718 1.28 kent
719 1.28 kent return block & -4;
720 1.1 augustss }
721 1.1 augustss
722 1.1 augustss static int
723 1.28 kent cmpci_halt_output(void *handle)
724 1.1 augustss {
725 1.28 kent struct cmpci_softc *sc;
726 1.1 augustss
727 1.28 kent sc = handle;
728 1.1 augustss sc->sc_play.intr = NULL;
729 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
730 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
731 1.1 augustss /* wait for reset DMA */
732 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
733 1.1 augustss delay(10);
734 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
735 1.10 itohy
736 1.1 augustss return 0;
737 1.1 augustss }
738 1.1 augustss
739 1.1 augustss static int
740 1.28 kent cmpci_halt_input(void *handle)
741 1.1 augustss {
742 1.28 kent struct cmpci_softc *sc;
743 1.10 itohy
744 1.28 kent sc = handle;
745 1.1 augustss sc->sc_rec.intr = NULL;
746 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
747 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
748 1.1 augustss /* wait for reset DMA */
749 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
750 1.1 augustss delay(10);
751 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
752 1.10 itohy
753 1.1 augustss return 0;
754 1.1 augustss }
755 1.1 augustss
756 1.1 augustss /* get audio device information */
757 1.1 augustss static int
758 1.28 kent cmpci_getdev(void *handle, struct audio_device *ad)
759 1.1 augustss {
760 1.28 kent struct cmpci_softc *sc;
761 1.1 augustss
762 1.28 kent sc = handle;
763 1.1 augustss strncpy(ad->name, "CMI PCI Audio", sizeof(ad->name));
764 1.7 tshiozak snprintf(ad->version, sizeof(ad->version), "0x%02x",
765 1.7 tshiozak PCI_REVISION(sc->sc_class));
766 1.7 tshiozak switch (PCI_PRODUCT(sc->sc_id)) {
767 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338A:
768 1.1 augustss strncpy(ad->config, "CMI8338A", sizeof(ad->config));
769 1.1 augustss break;
770 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338B:
771 1.1 augustss strncpy(ad->config, "CMI8338B", sizeof(ad->config));
772 1.1 augustss break;
773 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8738:
774 1.1 augustss strncpy(ad->config, "CMI8738", sizeof(ad->config));
775 1.1 augustss break;
776 1.7 tshiozak case PCI_PRODUCT_CMEDIA_CMI8738B:
777 1.7 tshiozak strncpy(ad->config, "CMI8738B", sizeof(ad->config));
778 1.7 tshiozak break;
779 1.1 augustss default:
780 1.1 augustss strncpy(ad->config, "unknown", sizeof(ad->config));
781 1.1 augustss }
782 1.1 augustss
783 1.1 augustss return 0;
784 1.1 augustss }
785 1.1 augustss
786 1.1 augustss /* mixer device information */
787 1.1 augustss int
788 1.28 kent cmpci_query_devinfo(void *handle, mixer_devinfo_t *dip)
789 1.1 augustss {
790 1.10 itohy static const char *const mixer_port_names[] = {
791 1.10 itohy AudioNdac, AudioNfmsynth, AudioNcd, AudioNline, AudioNaux,
792 1.10 itohy AudioNmicrophone
793 1.10 itohy };
794 1.10 itohy static const char *const mixer_classes[] = {
795 1.10 itohy AudioCinputs, AudioCoutputs, AudioCrecord, CmpciCplayback,
796 1.10 itohy CmpciCspdif
797 1.10 itohy };
798 1.28 kent struct cmpci_softc *sc;
799 1.10 itohy int i;
800 1.10 itohy
801 1.28 kent sc = handle;
802 1.10 itohy dip->prev = dip->next = AUDIO_MIXER_LAST;
803 1.10 itohy
804 1.1 augustss switch (dip->index) {
805 1.10 itohy case CMPCI_INPUT_CLASS:
806 1.10 itohy case CMPCI_OUTPUT_CLASS:
807 1.10 itohy case CMPCI_RECORD_CLASS:
808 1.10 itohy case CMPCI_PLAYBACK_CLASS:
809 1.10 itohy case CMPCI_SPDIF_CLASS:
810 1.10 itohy dip->type = AUDIO_MIXER_CLASS;
811 1.10 itohy dip->mixer_class = dip->index;
812 1.10 itohy strcpy(dip->label.name,
813 1.10 itohy mixer_classes[dip->index - CMPCI_INPUT_CLASS]);
814 1.1 augustss return 0;
815 1.10 itohy
816 1.10 itohy case CMPCI_AUX_IN_VOL:
817 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_REG_AUX_VALBITS);
818 1.10 itohy goto vol1;
819 1.10 itohy case CMPCI_DAC_VOL:
820 1.1 augustss case CMPCI_FM_VOL:
821 1.10 itohy case CMPCI_CD_VOL:
822 1.10 itohy case CMPCI_LINE_IN_VOL:
823 1.10 itohy case CMPCI_MIC_VOL:
824 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS);
825 1.10 itohy vol1: dip->mixer_class = CMPCI_INPUT_CLASS;
826 1.10 itohy dip->next = dip->index + 6; /* CMPCI_xxx_MUTE */
827 1.10 itohy strcpy(dip->label.name, mixer_port_names[dip->index]);
828 1.10 itohy dip->un.v.num_channels = (dip->index == CMPCI_MIC_VOL ? 1 : 2);
829 1.10 itohy vol:
830 1.1 augustss dip->type = AUDIO_MIXER_VALUE;
831 1.1 augustss strcpy(dip->un.v.units.name, AudioNvolume);
832 1.1 augustss return 0;
833 1.10 itohy
834 1.10 itohy case CMPCI_MIC_MUTE:
835 1.10 itohy dip->next = CMPCI_MIC_PREAMP;
836 1.10 itohy /* FALLTHROUGH */
837 1.10 itohy case CMPCI_DAC_MUTE:
838 1.10 itohy case CMPCI_FM_MUTE:
839 1.10 itohy case CMPCI_CD_MUTE:
840 1.10 itohy case CMPCI_LINE_IN_MUTE:
841 1.10 itohy case CMPCI_AUX_IN_MUTE:
842 1.10 itohy dip->prev = dip->index - 6; /* CMPCI_xxx_VOL */
843 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
844 1.10 itohy strcpy(dip->label.name, AudioNmute);
845 1.10 itohy goto on_off;
846 1.10 itohy on_off:
847 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
848 1.10 itohy dip->un.e.num_mem = 2;
849 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNoff);
850 1.10 itohy dip->un.e.member[0].ord = 0;
851 1.10 itohy strcpy(dip->un.e.member[1].label.name, AudioNon);
852 1.10 itohy dip->un.e.member[1].ord = 1;
853 1.1 augustss return 0;
854 1.10 itohy
855 1.10 itohy case CMPCI_MIC_PREAMP:
856 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
857 1.10 itohy dip->prev = CMPCI_MIC_MUTE;
858 1.10 itohy strcpy(dip->label.name, AudioNpreamp);
859 1.10 itohy goto on_off;
860 1.10 itohy case CMPCI_PCSPEAKER:
861 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
862 1.10 itohy strcpy(dip->label.name, AudioNspeaker);
863 1.1 augustss dip->un.v.num_channels = 1;
864 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_SPEAKER_VALBITS);
865 1.10 itohy goto vol;
866 1.1 augustss case CMPCI_RECORD_SOURCE:
867 1.1 augustss dip->mixer_class = CMPCI_RECORD_CLASS;
868 1.1 augustss strcpy(dip->label.name, AudioNsource);
869 1.1 augustss dip->type = AUDIO_MIXER_SET;
870 1.10 itohy dip->un.s.num_mem = 7;
871 1.1 augustss strcpy(dip->un.s.member[0].label.name, AudioNmicrophone);
872 1.8 itohy dip->un.s.member[0].mask = CMPCI_RECORD_SOURCE_MIC;
873 1.1 augustss strcpy(dip->un.s.member[1].label.name, AudioNcd);
874 1.8 itohy dip->un.s.member[1].mask = CMPCI_RECORD_SOURCE_CD;
875 1.1 augustss strcpy(dip->un.s.member[2].label.name, AudioNline);
876 1.8 itohy dip->un.s.member[2].mask = CMPCI_RECORD_SOURCE_LINE_IN;
877 1.10 itohy strcpy(dip->un.s.member[3].label.name, AudioNaux);
878 1.10 itohy dip->un.s.member[3].mask = CMPCI_RECORD_SOURCE_AUX_IN;
879 1.10 itohy strcpy(dip->un.s.member[4].label.name, AudioNwave);
880 1.10 itohy dip->un.s.member[4].mask = CMPCI_RECORD_SOURCE_WAVE;
881 1.10 itohy strcpy(dip->un.s.member[5].label.name, AudioNfmsynth);
882 1.10 itohy dip->un.s.member[5].mask = CMPCI_RECORD_SOURCE_FM;
883 1.10 itohy strcpy(dip->un.s.member[6].label.name, CmpciNspdif);
884 1.10 itohy dip->un.s.member[6].mask = CMPCI_RECORD_SOURCE_SPDIF;
885 1.1 augustss return 0;
886 1.10 itohy case CMPCI_MIC_RECVOL:
887 1.1 augustss dip->mixer_class = CMPCI_RECORD_CLASS;
888 1.10 itohy strcpy(dip->label.name, AudioNmicrophone);
889 1.1 augustss dip->un.v.num_channels = 1;
890 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_REG_ADMIC_VALBITS);
891 1.10 itohy goto vol;
892 1.10 itohy
893 1.10 itohy case CMPCI_PLAYBACK_MODE:
894 1.10 itohy dip->mixer_class = CMPCI_PLAYBACK_CLASS;
895 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
896 1.10 itohy strcpy(dip->label.name, AudioNmode);
897 1.10 itohy dip->un.e.num_mem = 2;
898 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNdac);
899 1.10 itohy dip->un.e.member[0].ord = CMPCI_PLAYBACK_MODE_WAVE;
900 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdif);
901 1.10 itohy dip->un.e.member[1].ord = CMPCI_PLAYBACK_MODE_SPDIF;
902 1.1 augustss return 0;
903 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
904 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
905 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
906 1.10 itohy dip->next = CMPCI_SPDIF_IN_PHASE;
907 1.1 augustss strcpy(dip->label.name, AudioNinput);
908 1.10 itohy i = 0;
909 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdin1);
910 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN1;
911 1.10 itohy if (CMPCI_ISCAP(sc, 2ND_SPDIN)) {
912 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdin2);
913 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN2;
914 1.10 itohy }
915 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdout);
916 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDOUT;
917 1.10 itohy dip->un.e.num_mem = i;
918 1.10 itohy return 0;
919 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
920 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
921 1.10 itohy dip->prev = CMPCI_SPDIF_IN_SELECT;
922 1.10 itohy strcpy(dip->label.name, CmpciNphase);
923 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
924 1.10 itohy dip->un.e.num_mem = 2;
925 1.10 itohy strcpy(dip->un.e.member[0].label.name, CmpciNpositive);
926 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_IN_PHASE_POSITIVE;
927 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNnegative);
928 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_IN_PHASE_NEGATIVE;
929 1.1 augustss return 0;
930 1.10 itohy case CMPCI_SPDIF_LOOP:
931 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
932 1.10 itohy dip->next = CMPCI_SPDIF_OUT_PLAYBACK;
933 1.1 augustss strcpy(dip->label.name, AudioNoutput);
934 1.1 augustss dip->type = AUDIO_MIXER_ENUM;
935 1.10 itohy dip->un.e.num_mem = 2;
936 1.10 itohy strcpy(dip->un.e.member[0].label.name, CmpciNplayback);
937 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_LOOP_OFF;
938 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdin);
939 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_LOOP_ON;
940 1.7 tshiozak return 0;
941 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
942 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
943 1.10 itohy dip->prev = CMPCI_SPDIF_LOOP;
944 1.10 itohy dip->next = CMPCI_SPDIF_OUT_VOLTAGE;
945 1.10 itohy strcpy(dip->label.name, CmpciNplayback);
946 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
947 1.10 itohy dip->un.e.num_mem = 2;
948 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNwave);
949 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_PLAYBACK_WAVE;
950 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNlegacy);
951 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_PLAYBACK_LEGACY;
952 1.7 tshiozak return 0;
953 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
954 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
955 1.10 itohy dip->prev = CMPCI_SPDIF_OUT_PLAYBACK;
956 1.10 itohy strcpy(dip->label.name, CmpciNvoltage);
957 1.7 tshiozak dip->type = AUDIO_MIXER_ENUM;
958 1.7 tshiozak dip->un.e.num_mem = 2;
959 1.21 itohy strcpy(dip->un.e.member[0].label.name, CmpciNhigh_v);
960 1.21 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_VOLTAGE_HIGH;
961 1.21 itohy strcpy(dip->un.e.member[1].label.name, CmpciNlow_v);
962 1.21 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_VOLTAGE_LOW;
963 1.7 tshiozak return 0;
964 1.10 itohy case CMPCI_MONITOR_DAC:
965 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
966 1.10 itohy strcpy(dip->label.name, AudioNmonitor);
967 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
968 1.10 itohy dip->un.e.num_mem = 3;
969 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNoff);
970 1.10 itohy dip->un.e.member[0].ord = CMPCI_MONITOR_DAC_OFF;
971 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdin);
972 1.10 itohy dip->un.e.member[1].ord = CMPCI_MONITOR_DAC_SPDIN;
973 1.10 itohy strcpy(dip->un.e.member[2].label.name, CmpciNspdout);
974 1.10 itohy dip->un.e.member[2].ord = CMPCI_MONITOR_DAC_SPDOUT;
975 1.10 itohy return 0;
976 1.10 itohy
977 1.10 itohy case CMPCI_MASTER_VOL:
978 1.10 itohy dip->mixer_class = CMPCI_OUTPUT_CLASS;
979 1.10 itohy strcpy(dip->label.name, AudioNmaster);
980 1.10 itohy dip->un.v.num_channels = 2;
981 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS);
982 1.10 itohy goto vol;
983 1.7 tshiozak case CMPCI_REAR:
984 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
985 1.7 tshiozak dip->next = CMPCI_INDIVIDUAL;
986 1.7 tshiozak strcpy(dip->label.name, CmpciNrear);
987 1.7 tshiozak goto on_off;
988 1.7 tshiozak case CMPCI_INDIVIDUAL:
989 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
990 1.7 tshiozak dip->prev = CMPCI_REAR;
991 1.7 tshiozak dip->next = CMPCI_REVERSE;
992 1.7 tshiozak strcpy(dip->label.name, CmpciNindividual);
993 1.7 tshiozak goto on_off;
994 1.7 tshiozak case CMPCI_REVERSE:
995 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
996 1.7 tshiozak dip->prev = CMPCI_INDIVIDUAL;
997 1.7 tshiozak strcpy(dip->label.name, CmpciNreverse);
998 1.10 itohy goto on_off;
999 1.7 tshiozak case CMPCI_SURROUND:
1000 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1001 1.7 tshiozak strcpy(dip->label.name, CmpciNsurround);
1002 1.7 tshiozak goto on_off;
1003 1.10 itohy }
1004 1.7 tshiozak
1005 1.1 augustss return ENXIO;
1006 1.1 augustss }
1007 1.1 augustss
1008 1.1 augustss static int
1009 1.43 jmcneill cmpci_alloc_dmamem(struct cmpci_softc *sc, size_t size, void **r_addr)
1010 1.1 augustss {
1011 1.28 kent int error;
1012 1.1 augustss struct cmpci_dmanode *n;
1013 1.1 augustss
1014 1.28 kent error = 0;
1015 1.49 maxv n = kmem_alloc(sizeof(*n), KM_SLEEP);
1016 1.1 augustss
1017 1.1 augustss #define CMPCI_DMABUF_ALIGN 0x4
1018 1.1 augustss #define CMPCI_DMABUF_BOUNDARY 0x0
1019 1.1 augustss n->cd_tag = sc->sc_dmat;
1020 1.1 augustss n->cd_size = size;
1021 1.1 augustss error = bus_dmamem_alloc(n->cd_tag, n->cd_size,
1022 1.1 augustss CMPCI_DMABUF_ALIGN, CMPCI_DMABUF_BOUNDARY, n->cd_segs,
1023 1.43 jmcneill sizeof(n->cd_segs)/sizeof(n->cd_segs[0]), &n->cd_nsegs,
1024 1.43 jmcneill BUS_DMA_WAITOK);
1025 1.1 augustss if (error)
1026 1.1 augustss goto mfree;
1027 1.1 augustss error = bus_dmamem_map(n->cd_tag, n->cd_segs, n->cd_nsegs, n->cd_size,
1028 1.43 jmcneill &n->cd_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
1029 1.1 augustss if (error)
1030 1.1 augustss goto dmafree;
1031 1.1 augustss error = bus_dmamap_create(n->cd_tag, n->cd_size, 1, n->cd_size, 0,
1032 1.43 jmcneill BUS_DMA_WAITOK, &n->cd_map);
1033 1.1 augustss if (error)
1034 1.1 augustss goto unmap;
1035 1.1 augustss error = bus_dmamap_load(n->cd_tag, n->cd_map, n->cd_addr, n->cd_size,
1036 1.43 jmcneill NULL, BUS_DMA_WAITOK);
1037 1.1 augustss if (error)
1038 1.1 augustss goto destroy;
1039 1.10 itohy
1040 1.1 augustss n->cd_next = sc->sc_dmap;
1041 1.1 augustss sc->sc_dmap = n;
1042 1.1 augustss *r_addr = KVADDR(n);
1043 1.1 augustss return 0;
1044 1.10 itohy
1045 1.1 augustss destroy:
1046 1.1 augustss bus_dmamap_destroy(n->cd_tag, n->cd_map);
1047 1.1 augustss unmap:
1048 1.1 augustss bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size);
1049 1.1 augustss dmafree:
1050 1.1 augustss bus_dmamem_free(n->cd_tag,
1051 1.1 augustss n->cd_segs, sizeof(n->cd_segs)/sizeof(n->cd_segs[0]));
1052 1.1 augustss mfree:
1053 1.43 jmcneill kmem_free(n, sizeof(*n));
1054 1.1 augustss return error;
1055 1.1 augustss }
1056 1.1 augustss
1057 1.1 augustss static int
1058 1.43 jmcneill cmpci_free_dmamem(struct cmpci_softc *sc, void *addr, size_t size)
1059 1.1 augustss {
1060 1.1 augustss struct cmpci_dmanode **nnp;
1061 1.10 itohy
1062 1.1 augustss for (nnp = &sc->sc_dmap; *nnp; nnp= &(*nnp)->cd_next) {
1063 1.1 augustss if ((*nnp)->cd_addr == addr) {
1064 1.1 augustss struct cmpci_dmanode *n = *nnp;
1065 1.1 augustss bus_dmamap_unload(n->cd_tag, n->cd_map);
1066 1.1 augustss bus_dmamap_destroy(n->cd_tag, n->cd_map);
1067 1.1 augustss bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size);
1068 1.1 augustss bus_dmamem_free(n->cd_tag, n->cd_segs,
1069 1.1 augustss sizeof(n->cd_segs)/sizeof(n->cd_segs[0]));
1070 1.43 jmcneill kmem_free(n, sizeof(*n));
1071 1.1 augustss return 0;
1072 1.1 augustss }
1073 1.1 augustss }
1074 1.1 augustss return -1;
1075 1.1 augustss }
1076 1.1 augustss
1077 1.1 augustss static struct cmpci_dmanode *
1078 1.35 christos cmpci_find_dmamem(struct cmpci_softc *sc, void *addr)
1079 1.1 augustss {
1080 1.1 augustss struct cmpci_dmanode *p;
1081 1.10 itohy
1082 1.28 kent for (p = sc->sc_dmap; p; p = p->cd_next)
1083 1.28 kent if (KVADDR(p) == (void *)addr)
1084 1.1 augustss break;
1085 1.1 augustss return p;
1086 1.1 augustss }
1087 1.1 augustss
1088 1.1 augustss #if 0
1089 1.1 augustss static void
1090 1.28 kent cmpci_print_dmamem(struct cmpci_dmanode *);
1091 1.1 augustss static void
1092 1.28 kent cmpci_print_dmamem(struct cmpci_dmanode *p)
1093 1.1 augustss {
1094 1.28 kent
1095 1.1 augustss DPRINTF(("DMA at virt:%p, dmaseg:%p, mapseg:%p, size:%p\n",
1096 1.1 augustss (void *)p->cd_addr, (void *)p->cd_segs[0].ds_addr,
1097 1.1 augustss (void *)DMAADDR(p), (void *)p->cd_size));
1098 1.1 augustss }
1099 1.1 augustss #endif /* DEBUG */
1100 1.1 augustss
1101 1.1 augustss static void *
1102 1.43 jmcneill cmpci_allocm(void *handle, int direction, size_t size)
1103 1.1 augustss {
1104 1.35 christos void *addr;
1105 1.10 itohy
1106 1.31 mrg addr = NULL; /* XXX gcc */
1107 1.31 mrg
1108 1.43 jmcneill if (cmpci_alloc_dmamem(handle, size, &addr))
1109 1.1 augustss return NULL;
1110 1.1 augustss return addr;
1111 1.1 augustss }
1112 1.1 augustss
1113 1.1 augustss static void
1114 1.43 jmcneill cmpci_freem(void *handle, void *addr, size_t size)
1115 1.1 augustss {
1116 1.10 itohy
1117 1.43 jmcneill cmpci_free_dmamem(handle, addr, size);
1118 1.1 augustss }
1119 1.1 augustss
1120 1.1 augustss #define MAXVAL 256
1121 1.1 augustss static int
1122 1.28 kent cmpci_adjust(int val, int mask)
1123 1.1 augustss {
1124 1.28 kent
1125 1.1 augustss val += (MAXVAL - mask) >> 1;
1126 1.1 augustss if (val >= MAXVAL)
1127 1.1 augustss val = MAXVAL-1;
1128 1.1 augustss return val & mask;
1129 1.1 augustss }
1130 1.1 augustss
1131 1.1 augustss static void
1132 1.28 kent cmpci_set_mixer_gain(struct cmpci_softc *sc, int port)
1133 1.1 augustss {
1134 1.23 itohy int src;
1135 1.10 itohy int bits, mask;
1136 1.1 augustss
1137 1.1 augustss switch (port) {
1138 1.1 augustss case CMPCI_MIC_VOL:
1139 1.10 itohy cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_MIC,
1140 1.10 itohy CMPCI_ADJUST_MIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1141 1.23 itohy return;
1142 1.1 augustss case CMPCI_MASTER_VOL:
1143 1.1 augustss src = CMPCI_SB16_MIXER_MASTER_L;
1144 1.1 augustss break;
1145 1.1 augustss case CMPCI_LINE_IN_VOL:
1146 1.1 augustss src = CMPCI_SB16_MIXER_LINE_L;
1147 1.1 augustss break;
1148 1.10 itohy case CMPCI_AUX_IN_VOL:
1149 1.10 itohy bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MIXER_AUX,
1150 1.10 itohy CMPCI_ADJUST_AUX_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT],
1151 1.10 itohy sc->sc_gain[port][CMPCI_RIGHT]));
1152 1.10 itohy return;
1153 1.10 itohy case CMPCI_MIC_RECVOL:
1154 1.10 itohy cmpci_reg_partial_write_1(sc, CMPCI_REG_MIXER25,
1155 1.10 itohy CMPCI_REG_ADMIC_SHIFT, CMPCI_REG_ADMIC_MASK,
1156 1.10 itohy CMPCI_ADJUST_ADMIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1157 1.10 itohy return;
1158 1.10 itohy case CMPCI_DAC_VOL:
1159 1.1 augustss src = CMPCI_SB16_MIXER_VOICE_L;
1160 1.1 augustss break;
1161 1.1 augustss case CMPCI_FM_VOL:
1162 1.1 augustss src = CMPCI_SB16_MIXER_FM_L;
1163 1.1 augustss break;
1164 1.1 augustss case CMPCI_CD_VOL:
1165 1.1 augustss src = CMPCI_SB16_MIXER_CDDA_L;
1166 1.1 augustss break;
1167 1.1 augustss case CMPCI_PCSPEAKER:
1168 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_SPEAKER,
1169 1.10 itohy CMPCI_ADJUST_2_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1170 1.10 itohy return;
1171 1.10 itohy case CMPCI_MIC_PREAMP:
1172 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1173 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1174 1.10 itohy CMPCI_REG_MICGAINZ);
1175 1.10 itohy else
1176 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1177 1.10 itohy CMPCI_REG_MICGAINZ);
1178 1.7 tshiozak return;
1179 1.10 itohy
1180 1.10 itohy case CMPCI_DAC_MUTE:
1181 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1182 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1183 1.10 itohy CMPCI_REG_WSMUTE);
1184 1.10 itohy else
1185 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1186 1.10 itohy CMPCI_REG_WSMUTE);
1187 1.10 itohy return;
1188 1.10 itohy case CMPCI_FM_MUTE:
1189 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1190 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1191 1.10 itohy CMPCI_REG_FMMUTE);
1192 1.10 itohy else
1193 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1194 1.10 itohy CMPCI_REG_FMMUTE);
1195 1.10 itohy return;
1196 1.10 itohy case CMPCI_AUX_IN_MUTE:
1197 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1198 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1199 1.10 itohy CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM);
1200 1.10 itohy else
1201 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1202 1.10 itohy CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM);
1203 1.10 itohy return;
1204 1.10 itohy case CMPCI_CD_MUTE:
1205 1.10 itohy mask = CMPCI_SB16_SW_CD;
1206 1.10 itohy goto sbmute;
1207 1.10 itohy case CMPCI_MIC_MUTE:
1208 1.10 itohy mask = CMPCI_SB16_SW_MIC;
1209 1.10 itohy goto sbmute;
1210 1.10 itohy case CMPCI_LINE_IN_MUTE:
1211 1.10 itohy mask = CMPCI_SB16_SW_LINE;
1212 1.10 itohy sbmute:
1213 1.10 itohy bits = cmpci_mixerreg_read(sc, CMPCI_SB16_MIXER_OUTMIX);
1214 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1215 1.10 itohy bits = bits & ~mask;
1216 1.10 itohy else
1217 1.10 itohy bits = bits | mask;
1218 1.10 itohy cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX, bits);
1219 1.8 itohy return;
1220 1.10 itohy
1221 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1222 1.10 itohy case CMPCI_MONITOR_DAC:
1223 1.10 itohy case CMPCI_PLAYBACK_MODE:
1224 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1225 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1226 1.7 tshiozak cmpci_set_out_ports(sc);
1227 1.7 tshiozak return;
1228 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1229 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDOUT_VOLTAGE)) {
1230 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_OUT_VOLTAGE][CMPCI_LR]
1231 1.21 itohy == CMPCI_SPDIF_OUT_VOLTAGE_HIGH)
1232 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_5V);
1233 1.10 itohy else
1234 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_5V);
1235 1.7 tshiozak }
1236 1.7 tshiozak return;
1237 1.7 tshiozak case CMPCI_SURROUND:
1238 1.7 tshiozak if (CMPCI_ISCAP(sc, SURROUND)) {
1239 1.7 tshiozak if (sc->sc_gain[CMPCI_SURROUND][CMPCI_LR])
1240 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1241 1.7 tshiozak CMPCI_REG_SURROUND);
1242 1.7 tshiozak else
1243 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1244 1.7 tshiozak CMPCI_REG_SURROUND);
1245 1.7 tshiozak }
1246 1.7 tshiozak return;
1247 1.7 tshiozak case CMPCI_REAR:
1248 1.7 tshiozak if (CMPCI_ISCAP(sc, REAR)) {
1249 1.7 tshiozak if (sc->sc_gain[CMPCI_REAR][CMPCI_LR])
1250 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_N4SPK3D);
1251 1.7 tshiozak else
1252 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_N4SPK3D);
1253 1.7 tshiozak }
1254 1.7 tshiozak return;
1255 1.7 tshiozak case CMPCI_INDIVIDUAL:
1256 1.7 tshiozak if (CMPCI_ISCAP(sc, INDIVIDUAL_REAR)) {
1257 1.7 tshiozak if (sc->sc_gain[CMPCI_REAR][CMPCI_LR])
1258 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1259 1.7 tshiozak CMPCI_REG_INDIVIDUAL);
1260 1.7 tshiozak else
1261 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1262 1.7 tshiozak CMPCI_REG_INDIVIDUAL);
1263 1.7 tshiozak }
1264 1.7 tshiozak return;
1265 1.7 tshiozak case CMPCI_REVERSE:
1266 1.7 tshiozak if (CMPCI_ISCAP(sc, REVERSE_FR)) {
1267 1.7 tshiozak if (sc->sc_gain[CMPCI_REVERSE][CMPCI_LR])
1268 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1269 1.7 tshiozak CMPCI_REG_REVERSE_FR);
1270 1.7 tshiozak else
1271 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1272 1.7 tshiozak CMPCI_REG_REVERSE_FR);
1273 1.7 tshiozak }
1274 1.7 tshiozak return;
1275 1.7 tshiozak case CMPCI_SPDIF_IN_PHASE:
1276 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDIN_PHASE)) {
1277 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_IN_PHASE][CMPCI_LR]
1278 1.10 itohy == CMPCI_SPDIF_IN_PHASE_POSITIVE)
1279 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_CHANNEL_FORMAT,
1280 1.10 itohy CMPCI_REG_SPDIN_PHASE);
1281 1.10 itohy else
1282 1.8 itohy cmpci_reg_set_1(sc, CMPCI_REG_CHANNEL_FORMAT,
1283 1.8 itohy CMPCI_REG_SPDIN_PHASE);
1284 1.7 tshiozak }
1285 1.1 augustss return;
1286 1.1 augustss default:
1287 1.1 augustss return;
1288 1.1 augustss }
1289 1.10 itohy
1290 1.10 itohy cmpci_mixerreg_write(sc, src,
1291 1.10 itohy CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT]));
1292 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_L_TO_R(src),
1293 1.10 itohy CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_RIGHT]));
1294 1.7 tshiozak }
1295 1.7 tshiozak
1296 1.7 tshiozak static void
1297 1.28 kent cmpci_set_out_ports(struct cmpci_softc *sc)
1298 1.7 tshiozak {
1299 1.28 kent uint8_t v;
1300 1.28 kent int enspdout;
1301 1.10 itohy
1302 1.7 tshiozak if (!CMPCI_ISCAP(sc, SPDLOOP))
1303 1.7 tshiozak return;
1304 1.10 itohy
1305 1.10 itohy /* SPDIF/out select */
1306 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_LOOP][CMPCI_LR] == CMPCI_SPDIF_LOOP_OFF) {
1307 1.10 itohy /* playback */
1308 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
1309 1.10 itohy } else {
1310 1.10 itohy /* monitor SPDIF/in */
1311 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
1312 1.10 itohy }
1313 1.10 itohy
1314 1.10 itohy /* SPDIF in select */
1315 1.10 itohy v = sc->sc_gain[CMPCI_SPDIF_IN_SELECT][CMPCI_LR];
1316 1.10 itohy if (v & CMPCI_SPDIFIN_SPDIFIN2)
1317 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_2ND_SPDIFIN);
1318 1.10 itohy else
1319 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_2ND_SPDIFIN);
1320 1.10 itohy if (v & CMPCI_SPDIFIN_SPDIFOUT)
1321 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_SPDFLOOPI);
1322 1.10 itohy else
1323 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_SPDFLOOPI);
1324 1.10 itohy
1325 1.28 kent enspdout = 0;
1326 1.10 itohy /* playback to ... */
1327 1.10 itohy if (CMPCI_ISCAP(sc, SPDOUT) &&
1328 1.10 itohy sc->sc_gain[CMPCI_PLAYBACK_MODE][CMPCI_LR]
1329 1.10 itohy == CMPCI_PLAYBACK_MODE_SPDIF &&
1330 1.10 itohy (sc->sc_play.md_divide == CMPCI_REG_RATE_44100 ||
1331 1.10 itohy (CMPCI_ISCAP(sc, SPDOUT_48K) &&
1332 1.10 itohy sc->sc_play.md_divide==CMPCI_REG_RATE_48000))) {
1333 1.10 itohy /* playback to SPDIF */
1334 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF0_ENABLE);
1335 1.10 itohy enspdout = 1;
1336 1.10 itohy if (sc->sc_play.md_divide==CMPCI_REG_RATE_48000)
1337 1.21 itohy cmpci_reg_set_reg_misc(sc,
1338 1.21 itohy CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K);
1339 1.10 itohy else
1340 1.21 itohy cmpci_reg_clear_reg_misc(sc,
1341 1.21 itohy CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K);
1342 1.10 itohy } else {
1343 1.10 itohy /* playback to DAC */
1344 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1,
1345 1.10 itohy CMPCI_REG_SPDIF0_ENABLE);
1346 1.10 itohy if (CMPCI_ISCAP(sc, SPDOUT_48K))
1347 1.21 itohy cmpci_reg_clear_reg_misc(sc,
1348 1.21 itohy CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K);
1349 1.10 itohy }
1350 1.10 itohy
1351 1.10 itohy /* legacy to SPDIF/out or not */
1352 1.10 itohy if (CMPCI_ISCAP(sc, SPDLEGACY)) {
1353 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_OUT_PLAYBACK][CMPCI_LR]
1354 1.10 itohy == CMPCI_SPDIF_OUT_PLAYBACK_WAVE)
1355 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL,
1356 1.10 itohy CMPCI_REG_LEGACY_SPDIF_ENABLE);
1357 1.10 itohy else {
1358 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL,
1359 1.10 itohy CMPCI_REG_LEGACY_SPDIF_ENABLE);
1360 1.10 itohy enspdout = 1;
1361 1.10 itohy }
1362 1.10 itohy }
1363 1.10 itohy
1364 1.10 itohy /* enable/disable SPDIF/out */
1365 1.10 itohy if (CMPCI_ISCAP(sc, XSPDOUT) && enspdout)
1366 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL,
1367 1.10 itohy CMPCI_REG_XSPDIF_ENABLE);
1368 1.10 itohy else
1369 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL,
1370 1.10 itohy CMPCI_REG_XSPDIF_ENABLE);
1371 1.10 itohy
1372 1.25 xtraeme /* SPDIF monitor (digital to analog output) */
1373 1.10 itohy if (CMPCI_ISCAP(sc, SPDIN_MONITOR)) {
1374 1.10 itohy v = sc->sc_gain[CMPCI_MONITOR_DAC][CMPCI_LR];
1375 1.10 itohy if (!(v & CMPCI_MONDAC_ENABLE))
1376 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1377 1.10 itohy CMPCI_REG_SPDIN_MONITOR);
1378 1.10 itohy if (v & CMPCI_MONDAC_SPDOUT)
1379 1.7 tshiozak cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1,
1380 1.10 itohy CMPCI_REG_SPDIFOUT_DAC);
1381 1.10 itohy else
1382 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1,
1383 1.10 itohy CMPCI_REG_SPDIFOUT_DAC);
1384 1.10 itohy if (v & CMPCI_MONDAC_ENABLE)
1385 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1386 1.10 itohy CMPCI_REG_SPDIN_MONITOR);
1387 1.7 tshiozak }
1388 1.1 augustss }
1389 1.1 augustss
1390 1.1 augustss static int
1391 1.28 kent cmpci_set_in_ports(struct cmpci_softc *sc)
1392 1.10 itohy {
1393 1.1 augustss int mask;
1394 1.1 augustss int bitsl, bitsr;
1395 1.1 augustss
1396 1.10 itohy mask = sc->sc_in_mask;
1397 1.10 itohy
1398 1.10 itohy /*
1399 1.10 itohy * Note CMPCI_RECORD_SOURCE_CD, CMPCI_RECORD_SOURCE_LINE_IN and
1400 1.10 itohy * CMPCI_RECORD_SOURCE_FM are defined to the corresponding bit
1401 1.10 itohy * of the mixer register.
1402 1.10 itohy */
1403 1.10 itohy bitsr = mask & (CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |
1404 1.10 itohy CMPCI_RECORD_SOURCE_FM);
1405 1.10 itohy
1406 1.1 augustss bitsl = CMPCI_SB16_MIXER_SRC_R_TO_L(bitsr);
1407 1.8 itohy if (mask & CMPCI_RECORD_SOURCE_MIC) {
1408 1.1 augustss bitsl |= CMPCI_SB16_MIXER_MIC_SRC;
1409 1.1 augustss bitsr |= CMPCI_SB16_MIXER_MIC_SRC;
1410 1.1 augustss }
1411 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, bitsl);
1412 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, bitsr);
1413 1.10 itohy
1414 1.10 itohy if (mask & CMPCI_RECORD_SOURCE_AUX_IN)
1415 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1416 1.10 itohy CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN);
1417 1.10 itohy else
1418 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1419 1.10 itohy CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN);
1420 1.10 itohy
1421 1.10 itohy if (mask & CMPCI_RECORD_SOURCE_WAVE)
1422 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1423 1.10 itohy CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR);
1424 1.10 itohy else
1425 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1426 1.10 itohy CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR);
1427 1.10 itohy
1428 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDIN) &&
1429 1.10 itohy (sc->sc_rec.md_divide == CMPCI_REG_RATE_44100 ||
1430 1.10 itohy (CMPCI_ISCAP(sc, SPDOUT_48K) &&
1431 1.10 itohy sc->sc_rec.md_divide == CMPCI_REG_RATE_48000/* XXX? */))) {
1432 1.8 itohy if (mask & CMPCI_RECORD_SOURCE_SPDIF) {
1433 1.7 tshiozak /* enable SPDIF/in */
1434 1.7 tshiozak cmpci_reg_set_4(sc,
1435 1.7 tshiozak CMPCI_REG_FUNC_1,
1436 1.7 tshiozak CMPCI_REG_SPDIF1_ENABLE);
1437 1.7 tshiozak } else {
1438 1.7 tshiozak cmpci_reg_clear_4(sc,
1439 1.7 tshiozak CMPCI_REG_FUNC_1,
1440 1.7 tshiozak CMPCI_REG_SPDIF1_ENABLE);
1441 1.7 tshiozak }
1442 1.7 tshiozak }
1443 1.1 augustss
1444 1.1 augustss return 0;
1445 1.1 augustss }
1446 1.1 augustss
1447 1.1 augustss static int
1448 1.28 kent cmpci_set_port(void *handle, mixer_ctrl_t *cp)
1449 1.1 augustss {
1450 1.28 kent struct cmpci_softc *sc;
1451 1.1 augustss int lgain, rgain;
1452 1.10 itohy
1453 1.28 kent sc = handle;
1454 1.1 augustss switch (cp->dev) {
1455 1.10 itohy case CMPCI_MIC_VOL:
1456 1.1 augustss case CMPCI_PCSPEAKER:
1457 1.10 itohy case CMPCI_MIC_RECVOL:
1458 1.10 itohy if (cp->un.value.num_channels != 1)
1459 1.10 itohy return EINVAL;
1460 1.10 itohy /* FALLTHROUGH */
1461 1.10 itohy case CMPCI_DAC_VOL:
1462 1.1 augustss case CMPCI_FM_VOL:
1463 1.1 augustss case CMPCI_CD_VOL:
1464 1.10 itohy case CMPCI_LINE_IN_VOL:
1465 1.10 itohy case CMPCI_AUX_IN_VOL:
1466 1.1 augustss case CMPCI_MASTER_VOL:
1467 1.1 augustss if (cp->type != AUDIO_MIXER_VALUE)
1468 1.1 augustss return EINVAL;
1469 1.10 itohy switch (cp->un.value.num_channels) {
1470 1.10 itohy case 1:
1471 1.1 augustss lgain = rgain =
1472 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_MONO];
1473 1.1 augustss break;
1474 1.10 itohy case 2:
1475 1.10 itohy lgain = cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT];
1476 1.10 itohy rgain = cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT];
1477 1.1 augustss break;
1478 1.1 augustss default:
1479 1.10 itohy return EINVAL;
1480 1.1 augustss }
1481 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT] = lgain;
1482 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_RIGHT] = rgain;
1483 1.1 augustss
1484 1.1 augustss cmpci_set_mixer_gain(sc, cp->dev);
1485 1.1 augustss break;
1486 1.1 augustss
1487 1.1 augustss case CMPCI_RECORD_SOURCE:
1488 1.1 augustss if (cp->type != AUDIO_MIXER_SET)
1489 1.1 augustss return EINVAL;
1490 1.8 itohy
1491 1.10 itohy if (cp->un.mask & ~(CMPCI_RECORD_SOURCE_MIC |
1492 1.10 itohy CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |
1493 1.10 itohy CMPCI_RECORD_SOURCE_AUX_IN | CMPCI_RECORD_SOURCE_WAVE |
1494 1.10 itohy CMPCI_RECORD_SOURCE_FM | CMPCI_RECORD_SOURCE_SPDIF))
1495 1.10 itohy return EINVAL;
1496 1.10 itohy
1497 1.8 itohy if (cp->un.mask & CMPCI_RECORD_SOURCE_SPDIF)
1498 1.8 itohy cp->un.mask = CMPCI_RECORD_SOURCE_SPDIF;
1499 1.8 itohy
1500 1.10 itohy sc->sc_in_mask = cp->un.mask;
1501 1.10 itohy return cmpci_set_in_ports(sc);
1502 1.1 augustss
1503 1.10 itohy /* boolean */
1504 1.10 itohy case CMPCI_DAC_MUTE:
1505 1.10 itohy case CMPCI_FM_MUTE:
1506 1.10 itohy case CMPCI_CD_MUTE:
1507 1.10 itohy case CMPCI_LINE_IN_MUTE:
1508 1.10 itohy case CMPCI_AUX_IN_MUTE:
1509 1.10 itohy case CMPCI_MIC_MUTE:
1510 1.10 itohy case CMPCI_MIC_PREAMP:
1511 1.10 itohy case CMPCI_PLAYBACK_MODE:
1512 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
1513 1.10 itohy case CMPCI_SPDIF_LOOP:
1514 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1515 1.10 itohy case CMPCI_SPDIF_OUT_VOLTAGE:
1516 1.10 itohy case CMPCI_REAR:
1517 1.10 itohy case CMPCI_INDIVIDUAL:
1518 1.10 itohy case CMPCI_REVERSE:
1519 1.10 itohy case CMPCI_SURROUND:
1520 1.1 augustss if (cp->type != AUDIO_MIXER_ENUM)
1521 1.1 augustss return EINVAL;
1522 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord != 0;
1523 1.10 itohy cmpci_set_mixer_gain(sc, cp->dev);
1524 1.1 augustss break;
1525 1.1 augustss
1526 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1527 1.10 itohy switch (cp->un.ord) {
1528 1.10 itohy case CMPCI_SPDIF_IN_SPDIN1:
1529 1.10 itohy case CMPCI_SPDIF_IN_SPDIN2:
1530 1.10 itohy case CMPCI_SPDIF_IN_SPDOUT:
1531 1.10 itohy break;
1532 1.10 itohy default:
1533 1.1 augustss return EINVAL;
1534 1.1 augustss }
1535 1.10 itohy goto xenum;
1536 1.10 itohy case CMPCI_MONITOR_DAC:
1537 1.10 itohy switch (cp->un.ord) {
1538 1.10 itohy case CMPCI_MONITOR_DAC_OFF:
1539 1.10 itohy case CMPCI_MONITOR_DAC_SPDIN:
1540 1.10 itohy case CMPCI_MONITOR_DAC_SPDOUT:
1541 1.10 itohy break;
1542 1.10 itohy default:
1543 1.10 itohy return EINVAL;
1544 1.1 augustss }
1545 1.10 itohy xenum:
1546 1.10 itohy if (cp->type != AUDIO_MIXER_ENUM)
1547 1.10 itohy return EINVAL;
1548 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord;
1549 1.10 itohy cmpci_set_mixer_gain(sc, cp->dev);
1550 1.7 tshiozak break;
1551 1.10 itohy
1552 1.1 augustss default:
1553 1.1 augustss return EINVAL;
1554 1.1 augustss }
1555 1.10 itohy
1556 1.1 augustss return 0;
1557 1.1 augustss }
1558 1.1 augustss
1559 1.1 augustss static int
1560 1.28 kent cmpci_get_port(void *handle, mixer_ctrl_t *cp)
1561 1.1 augustss {
1562 1.28 kent struct cmpci_softc *sc;
1563 1.10 itohy
1564 1.28 kent sc = handle;
1565 1.1 augustss switch (cp->dev) {
1566 1.1 augustss case CMPCI_MIC_VOL:
1567 1.10 itohy case CMPCI_PCSPEAKER:
1568 1.10 itohy case CMPCI_MIC_RECVOL:
1569 1.1 augustss if (cp->un.value.num_channels != 1)
1570 1.1 augustss return EINVAL;
1571 1.12 itohy /*FALLTHROUGH*/
1572 1.10 itohy case CMPCI_DAC_VOL:
1573 1.1 augustss case CMPCI_FM_VOL:
1574 1.1 augustss case CMPCI_CD_VOL:
1575 1.10 itohy case CMPCI_LINE_IN_VOL:
1576 1.10 itohy case CMPCI_AUX_IN_VOL:
1577 1.1 augustss case CMPCI_MASTER_VOL:
1578 1.1 augustss switch (cp->un.value.num_channels) {
1579 1.1 augustss case 1:
1580 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
1581 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT];
1582 1.1 augustss break;
1583 1.1 augustss case 2:
1584 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
1585 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT];
1586 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
1587 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_RIGHT];
1588 1.1 augustss break;
1589 1.1 augustss default:
1590 1.1 augustss return EINVAL;
1591 1.1 augustss }
1592 1.1 augustss break;
1593 1.10 itohy
1594 1.1 augustss case CMPCI_RECORD_SOURCE:
1595 1.7 tshiozak cp->un.mask = sc->sc_in_mask;
1596 1.1 augustss break;
1597 1.1 augustss
1598 1.10 itohy case CMPCI_DAC_MUTE:
1599 1.10 itohy case CMPCI_FM_MUTE:
1600 1.10 itohy case CMPCI_CD_MUTE:
1601 1.1 augustss case CMPCI_LINE_IN_MUTE:
1602 1.10 itohy case CMPCI_AUX_IN_MUTE:
1603 1.10 itohy case CMPCI_MIC_MUTE:
1604 1.10 itohy case CMPCI_MIC_PREAMP:
1605 1.10 itohy case CMPCI_PLAYBACK_MODE:
1606 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1607 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
1608 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1609 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1610 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1611 1.10 itohy case CMPCI_MONITOR_DAC:
1612 1.7 tshiozak case CMPCI_REAR:
1613 1.7 tshiozak case CMPCI_INDIVIDUAL:
1614 1.7 tshiozak case CMPCI_REVERSE:
1615 1.7 tshiozak case CMPCI_SURROUND:
1616 1.7 tshiozak cp->un.ord = sc->sc_gain[cp->dev][CMPCI_LR];
1617 1.1 augustss break;
1618 1.1 augustss
1619 1.1 augustss default:
1620 1.1 augustss return EINVAL;
1621 1.1 augustss }
1622 1.1 augustss
1623 1.1 augustss return 0;
1624 1.1 augustss }
1625 1.1 augustss
1626 1.1 augustss /* ARGSUSED */
1627 1.1 augustss static size_t
1628 1.34 christos cmpci_round_buffersize(void *handle, int direction,
1629 1.33 christos size_t bufsize)
1630 1.1 augustss {
1631 1.28 kent
1632 1.1 augustss if (bufsize > 0x10000)
1633 1.1 augustss bufsize = 0x10000;
1634 1.10 itohy
1635 1.1 augustss return bufsize;
1636 1.1 augustss }
1637 1.1 augustss
1638 1.4 simonb static paddr_t
1639 1.28 kent cmpci_mappage(void *handle, void *addr, off_t offset, int prot)
1640 1.1 augustss {
1641 1.1 augustss struct cmpci_dmanode *p;
1642 1.10 itohy
1643 1.28 kent if (offset < 0 || NULL == (p = cmpci_find_dmamem(handle, addr)))
1644 1.1 augustss return -1;
1645 1.1 augustss
1646 1.1 augustss return bus_dmamem_mmap(p->cd_tag, p->cd_segs,
1647 1.7 tshiozak sizeof(p->cd_segs)/sizeof(p->cd_segs[0]),
1648 1.7 tshiozak offset, prot, BUS_DMA_WAITOK);
1649 1.1 augustss }
1650 1.1 augustss
1651 1.1 augustss /* ARGSUSED */
1652 1.1 augustss static int
1653 1.34 christos cmpci_get_props(void *handle)
1654 1.1 augustss {
1655 1.28 kent
1656 1.1 augustss return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
1657 1.1 augustss }
1658 1.1 augustss
1659 1.1 augustss static int
1660 1.28 kent cmpci_trigger_output(void *handle, void *start, void *end, int blksize,
1661 1.28 kent void (*intr)(void *), void *arg,
1662 1.28 kent const audio_params_t *param)
1663 1.1 augustss {
1664 1.28 kent struct cmpci_softc *sc;
1665 1.1 augustss struct cmpci_dmanode *p;
1666 1.1 augustss int bps;
1667 1.1 augustss
1668 1.28 kent sc = handle;
1669 1.1 augustss sc->sc_play.intr = intr;
1670 1.1 augustss sc->sc_play.intr_arg = arg;
1671 1.27 kent bps = param->channels * param->precision / 8;
1672 1.1 augustss if (!bps)
1673 1.1 augustss return EINVAL;
1674 1.1 augustss
1675 1.1 augustss /* set DMA frame */
1676 1.1 augustss if (!(p = cmpci_find_dmamem(sc, start)))
1677 1.1 augustss return EINVAL;
1678 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BASE,
1679 1.1 augustss DMAADDR(p));
1680 1.1 augustss delay(10);
1681 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BYTES,
1682 1.35 christos ((char *)end - (char *)start + 1) / bps - 1);
1683 1.1 augustss delay(10);
1684 1.1 augustss
1685 1.1 augustss /* set interrupt count */
1686 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_SAMPLES,
1687 1.1 augustss (blksize + bps - 1) / bps - 1);
1688 1.1 augustss delay(10);
1689 1.1 augustss
1690 1.1 augustss /* start DMA */
1691 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); /* PLAY */
1692 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
1693 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
1694 1.10 itohy
1695 1.1 augustss return 0;
1696 1.1 augustss }
1697 1.1 augustss
1698 1.1 augustss static int
1699 1.28 kent cmpci_trigger_input(void *handle, void *start, void *end, int blksize,
1700 1.28 kent void (*intr)(void *), void *arg,
1701 1.28 kent const audio_params_t *param)
1702 1.1 augustss {
1703 1.28 kent struct cmpci_softc *sc;
1704 1.1 augustss struct cmpci_dmanode *p;
1705 1.1 augustss int bps;
1706 1.1 augustss
1707 1.28 kent sc = handle;
1708 1.1 augustss sc->sc_rec.intr = intr;
1709 1.1 augustss sc->sc_rec.intr_arg = arg;
1710 1.27 kent bps = param->channels * param->precision / 8;
1711 1.1 augustss if (!bps)
1712 1.1 augustss return EINVAL;
1713 1.1 augustss
1714 1.1 augustss /* set DMA frame */
1715 1.1 augustss if (!(p=cmpci_find_dmamem(sc, start)))
1716 1.1 augustss return EINVAL;
1717 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BASE,
1718 1.1 augustss DMAADDR(p));
1719 1.1 augustss delay(10);
1720 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BYTES,
1721 1.35 christos ((char *)end - (char *)start + 1) / bps - 1);
1722 1.1 augustss delay(10);
1723 1.1 augustss
1724 1.1 augustss /* set interrupt count */
1725 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_SAMPLES,
1726 1.7 tshiozak (blksize + bps - 1) / bps - 1);
1727 1.1 augustss delay(10);
1728 1.1 augustss
1729 1.1 augustss /* start DMA */
1730 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); /* REC */
1731 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
1732 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
1733 1.10 itohy
1734 1.1 augustss return 0;
1735 1.1 augustss }
1736 1.1 augustss
1737 1.43 jmcneill static void
1738 1.43 jmcneill cmpci_get_locks(void *addr, kmutex_t **intr, kmutex_t **thread)
1739 1.43 jmcneill {
1740 1.43 jmcneill struct cmpci_softc *sc;
1741 1.43 jmcneill
1742 1.43 jmcneill sc = addr;
1743 1.43 jmcneill *intr = &sc->sc_intr_lock;
1744 1.43 jmcneill *thread = &sc->sc_lock;
1745 1.43 jmcneill }
1746 1.43 jmcneill
1747 1.1 augustss /* end of file */
1748