cmpci.c revision 1.58.8.1 1 1.58.8.1 thorpej /* $NetBSD: cmpci.c,v 1.58.8.1 2021/08/04 21:27:00 thorpej Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.43 jmcneill * Copyright (c) 2000, 2001, 2008 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.22 keihan * by Takuya SHIOZAKI <tshiozak (at) NetBSD.org> .
9 1.1 augustss *
10 1.10 itohy * This code is derived from software contributed to The NetBSD Foundation
11 1.10 itohy * by ITOH Yasufumi.
12 1.10 itohy *
13 1.1 augustss * Redistribution and use in source and binary forms, with or without
14 1.1 augustss * modification, are permitted provided that the following conditions
15 1.1 augustss * are met:
16 1.1 augustss * 1. Redistributions of source code must retain the above copyright
17 1.1 augustss * notice, this list of conditions and the following disclaimer.
18 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
19 1.1 augustss * notice, this list of conditions and the following disclaimer in the
20 1.1 augustss * documentation and/or other materials provided with the distribution.
21 1.1 augustss *
22 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 1.1 augustss * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.1 augustss * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 augustss * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 1.1 augustss * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 1.1 augustss * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 1.1 augustss * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.1 augustss * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.1 augustss * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.1 augustss * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.1 augustss * SUCH DAMAGE.
33 1.1 augustss *
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * C-Media CMI8x38 Audio Chip Support.
38 1.1 augustss *
39 1.1 augustss * TODO:
40 1.10 itohy * - 4ch / 6ch support.
41 1.10 itohy * - Joystick support.
42 1.1 augustss *
43 1.1 augustss */
44 1.11 lukem
45 1.11 lukem #include <sys/cdefs.h>
46 1.58.8.1 thorpej __KERNEL_RCSID(0, "$NetBSD: cmpci.c,v 1.58.8.1 2021/08/04 21:27:00 thorpej Exp $");
47 1.1 augustss
48 1.1 augustss #if defined(AUDIO_DEBUG) || defined(DEBUG)
49 1.7 tshiozak #define DPRINTF(x) if (cmpcidebug) printf x
50 1.7 tshiozak int cmpcidebug = 0;
51 1.1 augustss #else
52 1.1 augustss #define DPRINTF(x)
53 1.1 augustss #endif
54 1.1 augustss
55 1.8 itohy #include "mpu.h"
56 1.8 itohy
57 1.1 augustss #include <sys/param.h>
58 1.1 augustss #include <sys/systm.h>
59 1.1 augustss #include <sys/kernel.h>
60 1.43 jmcneill #include <sys/kmem.h>
61 1.1 augustss #include <sys/device.h>
62 1.1 augustss #include <sys/proc.h>
63 1.1 augustss
64 1.1 augustss #include <dev/pci/pcidevs.h>
65 1.1 augustss #include <dev/pci/pcivar.h>
66 1.1 augustss
67 1.1 augustss #include <sys/audioio.h>
68 1.54 isaki #include <dev/audio/audio_if.h>
69 1.1 augustss #include <dev/midi_if.h>
70 1.1 augustss
71 1.1 augustss #include <dev/pci/cmpcireg.h>
72 1.1 augustss #include <dev/pci/cmpcivar.h>
73 1.1 augustss
74 1.1 augustss #include <dev/ic/mpuvar.h>
75 1.36 ad #include <sys/bus.h>
76 1.36 ad #include <sys/intr.h>
77 1.1 augustss
78 1.1 augustss /*
79 1.1 augustss * Low-level HW interface
80 1.1 augustss */
81 1.30 perry static inline uint8_t cmpci_mixerreg_read(struct cmpci_softc *, uint8_t);
82 1.30 perry static inline void cmpci_mixerreg_write(struct cmpci_softc *,
83 1.28 kent uint8_t, uint8_t);
84 1.30 perry static inline void cmpci_reg_partial_write_1(struct cmpci_softc *, int, int,
85 1.28 kent unsigned, unsigned);
86 1.30 perry static inline void cmpci_reg_partial_write_4(struct cmpci_softc *, int, int,
87 1.28 kent uint32_t, uint32_t);
88 1.30 perry static inline void cmpci_reg_set_1(struct cmpci_softc *, int, uint8_t);
89 1.30 perry static inline void cmpci_reg_clear_1(struct cmpci_softc *, int, uint8_t);
90 1.30 perry static inline void cmpci_reg_set_4(struct cmpci_softc *, int, uint32_t);
91 1.30 perry static inline void cmpci_reg_clear_4(struct cmpci_softc *, int, uint32_t);
92 1.30 perry static inline void cmpci_reg_set_reg_misc(struct cmpci_softc *, uint32_t);
93 1.30 perry static inline void cmpci_reg_clear_reg_misc(struct cmpci_softc *, uint32_t);
94 1.28 kent static int cmpci_rate_to_index(int);
95 1.30 perry static inline int cmpci_index_to_divider(int);
96 1.28 kent
97 1.28 kent static int cmpci_adjust(int, int);
98 1.28 kent static void cmpci_set_mixer_gain(struct cmpci_softc *, int);
99 1.28 kent static void cmpci_set_out_ports(struct cmpci_softc *);
100 1.28 kent static int cmpci_set_in_ports(struct cmpci_softc *);
101 1.1 augustss
102 1.1 augustss
103 1.1 augustss /*
104 1.1 augustss * autoconf interface
105 1.1 augustss */
106 1.40 cegger static int cmpci_match(device_t, cfdata_t, void *);
107 1.40 cegger static void cmpci_attach(device_t, device_t, void *);
108 1.1 augustss
109 1.46 chs CFATTACH_DECL_NEW(cmpci, sizeof (struct cmpci_softc),
110 1.16 thorpej cmpci_match, cmpci_attach, NULL, NULL);
111 1.1 augustss
112 1.1 augustss /* interrupt */
113 1.28 kent static int cmpci_intr(void *);
114 1.1 augustss
115 1.1 augustss
116 1.1 augustss /*
117 1.1 augustss * DMA stuffs
118 1.1 augustss */
119 1.43 jmcneill static int cmpci_alloc_dmamem(struct cmpci_softc *, size_t, void **);
120 1.43 jmcneill static int cmpci_free_dmamem(struct cmpci_softc *, void *, size_t);
121 1.28 kent static struct cmpci_dmanode * cmpci_find_dmamem(struct cmpci_softc *,
122 1.35 christos void *);
123 1.1 augustss
124 1.1 augustss
125 1.1 augustss /*
126 1.1 augustss * interface to machine independent layer
127 1.1 augustss */
128 1.54 isaki static int cmpci_query_format(void *, audio_format_query_t *);
129 1.54 isaki static int cmpci_set_format(void *, int,
130 1.54 isaki const audio_params_t *, const audio_params_t *,
131 1.54 isaki audio_filter_reg_t *, audio_filter_reg_t *);
132 1.28 kent static int cmpci_halt_output(void *);
133 1.28 kent static int cmpci_halt_input(void *);
134 1.28 kent static int cmpci_getdev(void *, struct audio_device *);
135 1.28 kent static int cmpci_set_port(void *, mixer_ctrl_t *);
136 1.28 kent static int cmpci_get_port(void *, mixer_ctrl_t *);
137 1.28 kent static int cmpci_query_devinfo(void *, mixer_devinfo_t *);
138 1.43 jmcneill static void *cmpci_allocm(void *, int, size_t);
139 1.43 jmcneill static void cmpci_freem(void *, void *, size_t);
140 1.28 kent static size_t cmpci_round_buffersize(void *, int, size_t);
141 1.28 kent static int cmpci_get_props(void *);
142 1.28 kent static int cmpci_trigger_output(void *, void *, void *, int,
143 1.28 kent void (*)(void *), void *, const audio_params_t *);
144 1.28 kent static int cmpci_trigger_input(void *, void *, void *, int,
145 1.28 kent void (*)(void *), void *, const audio_params_t *);
146 1.43 jmcneill static void cmpci_get_locks(void *, kmutex_t **, kmutex_t **);
147 1.1 augustss
148 1.26 yamt static const struct audio_hw_if cmpci_hw_if = {
149 1.54 isaki .query_format = cmpci_query_format,
150 1.54 isaki .set_format = cmpci_set_format,
151 1.52 isaki .halt_output = cmpci_halt_output,
152 1.52 isaki .halt_input = cmpci_halt_input,
153 1.53 isaki .getdev = cmpci_getdev,
154 1.52 isaki .set_port = cmpci_set_port,
155 1.52 isaki .get_port = cmpci_get_port,
156 1.52 isaki .query_devinfo = cmpci_query_devinfo,
157 1.53 isaki .allocm = cmpci_allocm,
158 1.52 isaki .freem = cmpci_freem,
159 1.52 isaki .round_buffersize = cmpci_round_buffersize,
160 1.52 isaki .get_props = cmpci_get_props,
161 1.52 isaki .trigger_output = cmpci_trigger_output,
162 1.52 isaki .trigger_input = cmpci_trigger_input,
163 1.52 isaki .get_locks = cmpci_get_locks,
164 1.1 augustss };
165 1.1 augustss
166 1.54 isaki static const struct audio_format cmpci_formats[] = {
167 1.54 isaki {
168 1.54 isaki .mode = AUMODE_PLAY | AUMODE_RECORD,
169 1.54 isaki .encoding = AUDIO_ENCODING_SLINEAR_LE,
170 1.54 isaki .validbits = 16,
171 1.54 isaki .precision = 16,
172 1.54 isaki .channels = 2,
173 1.54 isaki .channel_mask = AUFMT_STEREO,
174 1.54 isaki .frequency_type = 8,
175 1.54 isaki .frequency =
176 1.54 isaki { 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000 },
177 1.54 isaki },
178 1.27 kent };
179 1.54 isaki #define CMPCI_NFORMATS __arraycount(cmpci_formats)
180 1.27 kent
181 1.1 augustss
182 1.1 augustss /*
183 1.1 augustss * Low-level HW interface
184 1.1 augustss */
185 1.1 augustss
186 1.1 augustss /* mixer register read/write */
187 1.30 perry static inline uint8_t
188 1.28 kent cmpci_mixerreg_read(struct cmpci_softc *sc, uint8_t no)
189 1.1 augustss {
190 1.1 augustss uint8_t ret;
191 1.1 augustss
192 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no);
193 1.1 augustss delay(10);
194 1.1 augustss ret = bus_space_read_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA);
195 1.1 augustss delay(10);
196 1.1 augustss return ret;
197 1.1 augustss }
198 1.1 augustss
199 1.30 perry static inline void
200 1.28 kent cmpci_mixerreg_write(struct cmpci_softc *sc, uint8_t no, uint8_t val)
201 1.1 augustss {
202 1.28 kent
203 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no);
204 1.1 augustss delay(10);
205 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA, val);
206 1.1 augustss delay(10);
207 1.1 augustss }
208 1.1 augustss
209 1.1 augustss
210 1.1 augustss /* register partial write */
211 1.30 perry static inline void
212 1.28 kent cmpci_reg_partial_write_1(struct cmpci_softc *sc, int no, int shift,
213 1.28 kent unsigned mask, unsigned val)
214 1.10 itohy {
215 1.28 kent
216 1.10 itohy bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
217 1.10 itohy (val<<shift) |
218 1.10 itohy (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));
219 1.10 itohy delay(10);
220 1.10 itohy }
221 1.10 itohy
222 1.30 perry static inline void
223 1.28 kent cmpci_reg_partial_write_4(struct cmpci_softc *sc, int no, int shift,
224 1.28 kent uint32_t mask, uint32_t val)
225 1.1 augustss {
226 1.28 kent
227 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
228 1.1 augustss (val<<shift) |
229 1.1 augustss (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));
230 1.1 augustss delay(10);
231 1.1 augustss }
232 1.1 augustss
233 1.1 augustss /* register set/clear bit */
234 1.30 perry static inline void
235 1.28 kent cmpci_reg_set_1(struct cmpci_softc *sc, int no, uint8_t mask)
236 1.7 tshiozak {
237 1.28 kent
238 1.7 tshiozak bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
239 1.7 tshiozak (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) | mask));
240 1.7 tshiozak delay(10);
241 1.7 tshiozak }
242 1.7 tshiozak
243 1.30 perry static inline void
244 1.28 kent cmpci_reg_clear_1(struct cmpci_softc *sc, int no, uint8_t mask)
245 1.7 tshiozak {
246 1.28 kent
247 1.7 tshiozak bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
248 1.7 tshiozak (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~mask));
249 1.7 tshiozak delay(10);
250 1.7 tshiozak }
251 1.7 tshiozak
252 1.30 perry static inline void
253 1.28 kent cmpci_reg_set_4(struct cmpci_softc *sc, int no, uint32_t mask)
254 1.1 augustss {
255 1.28 kent
256 1.21 itohy /* use cmpci_reg_set_reg_misc() for CMPCI_REG_MISC */
257 1.21 itohy KDASSERT(no != CMPCI_REG_MISC);
258 1.21 itohy
259 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
260 1.7 tshiozak (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) | mask));
261 1.1 augustss delay(10);
262 1.1 augustss }
263 1.1 augustss
264 1.30 perry static inline void
265 1.28 kent cmpci_reg_clear_4(struct cmpci_softc *sc, int no, uint32_t mask)
266 1.1 augustss {
267 1.28 kent
268 1.21 itohy /* use cmpci_reg_clear_reg_misc() for CMPCI_REG_MISC */
269 1.21 itohy KDASSERT(no != CMPCI_REG_MISC);
270 1.21 itohy
271 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
272 1.7 tshiozak (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~mask));
273 1.1 augustss delay(10);
274 1.1 augustss }
275 1.1 augustss
276 1.21 itohy /*
277 1.21 itohy * The CMPCI_REG_MISC register needs special handling, since one of
278 1.21 itohy * its bits has different read/write values.
279 1.21 itohy */
280 1.30 perry static inline void
281 1.28 kent cmpci_reg_set_reg_misc(struct cmpci_softc *sc, uint32_t mask)
282 1.21 itohy {
283 1.28 kent
284 1.21 itohy sc->sc_reg_misc |= mask;
285 1.21 itohy bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MISC,
286 1.21 itohy sc->sc_reg_misc);
287 1.21 itohy delay(10);
288 1.21 itohy }
289 1.21 itohy
290 1.30 perry static inline void
291 1.28 kent cmpci_reg_clear_reg_misc(struct cmpci_softc *sc, uint32_t mask)
292 1.21 itohy {
293 1.28 kent
294 1.21 itohy sc->sc_reg_misc &= ~mask;
295 1.21 itohy bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MISC,
296 1.21 itohy sc->sc_reg_misc);
297 1.21 itohy delay(10);
298 1.21 itohy }
299 1.21 itohy
300 1.1 augustss /* rate */
301 1.6 jdolecek static const struct {
302 1.1 augustss int rate;
303 1.1 augustss int divider;
304 1.1 augustss } cmpci_rate_table[CMPCI_REG_NUMRATE] = {
305 1.1 augustss #define _RATE(n) { n, CMPCI_REG_RATE_ ## n }
306 1.1 augustss _RATE(5512),
307 1.1 augustss _RATE(8000),
308 1.1 augustss _RATE(11025),
309 1.1 augustss _RATE(16000),
310 1.1 augustss _RATE(22050),
311 1.1 augustss _RATE(32000),
312 1.1 augustss _RATE(44100),
313 1.1 augustss _RATE(48000)
314 1.7 tshiozak #undef _RATE
315 1.1 augustss };
316 1.1 augustss
317 1.1 augustss static int
318 1.28 kent cmpci_rate_to_index(int rate)
319 1.1 augustss {
320 1.1 augustss int i;
321 1.1 augustss
322 1.13 augustss for (i = 0; i < CMPCI_REG_NUMRATE - 1; i++)
323 1.54 isaki if (rate == cmpci_rate_table[i].rate)
324 1.1 augustss return i;
325 1.1 augustss return i; /* 48000 */
326 1.1 augustss }
327 1.1 augustss
328 1.30 perry static inline int
329 1.28 kent cmpci_index_to_divider(int index)
330 1.1 augustss {
331 1.28 kent
332 1.1 augustss return cmpci_rate_table[index].divider;
333 1.1 augustss }
334 1.1 augustss
335 1.1 augustss /*
336 1.1 augustss * interface to configure the device.
337 1.1 augustss */
338 1.1 augustss static int
339 1.40 cegger cmpci_match(device_t parent, cfdata_t match, void *aux)
340 1.1 augustss {
341 1.28 kent struct pci_attach_args *pa;
342 1.1 augustss
343 1.28 kent pa = (struct pci_attach_args *)aux;
344 1.1 augustss if ( PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMEDIA &&
345 1.1 augustss (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338A ||
346 1.1 augustss PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338B ||
347 1.7 tshiozak PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738 ||
348 1.7 tshiozak PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738B) )
349 1.1 augustss return 1;
350 1.1 augustss
351 1.1 augustss return 0;
352 1.1 augustss }
353 1.1 augustss
354 1.1 augustss static void
355 1.40 cegger cmpci_attach(device_t parent, device_t self, void *aux)
356 1.1 augustss {
357 1.28 kent struct cmpci_softc *sc;
358 1.28 kent struct pci_attach_args *pa;
359 1.8 itohy struct audio_attach_args aa;
360 1.1 augustss pci_intr_handle_t ih;
361 1.1 augustss char const *strintr;
362 1.1 augustss int i, v;
363 1.47 christos char intrbuf[PCI_INTRSTR_LEN];
364 1.1 augustss
365 1.41 cegger sc = device_private(self);
366 1.46 chs sc->sc_dev = self;
367 1.28 kent pa = (struct pci_attach_args *)aux;
368 1.17 thorpej
369 1.7 tshiozak sc->sc_id = pa->pa_id;
370 1.7 tshiozak sc->sc_class = pa->pa_class;
371 1.45 drochner pci_aprint_devinfo(pa, "Audio controller");
372 1.7 tshiozak switch (PCI_PRODUCT(sc->sc_id)) {
373 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338A:
374 1.7 tshiozak /*FALLTHROUGH*/
375 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338B:
376 1.7 tshiozak sc->sc_capable = CMPCI_CAP_CMI8338;
377 1.1 augustss break;
378 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8738:
379 1.7 tshiozak /*FALLTHROUGH*/
380 1.7 tshiozak case PCI_PRODUCT_CMEDIA_CMI8738B:
381 1.7 tshiozak sc->sc_capable = CMPCI_CAP_CMI8738;
382 1.1 augustss break;
383 1.1 augustss }
384 1.1 augustss
385 1.2 augustss /* map I/O space */
386 1.1 augustss if (pci_mapreg_map(pa, CMPCI_PCI_IOBASEREG, PCI_MAPREG_TYPE_IO, 0,
387 1.7 tshiozak &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) {
388 1.46 chs aprint_error_dev(sc->sc_dev, "failed to map I/O space\n");
389 1.1 augustss return;
390 1.1 augustss }
391 1.1 augustss
392 1.43 jmcneill mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
393 1.44 mrg mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO);
394 1.43 jmcneill
395 1.2 augustss /* interrupt */
396 1.5 sommerfe if (pci_intr_map(pa, &ih)) {
397 1.46 chs aprint_error_dev(sc->sc_dev, "failed to map interrupt\n");
398 1.1 augustss return;
399 1.1 augustss }
400 1.47 christos strintr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
401 1.51 jdolecek sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_AUDIO,
402 1.51 jdolecek cmpci_intr, sc, device_xname(self));
403 1.1 augustss if (sc->sc_ih == NULL) {
404 1.46 chs aprint_error_dev(sc->sc_dev, "failed to establish interrupt");
405 1.1 augustss if (strintr != NULL)
406 1.42 njoly aprint_error(" at %s", strintr);
407 1.42 njoly aprint_error("\n");
408 1.43 jmcneill mutex_destroy(&sc->sc_lock);
409 1.43 jmcneill mutex_destroy(&sc->sc_intr_lock);
410 1.1 augustss return;
411 1.1 augustss }
412 1.46 chs aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", strintr);
413 1.1 augustss
414 1.1 augustss sc->sc_dmat = pa->pa_dmat;
415 1.1 augustss
416 1.46 chs audio_attach_mi(&cmpci_hw_if, sc, sc->sc_dev);
417 1.1 augustss
418 1.8 itohy /* attach OPL device */
419 1.8 itohy aa.type = AUDIODEV_TYPE_OPL;
420 1.8 itohy aa.hwif = NULL;
421 1.8 itohy aa.hdl = NULL;
422 1.58.8.1 thorpej (void)config_found(sc->sc_dev, &aa, audioprint, CFARGS_NONE);
423 1.8 itohy
424 1.8 itohy /* attach MPU-401 device */
425 1.8 itohy aa.type = AUDIODEV_TYPE_MPU;
426 1.8 itohy aa.hwif = NULL;
427 1.8 itohy aa.hdl = NULL;
428 1.8 itohy if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
429 1.8 itohy CMPCI_REG_MPU_BASE, CMPCI_REG_MPU_SIZE, &sc->sc_mpu_ioh) == 0)
430 1.58 thorpej sc->sc_mpudev = config_found(sc->sc_dev, &aa, audioprint,
431 1.58.8.1 thorpej CFARGS_NONE);
432 1.8 itohy
433 1.21 itohy /* get initial value (this is 0 and may be omitted but just in case) */
434 1.21 itohy sc->sc_reg_misc = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
435 1.21 itohy CMPCI_REG_MISC) & ~CMPCI_REG_SPDIF48K;
436 1.21 itohy
437 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_RESET, 0);
438 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
439 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
440 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX,
441 1.1 augustss CMPCI_SB16_SW_CD|CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
442 1.1 augustss for (i = 0; i < CMPCI_NDEVS; i++) {
443 1.48 msaitoh switch (i) {
444 1.10 itohy /*
445 1.10 itohy * CMI8738 defaults are
446 1.10 itohy * master: 0xe0 (0x00 - 0xf8)
447 1.12 itohy * FM, DAC: 0xc0 (0x00 - 0xf8)
448 1.10 itohy * PC speaker: 0x80 (0x00 - 0xc0)
449 1.10 itohy * others: 0
450 1.10 itohy */
451 1.10 itohy /* volume */
452 1.8 itohy case CMPCI_MASTER_VOL:
453 1.10 itohy v = 128; /* 224 */
454 1.10 itohy break;
455 1.8 itohy case CMPCI_FM_VOL:
456 1.10 itohy case CMPCI_DAC_VOL:
457 1.10 itohy v = 192;
458 1.10 itohy break;
459 1.8 itohy case CMPCI_PCSPEAKER:
460 1.10 itohy v = 128;
461 1.1 augustss break;
462 1.8 itohy
463 1.8 itohy /* booleans, set to true */
464 1.10 itohy case CMPCI_CD_MUTE:
465 1.10 itohy case CMPCI_MIC_MUTE:
466 1.10 itohy case CMPCI_LINE_IN_MUTE:
467 1.10 itohy case CMPCI_AUX_IN_MUTE:
468 1.8 itohy v = 1;
469 1.1 augustss break;
470 1.10 itohy
471 1.10 itohy /* volume with inital value 0 */
472 1.10 itohy case CMPCI_CD_VOL:
473 1.10 itohy case CMPCI_LINE_IN_VOL:
474 1.10 itohy case CMPCI_AUX_IN_VOL:
475 1.10 itohy case CMPCI_MIC_VOL:
476 1.10 itohy case CMPCI_MIC_RECVOL:
477 1.10 itohy /* FALLTHROUGH */
478 1.10 itohy
479 1.8 itohy /* others are cleared */
480 1.10 itohy case CMPCI_MIC_PREAMP:
481 1.8 itohy case CMPCI_RECORD_SOURCE:
482 1.10 itohy case CMPCI_PLAYBACK_MODE:
483 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
484 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
485 1.7 tshiozak case CMPCI_SPDIF_LOOP:
486 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
487 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
488 1.10 itohy case CMPCI_MONITOR_DAC:
489 1.7 tshiozak case CMPCI_REAR:
490 1.7 tshiozak case CMPCI_INDIVIDUAL:
491 1.7 tshiozak case CMPCI_REVERSE:
492 1.7 tshiozak case CMPCI_SURROUND:
493 1.8 itohy default:
494 1.1 augustss v = 0;
495 1.1 augustss break;
496 1.1 augustss }
497 1.7 tshiozak sc->sc_gain[i][CMPCI_LEFT] = sc->sc_gain[i][CMPCI_RIGHT] = v;
498 1.1 augustss cmpci_set_mixer_gain(sc, i);
499 1.1 augustss }
500 1.1 augustss }
501 1.1 augustss
502 1.1 augustss static int
503 1.28 kent cmpci_intr(void *handle)
504 1.1 augustss {
505 1.37 xtraeme struct cmpci_softc *sc = handle;
506 1.37 xtraeme #if NMPU > 0
507 1.37 xtraeme struct mpu_softc *sc_mpu = device_private(sc->sc_mpudev);
508 1.37 xtraeme #endif
509 1.1 augustss uint32_t intrstat;
510 1.1 augustss
511 1.43 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
512 1.43 jmcneill
513 1.1 augustss intrstat = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
514 1.1 augustss CMPCI_REG_INTR_STATUS);
515 1.1 augustss
516 1.43 jmcneill if (!(intrstat & CMPCI_REG_ANY_INTR)) {
517 1.43 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
518 1.1 augustss return 0;
519 1.43 jmcneill }
520 1.1 augustss
521 1.8 itohy delay(10);
522 1.8 itohy
523 1.1 augustss /* disable and reset intr */
524 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR)
525 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL,
526 1.1 augustss CMPCI_REG_CH0_INTR_ENABLE);
527 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR)
528 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL,
529 1.1 augustss CMPCI_REG_CH1_INTR_ENABLE);
530 1.1 augustss
531 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR) {
532 1.1 augustss if (sc->sc_play.intr != NULL)
533 1.1 augustss (*sc->sc_play.intr)(sc->sc_play.intr_arg);
534 1.1 augustss }
535 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR) {
536 1.1 augustss if (sc->sc_rec.intr != NULL)
537 1.1 augustss (*sc->sc_rec.intr)(sc->sc_rec.intr_arg);
538 1.1 augustss }
539 1.1 augustss
540 1.1 augustss /* enable intr */
541 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR)
542 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL,
543 1.1 augustss CMPCI_REG_CH0_INTR_ENABLE);
544 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR)
545 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL,
546 1.1 augustss CMPCI_REG_CH1_INTR_ENABLE);
547 1.8 itohy
548 1.8 itohy #if NMPU > 0
549 1.37 xtraeme if (intrstat & CMPCI_REG_UART_INTR && sc_mpu != NULL)
550 1.37 xtraeme mpu_intr(sc_mpu);
551 1.8 itohy #endif
552 1.8 itohy
553 1.43 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
554 1.8 itohy return 1;
555 1.1 augustss }
556 1.1 augustss
557 1.1 augustss static int
558 1.54 isaki cmpci_query_format(void *handle, audio_format_query_t *afp)
559 1.1 augustss {
560 1.28 kent
561 1.54 isaki return audio_query_format(cmpci_formats, CMPCI_NFORMATS, afp);
562 1.1 augustss }
563 1.1 augustss
564 1.1 augustss static int
565 1.54 isaki cmpci_set_format(void *handle, int setmode,
566 1.54 isaki const audio_params_t *play, const audio_params_t *rec,
567 1.54 isaki audio_filter_reg_t *pfil, audio_filter_reg_t *rfil)
568 1.1 augustss {
569 1.1 augustss int i;
570 1.28 kent struct cmpci_softc *sc;
571 1.1 augustss
572 1.28 kent sc = handle;
573 1.1 augustss for (i = 0; i < 2; i++) {
574 1.1 augustss int md_format;
575 1.1 augustss int md_divide;
576 1.1 augustss int md_index;
577 1.1 augustss int mode;
578 1.54 isaki const audio_params_t *p;
579 1.10 itohy
580 1.1 augustss switch (i) {
581 1.1 augustss case 0:
582 1.1 augustss mode = AUMODE_PLAY;
583 1.1 augustss p = play;
584 1.1 augustss break;
585 1.1 augustss case 1:
586 1.1 augustss mode = AUMODE_RECORD;
587 1.1 augustss p = rec;
588 1.1 augustss break;
589 1.19 christos default:
590 1.19 christos return EINVAL;
591 1.1 augustss }
592 1.10 itohy
593 1.1 augustss if (!(setmode & mode))
594 1.1 augustss continue;
595 1.1 augustss
596 1.27 kent md_index = cmpci_rate_to_index(p->sample_rate);
597 1.27 kent md_divide = cmpci_index_to_divider(md_index);
598 1.27 kent DPRINTF(("%s: sample:%u, divider=%d\n",
599 1.46 chs device_xname(sc->sc_dev), p->sample_rate, md_divide));
600 1.27 kent
601 1.1 augustss /* format */
602 1.27 kent md_format = p->channels == 1
603 1.27 kent ? CMPCI_REG_FORMAT_MONO : CMPCI_REG_FORMAT_STEREO;
604 1.27 kent md_format |= p->precision == 16
605 1.27 kent ? CMPCI_REG_FORMAT_16BIT : CMPCI_REG_FORMAT_8BIT;
606 1.27 kent if (mode & AUMODE_PLAY) {
607 1.1 augustss cmpci_reg_partial_write_4(sc,
608 1.7 tshiozak CMPCI_REG_CHANNEL_FORMAT,
609 1.7 tshiozak CMPCI_REG_CH0_FORMAT_SHIFT,
610 1.7 tshiozak CMPCI_REG_CH0_FORMAT_MASK, md_format);
611 1.1 augustss cmpci_reg_partial_write_4(sc,
612 1.1 augustss CMPCI_REG_FUNC_1, CMPCI_REG_DAC_FS_SHIFT,
613 1.1 augustss CMPCI_REG_DAC_FS_MASK, md_divide);
614 1.7 tshiozak sc->sc_play.md_divide = md_divide;
615 1.1 augustss } else {
616 1.1 augustss cmpci_reg_partial_write_4(sc,
617 1.27 kent CMPCI_REG_CHANNEL_FORMAT,
618 1.27 kent CMPCI_REG_CH1_FORMAT_SHIFT,
619 1.27 kent CMPCI_REG_CH1_FORMAT_MASK, md_format);
620 1.27 kent cmpci_reg_partial_write_4(sc,
621 1.1 augustss CMPCI_REG_FUNC_1, CMPCI_REG_ADC_FS_SHIFT,
622 1.1 augustss CMPCI_REG_ADC_FS_MASK, md_divide);
623 1.7 tshiozak sc->sc_rec.md_divide = md_divide;
624 1.1 augustss }
625 1.10 itohy cmpci_set_out_ports(sc);
626 1.10 itohy cmpci_set_in_ports(sc);
627 1.1 augustss }
628 1.1 augustss return 0;
629 1.1 augustss }
630 1.1 augustss
631 1.1 augustss static int
632 1.28 kent cmpci_halt_output(void *handle)
633 1.1 augustss {
634 1.28 kent struct cmpci_softc *sc;
635 1.1 augustss
636 1.28 kent sc = handle;
637 1.1 augustss sc->sc_play.intr = NULL;
638 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
639 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
640 1.1 augustss /* wait for reset DMA */
641 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
642 1.1 augustss delay(10);
643 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
644 1.10 itohy
645 1.1 augustss return 0;
646 1.1 augustss }
647 1.1 augustss
648 1.1 augustss static int
649 1.28 kent cmpci_halt_input(void *handle)
650 1.1 augustss {
651 1.28 kent struct cmpci_softc *sc;
652 1.10 itohy
653 1.28 kent sc = handle;
654 1.1 augustss sc->sc_rec.intr = NULL;
655 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
656 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
657 1.1 augustss /* wait for reset DMA */
658 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
659 1.1 augustss delay(10);
660 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
661 1.10 itohy
662 1.1 augustss return 0;
663 1.1 augustss }
664 1.1 augustss
665 1.1 augustss /* get audio device information */
666 1.1 augustss static int
667 1.28 kent cmpci_getdev(void *handle, struct audio_device *ad)
668 1.1 augustss {
669 1.28 kent struct cmpci_softc *sc;
670 1.1 augustss
671 1.28 kent sc = handle;
672 1.1 augustss strncpy(ad->name, "CMI PCI Audio", sizeof(ad->name));
673 1.7 tshiozak snprintf(ad->version, sizeof(ad->version), "0x%02x",
674 1.7 tshiozak PCI_REVISION(sc->sc_class));
675 1.7 tshiozak switch (PCI_PRODUCT(sc->sc_id)) {
676 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338A:
677 1.1 augustss strncpy(ad->config, "CMI8338A", sizeof(ad->config));
678 1.1 augustss break;
679 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338B:
680 1.1 augustss strncpy(ad->config, "CMI8338B", sizeof(ad->config));
681 1.1 augustss break;
682 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8738:
683 1.1 augustss strncpy(ad->config, "CMI8738", sizeof(ad->config));
684 1.1 augustss break;
685 1.7 tshiozak case PCI_PRODUCT_CMEDIA_CMI8738B:
686 1.7 tshiozak strncpy(ad->config, "CMI8738B", sizeof(ad->config));
687 1.7 tshiozak break;
688 1.1 augustss default:
689 1.1 augustss strncpy(ad->config, "unknown", sizeof(ad->config));
690 1.1 augustss }
691 1.1 augustss
692 1.1 augustss return 0;
693 1.1 augustss }
694 1.1 augustss
695 1.1 augustss /* mixer device information */
696 1.1 augustss int
697 1.28 kent cmpci_query_devinfo(void *handle, mixer_devinfo_t *dip)
698 1.1 augustss {
699 1.10 itohy static const char *const mixer_port_names[] = {
700 1.10 itohy AudioNdac, AudioNfmsynth, AudioNcd, AudioNline, AudioNaux,
701 1.10 itohy AudioNmicrophone
702 1.10 itohy };
703 1.10 itohy static const char *const mixer_classes[] = {
704 1.10 itohy AudioCinputs, AudioCoutputs, AudioCrecord, CmpciCplayback,
705 1.10 itohy CmpciCspdif
706 1.10 itohy };
707 1.28 kent struct cmpci_softc *sc;
708 1.10 itohy int i;
709 1.10 itohy
710 1.28 kent sc = handle;
711 1.10 itohy dip->prev = dip->next = AUDIO_MIXER_LAST;
712 1.10 itohy
713 1.1 augustss switch (dip->index) {
714 1.10 itohy case CMPCI_INPUT_CLASS:
715 1.10 itohy case CMPCI_OUTPUT_CLASS:
716 1.10 itohy case CMPCI_RECORD_CLASS:
717 1.10 itohy case CMPCI_PLAYBACK_CLASS:
718 1.10 itohy case CMPCI_SPDIF_CLASS:
719 1.10 itohy dip->type = AUDIO_MIXER_CLASS;
720 1.10 itohy dip->mixer_class = dip->index;
721 1.10 itohy strcpy(dip->label.name,
722 1.10 itohy mixer_classes[dip->index - CMPCI_INPUT_CLASS]);
723 1.1 augustss return 0;
724 1.10 itohy
725 1.10 itohy case CMPCI_AUX_IN_VOL:
726 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_REG_AUX_VALBITS);
727 1.10 itohy goto vol1;
728 1.10 itohy case CMPCI_DAC_VOL:
729 1.1 augustss case CMPCI_FM_VOL:
730 1.10 itohy case CMPCI_CD_VOL:
731 1.10 itohy case CMPCI_LINE_IN_VOL:
732 1.10 itohy case CMPCI_MIC_VOL:
733 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS);
734 1.10 itohy vol1: dip->mixer_class = CMPCI_INPUT_CLASS;
735 1.10 itohy dip->next = dip->index + 6; /* CMPCI_xxx_MUTE */
736 1.10 itohy strcpy(dip->label.name, mixer_port_names[dip->index]);
737 1.10 itohy dip->un.v.num_channels = (dip->index == CMPCI_MIC_VOL ? 1 : 2);
738 1.10 itohy vol:
739 1.1 augustss dip->type = AUDIO_MIXER_VALUE;
740 1.1 augustss strcpy(dip->un.v.units.name, AudioNvolume);
741 1.1 augustss return 0;
742 1.10 itohy
743 1.10 itohy case CMPCI_MIC_MUTE:
744 1.10 itohy dip->next = CMPCI_MIC_PREAMP;
745 1.10 itohy /* FALLTHROUGH */
746 1.10 itohy case CMPCI_DAC_MUTE:
747 1.10 itohy case CMPCI_FM_MUTE:
748 1.10 itohy case CMPCI_CD_MUTE:
749 1.10 itohy case CMPCI_LINE_IN_MUTE:
750 1.10 itohy case CMPCI_AUX_IN_MUTE:
751 1.10 itohy dip->prev = dip->index - 6; /* CMPCI_xxx_VOL */
752 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
753 1.10 itohy strcpy(dip->label.name, AudioNmute);
754 1.10 itohy goto on_off;
755 1.10 itohy on_off:
756 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
757 1.10 itohy dip->un.e.num_mem = 2;
758 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNoff);
759 1.10 itohy dip->un.e.member[0].ord = 0;
760 1.10 itohy strcpy(dip->un.e.member[1].label.name, AudioNon);
761 1.10 itohy dip->un.e.member[1].ord = 1;
762 1.1 augustss return 0;
763 1.10 itohy
764 1.10 itohy case CMPCI_MIC_PREAMP:
765 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
766 1.10 itohy dip->prev = CMPCI_MIC_MUTE;
767 1.10 itohy strcpy(dip->label.name, AudioNpreamp);
768 1.10 itohy goto on_off;
769 1.10 itohy case CMPCI_PCSPEAKER:
770 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
771 1.10 itohy strcpy(dip->label.name, AudioNspeaker);
772 1.1 augustss dip->un.v.num_channels = 1;
773 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_SPEAKER_VALBITS);
774 1.10 itohy goto vol;
775 1.1 augustss case CMPCI_RECORD_SOURCE:
776 1.1 augustss dip->mixer_class = CMPCI_RECORD_CLASS;
777 1.1 augustss strcpy(dip->label.name, AudioNsource);
778 1.1 augustss dip->type = AUDIO_MIXER_SET;
779 1.10 itohy dip->un.s.num_mem = 7;
780 1.1 augustss strcpy(dip->un.s.member[0].label.name, AudioNmicrophone);
781 1.8 itohy dip->un.s.member[0].mask = CMPCI_RECORD_SOURCE_MIC;
782 1.1 augustss strcpy(dip->un.s.member[1].label.name, AudioNcd);
783 1.8 itohy dip->un.s.member[1].mask = CMPCI_RECORD_SOURCE_CD;
784 1.1 augustss strcpy(dip->un.s.member[2].label.name, AudioNline);
785 1.8 itohy dip->un.s.member[2].mask = CMPCI_RECORD_SOURCE_LINE_IN;
786 1.10 itohy strcpy(dip->un.s.member[3].label.name, AudioNaux);
787 1.10 itohy dip->un.s.member[3].mask = CMPCI_RECORD_SOURCE_AUX_IN;
788 1.10 itohy strcpy(dip->un.s.member[4].label.name, AudioNwave);
789 1.10 itohy dip->un.s.member[4].mask = CMPCI_RECORD_SOURCE_WAVE;
790 1.10 itohy strcpy(dip->un.s.member[5].label.name, AudioNfmsynth);
791 1.10 itohy dip->un.s.member[5].mask = CMPCI_RECORD_SOURCE_FM;
792 1.10 itohy strcpy(dip->un.s.member[6].label.name, CmpciNspdif);
793 1.10 itohy dip->un.s.member[6].mask = CMPCI_RECORD_SOURCE_SPDIF;
794 1.1 augustss return 0;
795 1.10 itohy case CMPCI_MIC_RECVOL:
796 1.1 augustss dip->mixer_class = CMPCI_RECORD_CLASS;
797 1.10 itohy strcpy(dip->label.name, AudioNmicrophone);
798 1.1 augustss dip->un.v.num_channels = 1;
799 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_REG_ADMIC_VALBITS);
800 1.10 itohy goto vol;
801 1.10 itohy
802 1.10 itohy case CMPCI_PLAYBACK_MODE:
803 1.10 itohy dip->mixer_class = CMPCI_PLAYBACK_CLASS;
804 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
805 1.10 itohy strcpy(dip->label.name, AudioNmode);
806 1.10 itohy dip->un.e.num_mem = 2;
807 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNdac);
808 1.10 itohy dip->un.e.member[0].ord = CMPCI_PLAYBACK_MODE_WAVE;
809 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdif);
810 1.10 itohy dip->un.e.member[1].ord = CMPCI_PLAYBACK_MODE_SPDIF;
811 1.1 augustss return 0;
812 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
813 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
814 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
815 1.10 itohy dip->next = CMPCI_SPDIF_IN_PHASE;
816 1.1 augustss strcpy(dip->label.name, AudioNinput);
817 1.10 itohy i = 0;
818 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdin1);
819 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN1;
820 1.10 itohy if (CMPCI_ISCAP(sc, 2ND_SPDIN)) {
821 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdin2);
822 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN2;
823 1.10 itohy }
824 1.10 itohy strcpy(dip->un.e.member[i].label.name, CmpciNspdout);
825 1.10 itohy dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDOUT;
826 1.10 itohy dip->un.e.num_mem = i;
827 1.10 itohy return 0;
828 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
829 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
830 1.10 itohy dip->prev = CMPCI_SPDIF_IN_SELECT;
831 1.10 itohy strcpy(dip->label.name, CmpciNphase);
832 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
833 1.10 itohy dip->un.e.num_mem = 2;
834 1.10 itohy strcpy(dip->un.e.member[0].label.name, CmpciNpositive);
835 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_IN_PHASE_POSITIVE;
836 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNnegative);
837 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_IN_PHASE_NEGATIVE;
838 1.1 augustss return 0;
839 1.10 itohy case CMPCI_SPDIF_LOOP:
840 1.10 itohy dip->mixer_class = CMPCI_SPDIF_CLASS;
841 1.10 itohy dip->next = CMPCI_SPDIF_OUT_PLAYBACK;
842 1.1 augustss strcpy(dip->label.name, AudioNoutput);
843 1.1 augustss dip->type = AUDIO_MIXER_ENUM;
844 1.10 itohy dip->un.e.num_mem = 2;
845 1.10 itohy strcpy(dip->un.e.member[0].label.name, CmpciNplayback);
846 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_LOOP_OFF;
847 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdin);
848 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_LOOP_ON;
849 1.7 tshiozak return 0;
850 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
851 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
852 1.10 itohy dip->prev = CMPCI_SPDIF_LOOP;
853 1.10 itohy dip->next = CMPCI_SPDIF_OUT_VOLTAGE;
854 1.10 itohy strcpy(dip->label.name, CmpciNplayback);
855 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
856 1.10 itohy dip->un.e.num_mem = 2;
857 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNwave);
858 1.10 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_PLAYBACK_WAVE;
859 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNlegacy);
860 1.10 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_PLAYBACK_LEGACY;
861 1.7 tshiozak return 0;
862 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
863 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
864 1.10 itohy dip->prev = CMPCI_SPDIF_OUT_PLAYBACK;
865 1.10 itohy strcpy(dip->label.name, CmpciNvoltage);
866 1.7 tshiozak dip->type = AUDIO_MIXER_ENUM;
867 1.7 tshiozak dip->un.e.num_mem = 2;
868 1.21 itohy strcpy(dip->un.e.member[0].label.name, CmpciNhigh_v);
869 1.21 itohy dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_VOLTAGE_HIGH;
870 1.21 itohy strcpy(dip->un.e.member[1].label.name, CmpciNlow_v);
871 1.21 itohy dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_VOLTAGE_LOW;
872 1.7 tshiozak return 0;
873 1.10 itohy case CMPCI_MONITOR_DAC:
874 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
875 1.10 itohy strcpy(dip->label.name, AudioNmonitor);
876 1.10 itohy dip->type = AUDIO_MIXER_ENUM;
877 1.10 itohy dip->un.e.num_mem = 3;
878 1.10 itohy strcpy(dip->un.e.member[0].label.name, AudioNoff);
879 1.10 itohy dip->un.e.member[0].ord = CMPCI_MONITOR_DAC_OFF;
880 1.10 itohy strcpy(dip->un.e.member[1].label.name, CmpciNspdin);
881 1.10 itohy dip->un.e.member[1].ord = CMPCI_MONITOR_DAC_SPDIN;
882 1.10 itohy strcpy(dip->un.e.member[2].label.name, CmpciNspdout);
883 1.10 itohy dip->un.e.member[2].ord = CMPCI_MONITOR_DAC_SPDOUT;
884 1.10 itohy return 0;
885 1.10 itohy
886 1.10 itohy case CMPCI_MASTER_VOL:
887 1.10 itohy dip->mixer_class = CMPCI_OUTPUT_CLASS;
888 1.10 itohy strcpy(dip->label.name, AudioNmaster);
889 1.10 itohy dip->un.v.num_channels = 2;
890 1.10 itohy dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS);
891 1.10 itohy goto vol;
892 1.7 tshiozak case CMPCI_REAR:
893 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
894 1.7 tshiozak dip->next = CMPCI_INDIVIDUAL;
895 1.7 tshiozak strcpy(dip->label.name, CmpciNrear);
896 1.7 tshiozak goto on_off;
897 1.7 tshiozak case CMPCI_INDIVIDUAL:
898 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
899 1.7 tshiozak dip->prev = CMPCI_REAR;
900 1.7 tshiozak dip->next = CMPCI_REVERSE;
901 1.7 tshiozak strcpy(dip->label.name, CmpciNindividual);
902 1.7 tshiozak goto on_off;
903 1.7 tshiozak case CMPCI_REVERSE:
904 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
905 1.7 tshiozak dip->prev = CMPCI_INDIVIDUAL;
906 1.7 tshiozak strcpy(dip->label.name, CmpciNreverse);
907 1.10 itohy goto on_off;
908 1.7 tshiozak case CMPCI_SURROUND:
909 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
910 1.7 tshiozak strcpy(dip->label.name, CmpciNsurround);
911 1.7 tshiozak goto on_off;
912 1.10 itohy }
913 1.7 tshiozak
914 1.1 augustss return ENXIO;
915 1.1 augustss }
916 1.1 augustss
917 1.1 augustss static int
918 1.43 jmcneill cmpci_alloc_dmamem(struct cmpci_softc *sc, size_t size, void **r_addr)
919 1.1 augustss {
920 1.28 kent int error;
921 1.1 augustss struct cmpci_dmanode *n;
922 1.1 augustss
923 1.28 kent error = 0;
924 1.49 maxv n = kmem_alloc(sizeof(*n), KM_SLEEP);
925 1.1 augustss
926 1.1 augustss #define CMPCI_DMABUF_ALIGN 0x4
927 1.1 augustss #define CMPCI_DMABUF_BOUNDARY 0x0
928 1.1 augustss n->cd_tag = sc->sc_dmat;
929 1.1 augustss n->cd_size = size;
930 1.1 augustss error = bus_dmamem_alloc(n->cd_tag, n->cd_size,
931 1.1 augustss CMPCI_DMABUF_ALIGN, CMPCI_DMABUF_BOUNDARY, n->cd_segs,
932 1.43 jmcneill sizeof(n->cd_segs)/sizeof(n->cd_segs[0]), &n->cd_nsegs,
933 1.43 jmcneill BUS_DMA_WAITOK);
934 1.1 augustss if (error)
935 1.1 augustss goto mfree;
936 1.1 augustss error = bus_dmamem_map(n->cd_tag, n->cd_segs, n->cd_nsegs, n->cd_size,
937 1.43 jmcneill &n->cd_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
938 1.1 augustss if (error)
939 1.1 augustss goto dmafree;
940 1.1 augustss error = bus_dmamap_create(n->cd_tag, n->cd_size, 1, n->cd_size, 0,
941 1.43 jmcneill BUS_DMA_WAITOK, &n->cd_map);
942 1.1 augustss if (error)
943 1.1 augustss goto unmap;
944 1.1 augustss error = bus_dmamap_load(n->cd_tag, n->cd_map, n->cd_addr, n->cd_size,
945 1.43 jmcneill NULL, BUS_DMA_WAITOK);
946 1.1 augustss if (error)
947 1.1 augustss goto destroy;
948 1.10 itohy
949 1.1 augustss n->cd_next = sc->sc_dmap;
950 1.1 augustss sc->sc_dmap = n;
951 1.1 augustss *r_addr = KVADDR(n);
952 1.1 augustss return 0;
953 1.10 itohy
954 1.1 augustss destroy:
955 1.1 augustss bus_dmamap_destroy(n->cd_tag, n->cd_map);
956 1.1 augustss unmap:
957 1.1 augustss bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size);
958 1.1 augustss dmafree:
959 1.1 augustss bus_dmamem_free(n->cd_tag,
960 1.1 augustss n->cd_segs, sizeof(n->cd_segs)/sizeof(n->cd_segs[0]));
961 1.1 augustss mfree:
962 1.43 jmcneill kmem_free(n, sizeof(*n));
963 1.1 augustss return error;
964 1.1 augustss }
965 1.1 augustss
966 1.1 augustss static int
967 1.43 jmcneill cmpci_free_dmamem(struct cmpci_softc *sc, void *addr, size_t size)
968 1.1 augustss {
969 1.1 augustss struct cmpci_dmanode **nnp;
970 1.10 itohy
971 1.1 augustss for (nnp = &sc->sc_dmap; *nnp; nnp= &(*nnp)->cd_next) {
972 1.1 augustss if ((*nnp)->cd_addr == addr) {
973 1.1 augustss struct cmpci_dmanode *n = *nnp;
974 1.1 augustss bus_dmamap_unload(n->cd_tag, n->cd_map);
975 1.1 augustss bus_dmamap_destroy(n->cd_tag, n->cd_map);
976 1.1 augustss bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size);
977 1.1 augustss bus_dmamem_free(n->cd_tag, n->cd_segs,
978 1.1 augustss sizeof(n->cd_segs)/sizeof(n->cd_segs[0]));
979 1.43 jmcneill kmem_free(n, sizeof(*n));
980 1.1 augustss return 0;
981 1.1 augustss }
982 1.1 augustss }
983 1.1 augustss return -1;
984 1.1 augustss }
985 1.1 augustss
986 1.1 augustss static struct cmpci_dmanode *
987 1.35 christos cmpci_find_dmamem(struct cmpci_softc *sc, void *addr)
988 1.1 augustss {
989 1.1 augustss struct cmpci_dmanode *p;
990 1.10 itohy
991 1.28 kent for (p = sc->sc_dmap; p; p = p->cd_next)
992 1.28 kent if (KVADDR(p) == (void *)addr)
993 1.1 augustss break;
994 1.1 augustss return p;
995 1.1 augustss }
996 1.1 augustss
997 1.1 augustss #if 0
998 1.1 augustss static void
999 1.28 kent cmpci_print_dmamem(struct cmpci_dmanode *);
1000 1.1 augustss static void
1001 1.28 kent cmpci_print_dmamem(struct cmpci_dmanode *p)
1002 1.1 augustss {
1003 1.28 kent
1004 1.1 augustss DPRINTF(("DMA at virt:%p, dmaseg:%p, mapseg:%p, size:%p\n",
1005 1.1 augustss (void *)p->cd_addr, (void *)p->cd_segs[0].ds_addr,
1006 1.1 augustss (void *)DMAADDR(p), (void *)p->cd_size));
1007 1.1 augustss }
1008 1.1 augustss #endif /* DEBUG */
1009 1.1 augustss
1010 1.1 augustss static void *
1011 1.43 jmcneill cmpci_allocm(void *handle, int direction, size_t size)
1012 1.1 augustss {
1013 1.35 christos void *addr;
1014 1.10 itohy
1015 1.31 mrg addr = NULL; /* XXX gcc */
1016 1.31 mrg
1017 1.43 jmcneill if (cmpci_alloc_dmamem(handle, size, &addr))
1018 1.1 augustss return NULL;
1019 1.1 augustss return addr;
1020 1.1 augustss }
1021 1.1 augustss
1022 1.1 augustss static void
1023 1.43 jmcneill cmpci_freem(void *handle, void *addr, size_t size)
1024 1.1 augustss {
1025 1.10 itohy
1026 1.43 jmcneill cmpci_free_dmamem(handle, addr, size);
1027 1.1 augustss }
1028 1.1 augustss
1029 1.1 augustss #define MAXVAL 256
1030 1.1 augustss static int
1031 1.28 kent cmpci_adjust(int val, int mask)
1032 1.1 augustss {
1033 1.28 kent
1034 1.1 augustss val += (MAXVAL - mask) >> 1;
1035 1.1 augustss if (val >= MAXVAL)
1036 1.1 augustss val = MAXVAL-1;
1037 1.1 augustss return val & mask;
1038 1.1 augustss }
1039 1.1 augustss
1040 1.1 augustss static void
1041 1.28 kent cmpci_set_mixer_gain(struct cmpci_softc *sc, int port)
1042 1.1 augustss {
1043 1.23 itohy int src;
1044 1.10 itohy int bits, mask;
1045 1.1 augustss
1046 1.1 augustss switch (port) {
1047 1.1 augustss case CMPCI_MIC_VOL:
1048 1.10 itohy cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_MIC,
1049 1.10 itohy CMPCI_ADJUST_MIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1050 1.23 itohy return;
1051 1.1 augustss case CMPCI_MASTER_VOL:
1052 1.1 augustss src = CMPCI_SB16_MIXER_MASTER_L;
1053 1.1 augustss break;
1054 1.1 augustss case CMPCI_LINE_IN_VOL:
1055 1.1 augustss src = CMPCI_SB16_MIXER_LINE_L;
1056 1.1 augustss break;
1057 1.10 itohy case CMPCI_AUX_IN_VOL:
1058 1.10 itohy bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MIXER_AUX,
1059 1.10 itohy CMPCI_ADJUST_AUX_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT],
1060 1.10 itohy sc->sc_gain[port][CMPCI_RIGHT]));
1061 1.10 itohy return;
1062 1.10 itohy case CMPCI_MIC_RECVOL:
1063 1.10 itohy cmpci_reg_partial_write_1(sc, CMPCI_REG_MIXER25,
1064 1.10 itohy CMPCI_REG_ADMIC_SHIFT, CMPCI_REG_ADMIC_MASK,
1065 1.10 itohy CMPCI_ADJUST_ADMIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1066 1.10 itohy return;
1067 1.10 itohy case CMPCI_DAC_VOL:
1068 1.1 augustss src = CMPCI_SB16_MIXER_VOICE_L;
1069 1.1 augustss break;
1070 1.1 augustss case CMPCI_FM_VOL:
1071 1.1 augustss src = CMPCI_SB16_MIXER_FM_L;
1072 1.1 augustss break;
1073 1.1 augustss case CMPCI_CD_VOL:
1074 1.1 augustss src = CMPCI_SB16_MIXER_CDDA_L;
1075 1.1 augustss break;
1076 1.1 augustss case CMPCI_PCSPEAKER:
1077 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_SPEAKER,
1078 1.10 itohy CMPCI_ADJUST_2_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1079 1.10 itohy return;
1080 1.10 itohy case CMPCI_MIC_PREAMP:
1081 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1082 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1083 1.10 itohy CMPCI_REG_MICGAINZ);
1084 1.10 itohy else
1085 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1086 1.10 itohy CMPCI_REG_MICGAINZ);
1087 1.7 tshiozak return;
1088 1.10 itohy
1089 1.10 itohy case CMPCI_DAC_MUTE:
1090 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1091 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1092 1.10 itohy CMPCI_REG_WSMUTE);
1093 1.10 itohy else
1094 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1095 1.10 itohy CMPCI_REG_WSMUTE);
1096 1.10 itohy return;
1097 1.10 itohy case CMPCI_FM_MUTE:
1098 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1099 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1100 1.10 itohy CMPCI_REG_FMMUTE);
1101 1.10 itohy else
1102 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1103 1.10 itohy CMPCI_REG_FMMUTE);
1104 1.10 itohy return;
1105 1.10 itohy case CMPCI_AUX_IN_MUTE:
1106 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1107 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1108 1.10 itohy CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM);
1109 1.10 itohy else
1110 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1111 1.10 itohy CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM);
1112 1.10 itohy return;
1113 1.10 itohy case CMPCI_CD_MUTE:
1114 1.10 itohy mask = CMPCI_SB16_SW_CD;
1115 1.10 itohy goto sbmute;
1116 1.10 itohy case CMPCI_MIC_MUTE:
1117 1.10 itohy mask = CMPCI_SB16_SW_MIC;
1118 1.10 itohy goto sbmute;
1119 1.10 itohy case CMPCI_LINE_IN_MUTE:
1120 1.10 itohy mask = CMPCI_SB16_SW_LINE;
1121 1.10 itohy sbmute:
1122 1.10 itohy bits = cmpci_mixerreg_read(sc, CMPCI_SB16_MIXER_OUTMIX);
1123 1.10 itohy if (sc->sc_gain[port][CMPCI_LR])
1124 1.10 itohy bits = bits & ~mask;
1125 1.10 itohy else
1126 1.10 itohy bits = bits | mask;
1127 1.10 itohy cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX, bits);
1128 1.8 itohy return;
1129 1.10 itohy
1130 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1131 1.10 itohy case CMPCI_MONITOR_DAC:
1132 1.10 itohy case CMPCI_PLAYBACK_MODE:
1133 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1134 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1135 1.7 tshiozak cmpci_set_out_ports(sc);
1136 1.7 tshiozak return;
1137 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1138 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDOUT_VOLTAGE)) {
1139 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_OUT_VOLTAGE][CMPCI_LR]
1140 1.21 itohy == CMPCI_SPDIF_OUT_VOLTAGE_HIGH)
1141 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_5V);
1142 1.10 itohy else
1143 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_5V);
1144 1.7 tshiozak }
1145 1.7 tshiozak return;
1146 1.7 tshiozak case CMPCI_SURROUND:
1147 1.7 tshiozak if (CMPCI_ISCAP(sc, SURROUND)) {
1148 1.7 tshiozak if (sc->sc_gain[CMPCI_SURROUND][CMPCI_LR])
1149 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1150 1.7 tshiozak CMPCI_REG_SURROUND);
1151 1.7 tshiozak else
1152 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1153 1.7 tshiozak CMPCI_REG_SURROUND);
1154 1.7 tshiozak }
1155 1.7 tshiozak return;
1156 1.7 tshiozak case CMPCI_REAR:
1157 1.7 tshiozak if (CMPCI_ISCAP(sc, REAR)) {
1158 1.7 tshiozak if (sc->sc_gain[CMPCI_REAR][CMPCI_LR])
1159 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_N4SPK3D);
1160 1.7 tshiozak else
1161 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_N4SPK3D);
1162 1.7 tshiozak }
1163 1.7 tshiozak return;
1164 1.7 tshiozak case CMPCI_INDIVIDUAL:
1165 1.7 tshiozak if (CMPCI_ISCAP(sc, INDIVIDUAL_REAR)) {
1166 1.7 tshiozak if (sc->sc_gain[CMPCI_REAR][CMPCI_LR])
1167 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1168 1.7 tshiozak CMPCI_REG_INDIVIDUAL);
1169 1.7 tshiozak else
1170 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1171 1.7 tshiozak CMPCI_REG_INDIVIDUAL);
1172 1.7 tshiozak }
1173 1.7 tshiozak return;
1174 1.7 tshiozak case CMPCI_REVERSE:
1175 1.7 tshiozak if (CMPCI_ISCAP(sc, REVERSE_FR)) {
1176 1.7 tshiozak if (sc->sc_gain[CMPCI_REVERSE][CMPCI_LR])
1177 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1178 1.7 tshiozak CMPCI_REG_REVERSE_FR);
1179 1.7 tshiozak else
1180 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1181 1.7 tshiozak CMPCI_REG_REVERSE_FR);
1182 1.7 tshiozak }
1183 1.7 tshiozak return;
1184 1.7 tshiozak case CMPCI_SPDIF_IN_PHASE:
1185 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDIN_PHASE)) {
1186 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_IN_PHASE][CMPCI_LR]
1187 1.10 itohy == CMPCI_SPDIF_IN_PHASE_POSITIVE)
1188 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_CHANNEL_FORMAT,
1189 1.10 itohy CMPCI_REG_SPDIN_PHASE);
1190 1.10 itohy else
1191 1.8 itohy cmpci_reg_set_1(sc, CMPCI_REG_CHANNEL_FORMAT,
1192 1.8 itohy CMPCI_REG_SPDIN_PHASE);
1193 1.7 tshiozak }
1194 1.1 augustss return;
1195 1.1 augustss default:
1196 1.1 augustss return;
1197 1.1 augustss }
1198 1.10 itohy
1199 1.10 itohy cmpci_mixerreg_write(sc, src,
1200 1.10 itohy CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT]));
1201 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_L_TO_R(src),
1202 1.10 itohy CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_RIGHT]));
1203 1.7 tshiozak }
1204 1.7 tshiozak
1205 1.7 tshiozak static void
1206 1.28 kent cmpci_set_out_ports(struct cmpci_softc *sc)
1207 1.7 tshiozak {
1208 1.28 kent uint8_t v;
1209 1.28 kent int enspdout;
1210 1.10 itohy
1211 1.7 tshiozak if (!CMPCI_ISCAP(sc, SPDLOOP))
1212 1.7 tshiozak return;
1213 1.10 itohy
1214 1.10 itohy /* SPDIF/out select */
1215 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_LOOP][CMPCI_LR] == CMPCI_SPDIF_LOOP_OFF) {
1216 1.10 itohy /* playback */
1217 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
1218 1.10 itohy } else {
1219 1.10 itohy /* monitor SPDIF/in */
1220 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
1221 1.10 itohy }
1222 1.10 itohy
1223 1.10 itohy /* SPDIF in select */
1224 1.10 itohy v = sc->sc_gain[CMPCI_SPDIF_IN_SELECT][CMPCI_LR];
1225 1.10 itohy if (v & CMPCI_SPDIFIN_SPDIFIN2)
1226 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_2ND_SPDIFIN);
1227 1.10 itohy else
1228 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_2ND_SPDIFIN);
1229 1.10 itohy if (v & CMPCI_SPDIFIN_SPDIFOUT)
1230 1.21 itohy cmpci_reg_set_reg_misc(sc, CMPCI_REG_SPDFLOOPI);
1231 1.10 itohy else
1232 1.21 itohy cmpci_reg_clear_reg_misc(sc, CMPCI_REG_SPDFLOOPI);
1233 1.10 itohy
1234 1.28 kent enspdout = 0;
1235 1.10 itohy /* playback to ... */
1236 1.10 itohy if (CMPCI_ISCAP(sc, SPDOUT) &&
1237 1.10 itohy sc->sc_gain[CMPCI_PLAYBACK_MODE][CMPCI_LR]
1238 1.10 itohy == CMPCI_PLAYBACK_MODE_SPDIF &&
1239 1.10 itohy (sc->sc_play.md_divide == CMPCI_REG_RATE_44100 ||
1240 1.10 itohy (CMPCI_ISCAP(sc, SPDOUT_48K) &&
1241 1.10 itohy sc->sc_play.md_divide==CMPCI_REG_RATE_48000))) {
1242 1.10 itohy /* playback to SPDIF */
1243 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF0_ENABLE);
1244 1.10 itohy enspdout = 1;
1245 1.10 itohy if (sc->sc_play.md_divide==CMPCI_REG_RATE_48000)
1246 1.21 itohy cmpci_reg_set_reg_misc(sc,
1247 1.21 itohy CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K);
1248 1.10 itohy else
1249 1.21 itohy cmpci_reg_clear_reg_misc(sc,
1250 1.21 itohy CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K);
1251 1.10 itohy } else {
1252 1.10 itohy /* playback to DAC */
1253 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1,
1254 1.10 itohy CMPCI_REG_SPDIF0_ENABLE);
1255 1.10 itohy if (CMPCI_ISCAP(sc, SPDOUT_48K))
1256 1.21 itohy cmpci_reg_clear_reg_misc(sc,
1257 1.21 itohy CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K);
1258 1.10 itohy }
1259 1.10 itohy
1260 1.10 itohy /* legacy to SPDIF/out or not */
1261 1.10 itohy if (CMPCI_ISCAP(sc, SPDLEGACY)) {
1262 1.10 itohy if (sc->sc_gain[CMPCI_SPDIF_OUT_PLAYBACK][CMPCI_LR]
1263 1.10 itohy == CMPCI_SPDIF_OUT_PLAYBACK_WAVE)
1264 1.10 itohy cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL,
1265 1.10 itohy CMPCI_REG_LEGACY_SPDIF_ENABLE);
1266 1.10 itohy else {
1267 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL,
1268 1.10 itohy CMPCI_REG_LEGACY_SPDIF_ENABLE);
1269 1.10 itohy enspdout = 1;
1270 1.10 itohy }
1271 1.10 itohy }
1272 1.10 itohy
1273 1.10 itohy /* enable/disable SPDIF/out */
1274 1.10 itohy if (CMPCI_ISCAP(sc, XSPDOUT) && enspdout)
1275 1.10 itohy cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL,
1276 1.10 itohy CMPCI_REG_XSPDIF_ENABLE);
1277 1.10 itohy else
1278 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL,
1279 1.10 itohy CMPCI_REG_XSPDIF_ENABLE);
1280 1.10 itohy
1281 1.25 xtraeme /* SPDIF monitor (digital to analog output) */
1282 1.10 itohy if (CMPCI_ISCAP(sc, SPDIN_MONITOR)) {
1283 1.10 itohy v = sc->sc_gain[CMPCI_MONITOR_DAC][CMPCI_LR];
1284 1.10 itohy if (!(v & CMPCI_MONDAC_ENABLE))
1285 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1286 1.10 itohy CMPCI_REG_SPDIN_MONITOR);
1287 1.10 itohy if (v & CMPCI_MONDAC_SPDOUT)
1288 1.7 tshiozak cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1,
1289 1.10 itohy CMPCI_REG_SPDIFOUT_DAC);
1290 1.10 itohy else
1291 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1,
1292 1.10 itohy CMPCI_REG_SPDIFOUT_DAC);
1293 1.10 itohy if (v & CMPCI_MONDAC_ENABLE)
1294 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1295 1.10 itohy CMPCI_REG_SPDIN_MONITOR);
1296 1.7 tshiozak }
1297 1.1 augustss }
1298 1.1 augustss
1299 1.1 augustss static int
1300 1.28 kent cmpci_set_in_ports(struct cmpci_softc *sc)
1301 1.10 itohy {
1302 1.1 augustss int mask;
1303 1.1 augustss int bitsl, bitsr;
1304 1.1 augustss
1305 1.10 itohy mask = sc->sc_in_mask;
1306 1.10 itohy
1307 1.10 itohy /*
1308 1.10 itohy * Note CMPCI_RECORD_SOURCE_CD, CMPCI_RECORD_SOURCE_LINE_IN and
1309 1.10 itohy * CMPCI_RECORD_SOURCE_FM are defined to the corresponding bit
1310 1.10 itohy * of the mixer register.
1311 1.10 itohy */
1312 1.10 itohy bitsr = mask & (CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |
1313 1.10 itohy CMPCI_RECORD_SOURCE_FM);
1314 1.10 itohy
1315 1.1 augustss bitsl = CMPCI_SB16_MIXER_SRC_R_TO_L(bitsr);
1316 1.8 itohy if (mask & CMPCI_RECORD_SOURCE_MIC) {
1317 1.1 augustss bitsl |= CMPCI_SB16_MIXER_MIC_SRC;
1318 1.1 augustss bitsr |= CMPCI_SB16_MIXER_MIC_SRC;
1319 1.1 augustss }
1320 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, bitsl);
1321 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, bitsr);
1322 1.10 itohy
1323 1.10 itohy if (mask & CMPCI_RECORD_SOURCE_AUX_IN)
1324 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1325 1.10 itohy CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN);
1326 1.10 itohy else
1327 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1328 1.10 itohy CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN);
1329 1.10 itohy
1330 1.10 itohy if (mask & CMPCI_RECORD_SOURCE_WAVE)
1331 1.10 itohy cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1332 1.10 itohy CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR);
1333 1.10 itohy else
1334 1.10 itohy cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1335 1.10 itohy CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR);
1336 1.10 itohy
1337 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDIN) &&
1338 1.10 itohy (sc->sc_rec.md_divide == CMPCI_REG_RATE_44100 ||
1339 1.10 itohy (CMPCI_ISCAP(sc, SPDOUT_48K) &&
1340 1.10 itohy sc->sc_rec.md_divide == CMPCI_REG_RATE_48000/* XXX? */))) {
1341 1.8 itohy if (mask & CMPCI_RECORD_SOURCE_SPDIF) {
1342 1.7 tshiozak /* enable SPDIF/in */
1343 1.7 tshiozak cmpci_reg_set_4(sc,
1344 1.7 tshiozak CMPCI_REG_FUNC_1,
1345 1.7 tshiozak CMPCI_REG_SPDIF1_ENABLE);
1346 1.7 tshiozak } else {
1347 1.7 tshiozak cmpci_reg_clear_4(sc,
1348 1.7 tshiozak CMPCI_REG_FUNC_1,
1349 1.7 tshiozak CMPCI_REG_SPDIF1_ENABLE);
1350 1.7 tshiozak }
1351 1.7 tshiozak }
1352 1.1 augustss
1353 1.1 augustss return 0;
1354 1.1 augustss }
1355 1.1 augustss
1356 1.1 augustss static int
1357 1.28 kent cmpci_set_port(void *handle, mixer_ctrl_t *cp)
1358 1.1 augustss {
1359 1.28 kent struct cmpci_softc *sc;
1360 1.1 augustss int lgain, rgain;
1361 1.10 itohy
1362 1.28 kent sc = handle;
1363 1.1 augustss switch (cp->dev) {
1364 1.10 itohy case CMPCI_MIC_VOL:
1365 1.1 augustss case CMPCI_PCSPEAKER:
1366 1.10 itohy case CMPCI_MIC_RECVOL:
1367 1.10 itohy if (cp->un.value.num_channels != 1)
1368 1.10 itohy return EINVAL;
1369 1.10 itohy /* FALLTHROUGH */
1370 1.10 itohy case CMPCI_DAC_VOL:
1371 1.1 augustss case CMPCI_FM_VOL:
1372 1.1 augustss case CMPCI_CD_VOL:
1373 1.10 itohy case CMPCI_LINE_IN_VOL:
1374 1.10 itohy case CMPCI_AUX_IN_VOL:
1375 1.1 augustss case CMPCI_MASTER_VOL:
1376 1.1 augustss if (cp->type != AUDIO_MIXER_VALUE)
1377 1.1 augustss return EINVAL;
1378 1.10 itohy switch (cp->un.value.num_channels) {
1379 1.10 itohy case 1:
1380 1.1 augustss lgain = rgain =
1381 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_MONO];
1382 1.1 augustss break;
1383 1.10 itohy case 2:
1384 1.10 itohy lgain = cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT];
1385 1.10 itohy rgain = cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT];
1386 1.1 augustss break;
1387 1.1 augustss default:
1388 1.10 itohy return EINVAL;
1389 1.1 augustss }
1390 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT] = lgain;
1391 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_RIGHT] = rgain;
1392 1.1 augustss
1393 1.1 augustss cmpci_set_mixer_gain(sc, cp->dev);
1394 1.1 augustss break;
1395 1.1 augustss
1396 1.1 augustss case CMPCI_RECORD_SOURCE:
1397 1.1 augustss if (cp->type != AUDIO_MIXER_SET)
1398 1.1 augustss return EINVAL;
1399 1.8 itohy
1400 1.10 itohy if (cp->un.mask & ~(CMPCI_RECORD_SOURCE_MIC |
1401 1.10 itohy CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |
1402 1.10 itohy CMPCI_RECORD_SOURCE_AUX_IN | CMPCI_RECORD_SOURCE_WAVE |
1403 1.10 itohy CMPCI_RECORD_SOURCE_FM | CMPCI_RECORD_SOURCE_SPDIF))
1404 1.10 itohy return EINVAL;
1405 1.10 itohy
1406 1.8 itohy if (cp->un.mask & CMPCI_RECORD_SOURCE_SPDIF)
1407 1.8 itohy cp->un.mask = CMPCI_RECORD_SOURCE_SPDIF;
1408 1.8 itohy
1409 1.10 itohy sc->sc_in_mask = cp->un.mask;
1410 1.10 itohy return cmpci_set_in_ports(sc);
1411 1.1 augustss
1412 1.10 itohy /* boolean */
1413 1.10 itohy case CMPCI_DAC_MUTE:
1414 1.10 itohy case CMPCI_FM_MUTE:
1415 1.10 itohy case CMPCI_CD_MUTE:
1416 1.10 itohy case CMPCI_LINE_IN_MUTE:
1417 1.10 itohy case CMPCI_AUX_IN_MUTE:
1418 1.10 itohy case CMPCI_MIC_MUTE:
1419 1.10 itohy case CMPCI_MIC_PREAMP:
1420 1.10 itohy case CMPCI_PLAYBACK_MODE:
1421 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
1422 1.10 itohy case CMPCI_SPDIF_LOOP:
1423 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1424 1.10 itohy case CMPCI_SPDIF_OUT_VOLTAGE:
1425 1.10 itohy case CMPCI_REAR:
1426 1.10 itohy case CMPCI_INDIVIDUAL:
1427 1.10 itohy case CMPCI_REVERSE:
1428 1.10 itohy case CMPCI_SURROUND:
1429 1.1 augustss if (cp->type != AUDIO_MIXER_ENUM)
1430 1.1 augustss return EINVAL;
1431 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord != 0;
1432 1.10 itohy cmpci_set_mixer_gain(sc, cp->dev);
1433 1.1 augustss break;
1434 1.1 augustss
1435 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1436 1.10 itohy switch (cp->un.ord) {
1437 1.10 itohy case CMPCI_SPDIF_IN_SPDIN1:
1438 1.10 itohy case CMPCI_SPDIF_IN_SPDIN2:
1439 1.10 itohy case CMPCI_SPDIF_IN_SPDOUT:
1440 1.10 itohy break;
1441 1.10 itohy default:
1442 1.1 augustss return EINVAL;
1443 1.1 augustss }
1444 1.10 itohy goto xenum;
1445 1.10 itohy case CMPCI_MONITOR_DAC:
1446 1.10 itohy switch (cp->un.ord) {
1447 1.10 itohy case CMPCI_MONITOR_DAC_OFF:
1448 1.10 itohy case CMPCI_MONITOR_DAC_SPDIN:
1449 1.10 itohy case CMPCI_MONITOR_DAC_SPDOUT:
1450 1.10 itohy break;
1451 1.10 itohy default:
1452 1.10 itohy return EINVAL;
1453 1.1 augustss }
1454 1.10 itohy xenum:
1455 1.10 itohy if (cp->type != AUDIO_MIXER_ENUM)
1456 1.10 itohy return EINVAL;
1457 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord;
1458 1.10 itohy cmpci_set_mixer_gain(sc, cp->dev);
1459 1.7 tshiozak break;
1460 1.10 itohy
1461 1.1 augustss default:
1462 1.1 augustss return EINVAL;
1463 1.1 augustss }
1464 1.10 itohy
1465 1.1 augustss return 0;
1466 1.1 augustss }
1467 1.1 augustss
1468 1.1 augustss static int
1469 1.28 kent cmpci_get_port(void *handle, mixer_ctrl_t *cp)
1470 1.1 augustss {
1471 1.28 kent struct cmpci_softc *sc;
1472 1.10 itohy
1473 1.28 kent sc = handle;
1474 1.1 augustss switch (cp->dev) {
1475 1.1 augustss case CMPCI_MIC_VOL:
1476 1.10 itohy case CMPCI_PCSPEAKER:
1477 1.10 itohy case CMPCI_MIC_RECVOL:
1478 1.1 augustss if (cp->un.value.num_channels != 1)
1479 1.1 augustss return EINVAL;
1480 1.12 itohy /*FALLTHROUGH*/
1481 1.10 itohy case CMPCI_DAC_VOL:
1482 1.1 augustss case CMPCI_FM_VOL:
1483 1.1 augustss case CMPCI_CD_VOL:
1484 1.10 itohy case CMPCI_LINE_IN_VOL:
1485 1.10 itohy case CMPCI_AUX_IN_VOL:
1486 1.1 augustss case CMPCI_MASTER_VOL:
1487 1.1 augustss switch (cp->un.value.num_channels) {
1488 1.1 augustss case 1:
1489 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
1490 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT];
1491 1.1 augustss break;
1492 1.1 augustss case 2:
1493 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
1494 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT];
1495 1.10 itohy cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
1496 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_RIGHT];
1497 1.1 augustss break;
1498 1.1 augustss default:
1499 1.1 augustss return EINVAL;
1500 1.1 augustss }
1501 1.1 augustss break;
1502 1.10 itohy
1503 1.1 augustss case CMPCI_RECORD_SOURCE:
1504 1.7 tshiozak cp->un.mask = sc->sc_in_mask;
1505 1.1 augustss break;
1506 1.1 augustss
1507 1.10 itohy case CMPCI_DAC_MUTE:
1508 1.10 itohy case CMPCI_FM_MUTE:
1509 1.10 itohy case CMPCI_CD_MUTE:
1510 1.1 augustss case CMPCI_LINE_IN_MUTE:
1511 1.10 itohy case CMPCI_AUX_IN_MUTE:
1512 1.10 itohy case CMPCI_MIC_MUTE:
1513 1.10 itohy case CMPCI_MIC_PREAMP:
1514 1.10 itohy case CMPCI_PLAYBACK_MODE:
1515 1.10 itohy case CMPCI_SPDIF_IN_SELECT:
1516 1.10 itohy case CMPCI_SPDIF_IN_PHASE:
1517 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1518 1.10 itohy case CMPCI_SPDIF_OUT_PLAYBACK:
1519 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1520 1.10 itohy case CMPCI_MONITOR_DAC:
1521 1.7 tshiozak case CMPCI_REAR:
1522 1.7 tshiozak case CMPCI_INDIVIDUAL:
1523 1.7 tshiozak case CMPCI_REVERSE:
1524 1.7 tshiozak case CMPCI_SURROUND:
1525 1.7 tshiozak cp->un.ord = sc->sc_gain[cp->dev][CMPCI_LR];
1526 1.1 augustss break;
1527 1.1 augustss
1528 1.1 augustss default:
1529 1.1 augustss return EINVAL;
1530 1.1 augustss }
1531 1.1 augustss
1532 1.1 augustss return 0;
1533 1.1 augustss }
1534 1.1 augustss
1535 1.1 augustss /* ARGSUSED */
1536 1.1 augustss static size_t
1537 1.34 christos cmpci_round_buffersize(void *handle, int direction,
1538 1.33 christos size_t bufsize)
1539 1.1 augustss {
1540 1.28 kent
1541 1.1 augustss if (bufsize > 0x10000)
1542 1.1 augustss bufsize = 0x10000;
1543 1.10 itohy
1544 1.1 augustss return bufsize;
1545 1.1 augustss }
1546 1.1 augustss
1547 1.1 augustss /* ARGSUSED */
1548 1.1 augustss static int
1549 1.34 christos cmpci_get_props(void *handle)
1550 1.1 augustss {
1551 1.28 kent
1552 1.56 isaki return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE |
1553 1.56 isaki AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
1554 1.1 augustss }
1555 1.1 augustss
1556 1.1 augustss static int
1557 1.28 kent cmpci_trigger_output(void *handle, void *start, void *end, int blksize,
1558 1.28 kent void (*intr)(void *), void *arg,
1559 1.28 kent const audio_params_t *param)
1560 1.1 augustss {
1561 1.28 kent struct cmpci_softc *sc;
1562 1.1 augustss struct cmpci_dmanode *p;
1563 1.1 augustss int bps;
1564 1.1 augustss
1565 1.28 kent sc = handle;
1566 1.1 augustss sc->sc_play.intr = intr;
1567 1.1 augustss sc->sc_play.intr_arg = arg;
1568 1.27 kent bps = param->channels * param->precision / 8;
1569 1.1 augustss if (!bps)
1570 1.1 augustss return EINVAL;
1571 1.1 augustss
1572 1.1 augustss /* set DMA frame */
1573 1.1 augustss if (!(p = cmpci_find_dmamem(sc, start)))
1574 1.1 augustss return EINVAL;
1575 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BASE,
1576 1.1 augustss DMAADDR(p));
1577 1.1 augustss delay(10);
1578 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BYTES,
1579 1.35 christos ((char *)end - (char *)start + 1) / bps - 1);
1580 1.1 augustss delay(10);
1581 1.1 augustss
1582 1.1 augustss /* set interrupt count */
1583 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_SAMPLES,
1584 1.1 augustss (blksize + bps - 1) / bps - 1);
1585 1.1 augustss delay(10);
1586 1.1 augustss
1587 1.1 augustss /* start DMA */
1588 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); /* PLAY */
1589 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
1590 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
1591 1.10 itohy
1592 1.1 augustss return 0;
1593 1.1 augustss }
1594 1.1 augustss
1595 1.1 augustss static int
1596 1.28 kent cmpci_trigger_input(void *handle, void *start, void *end, int blksize,
1597 1.28 kent void (*intr)(void *), void *arg,
1598 1.28 kent const audio_params_t *param)
1599 1.1 augustss {
1600 1.28 kent struct cmpci_softc *sc;
1601 1.1 augustss struct cmpci_dmanode *p;
1602 1.1 augustss int bps;
1603 1.1 augustss
1604 1.28 kent sc = handle;
1605 1.1 augustss sc->sc_rec.intr = intr;
1606 1.1 augustss sc->sc_rec.intr_arg = arg;
1607 1.27 kent bps = param->channels * param->precision / 8;
1608 1.1 augustss if (!bps)
1609 1.1 augustss return EINVAL;
1610 1.1 augustss
1611 1.1 augustss /* set DMA frame */
1612 1.1 augustss if (!(p=cmpci_find_dmamem(sc, start)))
1613 1.1 augustss return EINVAL;
1614 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BASE,
1615 1.1 augustss DMAADDR(p));
1616 1.1 augustss delay(10);
1617 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BYTES,
1618 1.35 christos ((char *)end - (char *)start + 1) / bps - 1);
1619 1.1 augustss delay(10);
1620 1.1 augustss
1621 1.1 augustss /* set interrupt count */
1622 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_SAMPLES,
1623 1.7 tshiozak (blksize + bps - 1) / bps - 1);
1624 1.1 augustss delay(10);
1625 1.1 augustss
1626 1.1 augustss /* start DMA */
1627 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); /* REC */
1628 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
1629 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
1630 1.10 itohy
1631 1.1 augustss return 0;
1632 1.1 augustss }
1633 1.1 augustss
1634 1.43 jmcneill static void
1635 1.43 jmcneill cmpci_get_locks(void *addr, kmutex_t **intr, kmutex_t **thread)
1636 1.43 jmcneill {
1637 1.43 jmcneill struct cmpci_softc *sc;
1638 1.43 jmcneill
1639 1.43 jmcneill sc = addr;
1640 1.43 jmcneill *intr = &sc->sc_intr_lock;
1641 1.43 jmcneill *thread = &sc->sc_lock;
1642 1.43 jmcneill }
1643 1.43 jmcneill
1644 1.1 augustss /* end of file */
1645