cmpci.c revision 1.7.2.6 1 1.7.2.6 nathanw /* $NetBSD: cmpci.c,v 1.7.2.6 2002/10/18 02:42:56 nathanw Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.7.2.3 nathanw * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.7 tshiozak * by Takuya SHIOZAKI <tshiozak (at) netbsd.org> .
9 1.1 augustss *
10 1.7.2.3 nathanw * This code is derived from software contributed to The NetBSD Foundation
11 1.7.2.3 nathanw * by ITOH Yasufumi.
12 1.7.2.3 nathanw *
13 1.1 augustss * Redistribution and use in source and binary forms, with or without
14 1.1 augustss * modification, are permitted provided that the following conditions
15 1.1 augustss * are met:
16 1.1 augustss * 1. Redistributions of source code must retain the above copyright
17 1.1 augustss * notice, this list of conditions and the following disclaimer.
18 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
19 1.1 augustss * notice, this list of conditions and the following disclaimer in the
20 1.1 augustss * documentation and/or other materials provided with the distribution.
21 1.1 augustss *
22 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 1.1 augustss * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.1 augustss * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 augustss * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 1.1 augustss * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 1.1 augustss * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 1.1 augustss * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.1 augustss * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.1 augustss * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.1 augustss * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.1 augustss * SUCH DAMAGE.
33 1.1 augustss *
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * C-Media CMI8x38 Audio Chip Support.
38 1.1 augustss *
39 1.1 augustss * TODO:
40 1.7.2.3 nathanw * - 4ch / 6ch support.
41 1.7.2.3 nathanw * - Joystick support.
42 1.1 augustss *
43 1.1 augustss */
44 1.1 augustss
45 1.7.2.3 nathanw #include <sys/cdefs.h>
46 1.7.2.6 nathanw __KERNEL_RCSID(0, "$NetBSD: cmpci.c,v 1.7.2.6 2002/10/18 02:42:56 nathanw Exp $");
47 1.7.2.3 nathanw
48 1.1 augustss #if defined(AUDIO_DEBUG) || defined(DEBUG)
49 1.7 tshiozak #define DPRINTF(x) if (cmpcidebug) printf x
50 1.7 tshiozak int cmpcidebug = 0;
51 1.1 augustss #else
52 1.1 augustss #define DPRINTF(x)
53 1.1 augustss #endif
54 1.1 augustss
55 1.7.2.1 nathanw #include "mpu.h"
56 1.7.2.1 nathanw
57 1.1 augustss #include <sys/param.h>
58 1.1 augustss #include <sys/systm.h>
59 1.1 augustss #include <sys/kernel.h>
60 1.1 augustss #include <sys/malloc.h>
61 1.1 augustss #include <sys/device.h>
62 1.1 augustss #include <sys/proc.h>
63 1.1 augustss
64 1.1 augustss #include <dev/pci/pcidevs.h>
65 1.1 augustss #include <dev/pci/pcivar.h>
66 1.1 augustss
67 1.1 augustss #include <sys/audioio.h>
68 1.1 augustss #include <dev/audio_if.h>
69 1.1 augustss #include <dev/midi_if.h>
70 1.1 augustss
71 1.1 augustss #include <dev/mulaw.h>
72 1.1 augustss #include <dev/auconv.h>
73 1.1 augustss #include <dev/pci/cmpcireg.h>
74 1.1 augustss #include <dev/pci/cmpcivar.h>
75 1.1 augustss
76 1.1 augustss #include <dev/ic/mpuvar.h>
77 1.1 augustss #include <machine/bus.h>
78 1.1 augustss #include <machine/intr.h>
79 1.1 augustss
80 1.1 augustss /*
81 1.1 augustss * Low-level HW interface
82 1.1 augustss */
83 1.1 augustss static __inline uint8_t cmpci_mixerreg_read __P((struct cmpci_softc *,
84 1.7 tshiozak uint8_t));
85 1.1 augustss static __inline void cmpci_mixerreg_write __P((struct cmpci_softc *,
86 1.7 tshiozak uint8_t, uint8_t));
87 1.7.2.3 nathanw static __inline void cmpci_reg_partial_write_1 __P((struct cmpci_softc *,
88 1.7.2.3 nathanw int, int,
89 1.7.2.3 nathanw unsigned, unsigned));
90 1.1 augustss static __inline void cmpci_reg_partial_write_4 __P((struct cmpci_softc *,
91 1.7 tshiozak int, int,
92 1.7 tshiozak uint32_t, uint32_t));
93 1.7 tshiozak static __inline void cmpci_reg_set_1 __P((struct cmpci_softc *,
94 1.7 tshiozak int, uint8_t));
95 1.7 tshiozak static __inline void cmpci_reg_clear_1 __P((struct cmpci_softc *,
96 1.7 tshiozak int, uint8_t));
97 1.1 augustss static __inline void cmpci_reg_set_4 __P((struct cmpci_softc *,
98 1.7 tshiozak int, uint32_t));
99 1.1 augustss static __inline void cmpci_reg_clear_4 __P((struct cmpci_softc *,
100 1.7 tshiozak int, uint32_t));
101 1.1 augustss static int cmpci_rate_to_index __P((int));
102 1.1 augustss static __inline int cmpci_index_to_rate __P((int));
103 1.1 augustss static __inline int cmpci_index_to_divider __P((int));
104 1.1 augustss
105 1.1 augustss static int cmpci_adjust __P((int, int));
106 1.1 augustss static void cmpci_set_mixer_gain __P((struct cmpci_softc *, int));
107 1.7 tshiozak static void cmpci_set_out_ports __P((struct cmpci_softc *));
108 1.7.2.3 nathanw static int cmpci_set_in_ports __P((struct cmpci_softc *));
109 1.1 augustss
110 1.1 augustss
111 1.1 augustss /*
112 1.1 augustss * autoconf interface
113 1.1 augustss */
114 1.1 augustss static int cmpci_match __P((struct device *, struct cfdata *, void *));
115 1.1 augustss static void cmpci_attach __P((struct device *, struct device *, void *));
116 1.1 augustss
117 1.7.2.6 nathanw CFATTACH_DECL(cmpci, sizeof (struct cmpci_softc),
118 1.7.2.6 nathanw cmpci_match, cmpci_attach, NULL, NULL);
119 1.1 augustss
120 1.1 augustss /* interrupt */
121 1.1 augustss static int cmpci_intr __P((void *));
122 1.1 augustss
123 1.1 augustss
124 1.1 augustss /*
125 1.1 augustss * DMA stuffs
126 1.1 augustss */
127 1.1 augustss static int cmpci_alloc_dmamem __P((struct cmpci_softc *,
128 1.7 tshiozak size_t, int, int, caddr_t *));
129 1.1 augustss static int cmpci_free_dmamem __P((struct cmpci_softc *, caddr_t, int));
130 1.1 augustss static struct cmpci_dmanode * cmpci_find_dmamem __P((struct cmpci_softc *,
131 1.7 tshiozak caddr_t));
132 1.1 augustss
133 1.1 augustss
134 1.1 augustss /*
135 1.1 augustss * interface to machine independent layer
136 1.1 augustss */
137 1.1 augustss static int cmpci_open __P((void *, int));
138 1.1 augustss static void cmpci_close __P((void *));
139 1.1 augustss static int cmpci_query_encoding __P((void *, struct audio_encoding *));
140 1.1 augustss static int cmpci_set_params __P((void *, int, int,
141 1.7 tshiozak struct audio_params *,
142 1.7 tshiozak struct audio_params *));
143 1.1 augustss static int cmpci_round_blocksize __P((void *, int));
144 1.1 augustss static int cmpci_halt_output __P((void *));
145 1.1 augustss static int cmpci_halt_input __P((void *));
146 1.1 augustss static int cmpci_getdev __P((void *, struct audio_device *));
147 1.1 augustss static int cmpci_set_port __P((void *, mixer_ctrl_t *));
148 1.1 augustss static int cmpci_get_port __P((void *, mixer_ctrl_t *));
149 1.1 augustss static int cmpci_query_devinfo __P((void *, mixer_devinfo_t *));
150 1.1 augustss static void *cmpci_allocm __P((void *, int, size_t, int, int));
151 1.1 augustss static void cmpci_freem __P((void *, void *, int));
152 1.1 augustss static size_t cmpci_round_buffersize __P((void *, int, size_t));
153 1.4 simonb static paddr_t cmpci_mappage __P((void *, void *, off_t, int));
154 1.1 augustss static int cmpci_get_props __P((void *));
155 1.1 augustss static int cmpci_trigger_output __P((void *, void *, void *, int,
156 1.7 tshiozak void (*)(void *), void *,
157 1.7 tshiozak struct audio_params *));
158 1.1 augustss static int cmpci_trigger_input __P((void *, void *, void *, int,
159 1.7 tshiozak void (*)(void *), void *,
160 1.7 tshiozak struct audio_params *));
161 1.1 augustss
162 1.1 augustss static struct audio_hw_if cmpci_hw_if = {
163 1.3 gmcgarry cmpci_open, /* open */
164 1.3 gmcgarry cmpci_close, /* close */
165 1.1 augustss NULL, /* drain */
166 1.3 gmcgarry cmpci_query_encoding, /* query_encoding */
167 1.3 gmcgarry cmpci_set_params, /* set_params */
168 1.3 gmcgarry cmpci_round_blocksize, /* round_blocksize */
169 1.1 augustss NULL, /* commit_settings */
170 1.1 augustss NULL, /* init_output */
171 1.1 augustss NULL, /* init_input */
172 1.1 augustss NULL, /* start_output */
173 1.1 augustss NULL, /* start_input */
174 1.3 gmcgarry cmpci_halt_output, /* halt_output */
175 1.3 gmcgarry cmpci_halt_input, /* halt_input */
176 1.1 augustss NULL, /* speaker_ctl */
177 1.3 gmcgarry cmpci_getdev, /* getdev */
178 1.1 augustss NULL, /* setfd */
179 1.3 gmcgarry cmpci_set_port, /* set_port */
180 1.3 gmcgarry cmpci_get_port, /* get_port */
181 1.3 gmcgarry cmpci_query_devinfo, /* query_devinfo */
182 1.3 gmcgarry cmpci_allocm, /* allocm */
183 1.3 gmcgarry cmpci_freem, /* freem */
184 1.3 gmcgarry cmpci_round_buffersize,/* round_buffersize */
185 1.3 gmcgarry cmpci_mappage, /* mappage */
186 1.3 gmcgarry cmpci_get_props, /* get_props */
187 1.3 gmcgarry cmpci_trigger_output, /* trigger_output */
188 1.7.2.2 nathanw cmpci_trigger_input, /* trigger_input */
189 1.7.2.2 nathanw NULL, /* dev_ioctl */
190 1.1 augustss };
191 1.1 augustss
192 1.1 augustss
193 1.1 augustss /*
194 1.1 augustss * Low-level HW interface
195 1.1 augustss */
196 1.1 augustss
197 1.1 augustss /* mixer register read/write */
198 1.1 augustss static __inline uint8_t
199 1.1 augustss cmpci_mixerreg_read(sc, no)
200 1.1 augustss struct cmpci_softc *sc;
201 1.1 augustss uint8_t no;
202 1.1 augustss {
203 1.1 augustss uint8_t ret;
204 1.1 augustss
205 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no);
206 1.1 augustss delay(10);
207 1.1 augustss ret = bus_space_read_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA);
208 1.1 augustss delay(10);
209 1.1 augustss return ret;
210 1.1 augustss }
211 1.1 augustss
212 1.1 augustss static __inline void
213 1.1 augustss cmpci_mixerreg_write(sc, no, val)
214 1.1 augustss struct cmpci_softc *sc;
215 1.1 augustss uint8_t no, val;
216 1.1 augustss {
217 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no);
218 1.1 augustss delay(10);
219 1.1 augustss bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA, val);
220 1.1 augustss delay(10);
221 1.1 augustss }
222 1.1 augustss
223 1.1 augustss
224 1.1 augustss /* register partial write */
225 1.1 augustss static __inline void
226 1.7.2.3 nathanw cmpci_reg_partial_write_1(sc, no, shift, mask, val)
227 1.7.2.3 nathanw struct cmpci_softc *sc;
228 1.7.2.3 nathanw int no, shift;
229 1.7.2.3 nathanw unsigned mask, val;
230 1.7.2.3 nathanw {
231 1.7.2.3 nathanw bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
232 1.7.2.3 nathanw (val<<shift) |
233 1.7.2.3 nathanw (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));
234 1.7.2.3 nathanw delay(10);
235 1.7.2.3 nathanw }
236 1.7.2.3 nathanw
237 1.7.2.3 nathanw static __inline void
238 1.1 augustss cmpci_reg_partial_write_4(sc, no, shift, mask, val)
239 1.1 augustss struct cmpci_softc *sc;
240 1.1 augustss int no, shift;
241 1.1 augustss uint32_t mask, val;
242 1.1 augustss {
243 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
244 1.1 augustss (val<<shift) |
245 1.1 augustss (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));
246 1.1 augustss delay(10);
247 1.1 augustss }
248 1.1 augustss
249 1.1 augustss /* register set/clear bit */
250 1.1 augustss static __inline void
251 1.7 tshiozak cmpci_reg_set_1(sc, no, mask)
252 1.7 tshiozak struct cmpci_softc *sc;
253 1.7 tshiozak int no;
254 1.7 tshiozak uint8_t mask;
255 1.7 tshiozak {
256 1.7 tshiozak bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
257 1.7 tshiozak (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) | mask));
258 1.7 tshiozak delay(10);
259 1.7 tshiozak }
260 1.7 tshiozak
261 1.7 tshiozak static __inline void
262 1.7 tshiozak cmpci_reg_clear_1(sc, no, mask)
263 1.7 tshiozak struct cmpci_softc *sc;
264 1.7 tshiozak int no;
265 1.7 tshiozak uint8_t mask;
266 1.7 tshiozak {
267 1.7 tshiozak bus_space_write_1(sc->sc_iot, sc->sc_ioh, no,
268 1.7 tshiozak (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~mask));
269 1.7 tshiozak delay(10);
270 1.7 tshiozak }
271 1.7 tshiozak
272 1.7 tshiozak
273 1.7 tshiozak static __inline void
274 1.1 augustss cmpci_reg_set_4(sc, no, mask)
275 1.1 augustss struct cmpci_softc *sc;
276 1.1 augustss int no;
277 1.1 augustss uint32_t mask;
278 1.1 augustss {
279 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
280 1.7 tshiozak (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) | mask));
281 1.1 augustss delay(10);
282 1.1 augustss }
283 1.1 augustss
284 1.1 augustss static __inline void
285 1.1 augustss cmpci_reg_clear_4(sc, no, mask)
286 1.1 augustss struct cmpci_softc *sc;
287 1.1 augustss int no;
288 1.1 augustss uint32_t mask;
289 1.1 augustss {
290 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, no,
291 1.7 tshiozak (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~mask));
292 1.1 augustss delay(10);
293 1.1 augustss }
294 1.1 augustss
295 1.1 augustss
296 1.1 augustss /* rate */
297 1.6 jdolecek static const struct {
298 1.1 augustss int rate;
299 1.1 augustss int divider;
300 1.1 augustss } cmpci_rate_table[CMPCI_REG_NUMRATE] = {
301 1.1 augustss #define _RATE(n) { n, CMPCI_REG_RATE_ ## n }
302 1.1 augustss _RATE(5512),
303 1.1 augustss _RATE(8000),
304 1.1 augustss _RATE(11025),
305 1.1 augustss _RATE(16000),
306 1.1 augustss _RATE(22050),
307 1.1 augustss _RATE(32000),
308 1.1 augustss _RATE(44100),
309 1.1 augustss _RATE(48000)
310 1.7 tshiozak #undef _RATE
311 1.1 augustss };
312 1.1 augustss
313 1.1 augustss static int
314 1.1 augustss cmpci_rate_to_index(rate)
315 1.1 augustss int rate;
316 1.1 augustss {
317 1.1 augustss int i;
318 1.1 augustss
319 1.7.2.5 nathanw for (i = 0; i < CMPCI_REG_NUMRATE - 1; i++)
320 1.1 augustss if (rate <=
321 1.1 augustss (cmpci_rate_table[i].rate+cmpci_rate_table[i+1].rate) / 2)
322 1.1 augustss return i;
323 1.1 augustss return i; /* 48000 */
324 1.1 augustss }
325 1.1 augustss
326 1.1 augustss static __inline int
327 1.1 augustss cmpci_index_to_rate(index)
328 1.1 augustss int index;
329 1.1 augustss {
330 1.1 augustss return cmpci_rate_table[index].rate;
331 1.1 augustss }
332 1.1 augustss
333 1.1 augustss static __inline int
334 1.1 augustss cmpci_index_to_divider(index)
335 1.1 augustss int index;
336 1.1 augustss {
337 1.1 augustss return cmpci_rate_table[index].divider;
338 1.1 augustss }
339 1.1 augustss
340 1.1 augustss
341 1.1 augustss /*
342 1.1 augustss * interface to configure the device.
343 1.1 augustss */
344 1.1 augustss
345 1.1 augustss static int
346 1.1 augustss cmpci_match(parent, match, aux)
347 1.1 augustss struct device *parent;
348 1.1 augustss struct cfdata *match;
349 1.1 augustss void *aux;
350 1.1 augustss {
351 1.1 augustss struct pci_attach_args *pa = (struct pci_attach_args *)aux;
352 1.1 augustss
353 1.1 augustss if ( PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMEDIA &&
354 1.1 augustss (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338A ||
355 1.1 augustss PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338B ||
356 1.7 tshiozak PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738 ||
357 1.7 tshiozak PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738B) )
358 1.1 augustss return 1;
359 1.1 augustss
360 1.1 augustss return 0;
361 1.1 augustss }
362 1.1 augustss
363 1.1 augustss static void
364 1.1 augustss cmpci_attach(parent, self, aux)
365 1.1 augustss struct device *parent, *self;
366 1.1 augustss void *aux;
367 1.1 augustss {
368 1.1 augustss struct cmpci_softc *sc = (struct cmpci_softc *)self;
369 1.1 augustss struct pci_attach_args *pa = (struct pci_attach_args *)aux;
370 1.7.2.1 nathanw struct audio_attach_args aa;
371 1.1 augustss pci_intr_handle_t ih;
372 1.1 augustss char const *strintr;
373 1.7 tshiozak char devinfo[256];
374 1.1 augustss int i, v;
375 1.1 augustss
376 1.7 tshiozak sc->sc_id = pa->pa_id;
377 1.7 tshiozak sc->sc_class = pa->pa_class;
378 1.7 tshiozak pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
379 1.7 tshiozak printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(sc->sc_class));
380 1.7 tshiozak switch (PCI_PRODUCT(sc->sc_id)) {
381 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338A:
382 1.7 tshiozak /*FALLTHROUGH*/
383 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338B:
384 1.7 tshiozak sc->sc_capable = CMPCI_CAP_CMI8338;
385 1.1 augustss break;
386 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8738:
387 1.7 tshiozak /*FALLTHROUGH*/
388 1.7 tshiozak case PCI_PRODUCT_CMEDIA_CMI8738B:
389 1.7 tshiozak sc->sc_capable = CMPCI_CAP_CMI8738;
390 1.1 augustss break;
391 1.1 augustss }
392 1.1 augustss
393 1.2 augustss /* map I/O space */
394 1.1 augustss if (pci_mapreg_map(pa, CMPCI_PCI_IOBASEREG, PCI_MAPREG_TYPE_IO, 0,
395 1.7 tshiozak &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) {
396 1.1 augustss printf("%s: failed to map I/O space\n", sc->sc_dev.dv_xname);
397 1.1 augustss return;
398 1.1 augustss }
399 1.1 augustss
400 1.2 augustss /* interrupt */
401 1.5 sommerfe if (pci_intr_map(pa, &ih)) {
402 1.1 augustss printf("%s: failed to map interrupt\n", sc->sc_dev.dv_xname);
403 1.1 augustss return;
404 1.1 augustss }
405 1.1 augustss strintr = pci_intr_string(pa->pa_pc, ih);
406 1.1 augustss sc->sc_ih=pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, cmpci_intr, sc);
407 1.1 augustss if (sc->sc_ih == NULL) {
408 1.1 augustss printf("%s: failed to establish interrupt",
409 1.1 augustss sc->sc_dev.dv_xname);
410 1.1 augustss if (strintr != NULL)
411 1.1 augustss printf(" at %s", strintr);
412 1.1 augustss printf("\n");
413 1.1 augustss return;
414 1.1 augustss }
415 1.3 gmcgarry printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, strintr);
416 1.1 augustss
417 1.1 augustss sc->sc_dmat = pa->pa_dmat;
418 1.1 augustss
419 1.1 augustss audio_attach_mi(&cmpci_hw_if, sc, &sc->sc_dev);
420 1.1 augustss
421 1.7.2.1 nathanw /* attach OPL device */
422 1.7.2.1 nathanw aa.type = AUDIODEV_TYPE_OPL;
423 1.7.2.1 nathanw aa.hwif = NULL;
424 1.7.2.1 nathanw aa.hdl = NULL;
425 1.7.2.1 nathanw (void)config_found(&sc->sc_dev, &aa, audioprint);
426 1.7.2.1 nathanw
427 1.7.2.1 nathanw /* attach MPU-401 device */
428 1.7.2.1 nathanw aa.type = AUDIODEV_TYPE_MPU;
429 1.7.2.1 nathanw aa.hwif = NULL;
430 1.7.2.1 nathanw aa.hdl = NULL;
431 1.7.2.1 nathanw if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
432 1.7.2.1 nathanw CMPCI_REG_MPU_BASE, CMPCI_REG_MPU_SIZE, &sc->sc_mpu_ioh) == 0)
433 1.7.2.1 nathanw sc->sc_mpudev = config_found(&sc->sc_dev, &aa, audioprint);
434 1.7.2.1 nathanw
435 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_RESET, 0);
436 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
437 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
438 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX,
439 1.1 augustss CMPCI_SB16_SW_CD|CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
440 1.1 augustss for (i = 0; i < CMPCI_NDEVS; i++) {
441 1.1 augustss switch(i) {
442 1.7.2.3 nathanw /*
443 1.7.2.3 nathanw * CMI8738 defaults are
444 1.7.2.3 nathanw * master: 0xe0 (0x00 - 0xf8)
445 1.7.2.4 nathanw * FM, DAC: 0xc0 (0x00 - 0xf8)
446 1.7.2.3 nathanw * PC speaker: 0x80 (0x00 - 0xc0)
447 1.7.2.3 nathanw * others: 0
448 1.7.2.3 nathanw */
449 1.7.2.3 nathanw /* volume */
450 1.7.2.1 nathanw case CMPCI_MASTER_VOL:
451 1.7.2.3 nathanw v = 128; /* 224 */
452 1.7.2.3 nathanw break;
453 1.7.2.1 nathanw case CMPCI_FM_VOL:
454 1.7.2.3 nathanw case CMPCI_DAC_VOL:
455 1.7.2.3 nathanw v = 192;
456 1.7.2.1 nathanw break;
457 1.7.2.3 nathanw case CMPCI_PCSPEAKER:
458 1.7.2.3 nathanw v = 128;
459 1.1 augustss break;
460 1.7.2.1 nathanw
461 1.7.2.1 nathanw /* booleans, set to true */
462 1.7.2.3 nathanw case CMPCI_CD_MUTE:
463 1.7.2.3 nathanw case CMPCI_MIC_MUTE:
464 1.7.2.3 nathanw case CMPCI_LINE_IN_MUTE:
465 1.7.2.3 nathanw case CMPCI_AUX_IN_MUTE:
466 1.7.2.1 nathanw v = 1;
467 1.1 augustss break;
468 1.7.2.3 nathanw
469 1.7.2.3 nathanw /* volume with inital value 0 */
470 1.7.2.3 nathanw case CMPCI_CD_VOL:
471 1.7.2.3 nathanw case CMPCI_LINE_IN_VOL:
472 1.7.2.3 nathanw case CMPCI_AUX_IN_VOL:
473 1.7.2.3 nathanw case CMPCI_MIC_VOL:
474 1.7.2.3 nathanw case CMPCI_MIC_RECVOL:
475 1.7.2.3 nathanw /* FALLTHROUGH */
476 1.7.2.3 nathanw
477 1.7.2.1 nathanw /* others are cleared */
478 1.7.2.3 nathanw case CMPCI_MIC_PREAMP:
479 1.7.2.1 nathanw case CMPCI_RECORD_SOURCE:
480 1.7.2.3 nathanw case CMPCI_PLAYBACK_MODE:
481 1.7.2.3 nathanw case CMPCI_SPDIF_IN_SELECT:
482 1.7.2.3 nathanw case CMPCI_SPDIF_IN_PHASE:
483 1.7 tshiozak case CMPCI_SPDIF_LOOP:
484 1.7.2.3 nathanw case CMPCI_SPDIF_OUT_PLAYBACK:
485 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
486 1.7.2.3 nathanw case CMPCI_MONITOR_DAC:
487 1.7 tshiozak case CMPCI_REAR:
488 1.7 tshiozak case CMPCI_INDIVIDUAL:
489 1.7 tshiozak case CMPCI_REVERSE:
490 1.7 tshiozak case CMPCI_SURROUND:
491 1.7.2.1 nathanw default:
492 1.1 augustss v = 0;
493 1.1 augustss break;
494 1.1 augustss }
495 1.7 tshiozak sc->sc_gain[i][CMPCI_LEFT] = sc->sc_gain[i][CMPCI_RIGHT] = v;
496 1.1 augustss cmpci_set_mixer_gain(sc, i);
497 1.1 augustss }
498 1.1 augustss }
499 1.1 augustss
500 1.1 augustss
501 1.1 augustss static int
502 1.1 augustss cmpci_intr(handle)
503 1.1 augustss void *handle;
504 1.1 augustss {
505 1.1 augustss struct cmpci_softc *sc = handle;
506 1.1 augustss uint32_t intrstat;
507 1.1 augustss
508 1.1 augustss intrstat = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
509 1.1 augustss CMPCI_REG_INTR_STATUS);
510 1.1 augustss
511 1.1 augustss if (!(intrstat & CMPCI_REG_ANY_INTR))
512 1.1 augustss return 0;
513 1.1 augustss
514 1.7.2.1 nathanw delay(10);
515 1.7.2.1 nathanw
516 1.1 augustss /* disable and reset intr */
517 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR)
518 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL,
519 1.1 augustss CMPCI_REG_CH0_INTR_ENABLE);
520 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR)
521 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL,
522 1.1 augustss CMPCI_REG_CH1_INTR_ENABLE);
523 1.1 augustss
524 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR) {
525 1.1 augustss if (sc->sc_play.intr != NULL)
526 1.1 augustss (*sc->sc_play.intr)(sc->sc_play.intr_arg);
527 1.1 augustss }
528 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR) {
529 1.1 augustss if (sc->sc_rec.intr != NULL)
530 1.1 augustss (*sc->sc_rec.intr)(sc->sc_rec.intr_arg);
531 1.1 augustss }
532 1.1 augustss
533 1.1 augustss /* enable intr */
534 1.1 augustss if (intrstat & CMPCI_REG_CH0_INTR)
535 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL,
536 1.1 augustss CMPCI_REG_CH0_INTR_ENABLE);
537 1.1 augustss if (intrstat & CMPCI_REG_CH1_INTR)
538 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL,
539 1.1 augustss CMPCI_REG_CH1_INTR_ENABLE);
540 1.7.2.1 nathanw
541 1.7.2.1 nathanw #if NMPU > 0
542 1.7.2.1 nathanw if (intrstat & CMPCI_REG_UART_INTR && sc->sc_mpudev != NULL)
543 1.7.2.1 nathanw mpu_intr(sc->sc_mpudev);
544 1.7.2.1 nathanw #endif
545 1.7.2.1 nathanw
546 1.7.2.1 nathanw return 1;
547 1.1 augustss }
548 1.1 augustss
549 1.1 augustss
550 1.1 augustss /* open/close */
551 1.1 augustss static int
552 1.1 augustss cmpci_open(handle, flags)
553 1.1 augustss void *handle;
554 1.1 augustss int flags;
555 1.1 augustss {
556 1.1 augustss return 0;
557 1.1 augustss }
558 1.1 augustss
559 1.1 augustss static void
560 1.1 augustss cmpci_close(handle)
561 1.1 augustss void *handle;
562 1.1 augustss {
563 1.1 augustss }
564 1.1 augustss
565 1.1 augustss static int
566 1.1 augustss cmpci_query_encoding(handle, fp)
567 1.1 augustss void *handle;
568 1.1 augustss struct audio_encoding *fp;
569 1.1 augustss {
570 1.1 augustss switch (fp->index) {
571 1.1 augustss case 0:
572 1.1 augustss strcpy(fp->name, AudioEulinear);
573 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR;
574 1.1 augustss fp->precision = 8;
575 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
576 1.1 augustss break;
577 1.1 augustss case 1:
578 1.1 augustss strcpy(fp->name, AudioEmulaw);
579 1.1 augustss fp->encoding = AUDIO_ENCODING_ULAW;
580 1.1 augustss fp->precision = 8;
581 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
582 1.1 augustss break;
583 1.1 augustss case 2:
584 1.1 augustss strcpy(fp->name, AudioEalaw);
585 1.1 augustss fp->encoding = AUDIO_ENCODING_ALAW;
586 1.1 augustss fp->precision = 8;
587 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
588 1.1 augustss break;
589 1.1 augustss case 3:
590 1.1 augustss strcpy(fp->name, AudioEslinear);
591 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR;
592 1.1 augustss fp->precision = 8;
593 1.1 augustss fp->flags = 0;
594 1.1 augustss break;
595 1.1 augustss case 4:
596 1.1 augustss strcpy(fp->name, AudioEslinear_le);
597 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR_LE;
598 1.1 augustss fp->precision = 16;
599 1.1 augustss fp->flags = 0;
600 1.1 augustss break;
601 1.1 augustss case 5:
602 1.1 augustss strcpy(fp->name, AudioEulinear_le);
603 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR_LE;
604 1.1 augustss fp->precision = 16;
605 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
606 1.1 augustss break;
607 1.1 augustss case 6:
608 1.1 augustss strcpy(fp->name, AudioEslinear_be);
609 1.1 augustss fp->encoding = AUDIO_ENCODING_SLINEAR_BE;
610 1.1 augustss fp->precision = 16;
611 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
612 1.1 augustss break;
613 1.1 augustss case 7:
614 1.1 augustss strcpy(fp->name, AudioEulinear_be);
615 1.1 augustss fp->encoding = AUDIO_ENCODING_ULINEAR_BE;
616 1.1 augustss fp->precision = 16;
617 1.1 augustss fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
618 1.1 augustss break;
619 1.1 augustss default:
620 1.1 augustss return EINVAL;
621 1.1 augustss }
622 1.1 augustss return 0;
623 1.1 augustss }
624 1.1 augustss
625 1.1 augustss
626 1.1 augustss static int
627 1.1 augustss cmpci_set_params(handle, setmode, usemode, play, rec)
628 1.1 augustss void *handle;
629 1.1 augustss int setmode, usemode;
630 1.1 augustss struct audio_params *play, *rec;
631 1.1 augustss {
632 1.1 augustss int i;
633 1.1 augustss struct cmpci_softc *sc = handle;
634 1.1 augustss
635 1.1 augustss for (i = 0; i < 2; i++) {
636 1.1 augustss int md_format;
637 1.1 augustss int md_divide;
638 1.1 augustss int md_index;
639 1.1 augustss int mode;
640 1.1 augustss struct audio_params *p;
641 1.7.2.3 nathanw
642 1.1 augustss switch (i) {
643 1.1 augustss case 0:
644 1.1 augustss mode = AUMODE_PLAY;
645 1.1 augustss p = play;
646 1.1 augustss break;
647 1.1 augustss case 1:
648 1.1 augustss mode = AUMODE_RECORD;
649 1.1 augustss p = rec;
650 1.1 augustss break;
651 1.1 augustss }
652 1.7.2.3 nathanw
653 1.1 augustss if (!(setmode & mode))
654 1.1 augustss continue;
655 1.1 augustss
656 1.1 augustss
657 1.1 augustss /* format */
658 1.1 augustss p->sw_code = NULL;
659 1.1 augustss switch ( p->channels ) {
660 1.1 augustss case 1:
661 1.1 augustss md_format = CMPCI_REG_FORMAT_MONO;
662 1.1 augustss break;
663 1.1 augustss case 2:
664 1.1 augustss md_format = CMPCI_REG_FORMAT_STEREO;
665 1.1 augustss break;
666 1.1 augustss default:
667 1.1 augustss return (EINVAL);
668 1.1 augustss }
669 1.1 augustss switch (p->encoding) {
670 1.1 augustss case AUDIO_ENCODING_ULAW:
671 1.1 augustss if (p->precision != 8)
672 1.1 augustss return (EINVAL);
673 1.1 augustss if (mode & AUMODE_PLAY) {
674 1.1 augustss p->factor = 2;
675 1.1 augustss p->sw_code = mulaw_to_slinear16_le;
676 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
677 1.1 augustss } else {
678 1.1 augustss p->sw_code = ulinear8_to_mulaw;
679 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
680 1.1 augustss }
681 1.1 augustss break;
682 1.1 augustss case AUDIO_ENCODING_ALAW:
683 1.1 augustss if (p->precision != 8)
684 1.1 augustss return (EINVAL);
685 1.1 augustss if (mode & AUMODE_PLAY) {
686 1.1 augustss p->factor = 2;
687 1.1 augustss p->sw_code = alaw_to_slinear16_le;
688 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
689 1.1 augustss } else {
690 1.1 augustss p->sw_code = ulinear8_to_alaw;
691 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
692 1.1 augustss }
693 1.1 augustss break;
694 1.1 augustss case AUDIO_ENCODING_SLINEAR_LE:
695 1.1 augustss switch (p->precision) {
696 1.1 augustss case 8:
697 1.1 augustss p->sw_code = change_sign8;
698 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
699 1.1 augustss break;
700 1.1 augustss case 16:
701 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
702 1.1 augustss break;
703 1.1 augustss default:
704 1.1 augustss return (EINVAL);
705 1.1 augustss }
706 1.1 augustss break;
707 1.1 augustss case AUDIO_ENCODING_SLINEAR_BE:
708 1.1 augustss switch (p->precision) {
709 1.1 augustss case 8:
710 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
711 1.1 augustss p->sw_code = change_sign8;
712 1.1 augustss break;
713 1.1 augustss case 16:
714 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
715 1.1 augustss p->sw_code = swap_bytes;
716 1.1 augustss break;
717 1.1 augustss default:
718 1.1 augustss return (EINVAL);
719 1.1 augustss }
720 1.1 augustss break;
721 1.1 augustss case AUDIO_ENCODING_ULINEAR_LE:
722 1.1 augustss switch (p->precision) {
723 1.1 augustss case 8:
724 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
725 1.1 augustss break;
726 1.1 augustss case 16:
727 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
728 1.1 augustss p->sw_code = change_sign16_le;
729 1.1 augustss break;
730 1.1 augustss default:
731 1.1 augustss return (EINVAL);
732 1.1 augustss }
733 1.1 augustss break;
734 1.1 augustss case AUDIO_ENCODING_ULINEAR_BE:
735 1.1 augustss switch (p->precision) {
736 1.1 augustss case 8:
737 1.1 augustss md_format |= CMPCI_REG_FORMAT_8BIT;
738 1.1 augustss break;
739 1.1 augustss case 16:
740 1.1 augustss md_format |= CMPCI_REG_FORMAT_16BIT;
741 1.1 augustss if (mode & AUMODE_PLAY)
742 1.7 tshiozak p->sw_code =
743 1.7 tshiozak swap_bytes_change_sign16_le;
744 1.1 augustss else
745 1.7 tshiozak p->sw_code =
746 1.7 tshiozak change_sign16_swap_bytes_le;
747 1.1 augustss break;
748 1.1 augustss default:
749 1.1 augustss return (EINVAL);
750 1.1 augustss }
751 1.1 augustss break;
752 1.1 augustss default:
753 1.1 augustss return (EINVAL);
754 1.1 augustss }
755 1.1 augustss if (mode & AUMODE_PLAY)
756 1.1 augustss cmpci_reg_partial_write_4(sc,
757 1.7 tshiozak CMPCI_REG_CHANNEL_FORMAT,
758 1.7 tshiozak CMPCI_REG_CH0_FORMAT_SHIFT,
759 1.7 tshiozak CMPCI_REG_CH0_FORMAT_MASK, md_format);
760 1.1 augustss else
761 1.1 augustss cmpci_reg_partial_write_4(sc,
762 1.7 tshiozak CMPCI_REG_CHANNEL_FORMAT,
763 1.7 tshiozak CMPCI_REG_CH1_FORMAT_SHIFT,
764 1.1 augustss CMPCI_REG_CH1_FORMAT_MASK, md_format);
765 1.1 augustss /* sample rate */
766 1.1 augustss md_index = cmpci_rate_to_index(p->sample_rate);
767 1.1 augustss md_divide = cmpci_index_to_divider(md_index);
768 1.1 augustss p->sample_rate = cmpci_index_to_rate(md_index);
769 1.1 augustss DPRINTF(("%s: sample:%d, divider=%d\n",
770 1.1 augustss sc->sc_dev.dv_xname, (int)p->sample_rate, md_divide));
771 1.1 augustss if (mode & AUMODE_PLAY) {
772 1.1 augustss cmpci_reg_partial_write_4(sc,
773 1.1 augustss CMPCI_REG_FUNC_1, CMPCI_REG_DAC_FS_SHIFT,
774 1.1 augustss CMPCI_REG_DAC_FS_MASK, md_divide);
775 1.7 tshiozak sc->sc_play.md_divide = md_divide;
776 1.1 augustss } else {
777 1.1 augustss cmpci_reg_partial_write_4(sc,
778 1.1 augustss CMPCI_REG_FUNC_1, CMPCI_REG_ADC_FS_SHIFT,
779 1.1 augustss CMPCI_REG_ADC_FS_MASK, md_divide);
780 1.7 tshiozak sc->sc_rec.md_divide = md_divide;
781 1.1 augustss }
782 1.7.2.3 nathanw cmpci_set_out_ports(sc);
783 1.7.2.3 nathanw cmpci_set_in_ports(sc);
784 1.1 augustss }
785 1.1 augustss return 0;
786 1.1 augustss }
787 1.1 augustss
788 1.1 augustss /* ARGSUSED */
789 1.1 augustss static int
790 1.1 augustss cmpci_round_blocksize(handle, block)
791 1.1 augustss void *handle;
792 1.1 augustss int block;
793 1.1 augustss {
794 1.1 augustss return (block & -4);
795 1.1 augustss }
796 1.1 augustss
797 1.1 augustss static int
798 1.1 augustss cmpci_halt_output(handle)
799 1.1 augustss void *handle;
800 1.1 augustss {
801 1.1 augustss struct cmpci_softc *sc = handle;
802 1.1 augustss int s;
803 1.1 augustss
804 1.1 augustss s = splaudio();
805 1.1 augustss sc->sc_play.intr = NULL;
806 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
807 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
808 1.1 augustss /* wait for reset DMA */
809 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
810 1.1 augustss delay(10);
811 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
812 1.1 augustss splx(s);
813 1.7.2.3 nathanw
814 1.1 augustss return 0;
815 1.1 augustss }
816 1.1 augustss
817 1.1 augustss static int
818 1.1 augustss cmpci_halt_input(handle)
819 1.1 augustss void *handle;
820 1.1 augustss {
821 1.1 augustss struct cmpci_softc *sc = handle;
822 1.1 augustss int s;
823 1.7.2.3 nathanw
824 1.1 augustss s = splaudio();
825 1.1 augustss sc->sc_rec.intr = NULL;
826 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
827 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
828 1.1 augustss /* wait for reset DMA */
829 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
830 1.1 augustss delay(10);
831 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
832 1.1 augustss splx(s);
833 1.7.2.3 nathanw
834 1.1 augustss return 0;
835 1.1 augustss }
836 1.1 augustss
837 1.1 augustss
838 1.1 augustss /* get audio device information */
839 1.1 augustss static int
840 1.1 augustss cmpci_getdev(handle, ad)
841 1.7 tshiozak void *handle;
842 1.7 tshiozak struct audio_device *ad;
843 1.1 augustss {
844 1.1 augustss struct cmpci_softc *sc = handle;
845 1.1 augustss
846 1.1 augustss strncpy(ad->name, "CMI PCI Audio", sizeof(ad->name));
847 1.7 tshiozak snprintf(ad->version, sizeof(ad->version), "0x%02x",
848 1.7 tshiozak PCI_REVISION(sc->sc_class));
849 1.7 tshiozak switch (PCI_PRODUCT(sc->sc_id)) {
850 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338A:
851 1.1 augustss strncpy(ad->config, "CMI8338A", sizeof(ad->config));
852 1.1 augustss break;
853 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8338B:
854 1.1 augustss strncpy(ad->config, "CMI8338B", sizeof(ad->config));
855 1.1 augustss break;
856 1.1 augustss case PCI_PRODUCT_CMEDIA_CMI8738:
857 1.1 augustss strncpy(ad->config, "CMI8738", sizeof(ad->config));
858 1.1 augustss break;
859 1.7 tshiozak case PCI_PRODUCT_CMEDIA_CMI8738B:
860 1.7 tshiozak strncpy(ad->config, "CMI8738B", sizeof(ad->config));
861 1.7 tshiozak break;
862 1.1 augustss default:
863 1.1 augustss strncpy(ad->config, "unknown", sizeof(ad->config));
864 1.1 augustss }
865 1.1 augustss
866 1.1 augustss return 0;
867 1.1 augustss }
868 1.1 augustss
869 1.1 augustss
870 1.1 augustss /* mixer device information */
871 1.1 augustss int
872 1.1 augustss cmpci_query_devinfo(handle, dip)
873 1.1 augustss void *handle;
874 1.1 augustss mixer_devinfo_t *dip;
875 1.1 augustss {
876 1.7.2.3 nathanw static const char *const mixer_port_names[] = {
877 1.7.2.3 nathanw AudioNdac, AudioNfmsynth, AudioNcd, AudioNline, AudioNaux,
878 1.7.2.3 nathanw AudioNmicrophone
879 1.7.2.3 nathanw };
880 1.7.2.3 nathanw static const char *const mixer_classes[] = {
881 1.7.2.3 nathanw AudioCinputs, AudioCoutputs, AudioCrecord, CmpciCplayback,
882 1.7.2.3 nathanw CmpciCspdif
883 1.7.2.3 nathanw };
884 1.7.2.3 nathanw struct cmpci_softc *sc = handle;
885 1.7.2.3 nathanw int i;
886 1.7.2.3 nathanw
887 1.7.2.3 nathanw dip->prev = dip->next = AUDIO_MIXER_LAST;
888 1.7.2.3 nathanw
889 1.1 augustss switch (dip->index) {
890 1.7.2.3 nathanw case CMPCI_INPUT_CLASS:
891 1.7.2.3 nathanw case CMPCI_OUTPUT_CLASS:
892 1.7.2.3 nathanw case CMPCI_RECORD_CLASS:
893 1.7.2.3 nathanw case CMPCI_PLAYBACK_CLASS:
894 1.7.2.3 nathanw case CMPCI_SPDIF_CLASS:
895 1.7.2.3 nathanw dip->type = AUDIO_MIXER_CLASS;
896 1.7.2.3 nathanw dip->mixer_class = dip->index;
897 1.7.2.3 nathanw strcpy(dip->label.name,
898 1.7.2.3 nathanw mixer_classes[dip->index - CMPCI_INPUT_CLASS]);
899 1.1 augustss return 0;
900 1.7.2.3 nathanw
901 1.7.2.3 nathanw case CMPCI_AUX_IN_VOL:
902 1.7.2.3 nathanw dip->un.v.delta = 1 << (8 - CMPCI_REG_AUX_VALBITS);
903 1.7.2.3 nathanw goto vol1;
904 1.7.2.3 nathanw case CMPCI_DAC_VOL:
905 1.1 augustss case CMPCI_FM_VOL:
906 1.1 augustss case CMPCI_CD_VOL:
907 1.7.2.3 nathanw case CMPCI_LINE_IN_VOL:
908 1.7.2.3 nathanw case CMPCI_MIC_VOL:
909 1.7.2.3 nathanw dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS);
910 1.7.2.3 nathanw vol1: dip->mixer_class = CMPCI_INPUT_CLASS;
911 1.7.2.3 nathanw dip->next = dip->index + 6; /* CMPCI_xxx_MUTE */
912 1.7.2.3 nathanw strcpy(dip->label.name, mixer_port_names[dip->index]);
913 1.7.2.3 nathanw dip->un.v.num_channels = (dip->index == CMPCI_MIC_VOL ? 1 : 2);
914 1.7.2.3 nathanw vol:
915 1.1 augustss dip->type = AUDIO_MIXER_VALUE;
916 1.1 augustss strcpy(dip->un.v.units.name, AudioNvolume);
917 1.1 augustss return 0;
918 1.7.2.3 nathanw
919 1.7.2.3 nathanw case CMPCI_MIC_MUTE:
920 1.7.2.3 nathanw dip->next = CMPCI_MIC_PREAMP;
921 1.7.2.3 nathanw /* FALLTHROUGH */
922 1.7.2.3 nathanw case CMPCI_DAC_MUTE:
923 1.7.2.3 nathanw case CMPCI_FM_MUTE:
924 1.7.2.3 nathanw case CMPCI_CD_MUTE:
925 1.7.2.3 nathanw case CMPCI_LINE_IN_MUTE:
926 1.7.2.3 nathanw case CMPCI_AUX_IN_MUTE:
927 1.7.2.3 nathanw dip->prev = dip->index - 6; /* CMPCI_xxx_VOL */
928 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
929 1.7.2.3 nathanw strcpy(dip->label.name, AudioNmute);
930 1.7.2.3 nathanw goto on_off;
931 1.7.2.3 nathanw on_off:
932 1.7.2.3 nathanw dip->type = AUDIO_MIXER_ENUM;
933 1.7.2.3 nathanw dip->un.e.num_mem = 2;
934 1.7.2.3 nathanw strcpy(dip->un.e.member[0].label.name, AudioNoff);
935 1.7.2.3 nathanw dip->un.e.member[0].ord = 0;
936 1.7.2.3 nathanw strcpy(dip->un.e.member[1].label.name, AudioNon);
937 1.7.2.3 nathanw dip->un.e.member[1].ord = 1;
938 1.1 augustss return 0;
939 1.7.2.3 nathanw
940 1.7.2.3 nathanw case CMPCI_MIC_PREAMP:
941 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
942 1.7.2.3 nathanw dip->prev = CMPCI_MIC_MUTE;
943 1.7.2.3 nathanw strcpy(dip->label.name, AudioNpreamp);
944 1.7.2.3 nathanw goto on_off;
945 1.7.2.3 nathanw case CMPCI_PCSPEAKER:
946 1.1 augustss dip->mixer_class = CMPCI_INPUT_CLASS;
947 1.7.2.3 nathanw strcpy(dip->label.name, AudioNspeaker);
948 1.7.2.3 nathanw dip->un.v.num_channels = 1;
949 1.7.2.3 nathanw dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_SPEAKER_VALBITS);
950 1.7.2.3 nathanw goto vol;
951 1.1 augustss case CMPCI_RECORD_SOURCE:
952 1.1 augustss dip->mixer_class = CMPCI_RECORD_CLASS;
953 1.1 augustss strcpy(dip->label.name, AudioNsource);
954 1.1 augustss dip->type = AUDIO_MIXER_SET;
955 1.7.2.3 nathanw dip->un.s.num_mem = 7;
956 1.1 augustss strcpy(dip->un.s.member[0].label.name, AudioNmicrophone);
957 1.7.2.1 nathanw dip->un.s.member[0].mask = CMPCI_RECORD_SOURCE_MIC;
958 1.1 augustss strcpy(dip->un.s.member[1].label.name, AudioNcd);
959 1.7.2.1 nathanw dip->un.s.member[1].mask = CMPCI_RECORD_SOURCE_CD;
960 1.1 augustss strcpy(dip->un.s.member[2].label.name, AudioNline);
961 1.7.2.1 nathanw dip->un.s.member[2].mask = CMPCI_RECORD_SOURCE_LINE_IN;
962 1.7.2.3 nathanw strcpy(dip->un.s.member[3].label.name, AudioNaux);
963 1.7.2.3 nathanw dip->un.s.member[3].mask = CMPCI_RECORD_SOURCE_AUX_IN;
964 1.7.2.3 nathanw strcpy(dip->un.s.member[4].label.name, AudioNwave);
965 1.7.2.3 nathanw dip->un.s.member[4].mask = CMPCI_RECORD_SOURCE_WAVE;
966 1.7.2.3 nathanw strcpy(dip->un.s.member[5].label.name, AudioNfmsynth);
967 1.7.2.3 nathanw dip->un.s.member[5].mask = CMPCI_RECORD_SOURCE_FM;
968 1.7.2.3 nathanw strcpy(dip->un.s.member[6].label.name, CmpciNspdif);
969 1.7.2.3 nathanw dip->un.s.member[6].mask = CMPCI_RECORD_SOURCE_SPDIF;
970 1.1 augustss return 0;
971 1.7.2.3 nathanw case CMPCI_MIC_RECVOL:
972 1.1 augustss dip->mixer_class = CMPCI_RECORD_CLASS;
973 1.7.2.3 nathanw strcpy(dip->label.name, AudioNmicrophone);
974 1.1 augustss dip->un.v.num_channels = 1;
975 1.7.2.3 nathanw dip->un.v.delta = 1 << (8 - CMPCI_REG_ADMIC_VALBITS);
976 1.7.2.3 nathanw goto vol;
977 1.7.2.3 nathanw
978 1.7.2.3 nathanw case CMPCI_PLAYBACK_MODE:
979 1.7.2.3 nathanw dip->mixer_class = CMPCI_PLAYBACK_CLASS;
980 1.1 augustss dip->type = AUDIO_MIXER_ENUM;
981 1.7.2.3 nathanw strcpy(dip->label.name, AudioNmode);
982 1.7.2.3 nathanw dip->un.e.num_mem = 2;
983 1.7.2.3 nathanw strcpy(dip->un.e.member[0].label.name, AudioNdac);
984 1.7.2.3 nathanw dip->un.e.member[0].ord = CMPCI_PLAYBACK_MODE_WAVE;
985 1.7.2.3 nathanw strcpy(dip->un.e.member[1].label.name, CmpciNspdif);
986 1.7.2.3 nathanw dip->un.e.member[1].ord = CMPCI_PLAYBACK_MODE_SPDIF;
987 1.1 augustss return 0;
988 1.7.2.3 nathanw case CMPCI_SPDIF_IN_SELECT:
989 1.7.2.3 nathanw dip->mixer_class = CMPCI_SPDIF_CLASS;
990 1.7.2.3 nathanw dip->type = AUDIO_MIXER_ENUM;
991 1.7.2.3 nathanw dip->next = CMPCI_SPDIF_IN_PHASE;
992 1.7.2.3 nathanw strcpy(dip->label.name, AudioNinput);
993 1.7.2.3 nathanw i = 0;
994 1.7.2.3 nathanw strcpy(dip->un.e.member[i].label.name, CmpciNspdin1);
995 1.7.2.3 nathanw dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN1;
996 1.7.2.3 nathanw if (CMPCI_ISCAP(sc, 2ND_SPDIN)) {
997 1.7.2.3 nathanw strcpy(dip->un.e.member[i].label.name, CmpciNspdin2);
998 1.7.2.3 nathanw dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN2;
999 1.7.2.3 nathanw }
1000 1.7.2.3 nathanw strcpy(dip->un.e.member[i].label.name, CmpciNspdout);
1001 1.7.2.3 nathanw dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDOUT;
1002 1.7.2.3 nathanw dip->un.e.num_mem = i;
1003 1.7 tshiozak return 0;
1004 1.7.2.3 nathanw case CMPCI_SPDIF_IN_PHASE:
1005 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
1006 1.7.2.3 nathanw dip->prev = CMPCI_SPDIF_IN_SELECT;
1007 1.7.2.3 nathanw strcpy(dip->label.name, CmpciNphase);
1008 1.7.2.3 nathanw dip->type = AUDIO_MIXER_ENUM;
1009 1.7.2.3 nathanw dip->un.e.num_mem = 2;
1010 1.7.2.3 nathanw strcpy(dip->un.e.member[0].label.name, CmpciNpositive);
1011 1.7.2.3 nathanw dip->un.e.member[0].ord = CMPCI_SPDIF_IN_PHASE_POSITIVE;
1012 1.7.2.3 nathanw strcpy(dip->un.e.member[1].label.name, CmpciNnegative);
1013 1.7.2.3 nathanw dip->un.e.member[1].ord = CMPCI_SPDIF_IN_PHASE_NEGATIVE;
1014 1.7 tshiozak return 0;
1015 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1016 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
1017 1.7.2.3 nathanw dip->next = CMPCI_SPDIF_OUT_PLAYBACK;
1018 1.7.2.3 nathanw strcpy(dip->label.name, AudioNoutput);
1019 1.7.2.3 nathanw dip->type = AUDIO_MIXER_ENUM;
1020 1.7.2.3 nathanw dip->un.e.num_mem = 2;
1021 1.7.2.3 nathanw strcpy(dip->un.e.member[0].label.name, CmpciNplayback);
1022 1.7.2.3 nathanw dip->un.e.member[0].ord = CMPCI_SPDIF_LOOP_OFF;
1023 1.7.2.3 nathanw strcpy(dip->un.e.member[1].label.name, CmpciNspdin);
1024 1.7.2.3 nathanw dip->un.e.member[1].ord = CMPCI_SPDIF_LOOP_ON;
1025 1.7.2.3 nathanw return 0;
1026 1.7.2.3 nathanw case CMPCI_SPDIF_OUT_PLAYBACK:
1027 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
1028 1.7.2.3 nathanw dip->prev = CMPCI_SPDIF_LOOP;
1029 1.7.2.3 nathanw dip->next = CMPCI_SPDIF_OUT_VOLTAGE;
1030 1.7.2.3 nathanw strcpy(dip->label.name, CmpciNplayback);
1031 1.7.2.3 nathanw dip->type = AUDIO_MIXER_ENUM;
1032 1.7.2.3 nathanw dip->un.e.num_mem = 2;
1033 1.7.2.3 nathanw strcpy(dip->un.e.member[0].label.name, AudioNwave);
1034 1.7.2.3 nathanw dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_PLAYBACK_WAVE;
1035 1.7.2.3 nathanw strcpy(dip->un.e.member[1].label.name, CmpciNlegacy);
1036 1.7.2.3 nathanw dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_PLAYBACK_LEGACY;
1037 1.7.2.3 nathanw return 0;
1038 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1039 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
1040 1.7.2.3 nathanw dip->prev = CMPCI_SPDIF_OUT_PLAYBACK;
1041 1.7.2.3 nathanw strcpy(dip->label.name, CmpciNvoltage);
1042 1.7 tshiozak dip->type = AUDIO_MIXER_ENUM;
1043 1.7 tshiozak dip->un.e.num_mem = 2;
1044 1.7 tshiozak strcpy(dip->un.e.member[0].label.name, CmpciNlow_v);
1045 1.7.2.3 nathanw dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_VOLTAGE_LOW;
1046 1.7 tshiozak strcpy(dip->un.e.member[1].label.name, CmpciNhigh_v);
1047 1.7.2.3 nathanw dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_VOLTAGE_HIGH;
1048 1.7 tshiozak return 0;
1049 1.7.2.3 nathanw case CMPCI_MONITOR_DAC:
1050 1.7 tshiozak dip->mixer_class = CMPCI_SPDIF_CLASS;
1051 1.7.2.3 nathanw strcpy(dip->label.name, AudioNmonitor);
1052 1.7.2.3 nathanw dip->type = AUDIO_MIXER_ENUM;
1053 1.7.2.3 nathanw dip->un.e.num_mem = 3;
1054 1.7.2.3 nathanw strcpy(dip->un.e.member[0].label.name, AudioNoff);
1055 1.7.2.3 nathanw dip->un.e.member[0].ord = CMPCI_MONITOR_DAC_OFF;
1056 1.7.2.3 nathanw strcpy(dip->un.e.member[1].label.name, CmpciNspdin);
1057 1.7.2.3 nathanw dip->un.e.member[1].ord = CMPCI_MONITOR_DAC_SPDIN;
1058 1.7.2.3 nathanw strcpy(dip->un.e.member[2].label.name, CmpciNspdout);
1059 1.7.2.3 nathanw dip->un.e.member[2].ord = CMPCI_MONITOR_DAC_SPDOUT;
1060 1.7.2.3 nathanw return 0;
1061 1.7.2.3 nathanw
1062 1.7.2.3 nathanw case CMPCI_MASTER_VOL:
1063 1.7.2.3 nathanw dip->mixer_class = CMPCI_OUTPUT_CLASS;
1064 1.7.2.3 nathanw strcpy(dip->label.name, AudioNmaster);
1065 1.7.2.3 nathanw dip->un.v.num_channels = 2;
1066 1.7.2.3 nathanw dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS);
1067 1.7.2.3 nathanw goto vol;
1068 1.7 tshiozak case CMPCI_REAR:
1069 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1070 1.7 tshiozak dip->next = CMPCI_INDIVIDUAL;
1071 1.7 tshiozak strcpy(dip->label.name, CmpciNrear);
1072 1.7 tshiozak goto on_off;
1073 1.7 tshiozak case CMPCI_INDIVIDUAL:
1074 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1075 1.7 tshiozak dip->prev = CMPCI_REAR;
1076 1.7 tshiozak dip->next = CMPCI_REVERSE;
1077 1.7 tshiozak strcpy(dip->label.name, CmpciNindividual);
1078 1.7 tshiozak goto on_off;
1079 1.7 tshiozak case CMPCI_REVERSE:
1080 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1081 1.7 tshiozak dip->prev = CMPCI_INDIVIDUAL;
1082 1.7 tshiozak strcpy(dip->label.name, CmpciNreverse);
1083 1.7.2.3 nathanw goto on_off;
1084 1.7 tshiozak case CMPCI_SURROUND:
1085 1.7 tshiozak dip->mixer_class = CMPCI_OUTPUT_CLASS;
1086 1.7 tshiozak strcpy(dip->label.name, CmpciNsurround);
1087 1.7 tshiozak goto on_off;
1088 1.1 augustss }
1089 1.7.2.3 nathanw
1090 1.1 augustss return ENXIO;
1091 1.1 augustss }
1092 1.1 augustss
1093 1.1 augustss static int
1094 1.1 augustss cmpci_alloc_dmamem(sc, size, type, flags, r_addr)
1095 1.1 augustss struct cmpci_softc *sc;
1096 1.1 augustss size_t size;
1097 1.1 augustss int type, flags;
1098 1.1 augustss caddr_t *r_addr;
1099 1.1 augustss {
1100 1.1 augustss int error = 0;
1101 1.1 augustss struct cmpci_dmanode *n;
1102 1.1 augustss int w;
1103 1.1 augustss
1104 1.1 augustss n = malloc(sizeof(struct cmpci_dmanode), type, flags);
1105 1.1 augustss if (n == NULL) {
1106 1.1 augustss error = ENOMEM;
1107 1.1 augustss goto quit;
1108 1.1 augustss }
1109 1.1 augustss
1110 1.1 augustss w = (flags & M_NOWAIT) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK;
1111 1.1 augustss #define CMPCI_DMABUF_ALIGN 0x4
1112 1.1 augustss #define CMPCI_DMABUF_BOUNDARY 0x0
1113 1.1 augustss n->cd_tag = sc->sc_dmat;
1114 1.1 augustss n->cd_size = size;
1115 1.1 augustss error = bus_dmamem_alloc(n->cd_tag, n->cd_size,
1116 1.1 augustss CMPCI_DMABUF_ALIGN, CMPCI_DMABUF_BOUNDARY, n->cd_segs,
1117 1.7 tshiozak sizeof(n->cd_segs)/sizeof(n->cd_segs[0]), &n->cd_nsegs, w);
1118 1.1 augustss if (error)
1119 1.1 augustss goto mfree;
1120 1.1 augustss error = bus_dmamem_map(n->cd_tag, n->cd_segs, n->cd_nsegs, n->cd_size,
1121 1.1 augustss &n->cd_addr, w | BUS_DMA_COHERENT);
1122 1.1 augustss if (error)
1123 1.1 augustss goto dmafree;
1124 1.1 augustss error = bus_dmamap_create(n->cd_tag, n->cd_size, 1, n->cd_size, 0,
1125 1.1 augustss w, &n->cd_map);
1126 1.1 augustss if (error)
1127 1.1 augustss goto unmap;
1128 1.1 augustss error = bus_dmamap_load(n->cd_tag, n->cd_map, n->cd_addr, n->cd_size,
1129 1.1 augustss NULL, w);
1130 1.1 augustss if (error)
1131 1.1 augustss goto destroy;
1132 1.7.2.3 nathanw
1133 1.1 augustss n->cd_next = sc->sc_dmap;
1134 1.1 augustss sc->sc_dmap = n;
1135 1.1 augustss *r_addr = KVADDR(n);
1136 1.1 augustss return 0;
1137 1.7.2.3 nathanw
1138 1.1 augustss destroy:
1139 1.1 augustss bus_dmamap_destroy(n->cd_tag, n->cd_map);
1140 1.1 augustss unmap:
1141 1.1 augustss bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size);
1142 1.1 augustss dmafree:
1143 1.1 augustss bus_dmamem_free(n->cd_tag,
1144 1.1 augustss n->cd_segs, sizeof(n->cd_segs)/sizeof(n->cd_segs[0]));
1145 1.1 augustss mfree:
1146 1.1 augustss free(n, type);
1147 1.1 augustss quit:
1148 1.1 augustss return error;
1149 1.1 augustss }
1150 1.1 augustss
1151 1.1 augustss static int
1152 1.1 augustss cmpci_free_dmamem(sc, addr, type)
1153 1.1 augustss struct cmpci_softc *sc;
1154 1.1 augustss caddr_t addr;
1155 1.1 augustss int type;
1156 1.1 augustss {
1157 1.1 augustss struct cmpci_dmanode **nnp;
1158 1.7.2.3 nathanw
1159 1.1 augustss for (nnp = &sc->sc_dmap; *nnp; nnp= &(*nnp)->cd_next) {
1160 1.1 augustss if ((*nnp)->cd_addr == addr) {
1161 1.1 augustss struct cmpci_dmanode *n = *nnp;
1162 1.1 augustss bus_dmamap_unload(n->cd_tag, n->cd_map);
1163 1.1 augustss bus_dmamap_destroy(n->cd_tag, n->cd_map);
1164 1.1 augustss bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size);
1165 1.1 augustss bus_dmamem_free(n->cd_tag, n->cd_segs,
1166 1.1 augustss sizeof(n->cd_segs)/sizeof(n->cd_segs[0]));
1167 1.1 augustss free(n, type);
1168 1.1 augustss return 0;
1169 1.1 augustss }
1170 1.1 augustss }
1171 1.1 augustss return -1;
1172 1.1 augustss }
1173 1.1 augustss
1174 1.1 augustss static struct cmpci_dmanode *
1175 1.1 augustss cmpci_find_dmamem(sc, addr)
1176 1.1 augustss struct cmpci_softc *sc;
1177 1.1 augustss caddr_t addr;
1178 1.1 augustss {
1179 1.1 augustss struct cmpci_dmanode *p;
1180 1.7.2.3 nathanw
1181 1.1 augustss for (p=sc->sc_dmap; p; p=p->cd_next)
1182 1.1 augustss if ( KVADDR(p) == (void *)addr )
1183 1.1 augustss break;
1184 1.1 augustss return p;
1185 1.1 augustss }
1186 1.1 augustss
1187 1.1 augustss
1188 1.1 augustss #if 0
1189 1.1 augustss static void
1190 1.1 augustss cmpci_print_dmamem __P((struct cmpci_dmanode *p));
1191 1.1 augustss static void
1192 1.1 augustss cmpci_print_dmamem(p)
1193 1.1 augustss struct cmpci_dmanode *p;
1194 1.1 augustss {
1195 1.1 augustss DPRINTF(("DMA at virt:%p, dmaseg:%p, mapseg:%p, size:%p\n",
1196 1.1 augustss (void *)p->cd_addr, (void *)p->cd_segs[0].ds_addr,
1197 1.1 augustss (void *)DMAADDR(p), (void *)p->cd_size));
1198 1.1 augustss }
1199 1.1 augustss #endif /* DEBUG */
1200 1.1 augustss
1201 1.1 augustss
1202 1.1 augustss static void *
1203 1.1 augustss cmpci_allocm(handle, direction, size, type, flags)
1204 1.1 augustss void *handle;
1205 1.1 augustss int direction;
1206 1.1 augustss size_t size;
1207 1.1 augustss int type, flags;
1208 1.1 augustss {
1209 1.1 augustss struct cmpci_softc *sc = handle;
1210 1.1 augustss caddr_t addr;
1211 1.7.2.3 nathanw
1212 1.1 augustss if (cmpci_alloc_dmamem(sc, size, type, flags, &addr))
1213 1.1 augustss return NULL;
1214 1.1 augustss return addr;
1215 1.1 augustss }
1216 1.1 augustss
1217 1.1 augustss static void
1218 1.1 augustss cmpci_freem(handle, addr, type)
1219 1.7 tshiozak void *handle;
1220 1.7 tshiozak void *addr;
1221 1.7 tshiozak int type;
1222 1.1 augustss {
1223 1.1 augustss struct cmpci_softc *sc = handle;
1224 1.7.2.3 nathanw
1225 1.1 augustss cmpci_free_dmamem(sc, addr, type);
1226 1.1 augustss }
1227 1.1 augustss
1228 1.1 augustss
1229 1.1 augustss #define MAXVAL 256
1230 1.1 augustss static int
1231 1.1 augustss cmpci_adjust(val, mask)
1232 1.1 augustss int val, mask;
1233 1.1 augustss {
1234 1.1 augustss val += (MAXVAL - mask) >> 1;
1235 1.1 augustss if (val >= MAXVAL)
1236 1.1 augustss val = MAXVAL-1;
1237 1.1 augustss return val & mask;
1238 1.1 augustss }
1239 1.1 augustss
1240 1.1 augustss static void
1241 1.1 augustss cmpci_set_mixer_gain(sc, port)
1242 1.1 augustss struct cmpci_softc *sc;
1243 1.1 augustss int port;
1244 1.1 augustss {
1245 1.1 augustss int src;
1246 1.7.2.3 nathanw int bits, mask;
1247 1.1 augustss
1248 1.1 augustss switch (port) {
1249 1.1 augustss case CMPCI_MIC_VOL:
1250 1.7.2.3 nathanw cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_MIC,
1251 1.7.2.3 nathanw CMPCI_ADJUST_MIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1252 1.1 augustss break;
1253 1.1 augustss case CMPCI_MASTER_VOL:
1254 1.1 augustss src = CMPCI_SB16_MIXER_MASTER_L;
1255 1.1 augustss break;
1256 1.1 augustss case CMPCI_LINE_IN_VOL:
1257 1.1 augustss src = CMPCI_SB16_MIXER_LINE_L;
1258 1.1 augustss break;
1259 1.7.2.3 nathanw case CMPCI_AUX_IN_VOL:
1260 1.7.2.3 nathanw bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MIXER_AUX,
1261 1.7.2.3 nathanw CMPCI_ADJUST_AUX_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT],
1262 1.7.2.3 nathanw sc->sc_gain[port][CMPCI_RIGHT]));
1263 1.7.2.3 nathanw return;
1264 1.7.2.3 nathanw case CMPCI_MIC_RECVOL:
1265 1.7.2.3 nathanw cmpci_reg_partial_write_1(sc, CMPCI_REG_MIXER25,
1266 1.7.2.3 nathanw CMPCI_REG_ADMIC_SHIFT, CMPCI_REG_ADMIC_MASK,
1267 1.7.2.3 nathanw CMPCI_ADJUST_ADMIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1268 1.7.2.3 nathanw return;
1269 1.7.2.3 nathanw case CMPCI_DAC_VOL:
1270 1.1 augustss src = CMPCI_SB16_MIXER_VOICE_L;
1271 1.1 augustss break;
1272 1.1 augustss case CMPCI_FM_VOL:
1273 1.1 augustss src = CMPCI_SB16_MIXER_FM_L;
1274 1.1 augustss break;
1275 1.1 augustss case CMPCI_CD_VOL:
1276 1.1 augustss src = CMPCI_SB16_MIXER_CDDA_L;
1277 1.1 augustss break;
1278 1.1 augustss case CMPCI_PCSPEAKER:
1279 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_SPEAKER,
1280 1.7.2.3 nathanw CMPCI_ADJUST_2_GAIN(sc, sc->sc_gain[port][CMPCI_LR]));
1281 1.7 tshiozak return;
1282 1.7.2.3 nathanw case CMPCI_MIC_PREAMP:
1283 1.7.2.3 nathanw if (sc->sc_gain[port][CMPCI_LR])
1284 1.7.2.3 nathanw cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1285 1.7.2.3 nathanw CMPCI_REG_MICGAINZ);
1286 1.7.2.3 nathanw else
1287 1.7.2.3 nathanw cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1288 1.7.2.3 nathanw CMPCI_REG_MICGAINZ);
1289 1.7.2.3 nathanw return;
1290 1.7.2.3 nathanw
1291 1.7.2.3 nathanw case CMPCI_DAC_MUTE:
1292 1.7.2.3 nathanw if (sc->sc_gain[port][CMPCI_LR])
1293 1.7.2.3 nathanw cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1294 1.7.2.3 nathanw CMPCI_REG_WSMUTE);
1295 1.7.2.3 nathanw else
1296 1.7.2.3 nathanw cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1297 1.7.2.3 nathanw CMPCI_REG_WSMUTE);
1298 1.7.2.3 nathanw return;
1299 1.7.2.3 nathanw case CMPCI_FM_MUTE:
1300 1.7.2.3 nathanw if (sc->sc_gain[port][CMPCI_LR])
1301 1.7.2.3 nathanw cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1302 1.7.2.3 nathanw CMPCI_REG_FMMUTE);
1303 1.7.2.3 nathanw else
1304 1.7.2.3 nathanw cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1305 1.7.2.3 nathanw CMPCI_REG_FMMUTE);
1306 1.7.2.3 nathanw return;
1307 1.7.2.3 nathanw case CMPCI_AUX_IN_MUTE:
1308 1.7.2.3 nathanw if (sc->sc_gain[port][CMPCI_LR])
1309 1.7.2.3 nathanw cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1310 1.7.2.3 nathanw CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM);
1311 1.7.2.3 nathanw else
1312 1.7.2.3 nathanw cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1313 1.7.2.3 nathanw CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM);
1314 1.7.2.3 nathanw return;
1315 1.7.2.3 nathanw case CMPCI_CD_MUTE:
1316 1.7.2.3 nathanw mask = CMPCI_SB16_SW_CD;
1317 1.7.2.3 nathanw goto sbmute;
1318 1.7.2.3 nathanw case CMPCI_MIC_MUTE:
1319 1.7.2.3 nathanw mask = CMPCI_SB16_SW_MIC;
1320 1.7.2.3 nathanw goto sbmute;
1321 1.7.2.3 nathanw case CMPCI_LINE_IN_MUTE:
1322 1.7.2.3 nathanw mask = CMPCI_SB16_SW_LINE;
1323 1.7.2.3 nathanw sbmute:
1324 1.7.2.3 nathanw bits = cmpci_mixerreg_read(sc, CMPCI_SB16_MIXER_OUTMIX);
1325 1.7.2.3 nathanw if (sc->sc_gain[port][CMPCI_LR])
1326 1.7.2.3 nathanw bits = bits & ~mask;
1327 1.7.2.3 nathanw else
1328 1.7.2.3 nathanw bits = bits | mask;
1329 1.7.2.3 nathanw cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX, bits);
1330 1.7.2.1 nathanw return;
1331 1.7.2.3 nathanw
1332 1.7.2.3 nathanw case CMPCI_SPDIF_IN_SELECT:
1333 1.7.2.3 nathanw case CMPCI_MONITOR_DAC:
1334 1.7.2.3 nathanw case CMPCI_PLAYBACK_MODE:
1335 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1336 1.7.2.3 nathanw case CMPCI_SPDIF_OUT_PLAYBACK:
1337 1.7 tshiozak cmpci_set_out_ports(sc);
1338 1.7 tshiozak return;
1339 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1340 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDOUT_VOLTAGE)) {
1341 1.7.2.3 nathanw if (sc->sc_gain[CMPCI_SPDIF_OUT_VOLTAGE][CMPCI_LR]
1342 1.7.2.3 nathanw == CMPCI_SPDIF_OUT_VOLTAGE_LOW)
1343 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_MISC,
1344 1.7 tshiozak CMPCI_REG_5V);
1345 1.7.2.3 nathanw else
1346 1.7.2.3 nathanw cmpci_reg_set_4(sc, CMPCI_REG_MISC,
1347 1.7.2.3 nathanw CMPCI_REG_5V);
1348 1.7 tshiozak }
1349 1.7 tshiozak return;
1350 1.7 tshiozak case CMPCI_SURROUND:
1351 1.7 tshiozak if (CMPCI_ISCAP(sc, SURROUND)) {
1352 1.7 tshiozak if (sc->sc_gain[CMPCI_SURROUND][CMPCI_LR])
1353 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1354 1.7 tshiozak CMPCI_REG_SURROUND);
1355 1.7 tshiozak else
1356 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1357 1.7 tshiozak CMPCI_REG_SURROUND);
1358 1.7 tshiozak }
1359 1.7 tshiozak return;
1360 1.7 tshiozak case CMPCI_REAR:
1361 1.7 tshiozak if (CMPCI_ISCAP(sc, REAR)) {
1362 1.7 tshiozak if (sc->sc_gain[CMPCI_REAR][CMPCI_LR])
1363 1.7 tshiozak cmpci_reg_set_4(sc, CMPCI_REG_MISC,
1364 1.7 tshiozak CMPCI_REG_N4SPK3D);
1365 1.7 tshiozak else
1366 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_MISC,
1367 1.7 tshiozak CMPCI_REG_N4SPK3D);
1368 1.7 tshiozak }
1369 1.7 tshiozak return;
1370 1.7 tshiozak case CMPCI_INDIVIDUAL:
1371 1.7 tshiozak if (CMPCI_ISCAP(sc, INDIVIDUAL_REAR)) {
1372 1.7 tshiozak if (sc->sc_gain[CMPCI_REAR][CMPCI_LR])
1373 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1374 1.7 tshiozak CMPCI_REG_INDIVIDUAL);
1375 1.7 tshiozak else
1376 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1377 1.7 tshiozak CMPCI_REG_INDIVIDUAL);
1378 1.7 tshiozak }
1379 1.7 tshiozak return;
1380 1.7 tshiozak case CMPCI_REVERSE:
1381 1.7 tshiozak if (CMPCI_ISCAP(sc, REVERSE_FR)) {
1382 1.7 tshiozak if (sc->sc_gain[CMPCI_REVERSE][CMPCI_LR])
1383 1.7 tshiozak cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1384 1.7 tshiozak CMPCI_REG_REVERSE_FR);
1385 1.7 tshiozak else
1386 1.7 tshiozak cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1387 1.7 tshiozak CMPCI_REG_REVERSE_FR);
1388 1.7 tshiozak }
1389 1.7 tshiozak return;
1390 1.7 tshiozak case CMPCI_SPDIF_IN_PHASE:
1391 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDIN_PHASE)) {
1392 1.7.2.3 nathanw if (sc->sc_gain[CMPCI_SPDIF_IN_PHASE][CMPCI_LR]
1393 1.7.2.3 nathanw == CMPCI_SPDIF_IN_PHASE_POSITIVE)
1394 1.7.2.1 nathanw cmpci_reg_clear_1(sc, CMPCI_REG_CHANNEL_FORMAT,
1395 1.7.2.1 nathanw CMPCI_REG_SPDIN_PHASE);
1396 1.7.2.3 nathanw else
1397 1.7.2.3 nathanw cmpci_reg_set_1(sc, CMPCI_REG_CHANNEL_FORMAT,
1398 1.7.2.3 nathanw CMPCI_REG_SPDIN_PHASE);
1399 1.7 tshiozak }
1400 1.1 augustss return;
1401 1.1 augustss default:
1402 1.1 augustss return;
1403 1.1 augustss }
1404 1.7.2.3 nathanw
1405 1.7.2.3 nathanw cmpci_mixerreg_write(sc, src,
1406 1.7.2.3 nathanw CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT]));
1407 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_L_TO_R(src),
1408 1.7.2.3 nathanw CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_RIGHT]));
1409 1.7 tshiozak }
1410 1.7 tshiozak
1411 1.7 tshiozak static void
1412 1.7 tshiozak cmpci_set_out_ports(sc)
1413 1.7 tshiozak struct cmpci_softc *sc;
1414 1.7 tshiozak {
1415 1.7.2.3 nathanw u_int8_t v;
1416 1.7.2.3 nathanw int enspdout = 0;
1417 1.7.2.3 nathanw
1418 1.7 tshiozak if (!CMPCI_ISCAP(sc, SPDLOOP))
1419 1.7 tshiozak return;
1420 1.7.2.3 nathanw
1421 1.7.2.3 nathanw /* SPDIF/out select */
1422 1.7.2.3 nathanw if (sc->sc_gain[CMPCI_SPDIF_LOOP][CMPCI_LR] == CMPCI_SPDIF_LOOP_OFF) {
1423 1.7.2.3 nathanw /* playback */
1424 1.7.2.3 nathanw cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
1425 1.7 tshiozak } else {
1426 1.7.2.3 nathanw /* monitor SPDIF/in */
1427 1.7.2.3 nathanw cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
1428 1.7.2.3 nathanw }
1429 1.7.2.3 nathanw
1430 1.7.2.3 nathanw /* SPDIF in select */
1431 1.7.2.3 nathanw v = sc->sc_gain[CMPCI_SPDIF_IN_SELECT][CMPCI_LR];
1432 1.7.2.3 nathanw if (v & CMPCI_SPDIFIN_SPDIFIN2)
1433 1.7.2.3 nathanw cmpci_reg_set_4(sc, CMPCI_REG_MISC, CMPCI_REG_2ND_SPDIFIN);
1434 1.7.2.3 nathanw else
1435 1.7.2.3 nathanw cmpci_reg_clear_4(sc, CMPCI_REG_MISC, CMPCI_REG_2ND_SPDIFIN);
1436 1.7.2.3 nathanw if (v & CMPCI_SPDIFIN_SPDIFOUT)
1437 1.7.2.3 nathanw cmpci_reg_set_4(sc, CMPCI_REG_MISC, CMPCI_REG_SPDFLOOPI);
1438 1.7.2.3 nathanw else
1439 1.7.2.3 nathanw cmpci_reg_clear_4(sc, CMPCI_REG_MISC, CMPCI_REG_SPDFLOOPI);
1440 1.7.2.3 nathanw
1441 1.7.2.3 nathanw /* playback to ... */
1442 1.7.2.3 nathanw if (CMPCI_ISCAP(sc, SPDOUT) &&
1443 1.7.2.3 nathanw sc->sc_gain[CMPCI_PLAYBACK_MODE][CMPCI_LR]
1444 1.7.2.3 nathanw == CMPCI_PLAYBACK_MODE_SPDIF &&
1445 1.7.2.3 nathanw (sc->sc_play.md_divide == CMPCI_REG_RATE_44100 ||
1446 1.7.2.3 nathanw (CMPCI_ISCAP(sc, SPDOUT_48K) &&
1447 1.7.2.3 nathanw sc->sc_play.md_divide==CMPCI_REG_RATE_48000))) {
1448 1.7.2.3 nathanw /* playback to SPDIF */
1449 1.7.2.3 nathanw cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF0_ENABLE);
1450 1.7.2.3 nathanw enspdout = 1;
1451 1.7.2.3 nathanw if (sc->sc_play.md_divide==CMPCI_REG_RATE_48000)
1452 1.7.2.3 nathanw cmpci_reg_set_4(sc, CMPCI_REG_MISC,
1453 1.7.2.3 nathanw CMPCI_REG_SPDIF_48K);
1454 1.7.2.3 nathanw else
1455 1.7.2.3 nathanw cmpci_reg_clear_4(sc, CMPCI_REG_MISC,
1456 1.7.2.3 nathanw CMPCI_REG_SPDIF_48K);
1457 1.7.2.3 nathanw } else {
1458 1.7.2.3 nathanw /* playback to DAC */
1459 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1,
1460 1.7.2.3 nathanw CMPCI_REG_SPDIF0_ENABLE);
1461 1.7.2.3 nathanw if (CMPCI_ISCAP(sc, SPDOUT_48K))
1462 1.7.2.3 nathanw cmpci_reg_clear_4(sc, CMPCI_REG_MISC,
1463 1.7.2.3 nathanw CMPCI_REG_SPDIF_48K);
1464 1.7.2.3 nathanw }
1465 1.7.2.3 nathanw
1466 1.7.2.3 nathanw /* legacy to SPDIF/out or not */
1467 1.7.2.3 nathanw if (CMPCI_ISCAP(sc, SPDLEGACY)) {
1468 1.7.2.3 nathanw if (sc->sc_gain[CMPCI_SPDIF_OUT_PLAYBACK][CMPCI_LR]
1469 1.7.2.3 nathanw == CMPCI_SPDIF_OUT_PLAYBACK_WAVE)
1470 1.7.2.3 nathanw cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL,
1471 1.7.2.3 nathanw CMPCI_REG_LEGACY_SPDIF_ENABLE);
1472 1.7.2.3 nathanw else {
1473 1.7.2.3 nathanw cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL,
1474 1.7.2.3 nathanw CMPCI_REG_LEGACY_SPDIF_ENABLE);
1475 1.7.2.3 nathanw enspdout = 1;
1476 1.7.2.3 nathanw }
1477 1.7.2.3 nathanw }
1478 1.7.2.3 nathanw
1479 1.7.2.3 nathanw /* enable/disable SPDIF/out */
1480 1.7.2.3 nathanw if (CMPCI_ISCAP(sc, XSPDOUT) && enspdout)
1481 1.7.2.3 nathanw cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL,
1482 1.7.2.3 nathanw CMPCI_REG_XSPDIF_ENABLE);
1483 1.7.2.3 nathanw else
1484 1.7.2.3 nathanw cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL,
1485 1.7.2.3 nathanw CMPCI_REG_XSPDIF_ENABLE);
1486 1.7.2.3 nathanw
1487 1.7.2.3 nathanw /* SPDIF monitor (digital to alalog output) */
1488 1.7.2.3 nathanw if (CMPCI_ISCAP(sc, SPDIN_MONITOR)) {
1489 1.7.2.3 nathanw v = sc->sc_gain[CMPCI_MONITOR_DAC][CMPCI_LR];
1490 1.7.2.3 nathanw if (!(v & CMPCI_MONDAC_ENABLE))
1491 1.7.2.3 nathanw cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1492 1.7.2.3 nathanw CMPCI_REG_SPDIN_MONITOR);
1493 1.7.2.3 nathanw if (v & CMPCI_MONDAC_SPDOUT)
1494 1.7 tshiozak cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1,
1495 1.7.2.3 nathanw CMPCI_REG_SPDIFOUT_DAC);
1496 1.7.2.3 nathanw else
1497 1.7 tshiozak cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1,
1498 1.7.2.3 nathanw CMPCI_REG_SPDIFOUT_DAC);
1499 1.7.2.3 nathanw if (v & CMPCI_MONDAC_ENABLE)
1500 1.7.2.3 nathanw cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1501 1.7.2.3 nathanw CMPCI_REG_SPDIN_MONITOR);
1502 1.7 tshiozak }
1503 1.1 augustss }
1504 1.1 augustss
1505 1.1 augustss static int
1506 1.7.2.3 nathanw cmpci_set_in_ports(sc)
1507 1.1 augustss struct cmpci_softc *sc;
1508 1.1 augustss {
1509 1.7.2.3 nathanw int mask;
1510 1.1 augustss int bitsl, bitsr;
1511 1.1 augustss
1512 1.7.2.3 nathanw mask = sc->sc_in_mask;
1513 1.7.2.3 nathanw
1514 1.7.2.3 nathanw /*
1515 1.7.2.3 nathanw * Note CMPCI_RECORD_SOURCE_CD, CMPCI_RECORD_SOURCE_LINE_IN and
1516 1.7.2.3 nathanw * CMPCI_RECORD_SOURCE_FM are defined to the corresponding bit
1517 1.7.2.3 nathanw * of the mixer register.
1518 1.7.2.3 nathanw */
1519 1.7.2.3 nathanw bitsr = mask & (CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |
1520 1.7.2.3 nathanw CMPCI_RECORD_SOURCE_FM);
1521 1.7.2.3 nathanw
1522 1.1 augustss bitsl = CMPCI_SB16_MIXER_SRC_R_TO_L(bitsr);
1523 1.7.2.1 nathanw if (mask & CMPCI_RECORD_SOURCE_MIC) {
1524 1.1 augustss bitsl |= CMPCI_SB16_MIXER_MIC_SRC;
1525 1.1 augustss bitsr |= CMPCI_SB16_MIXER_MIC_SRC;
1526 1.1 augustss }
1527 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, bitsl);
1528 1.1 augustss cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, bitsr);
1529 1.7.2.3 nathanw
1530 1.7.2.3 nathanw if (mask & CMPCI_RECORD_SOURCE_AUX_IN)
1531 1.7.2.3 nathanw cmpci_reg_set_1(sc, CMPCI_REG_MIXER25,
1532 1.7.2.3 nathanw CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN);
1533 1.7.2.3 nathanw else
1534 1.7.2.3 nathanw cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25,
1535 1.7.2.3 nathanw CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN);
1536 1.7.2.3 nathanw
1537 1.7.2.3 nathanw if (mask & CMPCI_RECORD_SOURCE_WAVE)
1538 1.7.2.3 nathanw cmpci_reg_set_1(sc, CMPCI_REG_MIXER24,
1539 1.7.2.3 nathanw CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR);
1540 1.7.2.3 nathanw else
1541 1.7.2.3 nathanw cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24,
1542 1.7.2.3 nathanw CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR);
1543 1.7.2.3 nathanw
1544 1.7 tshiozak if (CMPCI_ISCAP(sc, SPDIN) &&
1545 1.7.2.3 nathanw (sc->sc_rec.md_divide == CMPCI_REG_RATE_44100 ||
1546 1.7.2.3 nathanw (CMPCI_ISCAP(sc, SPDOUT_48K) &&
1547 1.7.2.3 nathanw sc->sc_rec.md_divide == CMPCI_REG_RATE_48000/* XXX? */))) {
1548 1.7.2.1 nathanw if (mask & CMPCI_RECORD_SOURCE_SPDIF) {
1549 1.7 tshiozak /* enable SPDIF/in */
1550 1.7 tshiozak cmpci_reg_set_4(sc,
1551 1.7 tshiozak CMPCI_REG_FUNC_1,
1552 1.7 tshiozak CMPCI_REG_SPDIF1_ENABLE);
1553 1.7 tshiozak } else {
1554 1.7 tshiozak cmpci_reg_clear_4(sc,
1555 1.7 tshiozak CMPCI_REG_FUNC_1,
1556 1.7 tshiozak CMPCI_REG_SPDIF1_ENABLE);
1557 1.7 tshiozak }
1558 1.7 tshiozak }
1559 1.1 augustss
1560 1.1 augustss return 0;
1561 1.1 augustss }
1562 1.1 augustss
1563 1.1 augustss static int
1564 1.1 augustss cmpci_set_port(handle, cp)
1565 1.1 augustss void *handle;
1566 1.1 augustss mixer_ctrl_t *cp;
1567 1.1 augustss {
1568 1.1 augustss struct cmpci_softc *sc = handle;
1569 1.1 augustss int lgain, rgain;
1570 1.7.2.3 nathanw
1571 1.1 augustss switch (cp->dev) {
1572 1.1 augustss case CMPCI_MIC_VOL:
1573 1.7.2.3 nathanw case CMPCI_PCSPEAKER:
1574 1.7.2.3 nathanw case CMPCI_MIC_RECVOL:
1575 1.7.2.3 nathanw if (cp->un.value.num_channels != 1)
1576 1.7.2.3 nathanw return EINVAL;
1577 1.7.2.3 nathanw /* FALLTHROUGH */
1578 1.7.2.3 nathanw case CMPCI_DAC_VOL:
1579 1.1 augustss case CMPCI_FM_VOL:
1580 1.1 augustss case CMPCI_CD_VOL:
1581 1.7.2.3 nathanw case CMPCI_LINE_IN_VOL:
1582 1.7.2.3 nathanw case CMPCI_AUX_IN_VOL:
1583 1.1 augustss case CMPCI_MASTER_VOL:
1584 1.1 augustss if (cp->type != AUDIO_MIXER_VALUE)
1585 1.1 augustss return EINVAL;
1586 1.7.2.3 nathanw switch (cp->un.value.num_channels) {
1587 1.7.2.3 nathanw case 1:
1588 1.1 augustss lgain = rgain =
1589 1.7.2.3 nathanw cp->un.value.level[AUDIO_MIXER_LEVEL_MONO];
1590 1.1 augustss break;
1591 1.7.2.3 nathanw case 2:
1592 1.7.2.3 nathanw lgain = cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT];
1593 1.7.2.3 nathanw rgain = cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT];
1594 1.1 augustss break;
1595 1.1 augustss default:
1596 1.7.2.3 nathanw return EINVAL;
1597 1.1 augustss }
1598 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT] = lgain;
1599 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_RIGHT] = rgain;
1600 1.1 augustss
1601 1.1 augustss cmpci_set_mixer_gain(sc, cp->dev);
1602 1.1 augustss break;
1603 1.1 augustss
1604 1.1 augustss case CMPCI_RECORD_SOURCE:
1605 1.1 augustss if (cp->type != AUDIO_MIXER_SET)
1606 1.1 augustss return EINVAL;
1607 1.7.2.1 nathanw
1608 1.7.2.3 nathanw if (cp->un.mask & ~(CMPCI_RECORD_SOURCE_MIC |
1609 1.7.2.3 nathanw CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |
1610 1.7.2.3 nathanw CMPCI_RECORD_SOURCE_AUX_IN | CMPCI_RECORD_SOURCE_WAVE |
1611 1.7.2.3 nathanw CMPCI_RECORD_SOURCE_FM | CMPCI_RECORD_SOURCE_SPDIF))
1612 1.7.2.3 nathanw return EINVAL;
1613 1.7.2.3 nathanw
1614 1.7.2.1 nathanw if (cp->un.mask & CMPCI_RECORD_SOURCE_SPDIF)
1615 1.7.2.1 nathanw cp->un.mask = CMPCI_RECORD_SOURCE_SPDIF;
1616 1.7.2.1 nathanw
1617 1.7.2.3 nathanw sc->sc_in_mask = cp->un.mask;
1618 1.7.2.3 nathanw return cmpci_set_in_ports(sc);
1619 1.1 augustss
1620 1.7.2.3 nathanw /* boolean */
1621 1.7.2.3 nathanw case CMPCI_DAC_MUTE:
1622 1.7.2.3 nathanw case CMPCI_FM_MUTE:
1623 1.7.2.3 nathanw case CMPCI_CD_MUTE:
1624 1.7.2.3 nathanw case CMPCI_LINE_IN_MUTE:
1625 1.7.2.3 nathanw case CMPCI_AUX_IN_MUTE:
1626 1.7.2.3 nathanw case CMPCI_MIC_MUTE:
1627 1.7.2.3 nathanw case CMPCI_MIC_PREAMP:
1628 1.7.2.3 nathanw case CMPCI_PLAYBACK_MODE:
1629 1.7.2.3 nathanw case CMPCI_SPDIF_IN_PHASE:
1630 1.7.2.3 nathanw case CMPCI_SPDIF_LOOP:
1631 1.7.2.3 nathanw case CMPCI_SPDIF_OUT_PLAYBACK:
1632 1.7.2.3 nathanw case CMPCI_SPDIF_OUT_VOLTAGE:
1633 1.7.2.3 nathanw case CMPCI_REAR:
1634 1.7.2.3 nathanw case CMPCI_INDIVIDUAL:
1635 1.7.2.3 nathanw case CMPCI_REVERSE:
1636 1.7.2.3 nathanw case CMPCI_SURROUND:
1637 1.1 augustss if (cp->type != AUDIO_MIXER_ENUM)
1638 1.1 augustss return EINVAL;
1639 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord != 0;
1640 1.7.2.3 nathanw cmpci_set_mixer_gain(sc, cp->dev);
1641 1.1 augustss break;
1642 1.1 augustss
1643 1.7.2.3 nathanw case CMPCI_SPDIF_IN_SELECT:
1644 1.7.2.3 nathanw switch (cp->un.ord) {
1645 1.7.2.3 nathanw case CMPCI_SPDIF_IN_SPDIN1:
1646 1.7.2.3 nathanw case CMPCI_SPDIF_IN_SPDIN2:
1647 1.7.2.3 nathanw case CMPCI_SPDIF_IN_SPDOUT:
1648 1.7.2.3 nathanw break;
1649 1.7.2.3 nathanw default:
1650 1.1 augustss return EINVAL;
1651 1.1 augustss }
1652 1.7.2.3 nathanw goto xenum;
1653 1.7.2.3 nathanw case CMPCI_MONITOR_DAC:
1654 1.7.2.3 nathanw switch (cp->un.ord) {
1655 1.7.2.3 nathanw case CMPCI_MONITOR_DAC_OFF:
1656 1.7.2.3 nathanw case CMPCI_MONITOR_DAC_SPDIN:
1657 1.7.2.3 nathanw case CMPCI_MONITOR_DAC_SPDOUT:
1658 1.7.2.3 nathanw break;
1659 1.7.2.3 nathanw default:
1660 1.7.2.3 nathanw return EINVAL;
1661 1.1 augustss }
1662 1.7.2.3 nathanw xenum:
1663 1.7.2.3 nathanw if (cp->type != AUDIO_MIXER_ENUM)
1664 1.7.2.3 nathanw return EINVAL;
1665 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord;
1666 1.7.2.3 nathanw cmpci_set_mixer_gain(sc, cp->dev);
1667 1.7 tshiozak break;
1668 1.7.2.3 nathanw
1669 1.1 augustss default:
1670 1.1 augustss return EINVAL;
1671 1.1 augustss }
1672 1.7.2.3 nathanw
1673 1.1 augustss return 0;
1674 1.1 augustss }
1675 1.1 augustss
1676 1.1 augustss static int
1677 1.1 augustss cmpci_get_port(handle, cp)
1678 1.1 augustss void *handle;
1679 1.1 augustss mixer_ctrl_t *cp;
1680 1.1 augustss {
1681 1.1 augustss struct cmpci_softc *sc = handle;
1682 1.7.2.3 nathanw
1683 1.1 augustss switch (cp->dev) {
1684 1.1 augustss case CMPCI_MIC_VOL:
1685 1.7.2.3 nathanw case CMPCI_PCSPEAKER:
1686 1.7.2.3 nathanw case CMPCI_MIC_RECVOL:
1687 1.1 augustss if (cp->un.value.num_channels != 1)
1688 1.1 augustss return EINVAL;
1689 1.7.2.4 nathanw /*FALLTHROUGH*/
1690 1.7.2.3 nathanw case CMPCI_DAC_VOL:
1691 1.1 augustss case CMPCI_FM_VOL:
1692 1.1 augustss case CMPCI_CD_VOL:
1693 1.7.2.3 nathanw case CMPCI_LINE_IN_VOL:
1694 1.7.2.3 nathanw case CMPCI_AUX_IN_VOL:
1695 1.1 augustss case CMPCI_MASTER_VOL:
1696 1.1 augustss switch (cp->un.value.num_channels) {
1697 1.1 augustss case 1:
1698 1.7.2.3 nathanw cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
1699 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT];
1700 1.1 augustss break;
1701 1.1 augustss case 2:
1702 1.7.2.3 nathanw cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
1703 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_LEFT];
1704 1.7.2.3 nathanw cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
1705 1.7 tshiozak sc->sc_gain[cp->dev][CMPCI_RIGHT];
1706 1.1 augustss break;
1707 1.1 augustss default:
1708 1.1 augustss return EINVAL;
1709 1.1 augustss }
1710 1.1 augustss break;
1711 1.7.2.3 nathanw
1712 1.1 augustss case CMPCI_RECORD_SOURCE:
1713 1.7 tshiozak cp->un.mask = sc->sc_in_mask;
1714 1.1 augustss break;
1715 1.1 augustss
1716 1.7.2.3 nathanw case CMPCI_DAC_MUTE:
1717 1.7.2.3 nathanw case CMPCI_FM_MUTE:
1718 1.7.2.3 nathanw case CMPCI_CD_MUTE:
1719 1.1 augustss case CMPCI_LINE_IN_MUTE:
1720 1.7.2.3 nathanw case CMPCI_AUX_IN_MUTE:
1721 1.7.2.3 nathanw case CMPCI_MIC_MUTE:
1722 1.7.2.3 nathanw case CMPCI_MIC_PREAMP:
1723 1.7.2.3 nathanw case CMPCI_PLAYBACK_MODE:
1724 1.7.2.3 nathanw case CMPCI_SPDIF_IN_SELECT:
1725 1.7.2.3 nathanw case CMPCI_SPDIF_IN_PHASE:
1726 1.7 tshiozak case CMPCI_SPDIF_LOOP:
1727 1.7.2.3 nathanw case CMPCI_SPDIF_OUT_PLAYBACK:
1728 1.7 tshiozak case CMPCI_SPDIF_OUT_VOLTAGE:
1729 1.7.2.3 nathanw case CMPCI_MONITOR_DAC:
1730 1.7 tshiozak case CMPCI_REAR:
1731 1.7 tshiozak case CMPCI_INDIVIDUAL:
1732 1.7 tshiozak case CMPCI_REVERSE:
1733 1.7 tshiozak case CMPCI_SURROUND:
1734 1.7 tshiozak cp->un.ord = sc->sc_gain[cp->dev][CMPCI_LR];
1735 1.1 augustss break;
1736 1.1 augustss
1737 1.1 augustss default:
1738 1.1 augustss return EINVAL;
1739 1.1 augustss }
1740 1.1 augustss
1741 1.1 augustss return 0;
1742 1.1 augustss }
1743 1.1 augustss
1744 1.1 augustss /* ARGSUSED */
1745 1.1 augustss static size_t
1746 1.1 augustss cmpci_round_buffersize(handle, direction, bufsize)
1747 1.1 augustss void *handle;
1748 1.1 augustss int direction;
1749 1.1 augustss size_t bufsize;
1750 1.1 augustss {
1751 1.1 augustss if (bufsize > 0x10000)
1752 1.1 augustss bufsize = 0x10000;
1753 1.7.2.3 nathanw
1754 1.1 augustss return bufsize;
1755 1.1 augustss }
1756 1.1 augustss
1757 1.1 augustss
1758 1.4 simonb static paddr_t
1759 1.1 augustss cmpci_mappage(handle, addr, offset, prot)
1760 1.1 augustss void *handle;
1761 1.1 augustss void *addr;
1762 1.4 simonb off_t offset;
1763 1.4 simonb int prot;
1764 1.1 augustss {
1765 1.1 augustss struct cmpci_softc *sc = handle;
1766 1.1 augustss struct cmpci_dmanode *p;
1767 1.7.2.3 nathanw
1768 1.1 augustss if (offset < 0 || NULL == (p = cmpci_find_dmamem(sc, addr)))
1769 1.1 augustss return -1;
1770 1.1 augustss
1771 1.1 augustss return bus_dmamem_mmap(p->cd_tag, p->cd_segs,
1772 1.7 tshiozak sizeof(p->cd_segs)/sizeof(p->cd_segs[0]),
1773 1.7 tshiozak offset, prot, BUS_DMA_WAITOK);
1774 1.1 augustss }
1775 1.1 augustss
1776 1.1 augustss
1777 1.1 augustss /* ARGSUSED */
1778 1.1 augustss static int
1779 1.1 augustss cmpci_get_props(handle)
1780 1.1 augustss void *handle;
1781 1.1 augustss {
1782 1.1 augustss return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
1783 1.1 augustss }
1784 1.1 augustss
1785 1.1 augustss
1786 1.1 augustss static int
1787 1.1 augustss cmpci_trigger_output(handle, start, end, blksize, intr, arg, param)
1788 1.7 tshiozak void *handle;
1789 1.7 tshiozak void *start, *end;
1790 1.7 tshiozak int blksize;
1791 1.7 tshiozak void (*intr) __P((void *));
1792 1.7 tshiozak void *arg;
1793 1.7 tshiozak struct audio_params *param;
1794 1.1 augustss {
1795 1.1 augustss struct cmpci_softc *sc = handle;
1796 1.1 augustss struct cmpci_dmanode *p;
1797 1.1 augustss int bps;
1798 1.1 augustss
1799 1.1 augustss sc->sc_play.intr = intr;
1800 1.1 augustss sc->sc_play.intr_arg = arg;
1801 1.1 augustss bps = param->channels*param->precision*param->factor / 8;
1802 1.1 augustss if (!bps)
1803 1.1 augustss return EINVAL;
1804 1.1 augustss
1805 1.1 augustss /* set DMA frame */
1806 1.1 augustss if (!(p = cmpci_find_dmamem(sc, start)))
1807 1.1 augustss return EINVAL;
1808 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BASE,
1809 1.1 augustss DMAADDR(p));
1810 1.1 augustss delay(10);
1811 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BYTES,
1812 1.7 tshiozak ((caddr_t)end - (caddr_t)start + 1) / bps - 1);
1813 1.1 augustss delay(10);
1814 1.1 augustss
1815 1.1 augustss /* set interrupt count */
1816 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_SAMPLES,
1817 1.1 augustss (blksize + bps - 1) / bps - 1);
1818 1.1 augustss delay(10);
1819 1.1 augustss
1820 1.1 augustss /* start DMA */
1821 1.1 augustss cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); /* PLAY */
1822 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
1823 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
1824 1.7.2.3 nathanw
1825 1.1 augustss return 0;
1826 1.1 augustss }
1827 1.1 augustss
1828 1.1 augustss static int
1829 1.1 augustss cmpci_trigger_input(handle, start, end, blksize, intr, arg, param)
1830 1.7 tshiozak void *handle;
1831 1.7 tshiozak void *start, *end;
1832 1.7 tshiozak int blksize;
1833 1.7 tshiozak void (*intr) __P((void *));
1834 1.7 tshiozak void *arg;
1835 1.7 tshiozak struct audio_params *param;
1836 1.1 augustss {
1837 1.1 augustss struct cmpci_softc *sc = handle;
1838 1.1 augustss struct cmpci_dmanode *p;
1839 1.1 augustss int bps;
1840 1.1 augustss
1841 1.1 augustss sc->sc_rec.intr = intr;
1842 1.1 augustss sc->sc_rec.intr_arg = arg;
1843 1.1 augustss bps = param->channels*param->precision*param->factor/8;
1844 1.1 augustss if (!bps)
1845 1.1 augustss return EINVAL;
1846 1.1 augustss
1847 1.1 augustss /* set DMA frame */
1848 1.1 augustss if (!(p=cmpci_find_dmamem(sc, start)))
1849 1.1 augustss return EINVAL;
1850 1.1 augustss bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BASE,
1851 1.1 augustss DMAADDR(p));
1852 1.1 augustss delay(10);
1853 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BYTES,
1854 1.7 tshiozak ((caddr_t)end - (caddr_t)start + 1) / bps - 1);
1855 1.1 augustss delay(10);
1856 1.1 augustss
1857 1.1 augustss /* set interrupt count */
1858 1.1 augustss bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_SAMPLES,
1859 1.7 tshiozak (blksize + bps - 1) / bps - 1);
1860 1.1 augustss delay(10);
1861 1.1 augustss
1862 1.1 augustss /* start DMA */
1863 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); /* REC */
1864 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
1865 1.1 augustss cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
1866 1.7.2.3 nathanw
1867 1.1 augustss return 0;
1868 1.1 augustss }
1869 1.1 augustss
1870 1.1 augustss
1871 1.1 augustss /* end of file */
1872