cmpci.c revision 1.57
1 /* $NetBSD: cmpci.c,v 1.57 2020/02/29 05:51:11 isaki Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2001, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Takuya SHIOZAKI <tshiozak (at) NetBSD.org> . 9 * 10 * This code is derived from software contributed to The NetBSD Foundation 11 * by ITOH Yasufumi. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 /* 37 * C-Media CMI8x38 Audio Chip Support. 38 * 39 * TODO: 40 * - 4ch / 6ch support. 41 * - Joystick support. 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cmpci.c,v 1.57 2020/02/29 05:51:11 isaki Exp $"); 47 48 #if defined(AUDIO_DEBUG) || defined(DEBUG) 49 #define DPRINTF(x) if (cmpcidebug) printf x 50 int cmpcidebug = 0; 51 #else 52 #define DPRINTF(x) 53 #endif 54 55 #include "mpu.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/kernel.h> 60 #include <sys/kmem.h> 61 #include <sys/device.h> 62 #include <sys/proc.h> 63 64 #include <dev/pci/pcidevs.h> 65 #include <dev/pci/pcivar.h> 66 67 #include <sys/audioio.h> 68 #include <dev/audio/audio_if.h> 69 #include <dev/midi_if.h> 70 71 #include <dev/pci/cmpcireg.h> 72 #include <dev/pci/cmpcivar.h> 73 74 #include <dev/ic/mpuvar.h> 75 #include <sys/bus.h> 76 #include <sys/intr.h> 77 78 /* 79 * Low-level HW interface 80 */ 81 static inline uint8_t cmpci_mixerreg_read(struct cmpci_softc *, uint8_t); 82 static inline void cmpci_mixerreg_write(struct cmpci_softc *, 83 uint8_t, uint8_t); 84 static inline void cmpci_reg_partial_write_1(struct cmpci_softc *, int, int, 85 unsigned, unsigned); 86 static inline void cmpci_reg_partial_write_4(struct cmpci_softc *, int, int, 87 uint32_t, uint32_t); 88 static inline void cmpci_reg_set_1(struct cmpci_softc *, int, uint8_t); 89 static inline void cmpci_reg_clear_1(struct cmpci_softc *, int, uint8_t); 90 static inline void cmpci_reg_set_4(struct cmpci_softc *, int, uint32_t); 91 static inline void cmpci_reg_clear_4(struct cmpci_softc *, int, uint32_t); 92 static inline void cmpci_reg_set_reg_misc(struct cmpci_softc *, uint32_t); 93 static inline void cmpci_reg_clear_reg_misc(struct cmpci_softc *, uint32_t); 94 static int cmpci_rate_to_index(int); 95 static inline int cmpci_index_to_divider(int); 96 97 static int cmpci_adjust(int, int); 98 static void cmpci_set_mixer_gain(struct cmpci_softc *, int); 99 static void cmpci_set_out_ports(struct cmpci_softc *); 100 static int cmpci_set_in_ports(struct cmpci_softc *); 101 102 103 /* 104 * autoconf interface 105 */ 106 static int cmpci_match(device_t, cfdata_t, void *); 107 static void cmpci_attach(device_t, device_t, void *); 108 109 CFATTACH_DECL_NEW(cmpci, sizeof (struct cmpci_softc), 110 cmpci_match, cmpci_attach, NULL, NULL); 111 112 /* interrupt */ 113 static int cmpci_intr(void *); 114 115 116 /* 117 * DMA stuffs 118 */ 119 static int cmpci_alloc_dmamem(struct cmpci_softc *, size_t, void **); 120 static int cmpci_free_dmamem(struct cmpci_softc *, void *, size_t); 121 static struct cmpci_dmanode * cmpci_find_dmamem(struct cmpci_softc *, 122 void *); 123 124 125 /* 126 * interface to machine independent layer 127 */ 128 static int cmpci_query_format(void *, audio_format_query_t *); 129 static int cmpci_set_format(void *, int, 130 const audio_params_t *, const audio_params_t *, 131 audio_filter_reg_t *, audio_filter_reg_t *); 132 static int cmpci_halt_output(void *); 133 static int cmpci_halt_input(void *); 134 static int cmpci_getdev(void *, struct audio_device *); 135 static int cmpci_set_port(void *, mixer_ctrl_t *); 136 static int cmpci_get_port(void *, mixer_ctrl_t *); 137 static int cmpci_query_devinfo(void *, mixer_devinfo_t *); 138 static void *cmpci_allocm(void *, int, size_t); 139 static void cmpci_freem(void *, void *, size_t); 140 static size_t cmpci_round_buffersize(void *, int, size_t); 141 static int cmpci_get_props(void *); 142 static int cmpci_trigger_output(void *, void *, void *, int, 143 void (*)(void *), void *, const audio_params_t *); 144 static int cmpci_trigger_input(void *, void *, void *, int, 145 void (*)(void *), void *, const audio_params_t *); 146 static void cmpci_get_locks(void *, kmutex_t **, kmutex_t **); 147 148 static const struct audio_hw_if cmpci_hw_if = { 149 .query_format = cmpci_query_format, 150 .set_format = cmpci_set_format, 151 .halt_output = cmpci_halt_output, 152 .halt_input = cmpci_halt_input, 153 .getdev = cmpci_getdev, 154 .set_port = cmpci_set_port, 155 .get_port = cmpci_get_port, 156 .query_devinfo = cmpci_query_devinfo, 157 .allocm = cmpci_allocm, 158 .freem = cmpci_freem, 159 .round_buffersize = cmpci_round_buffersize, 160 .get_props = cmpci_get_props, 161 .trigger_output = cmpci_trigger_output, 162 .trigger_input = cmpci_trigger_input, 163 .get_locks = cmpci_get_locks, 164 }; 165 166 static const struct audio_format cmpci_formats[] = { 167 { 168 .mode = AUMODE_PLAY | AUMODE_RECORD, 169 .encoding = AUDIO_ENCODING_SLINEAR_LE, 170 .validbits = 16, 171 .precision = 16, 172 .channels = 2, 173 .channel_mask = AUFMT_STEREO, 174 .frequency_type = 8, 175 .frequency = 176 { 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000 }, 177 }, 178 }; 179 #define CMPCI_NFORMATS __arraycount(cmpci_formats) 180 181 182 /* 183 * Low-level HW interface 184 */ 185 186 /* mixer register read/write */ 187 static inline uint8_t 188 cmpci_mixerreg_read(struct cmpci_softc *sc, uint8_t no) 189 { 190 uint8_t ret; 191 192 bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no); 193 delay(10); 194 ret = bus_space_read_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA); 195 delay(10); 196 return ret; 197 } 198 199 static inline void 200 cmpci_mixerreg_write(struct cmpci_softc *sc, uint8_t no, uint8_t val) 201 { 202 203 bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no); 204 delay(10); 205 bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA, val); 206 delay(10); 207 } 208 209 210 /* register partial write */ 211 static inline void 212 cmpci_reg_partial_write_1(struct cmpci_softc *sc, int no, int shift, 213 unsigned mask, unsigned val) 214 { 215 216 bus_space_write_1(sc->sc_iot, sc->sc_ioh, no, 217 (val<<shift) | 218 (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift))); 219 delay(10); 220 } 221 222 static inline void 223 cmpci_reg_partial_write_4(struct cmpci_softc *sc, int no, int shift, 224 uint32_t mask, uint32_t val) 225 { 226 227 bus_space_write_4(sc->sc_iot, sc->sc_ioh, no, 228 (val<<shift) | 229 (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift))); 230 delay(10); 231 } 232 233 /* register set/clear bit */ 234 static inline void 235 cmpci_reg_set_1(struct cmpci_softc *sc, int no, uint8_t mask) 236 { 237 238 bus_space_write_1(sc->sc_iot, sc->sc_ioh, no, 239 (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) | mask)); 240 delay(10); 241 } 242 243 static inline void 244 cmpci_reg_clear_1(struct cmpci_softc *sc, int no, uint8_t mask) 245 { 246 247 bus_space_write_1(sc->sc_iot, sc->sc_ioh, no, 248 (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~mask)); 249 delay(10); 250 } 251 252 static inline void 253 cmpci_reg_set_4(struct cmpci_softc *sc, int no, uint32_t mask) 254 { 255 256 /* use cmpci_reg_set_reg_misc() for CMPCI_REG_MISC */ 257 KDASSERT(no != CMPCI_REG_MISC); 258 259 bus_space_write_4(sc->sc_iot, sc->sc_ioh, no, 260 (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) | mask)); 261 delay(10); 262 } 263 264 static inline void 265 cmpci_reg_clear_4(struct cmpci_softc *sc, int no, uint32_t mask) 266 { 267 268 /* use cmpci_reg_clear_reg_misc() for CMPCI_REG_MISC */ 269 KDASSERT(no != CMPCI_REG_MISC); 270 271 bus_space_write_4(sc->sc_iot, sc->sc_ioh, no, 272 (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~mask)); 273 delay(10); 274 } 275 276 /* 277 * The CMPCI_REG_MISC register needs special handling, since one of 278 * its bits has different read/write values. 279 */ 280 static inline void 281 cmpci_reg_set_reg_misc(struct cmpci_softc *sc, uint32_t mask) 282 { 283 284 sc->sc_reg_misc |= mask; 285 bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MISC, 286 sc->sc_reg_misc); 287 delay(10); 288 } 289 290 static inline void 291 cmpci_reg_clear_reg_misc(struct cmpci_softc *sc, uint32_t mask) 292 { 293 294 sc->sc_reg_misc &= ~mask; 295 bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MISC, 296 sc->sc_reg_misc); 297 delay(10); 298 } 299 300 /* rate */ 301 static const struct { 302 int rate; 303 int divider; 304 } cmpci_rate_table[CMPCI_REG_NUMRATE] = { 305 #define _RATE(n) { n, CMPCI_REG_RATE_ ## n } 306 _RATE(5512), 307 _RATE(8000), 308 _RATE(11025), 309 _RATE(16000), 310 _RATE(22050), 311 _RATE(32000), 312 _RATE(44100), 313 _RATE(48000) 314 #undef _RATE 315 }; 316 317 static int 318 cmpci_rate_to_index(int rate) 319 { 320 int i; 321 322 for (i = 0; i < CMPCI_REG_NUMRATE - 1; i++) 323 if (rate == cmpci_rate_table[i].rate) 324 return i; 325 return i; /* 48000 */ 326 } 327 328 static inline int 329 cmpci_index_to_divider(int index) 330 { 331 332 return cmpci_rate_table[index].divider; 333 } 334 335 /* 336 * interface to configure the device. 337 */ 338 static int 339 cmpci_match(device_t parent, cfdata_t match, void *aux) 340 { 341 struct pci_attach_args *pa; 342 343 pa = (struct pci_attach_args *)aux; 344 if ( PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMEDIA && 345 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338A || 346 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338B || 347 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738 || 348 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738B) ) 349 return 1; 350 351 return 0; 352 } 353 354 static void 355 cmpci_attach(device_t parent, device_t self, void *aux) 356 { 357 struct cmpci_softc *sc; 358 struct pci_attach_args *pa; 359 struct audio_attach_args aa; 360 pci_intr_handle_t ih; 361 char const *strintr; 362 int i, v; 363 char intrbuf[PCI_INTRSTR_LEN]; 364 365 sc = device_private(self); 366 sc->sc_dev = self; 367 pa = (struct pci_attach_args *)aux; 368 369 sc->sc_id = pa->pa_id; 370 sc->sc_class = pa->pa_class; 371 pci_aprint_devinfo(pa, "Audio controller"); 372 switch (PCI_PRODUCT(sc->sc_id)) { 373 case PCI_PRODUCT_CMEDIA_CMI8338A: 374 /*FALLTHROUGH*/ 375 case PCI_PRODUCT_CMEDIA_CMI8338B: 376 sc->sc_capable = CMPCI_CAP_CMI8338; 377 break; 378 case PCI_PRODUCT_CMEDIA_CMI8738: 379 /*FALLTHROUGH*/ 380 case PCI_PRODUCT_CMEDIA_CMI8738B: 381 sc->sc_capable = CMPCI_CAP_CMI8738; 382 break; 383 } 384 385 /* map I/O space */ 386 if (pci_mapreg_map(pa, CMPCI_PCI_IOBASEREG, PCI_MAPREG_TYPE_IO, 0, 387 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 388 aprint_error_dev(sc->sc_dev, "failed to map I/O space\n"); 389 return; 390 } 391 392 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 393 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 394 395 /* interrupt */ 396 if (pci_intr_map(pa, &ih)) { 397 aprint_error_dev(sc->sc_dev, "failed to map interrupt\n"); 398 return; 399 } 400 strintr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 401 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_AUDIO, 402 cmpci_intr, sc, device_xname(self)); 403 if (sc->sc_ih == NULL) { 404 aprint_error_dev(sc->sc_dev, "failed to establish interrupt"); 405 if (strintr != NULL) 406 aprint_error(" at %s", strintr); 407 aprint_error("\n"); 408 mutex_destroy(&sc->sc_lock); 409 mutex_destroy(&sc->sc_intr_lock); 410 return; 411 } 412 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", strintr); 413 414 sc->sc_dmat = pa->pa_dmat; 415 416 audio_attach_mi(&cmpci_hw_if, sc, sc->sc_dev); 417 418 /* attach OPL device */ 419 aa.type = AUDIODEV_TYPE_OPL; 420 aa.hwif = NULL; 421 aa.hdl = NULL; 422 (void)config_found(sc->sc_dev, &aa, audioprint); 423 424 /* attach MPU-401 device */ 425 aa.type = AUDIODEV_TYPE_MPU; 426 aa.hwif = NULL; 427 aa.hdl = NULL; 428 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 429 CMPCI_REG_MPU_BASE, CMPCI_REG_MPU_SIZE, &sc->sc_mpu_ioh) == 0) 430 sc->sc_mpudev = config_found(sc->sc_dev, &aa, audioprint); 431 432 /* get initial value (this is 0 and may be omitted but just in case) */ 433 sc->sc_reg_misc = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 434 CMPCI_REG_MISC) & ~CMPCI_REG_SPDIF48K; 435 436 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_RESET, 0); 437 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 438 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 439 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX, 440 CMPCI_SB16_SW_CD|CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 441 for (i = 0; i < CMPCI_NDEVS; i++) { 442 switch (i) { 443 /* 444 * CMI8738 defaults are 445 * master: 0xe0 (0x00 - 0xf8) 446 * FM, DAC: 0xc0 (0x00 - 0xf8) 447 * PC speaker: 0x80 (0x00 - 0xc0) 448 * others: 0 449 */ 450 /* volume */ 451 case CMPCI_MASTER_VOL: 452 v = 128; /* 224 */ 453 break; 454 case CMPCI_FM_VOL: 455 case CMPCI_DAC_VOL: 456 v = 192; 457 break; 458 case CMPCI_PCSPEAKER: 459 v = 128; 460 break; 461 462 /* booleans, set to true */ 463 case CMPCI_CD_MUTE: 464 case CMPCI_MIC_MUTE: 465 case CMPCI_LINE_IN_MUTE: 466 case CMPCI_AUX_IN_MUTE: 467 v = 1; 468 break; 469 470 /* volume with inital value 0 */ 471 case CMPCI_CD_VOL: 472 case CMPCI_LINE_IN_VOL: 473 case CMPCI_AUX_IN_VOL: 474 case CMPCI_MIC_VOL: 475 case CMPCI_MIC_RECVOL: 476 /* FALLTHROUGH */ 477 478 /* others are cleared */ 479 case CMPCI_MIC_PREAMP: 480 case CMPCI_RECORD_SOURCE: 481 case CMPCI_PLAYBACK_MODE: 482 case CMPCI_SPDIF_IN_SELECT: 483 case CMPCI_SPDIF_IN_PHASE: 484 case CMPCI_SPDIF_LOOP: 485 case CMPCI_SPDIF_OUT_PLAYBACK: 486 case CMPCI_SPDIF_OUT_VOLTAGE: 487 case CMPCI_MONITOR_DAC: 488 case CMPCI_REAR: 489 case CMPCI_INDIVIDUAL: 490 case CMPCI_REVERSE: 491 case CMPCI_SURROUND: 492 default: 493 v = 0; 494 break; 495 } 496 sc->sc_gain[i][CMPCI_LEFT] = sc->sc_gain[i][CMPCI_RIGHT] = v; 497 cmpci_set_mixer_gain(sc, i); 498 } 499 } 500 501 static int 502 cmpci_intr(void *handle) 503 { 504 struct cmpci_softc *sc = handle; 505 #if NMPU > 0 506 struct mpu_softc *sc_mpu = device_private(sc->sc_mpudev); 507 #endif 508 uint32_t intrstat; 509 510 mutex_spin_enter(&sc->sc_intr_lock); 511 512 intrstat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 513 CMPCI_REG_INTR_STATUS); 514 515 if (!(intrstat & CMPCI_REG_ANY_INTR)) { 516 mutex_spin_exit(&sc->sc_intr_lock); 517 return 0; 518 } 519 520 delay(10); 521 522 /* disable and reset intr */ 523 if (intrstat & CMPCI_REG_CH0_INTR) 524 cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, 525 CMPCI_REG_CH0_INTR_ENABLE); 526 if (intrstat & CMPCI_REG_CH1_INTR) 527 cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, 528 CMPCI_REG_CH1_INTR_ENABLE); 529 530 if (intrstat & CMPCI_REG_CH0_INTR) { 531 if (sc->sc_play.intr != NULL) 532 (*sc->sc_play.intr)(sc->sc_play.intr_arg); 533 } 534 if (intrstat & CMPCI_REG_CH1_INTR) { 535 if (sc->sc_rec.intr != NULL) 536 (*sc->sc_rec.intr)(sc->sc_rec.intr_arg); 537 } 538 539 /* enable intr */ 540 if (intrstat & CMPCI_REG_CH0_INTR) 541 cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, 542 CMPCI_REG_CH0_INTR_ENABLE); 543 if (intrstat & CMPCI_REG_CH1_INTR) 544 cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, 545 CMPCI_REG_CH1_INTR_ENABLE); 546 547 #if NMPU > 0 548 if (intrstat & CMPCI_REG_UART_INTR && sc_mpu != NULL) 549 mpu_intr(sc_mpu); 550 #endif 551 552 mutex_spin_exit(&sc->sc_intr_lock); 553 return 1; 554 } 555 556 static int 557 cmpci_query_format(void *handle, audio_format_query_t *afp) 558 { 559 560 return audio_query_format(cmpci_formats, CMPCI_NFORMATS, afp); 561 } 562 563 static int 564 cmpci_set_format(void *handle, int setmode, 565 const audio_params_t *play, const audio_params_t *rec, 566 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 567 { 568 int i; 569 struct cmpci_softc *sc; 570 571 sc = handle; 572 for (i = 0; i < 2; i++) { 573 int md_format; 574 int md_divide; 575 int md_index; 576 int mode; 577 const audio_params_t *p; 578 579 switch (i) { 580 case 0: 581 mode = AUMODE_PLAY; 582 p = play; 583 break; 584 case 1: 585 mode = AUMODE_RECORD; 586 p = rec; 587 break; 588 default: 589 return EINVAL; 590 } 591 592 if (!(setmode & mode)) 593 continue; 594 595 md_index = cmpci_rate_to_index(p->sample_rate); 596 md_divide = cmpci_index_to_divider(md_index); 597 DPRINTF(("%s: sample:%u, divider=%d\n", 598 device_xname(sc->sc_dev), p->sample_rate, md_divide)); 599 600 /* format */ 601 md_format = p->channels == 1 602 ? CMPCI_REG_FORMAT_MONO : CMPCI_REG_FORMAT_STEREO; 603 md_format |= p->precision == 16 604 ? CMPCI_REG_FORMAT_16BIT : CMPCI_REG_FORMAT_8BIT; 605 if (mode & AUMODE_PLAY) { 606 cmpci_reg_partial_write_4(sc, 607 CMPCI_REG_CHANNEL_FORMAT, 608 CMPCI_REG_CH0_FORMAT_SHIFT, 609 CMPCI_REG_CH0_FORMAT_MASK, md_format); 610 cmpci_reg_partial_write_4(sc, 611 CMPCI_REG_FUNC_1, CMPCI_REG_DAC_FS_SHIFT, 612 CMPCI_REG_DAC_FS_MASK, md_divide); 613 sc->sc_play.md_divide = md_divide; 614 } else { 615 cmpci_reg_partial_write_4(sc, 616 CMPCI_REG_CHANNEL_FORMAT, 617 CMPCI_REG_CH1_FORMAT_SHIFT, 618 CMPCI_REG_CH1_FORMAT_MASK, md_format); 619 cmpci_reg_partial_write_4(sc, 620 CMPCI_REG_FUNC_1, CMPCI_REG_ADC_FS_SHIFT, 621 CMPCI_REG_ADC_FS_MASK, md_divide); 622 sc->sc_rec.md_divide = md_divide; 623 } 624 cmpci_set_out_ports(sc); 625 cmpci_set_in_ports(sc); 626 } 627 return 0; 628 } 629 630 static int 631 cmpci_halt_output(void *handle) 632 { 633 struct cmpci_softc *sc; 634 635 sc = handle; 636 sc->sc_play.intr = NULL; 637 cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 638 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 639 /* wait for reset DMA */ 640 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 641 delay(10); 642 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 643 644 return 0; 645 } 646 647 static int 648 cmpci_halt_input(void *handle) 649 { 650 struct cmpci_softc *sc; 651 652 sc = handle; 653 sc->sc_rec.intr = NULL; 654 cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 655 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 656 /* wait for reset DMA */ 657 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 658 delay(10); 659 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 660 661 return 0; 662 } 663 664 /* get audio device information */ 665 static int 666 cmpci_getdev(void *handle, struct audio_device *ad) 667 { 668 struct cmpci_softc *sc; 669 670 sc = handle; 671 strncpy(ad->name, "CMI PCI Audio", sizeof(ad->name)); 672 snprintf(ad->version, sizeof(ad->version), "0x%02x", 673 PCI_REVISION(sc->sc_class)); 674 switch (PCI_PRODUCT(sc->sc_id)) { 675 case PCI_PRODUCT_CMEDIA_CMI8338A: 676 strncpy(ad->config, "CMI8338A", sizeof(ad->config)); 677 break; 678 case PCI_PRODUCT_CMEDIA_CMI8338B: 679 strncpy(ad->config, "CMI8338B", sizeof(ad->config)); 680 break; 681 case PCI_PRODUCT_CMEDIA_CMI8738: 682 strncpy(ad->config, "CMI8738", sizeof(ad->config)); 683 break; 684 case PCI_PRODUCT_CMEDIA_CMI8738B: 685 strncpy(ad->config, "CMI8738B", sizeof(ad->config)); 686 break; 687 default: 688 strncpy(ad->config, "unknown", sizeof(ad->config)); 689 } 690 691 return 0; 692 } 693 694 /* mixer device information */ 695 int 696 cmpci_query_devinfo(void *handle, mixer_devinfo_t *dip) 697 { 698 static const char *const mixer_port_names[] = { 699 AudioNdac, AudioNfmsynth, AudioNcd, AudioNline, AudioNaux, 700 AudioNmicrophone 701 }; 702 static const char *const mixer_classes[] = { 703 AudioCinputs, AudioCoutputs, AudioCrecord, CmpciCplayback, 704 CmpciCspdif 705 }; 706 struct cmpci_softc *sc; 707 int i; 708 709 sc = handle; 710 dip->prev = dip->next = AUDIO_MIXER_LAST; 711 712 switch (dip->index) { 713 case CMPCI_INPUT_CLASS: 714 case CMPCI_OUTPUT_CLASS: 715 case CMPCI_RECORD_CLASS: 716 case CMPCI_PLAYBACK_CLASS: 717 case CMPCI_SPDIF_CLASS: 718 dip->type = AUDIO_MIXER_CLASS; 719 dip->mixer_class = dip->index; 720 strcpy(dip->label.name, 721 mixer_classes[dip->index - CMPCI_INPUT_CLASS]); 722 return 0; 723 724 case CMPCI_AUX_IN_VOL: 725 dip->un.v.delta = 1 << (8 - CMPCI_REG_AUX_VALBITS); 726 goto vol1; 727 case CMPCI_DAC_VOL: 728 case CMPCI_FM_VOL: 729 case CMPCI_CD_VOL: 730 case CMPCI_LINE_IN_VOL: 731 case CMPCI_MIC_VOL: 732 dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS); 733 vol1: dip->mixer_class = CMPCI_INPUT_CLASS; 734 dip->next = dip->index + 6; /* CMPCI_xxx_MUTE */ 735 strcpy(dip->label.name, mixer_port_names[dip->index]); 736 dip->un.v.num_channels = (dip->index == CMPCI_MIC_VOL ? 1 : 2); 737 vol: 738 dip->type = AUDIO_MIXER_VALUE; 739 strcpy(dip->un.v.units.name, AudioNvolume); 740 return 0; 741 742 case CMPCI_MIC_MUTE: 743 dip->next = CMPCI_MIC_PREAMP; 744 /* FALLTHROUGH */ 745 case CMPCI_DAC_MUTE: 746 case CMPCI_FM_MUTE: 747 case CMPCI_CD_MUTE: 748 case CMPCI_LINE_IN_MUTE: 749 case CMPCI_AUX_IN_MUTE: 750 dip->prev = dip->index - 6; /* CMPCI_xxx_VOL */ 751 dip->mixer_class = CMPCI_INPUT_CLASS; 752 strcpy(dip->label.name, AudioNmute); 753 goto on_off; 754 on_off: 755 dip->type = AUDIO_MIXER_ENUM; 756 dip->un.e.num_mem = 2; 757 strcpy(dip->un.e.member[0].label.name, AudioNoff); 758 dip->un.e.member[0].ord = 0; 759 strcpy(dip->un.e.member[1].label.name, AudioNon); 760 dip->un.e.member[1].ord = 1; 761 return 0; 762 763 case CMPCI_MIC_PREAMP: 764 dip->mixer_class = CMPCI_INPUT_CLASS; 765 dip->prev = CMPCI_MIC_MUTE; 766 strcpy(dip->label.name, AudioNpreamp); 767 goto on_off; 768 case CMPCI_PCSPEAKER: 769 dip->mixer_class = CMPCI_INPUT_CLASS; 770 strcpy(dip->label.name, AudioNspeaker); 771 dip->un.v.num_channels = 1; 772 dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_SPEAKER_VALBITS); 773 goto vol; 774 case CMPCI_RECORD_SOURCE: 775 dip->mixer_class = CMPCI_RECORD_CLASS; 776 strcpy(dip->label.name, AudioNsource); 777 dip->type = AUDIO_MIXER_SET; 778 dip->un.s.num_mem = 7; 779 strcpy(dip->un.s.member[0].label.name, AudioNmicrophone); 780 dip->un.s.member[0].mask = CMPCI_RECORD_SOURCE_MIC; 781 strcpy(dip->un.s.member[1].label.name, AudioNcd); 782 dip->un.s.member[1].mask = CMPCI_RECORD_SOURCE_CD; 783 strcpy(dip->un.s.member[2].label.name, AudioNline); 784 dip->un.s.member[2].mask = CMPCI_RECORD_SOURCE_LINE_IN; 785 strcpy(dip->un.s.member[3].label.name, AudioNaux); 786 dip->un.s.member[3].mask = CMPCI_RECORD_SOURCE_AUX_IN; 787 strcpy(dip->un.s.member[4].label.name, AudioNwave); 788 dip->un.s.member[4].mask = CMPCI_RECORD_SOURCE_WAVE; 789 strcpy(dip->un.s.member[5].label.name, AudioNfmsynth); 790 dip->un.s.member[5].mask = CMPCI_RECORD_SOURCE_FM; 791 strcpy(dip->un.s.member[6].label.name, CmpciNspdif); 792 dip->un.s.member[6].mask = CMPCI_RECORD_SOURCE_SPDIF; 793 return 0; 794 case CMPCI_MIC_RECVOL: 795 dip->mixer_class = CMPCI_RECORD_CLASS; 796 strcpy(dip->label.name, AudioNmicrophone); 797 dip->un.v.num_channels = 1; 798 dip->un.v.delta = 1 << (8 - CMPCI_REG_ADMIC_VALBITS); 799 goto vol; 800 801 case CMPCI_PLAYBACK_MODE: 802 dip->mixer_class = CMPCI_PLAYBACK_CLASS; 803 dip->type = AUDIO_MIXER_ENUM; 804 strcpy(dip->label.name, AudioNmode); 805 dip->un.e.num_mem = 2; 806 strcpy(dip->un.e.member[0].label.name, AudioNdac); 807 dip->un.e.member[0].ord = CMPCI_PLAYBACK_MODE_WAVE; 808 strcpy(dip->un.e.member[1].label.name, CmpciNspdif); 809 dip->un.e.member[1].ord = CMPCI_PLAYBACK_MODE_SPDIF; 810 return 0; 811 case CMPCI_SPDIF_IN_SELECT: 812 dip->mixer_class = CMPCI_SPDIF_CLASS; 813 dip->type = AUDIO_MIXER_ENUM; 814 dip->next = CMPCI_SPDIF_IN_PHASE; 815 strcpy(dip->label.name, AudioNinput); 816 i = 0; 817 strcpy(dip->un.e.member[i].label.name, CmpciNspdin1); 818 dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN1; 819 if (CMPCI_ISCAP(sc, 2ND_SPDIN)) { 820 strcpy(dip->un.e.member[i].label.name, CmpciNspdin2); 821 dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN2; 822 } 823 strcpy(dip->un.e.member[i].label.name, CmpciNspdout); 824 dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDOUT; 825 dip->un.e.num_mem = i; 826 return 0; 827 case CMPCI_SPDIF_IN_PHASE: 828 dip->mixer_class = CMPCI_SPDIF_CLASS; 829 dip->prev = CMPCI_SPDIF_IN_SELECT; 830 strcpy(dip->label.name, CmpciNphase); 831 dip->type = AUDIO_MIXER_ENUM; 832 dip->un.e.num_mem = 2; 833 strcpy(dip->un.e.member[0].label.name, CmpciNpositive); 834 dip->un.e.member[0].ord = CMPCI_SPDIF_IN_PHASE_POSITIVE; 835 strcpy(dip->un.e.member[1].label.name, CmpciNnegative); 836 dip->un.e.member[1].ord = CMPCI_SPDIF_IN_PHASE_NEGATIVE; 837 return 0; 838 case CMPCI_SPDIF_LOOP: 839 dip->mixer_class = CMPCI_SPDIF_CLASS; 840 dip->next = CMPCI_SPDIF_OUT_PLAYBACK; 841 strcpy(dip->label.name, AudioNoutput); 842 dip->type = AUDIO_MIXER_ENUM; 843 dip->un.e.num_mem = 2; 844 strcpy(dip->un.e.member[0].label.name, CmpciNplayback); 845 dip->un.e.member[0].ord = CMPCI_SPDIF_LOOP_OFF; 846 strcpy(dip->un.e.member[1].label.name, CmpciNspdin); 847 dip->un.e.member[1].ord = CMPCI_SPDIF_LOOP_ON; 848 return 0; 849 case CMPCI_SPDIF_OUT_PLAYBACK: 850 dip->mixer_class = CMPCI_SPDIF_CLASS; 851 dip->prev = CMPCI_SPDIF_LOOP; 852 dip->next = CMPCI_SPDIF_OUT_VOLTAGE; 853 strcpy(dip->label.name, CmpciNplayback); 854 dip->type = AUDIO_MIXER_ENUM; 855 dip->un.e.num_mem = 2; 856 strcpy(dip->un.e.member[0].label.name, AudioNwave); 857 dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_PLAYBACK_WAVE; 858 strcpy(dip->un.e.member[1].label.name, CmpciNlegacy); 859 dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_PLAYBACK_LEGACY; 860 return 0; 861 case CMPCI_SPDIF_OUT_VOLTAGE: 862 dip->mixer_class = CMPCI_SPDIF_CLASS; 863 dip->prev = CMPCI_SPDIF_OUT_PLAYBACK; 864 strcpy(dip->label.name, CmpciNvoltage); 865 dip->type = AUDIO_MIXER_ENUM; 866 dip->un.e.num_mem = 2; 867 strcpy(dip->un.e.member[0].label.name, CmpciNhigh_v); 868 dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_VOLTAGE_HIGH; 869 strcpy(dip->un.e.member[1].label.name, CmpciNlow_v); 870 dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_VOLTAGE_LOW; 871 return 0; 872 case CMPCI_MONITOR_DAC: 873 dip->mixer_class = CMPCI_SPDIF_CLASS; 874 strcpy(dip->label.name, AudioNmonitor); 875 dip->type = AUDIO_MIXER_ENUM; 876 dip->un.e.num_mem = 3; 877 strcpy(dip->un.e.member[0].label.name, AudioNoff); 878 dip->un.e.member[0].ord = CMPCI_MONITOR_DAC_OFF; 879 strcpy(dip->un.e.member[1].label.name, CmpciNspdin); 880 dip->un.e.member[1].ord = CMPCI_MONITOR_DAC_SPDIN; 881 strcpy(dip->un.e.member[2].label.name, CmpciNspdout); 882 dip->un.e.member[2].ord = CMPCI_MONITOR_DAC_SPDOUT; 883 return 0; 884 885 case CMPCI_MASTER_VOL: 886 dip->mixer_class = CMPCI_OUTPUT_CLASS; 887 strcpy(dip->label.name, AudioNmaster); 888 dip->un.v.num_channels = 2; 889 dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS); 890 goto vol; 891 case CMPCI_REAR: 892 dip->mixer_class = CMPCI_OUTPUT_CLASS; 893 dip->next = CMPCI_INDIVIDUAL; 894 strcpy(dip->label.name, CmpciNrear); 895 goto on_off; 896 case CMPCI_INDIVIDUAL: 897 dip->mixer_class = CMPCI_OUTPUT_CLASS; 898 dip->prev = CMPCI_REAR; 899 dip->next = CMPCI_REVERSE; 900 strcpy(dip->label.name, CmpciNindividual); 901 goto on_off; 902 case CMPCI_REVERSE: 903 dip->mixer_class = CMPCI_OUTPUT_CLASS; 904 dip->prev = CMPCI_INDIVIDUAL; 905 strcpy(dip->label.name, CmpciNreverse); 906 goto on_off; 907 case CMPCI_SURROUND: 908 dip->mixer_class = CMPCI_OUTPUT_CLASS; 909 strcpy(dip->label.name, CmpciNsurround); 910 goto on_off; 911 } 912 913 return ENXIO; 914 } 915 916 static int 917 cmpci_alloc_dmamem(struct cmpci_softc *sc, size_t size, void **r_addr) 918 { 919 int error; 920 struct cmpci_dmanode *n; 921 922 error = 0; 923 n = kmem_alloc(sizeof(*n), KM_SLEEP); 924 925 #define CMPCI_DMABUF_ALIGN 0x4 926 #define CMPCI_DMABUF_BOUNDARY 0x0 927 n->cd_tag = sc->sc_dmat; 928 n->cd_size = size; 929 error = bus_dmamem_alloc(n->cd_tag, n->cd_size, 930 CMPCI_DMABUF_ALIGN, CMPCI_DMABUF_BOUNDARY, n->cd_segs, 931 sizeof(n->cd_segs)/sizeof(n->cd_segs[0]), &n->cd_nsegs, 932 BUS_DMA_WAITOK); 933 if (error) 934 goto mfree; 935 error = bus_dmamem_map(n->cd_tag, n->cd_segs, n->cd_nsegs, n->cd_size, 936 &n->cd_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 937 if (error) 938 goto dmafree; 939 error = bus_dmamap_create(n->cd_tag, n->cd_size, 1, n->cd_size, 0, 940 BUS_DMA_WAITOK, &n->cd_map); 941 if (error) 942 goto unmap; 943 error = bus_dmamap_load(n->cd_tag, n->cd_map, n->cd_addr, n->cd_size, 944 NULL, BUS_DMA_WAITOK); 945 if (error) 946 goto destroy; 947 948 n->cd_next = sc->sc_dmap; 949 sc->sc_dmap = n; 950 *r_addr = KVADDR(n); 951 return 0; 952 953 destroy: 954 bus_dmamap_destroy(n->cd_tag, n->cd_map); 955 unmap: 956 bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size); 957 dmafree: 958 bus_dmamem_free(n->cd_tag, 959 n->cd_segs, sizeof(n->cd_segs)/sizeof(n->cd_segs[0])); 960 mfree: 961 kmem_free(n, sizeof(*n)); 962 return error; 963 } 964 965 static int 966 cmpci_free_dmamem(struct cmpci_softc *sc, void *addr, size_t size) 967 { 968 struct cmpci_dmanode **nnp; 969 970 for (nnp = &sc->sc_dmap; *nnp; nnp= &(*nnp)->cd_next) { 971 if ((*nnp)->cd_addr == addr) { 972 struct cmpci_dmanode *n = *nnp; 973 bus_dmamap_unload(n->cd_tag, n->cd_map); 974 bus_dmamap_destroy(n->cd_tag, n->cd_map); 975 bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size); 976 bus_dmamem_free(n->cd_tag, n->cd_segs, 977 sizeof(n->cd_segs)/sizeof(n->cd_segs[0])); 978 kmem_free(n, sizeof(*n)); 979 return 0; 980 } 981 } 982 return -1; 983 } 984 985 static struct cmpci_dmanode * 986 cmpci_find_dmamem(struct cmpci_softc *sc, void *addr) 987 { 988 struct cmpci_dmanode *p; 989 990 for (p = sc->sc_dmap; p; p = p->cd_next) 991 if (KVADDR(p) == (void *)addr) 992 break; 993 return p; 994 } 995 996 #if 0 997 static void 998 cmpci_print_dmamem(struct cmpci_dmanode *); 999 static void 1000 cmpci_print_dmamem(struct cmpci_dmanode *p) 1001 { 1002 1003 DPRINTF(("DMA at virt:%p, dmaseg:%p, mapseg:%p, size:%p\n", 1004 (void *)p->cd_addr, (void *)p->cd_segs[0].ds_addr, 1005 (void *)DMAADDR(p), (void *)p->cd_size)); 1006 } 1007 #endif /* DEBUG */ 1008 1009 static void * 1010 cmpci_allocm(void *handle, int direction, size_t size) 1011 { 1012 void *addr; 1013 1014 addr = NULL; /* XXX gcc */ 1015 1016 if (cmpci_alloc_dmamem(handle, size, &addr)) 1017 return NULL; 1018 return addr; 1019 } 1020 1021 static void 1022 cmpci_freem(void *handle, void *addr, size_t size) 1023 { 1024 1025 cmpci_free_dmamem(handle, addr, size); 1026 } 1027 1028 #define MAXVAL 256 1029 static int 1030 cmpci_adjust(int val, int mask) 1031 { 1032 1033 val += (MAXVAL - mask) >> 1; 1034 if (val >= MAXVAL) 1035 val = MAXVAL-1; 1036 return val & mask; 1037 } 1038 1039 static void 1040 cmpci_set_mixer_gain(struct cmpci_softc *sc, int port) 1041 { 1042 int src; 1043 int bits, mask; 1044 1045 switch (port) { 1046 case CMPCI_MIC_VOL: 1047 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_MIC, 1048 CMPCI_ADJUST_MIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR])); 1049 return; 1050 case CMPCI_MASTER_VOL: 1051 src = CMPCI_SB16_MIXER_MASTER_L; 1052 break; 1053 case CMPCI_LINE_IN_VOL: 1054 src = CMPCI_SB16_MIXER_LINE_L; 1055 break; 1056 case CMPCI_AUX_IN_VOL: 1057 bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MIXER_AUX, 1058 CMPCI_ADJUST_AUX_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT], 1059 sc->sc_gain[port][CMPCI_RIGHT])); 1060 return; 1061 case CMPCI_MIC_RECVOL: 1062 cmpci_reg_partial_write_1(sc, CMPCI_REG_MIXER25, 1063 CMPCI_REG_ADMIC_SHIFT, CMPCI_REG_ADMIC_MASK, 1064 CMPCI_ADJUST_ADMIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR])); 1065 return; 1066 case CMPCI_DAC_VOL: 1067 src = CMPCI_SB16_MIXER_VOICE_L; 1068 break; 1069 case CMPCI_FM_VOL: 1070 src = CMPCI_SB16_MIXER_FM_L; 1071 break; 1072 case CMPCI_CD_VOL: 1073 src = CMPCI_SB16_MIXER_CDDA_L; 1074 break; 1075 case CMPCI_PCSPEAKER: 1076 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_SPEAKER, 1077 CMPCI_ADJUST_2_GAIN(sc, sc->sc_gain[port][CMPCI_LR])); 1078 return; 1079 case CMPCI_MIC_PREAMP: 1080 if (sc->sc_gain[port][CMPCI_LR]) 1081 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25, 1082 CMPCI_REG_MICGAINZ); 1083 else 1084 cmpci_reg_set_1(sc, CMPCI_REG_MIXER25, 1085 CMPCI_REG_MICGAINZ); 1086 return; 1087 1088 case CMPCI_DAC_MUTE: 1089 if (sc->sc_gain[port][CMPCI_LR]) 1090 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1091 CMPCI_REG_WSMUTE); 1092 else 1093 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1094 CMPCI_REG_WSMUTE); 1095 return; 1096 case CMPCI_FM_MUTE: 1097 if (sc->sc_gain[port][CMPCI_LR]) 1098 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1099 CMPCI_REG_FMMUTE); 1100 else 1101 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1102 CMPCI_REG_FMMUTE); 1103 return; 1104 case CMPCI_AUX_IN_MUTE: 1105 if (sc->sc_gain[port][CMPCI_LR]) 1106 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25, 1107 CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM); 1108 else 1109 cmpci_reg_set_1(sc, CMPCI_REG_MIXER25, 1110 CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM); 1111 return; 1112 case CMPCI_CD_MUTE: 1113 mask = CMPCI_SB16_SW_CD; 1114 goto sbmute; 1115 case CMPCI_MIC_MUTE: 1116 mask = CMPCI_SB16_SW_MIC; 1117 goto sbmute; 1118 case CMPCI_LINE_IN_MUTE: 1119 mask = CMPCI_SB16_SW_LINE; 1120 sbmute: 1121 bits = cmpci_mixerreg_read(sc, CMPCI_SB16_MIXER_OUTMIX); 1122 if (sc->sc_gain[port][CMPCI_LR]) 1123 bits = bits & ~mask; 1124 else 1125 bits = bits | mask; 1126 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX, bits); 1127 return; 1128 1129 case CMPCI_SPDIF_IN_SELECT: 1130 case CMPCI_MONITOR_DAC: 1131 case CMPCI_PLAYBACK_MODE: 1132 case CMPCI_SPDIF_LOOP: 1133 case CMPCI_SPDIF_OUT_PLAYBACK: 1134 cmpci_set_out_ports(sc); 1135 return; 1136 case CMPCI_SPDIF_OUT_VOLTAGE: 1137 if (CMPCI_ISCAP(sc, SPDOUT_VOLTAGE)) { 1138 if (sc->sc_gain[CMPCI_SPDIF_OUT_VOLTAGE][CMPCI_LR] 1139 == CMPCI_SPDIF_OUT_VOLTAGE_HIGH) 1140 cmpci_reg_clear_reg_misc(sc, CMPCI_REG_5V); 1141 else 1142 cmpci_reg_set_reg_misc(sc, CMPCI_REG_5V); 1143 } 1144 return; 1145 case CMPCI_SURROUND: 1146 if (CMPCI_ISCAP(sc, SURROUND)) { 1147 if (sc->sc_gain[CMPCI_SURROUND][CMPCI_LR]) 1148 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1149 CMPCI_REG_SURROUND); 1150 else 1151 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1152 CMPCI_REG_SURROUND); 1153 } 1154 return; 1155 case CMPCI_REAR: 1156 if (CMPCI_ISCAP(sc, REAR)) { 1157 if (sc->sc_gain[CMPCI_REAR][CMPCI_LR]) 1158 cmpci_reg_set_reg_misc(sc, CMPCI_REG_N4SPK3D); 1159 else 1160 cmpci_reg_clear_reg_misc(sc, CMPCI_REG_N4SPK3D); 1161 } 1162 return; 1163 case CMPCI_INDIVIDUAL: 1164 if (CMPCI_ISCAP(sc, INDIVIDUAL_REAR)) { 1165 if (sc->sc_gain[CMPCI_REAR][CMPCI_LR]) 1166 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1167 CMPCI_REG_INDIVIDUAL); 1168 else 1169 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1170 CMPCI_REG_INDIVIDUAL); 1171 } 1172 return; 1173 case CMPCI_REVERSE: 1174 if (CMPCI_ISCAP(sc, REVERSE_FR)) { 1175 if (sc->sc_gain[CMPCI_REVERSE][CMPCI_LR]) 1176 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1177 CMPCI_REG_REVERSE_FR); 1178 else 1179 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1180 CMPCI_REG_REVERSE_FR); 1181 } 1182 return; 1183 case CMPCI_SPDIF_IN_PHASE: 1184 if (CMPCI_ISCAP(sc, SPDIN_PHASE)) { 1185 if (sc->sc_gain[CMPCI_SPDIF_IN_PHASE][CMPCI_LR] 1186 == CMPCI_SPDIF_IN_PHASE_POSITIVE) 1187 cmpci_reg_clear_1(sc, CMPCI_REG_CHANNEL_FORMAT, 1188 CMPCI_REG_SPDIN_PHASE); 1189 else 1190 cmpci_reg_set_1(sc, CMPCI_REG_CHANNEL_FORMAT, 1191 CMPCI_REG_SPDIN_PHASE); 1192 } 1193 return; 1194 default: 1195 return; 1196 } 1197 1198 cmpci_mixerreg_write(sc, src, 1199 CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT])); 1200 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_L_TO_R(src), 1201 CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_RIGHT])); 1202 } 1203 1204 static void 1205 cmpci_set_out_ports(struct cmpci_softc *sc) 1206 { 1207 uint8_t v; 1208 int enspdout; 1209 1210 if (!CMPCI_ISCAP(sc, SPDLOOP)) 1211 return; 1212 1213 /* SPDIF/out select */ 1214 if (sc->sc_gain[CMPCI_SPDIF_LOOP][CMPCI_LR] == CMPCI_SPDIF_LOOP_OFF) { 1215 /* playback */ 1216 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 1217 } else { 1218 /* monitor SPDIF/in */ 1219 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 1220 } 1221 1222 /* SPDIF in select */ 1223 v = sc->sc_gain[CMPCI_SPDIF_IN_SELECT][CMPCI_LR]; 1224 if (v & CMPCI_SPDIFIN_SPDIFIN2) 1225 cmpci_reg_set_reg_misc(sc, CMPCI_REG_2ND_SPDIFIN); 1226 else 1227 cmpci_reg_clear_reg_misc(sc, CMPCI_REG_2ND_SPDIFIN); 1228 if (v & CMPCI_SPDIFIN_SPDIFOUT) 1229 cmpci_reg_set_reg_misc(sc, CMPCI_REG_SPDFLOOPI); 1230 else 1231 cmpci_reg_clear_reg_misc(sc, CMPCI_REG_SPDFLOOPI); 1232 1233 enspdout = 0; 1234 /* playback to ... */ 1235 if (CMPCI_ISCAP(sc, SPDOUT) && 1236 sc->sc_gain[CMPCI_PLAYBACK_MODE][CMPCI_LR] 1237 == CMPCI_PLAYBACK_MODE_SPDIF && 1238 (sc->sc_play.md_divide == CMPCI_REG_RATE_44100 || 1239 (CMPCI_ISCAP(sc, SPDOUT_48K) && 1240 sc->sc_play.md_divide==CMPCI_REG_RATE_48000))) { 1241 /* playback to SPDIF */ 1242 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF0_ENABLE); 1243 enspdout = 1; 1244 if (sc->sc_play.md_divide==CMPCI_REG_RATE_48000) 1245 cmpci_reg_set_reg_misc(sc, 1246 CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K); 1247 else 1248 cmpci_reg_clear_reg_misc(sc, 1249 CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K); 1250 } else { 1251 /* playback to DAC */ 1252 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1, 1253 CMPCI_REG_SPDIF0_ENABLE); 1254 if (CMPCI_ISCAP(sc, SPDOUT_48K)) 1255 cmpci_reg_clear_reg_misc(sc, 1256 CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K); 1257 } 1258 1259 /* legacy to SPDIF/out or not */ 1260 if (CMPCI_ISCAP(sc, SPDLEGACY)) { 1261 if (sc->sc_gain[CMPCI_SPDIF_OUT_PLAYBACK][CMPCI_LR] 1262 == CMPCI_SPDIF_OUT_PLAYBACK_WAVE) 1263 cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL, 1264 CMPCI_REG_LEGACY_SPDIF_ENABLE); 1265 else { 1266 cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL, 1267 CMPCI_REG_LEGACY_SPDIF_ENABLE); 1268 enspdout = 1; 1269 } 1270 } 1271 1272 /* enable/disable SPDIF/out */ 1273 if (CMPCI_ISCAP(sc, XSPDOUT) && enspdout) 1274 cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL, 1275 CMPCI_REG_XSPDIF_ENABLE); 1276 else 1277 cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL, 1278 CMPCI_REG_XSPDIF_ENABLE); 1279 1280 /* SPDIF monitor (digital to analog output) */ 1281 if (CMPCI_ISCAP(sc, SPDIN_MONITOR)) { 1282 v = sc->sc_gain[CMPCI_MONITOR_DAC][CMPCI_LR]; 1283 if (!(v & CMPCI_MONDAC_ENABLE)) 1284 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1285 CMPCI_REG_SPDIN_MONITOR); 1286 if (v & CMPCI_MONDAC_SPDOUT) 1287 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, 1288 CMPCI_REG_SPDIFOUT_DAC); 1289 else 1290 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1, 1291 CMPCI_REG_SPDIFOUT_DAC); 1292 if (v & CMPCI_MONDAC_ENABLE) 1293 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1294 CMPCI_REG_SPDIN_MONITOR); 1295 } 1296 } 1297 1298 static int 1299 cmpci_set_in_ports(struct cmpci_softc *sc) 1300 { 1301 int mask; 1302 int bitsl, bitsr; 1303 1304 mask = sc->sc_in_mask; 1305 1306 /* 1307 * Note CMPCI_RECORD_SOURCE_CD, CMPCI_RECORD_SOURCE_LINE_IN and 1308 * CMPCI_RECORD_SOURCE_FM are defined to the corresponding bit 1309 * of the mixer register. 1310 */ 1311 bitsr = mask & (CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN | 1312 CMPCI_RECORD_SOURCE_FM); 1313 1314 bitsl = CMPCI_SB16_MIXER_SRC_R_TO_L(bitsr); 1315 if (mask & CMPCI_RECORD_SOURCE_MIC) { 1316 bitsl |= CMPCI_SB16_MIXER_MIC_SRC; 1317 bitsr |= CMPCI_SB16_MIXER_MIC_SRC; 1318 } 1319 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, bitsl); 1320 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, bitsr); 1321 1322 if (mask & CMPCI_RECORD_SOURCE_AUX_IN) 1323 cmpci_reg_set_1(sc, CMPCI_REG_MIXER25, 1324 CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN); 1325 else 1326 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25, 1327 CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN); 1328 1329 if (mask & CMPCI_RECORD_SOURCE_WAVE) 1330 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1331 CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR); 1332 else 1333 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1334 CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR); 1335 1336 if (CMPCI_ISCAP(sc, SPDIN) && 1337 (sc->sc_rec.md_divide == CMPCI_REG_RATE_44100 || 1338 (CMPCI_ISCAP(sc, SPDOUT_48K) && 1339 sc->sc_rec.md_divide == CMPCI_REG_RATE_48000/* XXX? */))) { 1340 if (mask & CMPCI_RECORD_SOURCE_SPDIF) { 1341 /* enable SPDIF/in */ 1342 cmpci_reg_set_4(sc, 1343 CMPCI_REG_FUNC_1, 1344 CMPCI_REG_SPDIF1_ENABLE); 1345 } else { 1346 cmpci_reg_clear_4(sc, 1347 CMPCI_REG_FUNC_1, 1348 CMPCI_REG_SPDIF1_ENABLE); 1349 } 1350 } 1351 1352 return 0; 1353 } 1354 1355 static int 1356 cmpci_set_port(void *handle, mixer_ctrl_t *cp) 1357 { 1358 struct cmpci_softc *sc; 1359 int lgain, rgain; 1360 1361 sc = handle; 1362 switch (cp->dev) { 1363 case CMPCI_MIC_VOL: 1364 case CMPCI_PCSPEAKER: 1365 case CMPCI_MIC_RECVOL: 1366 if (cp->un.value.num_channels != 1) 1367 return EINVAL; 1368 /* FALLTHROUGH */ 1369 case CMPCI_DAC_VOL: 1370 case CMPCI_FM_VOL: 1371 case CMPCI_CD_VOL: 1372 case CMPCI_LINE_IN_VOL: 1373 case CMPCI_AUX_IN_VOL: 1374 case CMPCI_MASTER_VOL: 1375 if (cp->type != AUDIO_MIXER_VALUE) 1376 return EINVAL; 1377 switch (cp->un.value.num_channels) { 1378 case 1: 1379 lgain = rgain = 1380 cp->un.value.level[AUDIO_MIXER_LEVEL_MONO]; 1381 break; 1382 case 2: 1383 lgain = cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1384 rgain = cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1385 break; 1386 default: 1387 return EINVAL; 1388 } 1389 sc->sc_gain[cp->dev][CMPCI_LEFT] = lgain; 1390 sc->sc_gain[cp->dev][CMPCI_RIGHT] = rgain; 1391 1392 cmpci_set_mixer_gain(sc, cp->dev); 1393 break; 1394 1395 case CMPCI_RECORD_SOURCE: 1396 if (cp->type != AUDIO_MIXER_SET) 1397 return EINVAL; 1398 1399 if (cp->un.mask & ~(CMPCI_RECORD_SOURCE_MIC | 1400 CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN | 1401 CMPCI_RECORD_SOURCE_AUX_IN | CMPCI_RECORD_SOURCE_WAVE | 1402 CMPCI_RECORD_SOURCE_FM | CMPCI_RECORD_SOURCE_SPDIF)) 1403 return EINVAL; 1404 1405 if (cp->un.mask & CMPCI_RECORD_SOURCE_SPDIF) 1406 cp->un.mask = CMPCI_RECORD_SOURCE_SPDIF; 1407 1408 sc->sc_in_mask = cp->un.mask; 1409 return cmpci_set_in_ports(sc); 1410 1411 /* boolean */ 1412 case CMPCI_DAC_MUTE: 1413 case CMPCI_FM_MUTE: 1414 case CMPCI_CD_MUTE: 1415 case CMPCI_LINE_IN_MUTE: 1416 case CMPCI_AUX_IN_MUTE: 1417 case CMPCI_MIC_MUTE: 1418 case CMPCI_MIC_PREAMP: 1419 case CMPCI_PLAYBACK_MODE: 1420 case CMPCI_SPDIF_IN_PHASE: 1421 case CMPCI_SPDIF_LOOP: 1422 case CMPCI_SPDIF_OUT_PLAYBACK: 1423 case CMPCI_SPDIF_OUT_VOLTAGE: 1424 case CMPCI_REAR: 1425 case CMPCI_INDIVIDUAL: 1426 case CMPCI_REVERSE: 1427 case CMPCI_SURROUND: 1428 if (cp->type != AUDIO_MIXER_ENUM) 1429 return EINVAL; 1430 sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord != 0; 1431 cmpci_set_mixer_gain(sc, cp->dev); 1432 break; 1433 1434 case CMPCI_SPDIF_IN_SELECT: 1435 switch (cp->un.ord) { 1436 case CMPCI_SPDIF_IN_SPDIN1: 1437 case CMPCI_SPDIF_IN_SPDIN2: 1438 case CMPCI_SPDIF_IN_SPDOUT: 1439 break; 1440 default: 1441 return EINVAL; 1442 } 1443 goto xenum; 1444 case CMPCI_MONITOR_DAC: 1445 switch (cp->un.ord) { 1446 case CMPCI_MONITOR_DAC_OFF: 1447 case CMPCI_MONITOR_DAC_SPDIN: 1448 case CMPCI_MONITOR_DAC_SPDOUT: 1449 break; 1450 default: 1451 return EINVAL; 1452 } 1453 xenum: 1454 if (cp->type != AUDIO_MIXER_ENUM) 1455 return EINVAL; 1456 sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord; 1457 cmpci_set_mixer_gain(sc, cp->dev); 1458 break; 1459 1460 default: 1461 return EINVAL; 1462 } 1463 1464 return 0; 1465 } 1466 1467 static int 1468 cmpci_get_port(void *handle, mixer_ctrl_t *cp) 1469 { 1470 struct cmpci_softc *sc; 1471 1472 sc = handle; 1473 switch (cp->dev) { 1474 case CMPCI_MIC_VOL: 1475 case CMPCI_PCSPEAKER: 1476 case CMPCI_MIC_RECVOL: 1477 if (cp->un.value.num_channels != 1) 1478 return EINVAL; 1479 /*FALLTHROUGH*/ 1480 case CMPCI_DAC_VOL: 1481 case CMPCI_FM_VOL: 1482 case CMPCI_CD_VOL: 1483 case CMPCI_LINE_IN_VOL: 1484 case CMPCI_AUX_IN_VOL: 1485 case CMPCI_MASTER_VOL: 1486 switch (cp->un.value.num_channels) { 1487 case 1: 1488 cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] = 1489 sc->sc_gain[cp->dev][CMPCI_LEFT]; 1490 break; 1491 case 2: 1492 cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1493 sc->sc_gain[cp->dev][CMPCI_LEFT]; 1494 cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1495 sc->sc_gain[cp->dev][CMPCI_RIGHT]; 1496 break; 1497 default: 1498 return EINVAL; 1499 } 1500 break; 1501 1502 case CMPCI_RECORD_SOURCE: 1503 cp->un.mask = sc->sc_in_mask; 1504 break; 1505 1506 case CMPCI_DAC_MUTE: 1507 case CMPCI_FM_MUTE: 1508 case CMPCI_CD_MUTE: 1509 case CMPCI_LINE_IN_MUTE: 1510 case CMPCI_AUX_IN_MUTE: 1511 case CMPCI_MIC_MUTE: 1512 case CMPCI_MIC_PREAMP: 1513 case CMPCI_PLAYBACK_MODE: 1514 case CMPCI_SPDIF_IN_SELECT: 1515 case CMPCI_SPDIF_IN_PHASE: 1516 case CMPCI_SPDIF_LOOP: 1517 case CMPCI_SPDIF_OUT_PLAYBACK: 1518 case CMPCI_SPDIF_OUT_VOLTAGE: 1519 case CMPCI_MONITOR_DAC: 1520 case CMPCI_REAR: 1521 case CMPCI_INDIVIDUAL: 1522 case CMPCI_REVERSE: 1523 case CMPCI_SURROUND: 1524 cp->un.ord = sc->sc_gain[cp->dev][CMPCI_LR]; 1525 break; 1526 1527 default: 1528 return EINVAL; 1529 } 1530 1531 return 0; 1532 } 1533 1534 /* ARGSUSED */ 1535 static size_t 1536 cmpci_round_buffersize(void *handle, int direction, 1537 size_t bufsize) 1538 { 1539 1540 if (bufsize > 0x10000) 1541 bufsize = 0x10000; 1542 1543 return bufsize; 1544 } 1545 1546 /* ARGSUSED */ 1547 static int 1548 cmpci_get_props(void *handle) 1549 { 1550 1551 return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE | 1552 AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1553 } 1554 1555 static int 1556 cmpci_trigger_output(void *handle, void *start, void *end, int blksize, 1557 void (*intr)(void *), void *arg, 1558 const audio_params_t *param) 1559 { 1560 struct cmpci_softc *sc; 1561 struct cmpci_dmanode *p; 1562 int bps; 1563 1564 sc = handle; 1565 sc->sc_play.intr = intr; 1566 sc->sc_play.intr_arg = arg; 1567 bps = param->channels * param->precision / 8; 1568 if (!bps) 1569 return EINVAL; 1570 1571 /* set DMA frame */ 1572 if (!(p = cmpci_find_dmamem(sc, start))) 1573 return EINVAL; 1574 bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BASE, 1575 DMAADDR(p)); 1576 delay(10); 1577 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BYTES, 1578 ((char *)end - (char *)start + 1) / bps - 1); 1579 delay(10); 1580 1581 /* set interrupt count */ 1582 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_SAMPLES, 1583 (blksize + bps - 1) / bps - 1); 1584 delay(10); 1585 1586 /* start DMA */ 1587 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); /* PLAY */ 1588 cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 1589 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 1590 1591 return 0; 1592 } 1593 1594 static int 1595 cmpci_trigger_input(void *handle, void *start, void *end, int blksize, 1596 void (*intr)(void *), void *arg, 1597 const audio_params_t *param) 1598 { 1599 struct cmpci_softc *sc; 1600 struct cmpci_dmanode *p; 1601 int bps; 1602 1603 sc = handle; 1604 sc->sc_rec.intr = intr; 1605 sc->sc_rec.intr_arg = arg; 1606 bps = param->channels * param->precision / 8; 1607 if (!bps) 1608 return EINVAL; 1609 1610 /* set DMA frame */ 1611 if (!(p=cmpci_find_dmamem(sc, start))) 1612 return EINVAL; 1613 bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BASE, 1614 DMAADDR(p)); 1615 delay(10); 1616 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BYTES, 1617 ((char *)end - (char *)start + 1) / bps - 1); 1618 delay(10); 1619 1620 /* set interrupt count */ 1621 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_SAMPLES, 1622 (blksize + bps - 1) / bps - 1); 1623 delay(10); 1624 1625 /* start DMA */ 1626 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); /* REC */ 1627 cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 1628 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 1629 1630 return 0; 1631 } 1632 1633 static void 1634 cmpci_get_locks(void *addr, kmutex_t **intr, kmutex_t **thread) 1635 { 1636 struct cmpci_softc *sc; 1637 1638 sc = addr; 1639 *intr = &sc->sc_intr_lock; 1640 *thread = &sc->sc_lock; 1641 } 1642 1643 /* end of file */ 1644
Indexes created Sun Sep 28 07:09:56 GMT 2025