coram.c revision 1.1
1 /* $NetBSD: coram.c,v 1.1 2011/08/04 14:43:55 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: coram.c,v 1.1 2011/08/04 14:43:55 jakllsch Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 38 #include <sys/bus.h> 39 40 #include <dev/dtv/dtvif.h> 41 42 #include <dev/pci/cx23885reg.h> 43 #include <dev/pci/coramvar.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/i2c/i2cvar.h> 49 #include <dev/i2c/at24cxxvar.h> 50 51 #include <dev/i2c/cx24227var.h> 52 #include <dev/i2c/mt2131var.h> 53 54 static int coram_match(device_t, cfdata_t, void *); 55 static void coram_attach(device_t, device_t, void *); 56 static bool coram_resume(device_t, const pmf_qual_t *); 57 static int coram_intr(void *); 58 59 static int coram_iic_exec(void *, i2c_op_t, i2c_addr_t, 60 const void *, size_t, void *, size_t, int); 61 static int coram_iic_acquire_bus(void *, int); 62 static void coram_iic_release_bus(void *, int); 63 static int coram_iic_read(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 64 const void *, size_t, void *, size_t, int); 65 static int coram_iic_write(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 66 const void *, size_t, void *, size_t, int); 67 68 static void coram_dtv_get_devinfo(void *, struct dvb_frontend_info *); 69 static int coram_dtv_open(void *, int); 70 static void coram_dtv_close(void *); 71 static int coram_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 72 static fe_status_t coram_dtv_get_status(void *); 73 static uint16_t coram_dtv_get_signal_strength(void *); 74 static uint16_t coram_dtv_get_snr(void *); 75 static int coram_dtv_start_transfer(void *); 76 static int coram_dtv_stop_transfer(void *); 77 78 static int coram_mpeg_attach(struct coram_softc *); 79 static int coram_mpeg_reset(struct coram_softc *); 80 static void * coram_mpeg_malloc(struct coram_softc *, size_t); 81 static int coram_allocmem(struct coram_softc *, size_t, size_t, struct coram_dma *); 82 static void coram_mpeg_free(struct coram_softc *, void *); 83 static int coram_mpeg_halt(struct coram_softc *); 84 static int coram_freemem(struct coram_softc *, struct coram_dma *); 85 static int coram_mpeg_trigger(struct coram_softc *, void *); 86 static int coram_risc_buffer(struct coram_softc *, uint32_t, uint32_t); 87 static int coram_risc_field(struct coram_softc *, uint32_t *, uint32_t); 88 static int coram_sram_ch_setup(struct coram_softc *, struct coram_sram_ch *, uint32_t); 89 static int coram_mpeg_intr(struct coram_softc *); 90 91 CFATTACH_DECL_NEW(coram, sizeof(struct coram_softc), 92 coram_match, coram_attach, NULL, NULL); 93 94 #define CORAM_SRAM_CH6 0 95 96 #define CORAM_TS_PKTSIZE (188 * 8) 97 98 static struct coram_sram_ch coram_sram_chs[] = { 99 [CORAM_SRAM_CH6] = { 100 .csc_cmds= 0x10140, 101 .csc_iq = 0x10500, 102 .csc_iqsz = 0x40, 103 .csc_cdt = 0x10600, 104 .csc_cdtsz = 0x10, 105 .csc_fifo = 0x6000, 106 .csc_fifosz = 0x1000, 107 .csc_risc = 0x10800, 108 .csc_riscsz = 0x800, 109 .csc_ptr1 = DMA5_PTR1, 110 .csc_ptr2 = DMA5_PTR2, 111 .csc_cnt1 = DMA5_CNT1, 112 .csc_cnt2 = DMA5_CNT2, 113 }, 114 }; 115 116 //#define PCI_PRODUCT_CONEXANT_CX23885 0x8852 117 118 static const struct dtv_hw_if coram_dtv_if = { 119 .get_devinfo = coram_dtv_get_devinfo, 120 .open = coram_dtv_open, 121 .close = coram_dtv_close, 122 .set_tuner = coram_dtv_set_tuner, 123 .get_status = coram_dtv_get_status, 124 .get_signal_strength = coram_dtv_get_signal_strength, 125 .get_snr = coram_dtv_get_snr, 126 .start_transfer = coram_dtv_start_transfer, 127 .stop_transfer = coram_dtv_stop_transfer, 128 }; 129 130 static int 131 coram_match(device_t parent, cfdata_t match, void *v) 132 { 133 const struct pci_attach_args *pa = v; 134 135 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 136 return 0; 137 138 switch (PCI_PRODUCT(pa->pa_id)) { 139 case PCI_PRODUCT_CONEXANT_CX23885: 140 return 1; 141 } 142 143 /* XXX only match supported boards */ 144 145 return 0; 146 } 147 148 static void 149 coram_attach(device_t parent, device_t self, void *v) 150 { 151 struct coram_softc *sc; 152 const struct pci_attach_args *pa = v; 153 pci_intr_handle_t ih; 154 pcireg_t reg; 155 const char *intrstr; 156 char devinfo[76]; 157 struct coram_iic_softc *cic; 158 struct i2cbus_attach_args iba; 159 uint32_t value; 160 161 sc = device_private(self); 162 163 sc->sc_dev = self; 164 165 aprint_naive("\n"); 166 167 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 168 169 sc->sc_vendor = PCI_VENDOR(reg); 170 sc->sc_product = PCI_PRODUCT(reg); 171 172 pci_devinfo(reg, pa->pa_class, 0, devinfo, sizeof(devinfo)); 173 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 174 175 if (pci_mapreg_map(pa, CX23885_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 176 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 177 aprint_error_dev(self, "couldn't map memory space\n"); 178 return; 179 } 180 181 sc->sc_dmat = pa->pa_dmat; 182 183 if (pci_intr_map(pa, &ih)) { 184 aprint_error_dev(self, "couldn't map interrupt\n"); 185 return; 186 } 187 intrstr = pci_intr_string(pa->pa_pc, ih); 188 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_VM, 189 coram_intr, (void *)self); 190 if (sc->sc_ih == NULL) { 191 aprint_error_dev(self, "couldn't establish interrupt"); 192 if (intrstr != NULL) 193 aprint_error(" at %s", intrstr); 194 aprint_error("\n"); 195 return; 196 } 197 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 198 199 /* set master */ 200 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 201 reg |= PCI_COMMAND_MASTER_ENABLE; 202 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 203 204 int i; 205 206 /* I2C */ 207 for(i = 0; i < I2C_NUM; i++) { 208 cic = &sc->sc_iic[i]; 209 210 cic->cic_sc = sc; 211 if(bus_space_subregion(sc->sc_memt, sc->sc_memh, I2C_BASE + (I2C_SIZE * i), I2C_SIZE, &cic->cic_regh)) 212 panic("failed to subregion i2c"); 213 214 mutex_init(&cic->cic_busmutex, MUTEX_DRIVER, IPL_NONE); 215 cic->cic_i2c.ic_cookie = cic; 216 cic->cic_i2c.ic_acquire_bus = coram_iic_acquire_bus; 217 cic->cic_i2c.ic_release_bus = coram_iic_release_bus; 218 cic->cic_i2c.ic_exec = coram_iic_exec; 219 220 #if 1 221 /* attach iic(4) */ 222 memset(&iba, 0, sizeof(iba)); 223 iba.iba_tag = &cic->cic_i2c; 224 iba.iba_type = I2C_TYPE_SMBUS; 225 config_found_ia(self, "i2cbus", &iba, iicbus_print); 226 #endif 227 } 228 229 /* HVR1250 GPIO */ 230 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x110010); 231 #if 1 232 value &= ~0x00010001; 233 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 234 delay(5000); 235 #endif 236 value |= 0x00010001; 237 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 238 239 #if 0 240 int i; 241 uint8_t foo[256]; 242 uint8_t bar; 243 bar = 0; 244 // seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0, 256, foo, 256); 245 246 iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL); 247 iic_exec(&sc->sc_i2c, I2C_OP_READ_WITH_STOP, 0x50, &bar, 1, foo, 256, I2C_F_POLL); 248 iic_release_bus(&sc->sc_i2c, I2C_F_POLL); 249 250 printf("\n"); 251 for ( i = 0; i < 256; i++) { 252 if ( (i % 8) == 0 ) 253 printf("%02x: ", i); 254 255 printf("%02x", foo[i]); 256 257 if ( (i % 8) == 7 ) 258 printf("\n"); 259 else 260 printf(" "); 261 } 262 printf("\n"); 263 #endif 264 265 sc->sc_demod = cx24227_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x19); 266 if ( sc->sc_demod == NULL ) 267 panic("no demod"); 268 269 sc->sc_tuner = mt2131_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x61); 270 if ( sc->sc_tuner == NULL ) 271 panic("no tuner"); 272 273 coram_mpeg_attach(sc); 274 275 if (!pmf_device_register(self, NULL, coram_resume)) 276 aprint_error_dev(self, "couldn't establish power handler\n"); 277 278 return; 279 } 280 281 static int 282 coram_intr(void *v) 283 { 284 device_t self = v; 285 struct coram_softc *sc; 286 uint32_t val; 287 288 sc = device_private(self); 289 290 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSTAT ); 291 if (val == 0) 292 return 0; /* not ours */ 293 294 /* vid c */ 295 if (val & __BIT(2)) 296 coram_mpeg_intr(sc); 297 298 if (val & ~__BIT(2)) 299 printf("%s %08x\n", __func__, val); 300 301 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, val); 302 303 return 1; 304 } 305 306 #define CXDTV_TS_RISCI2 (1 << 4) 307 #define CXDTV_TS_RISCI1 (1 << 0) 308 309 #define CXDTV_TS_RISCI (CXDTV_TS_RISCI1|CXDTV_TS_RISCI2) 310 311 static int 312 coram_mpeg_intr(struct coram_softc *sc) 313 { 314 struct dtv_payload payload; 315 uint32_t s, m, v; 316 int i; 317 318 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT); 319 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 320 321 if ((s & m) == 0) 322 return 0; 323 324 if ( (s & ~CXDTV_TS_RISCI) != 0 ) { 325 printf("%s: unexpected TS IS %08x\n", 326 device_xname(sc->sc_dev), s); 327 328 printf("cmds:\n"); 329 for(i = 0; i < 20; i++) 330 { 331 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x10140 +(i*4)); 332 printf("%06x %08x\n", 0x10140+(i*4), v); 333 } 334 } 335 336 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 337 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 338 0, CORAM_TS_PKTSIZE, 339 BUS_DMASYNC_POSTREAD); 340 payload.data = KERNADDR(sc->sc_dma); 341 payload.size = CORAM_TS_PKTSIZE; 342 dtv_submit_payload(sc->sc_dtvdev, &payload); 343 } 344 345 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 346 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 347 CORAM_TS_PKTSIZE, CORAM_TS_PKTSIZE, 348 BUS_DMASYNC_POSTREAD); 349 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CORAM_TS_PKTSIZE; 350 payload.size = CORAM_TS_PKTSIZE; 351 dtv_submit_payload(sc->sc_dtvdev, &payload); 352 } 353 354 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, s); 355 356 return 1; 357 } 358 359 static bool 360 coram_resume(device_t dv, const pmf_qual_t *qual) 361 { 362 struct coram_softc *sc; 363 sc = device_private(dv); 364 365 device_printf(sc->sc_dev, "%s\n", __func__); 366 367 return true; 368 } 369 370 static int 371 coram_iic_acquire_bus(void *cookie, int flags) 372 { 373 struct coram_iic_softc *cic; 374 375 cic = cookie; 376 377 if (flags & I2C_F_POLL) { 378 while (mutex_tryenter(&cic->cic_busmutex) == 0) 379 delay(50); 380 return 0; 381 } 382 383 mutex_enter(&cic->cic_busmutex); 384 385 return 0; 386 } 387 388 static void 389 coram_iic_release_bus(void *cookie, int flags) 390 { 391 struct coram_iic_softc *cic; 392 393 cic = cookie; 394 395 mutex_exit(&cic->cic_busmutex); 396 397 return; 398 } 399 400 /* I2C Bus */ 401 402 #define I2C_ADDR 0x0000 403 #define I2C_WDATA 0x0004 404 #define I2C_CTRL 0x0008 405 #define I2C_RDATA 0x000c 406 #define I2C_STAT 0x0010 407 408 #define I2C_EXTEND (1 << 3) 409 #define I2C_NOSTOP (1 << 4) 410 411 static int 412 coram_iic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 413 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 414 { 415 struct coram_iic_softc *cic; 416 int ret; 417 418 cic = cookie; 419 420 if(cmdlen) { 421 ret = coram_iic_write(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 422 if(ret) 423 return ret; 424 } 425 426 if(len) { 427 ret = coram_iic_read(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 428 if(ret) 429 return ret; 430 } 431 432 433 return 0; 434 435 } 436 437 static int 438 coram_iic_read(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 439 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 440 { 441 uint8_t *rb; 442 uint32_t ctrl; 443 int bn; 444 445 rb = buf; 446 447 for ( bn = 0; bn < len; bn++) { 448 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2) | 1; 449 if ( bn < len - 1 ) 450 ctrl |= I2C_NOSTOP | I2C_EXTEND; 451 452 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addr<<25); 453 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 454 455 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 456 I2C_STAT) & 0x02)) { 457 delay(25); 458 } 459 if((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 460 I2C_STAT) & 0x01) == 0x00) { 461 // printf("%s %d no ack\n", __func__, bn); 462 return EIO; 463 } 464 465 rb[bn] = bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_RDATA); 466 467 } 468 469 return 0; 470 } 471 472 static int 473 coram_iic_write(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 474 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 475 { 476 const uint8_t *wb; 477 uint32_t wdata, addrreg, ctrl; 478 int bn; 479 480 wb = cmdbuf; 481 482 addrreg = (addr << 25) | wb[0]; 483 wdata = wb[0]; 484 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 485 486 if ( cmdlen > 1 ) 487 ctrl |= I2C_NOSTOP | I2C_EXTEND; 488 else if (len) 489 ctrl |= I2C_NOSTOP; 490 491 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 492 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 493 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 494 495 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 496 delay(25); } 497 498 for ( bn = 1; bn < cmdlen; bn++) { 499 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 500 wdata = wb[bn]; 501 502 if ( bn < cmdlen - 1 ) 503 ctrl |= I2C_NOSTOP | I2C_EXTEND; 504 else if (len) 505 ctrl |= I2C_NOSTOP; 506 507 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 508 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 509 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 510 511 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 512 delay(25); } 513 } 514 515 return 0; 516 } 517 518 static int 519 coram_mpeg_attach(struct coram_softc *sc) 520 { 521 struct dtv_attach_args daa; 522 struct coram_sram_ch *ch; 523 524 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 525 526 sc->sc_riscbufsz = ch->csc_riscsz; 527 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 528 529 if ( sc->sc_riscbuf == NULL ) 530 panic("riscbuf null"); 531 532 coram_mpeg_reset(sc); 533 534 daa.hw = &coram_dtv_if; 535 daa.priv = sc; 536 537 sc->sc_tsbuf = NULL; 538 539 sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus", &daa, dtv_print); 540 541 return (sc->sc_dtvdev != NULL); 542 } 543 544 545 static void 546 coram_dtv_get_devinfo(void *cookie, struct dvb_frontend_info *info) 547 { 548 memset(info, 0, sizeof(*info)); 549 strlcpy(info->name, "CX23885", sizeof(info->name)); 550 info->type = FE_ATSC; 551 info->frequency_min = 54000000; 552 info->frequency_max = 858000000; 553 info->frequency_stepsize = 62500; 554 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 555 } 556 557 static int 558 coram_dtv_open(void *cookie, int flags) 559 { 560 struct coram_softc *sc = cookie; 561 562 device_printf(sc->sc_dev, "%s\n", __func__); 563 564 //KASSERT(sc->sc_tsbuf == NULL); 565 566 coram_mpeg_reset(sc); 567 568 /* allocate two alternating DMA areas for MPEG TS packets */ 569 sc->sc_tsbuf = coram_mpeg_malloc(sc, CORAM_TS_PKTSIZE * 2); 570 571 if (sc->sc_tsbuf == NULL) 572 return ENOMEM; 573 574 return 0; 575 } 576 577 static void 578 coram_dtv_close(void *cookie) 579 { 580 struct coram_softc *sc = cookie; 581 582 device_printf(sc->sc_dev, "%s\n", __func__); 583 584 coram_mpeg_halt(sc); 585 586 if (sc->sc_tsbuf != NULL) { 587 coram_mpeg_free(sc, sc->sc_tsbuf); 588 sc->sc_tsbuf = NULL; 589 } 590 } 591 592 static int 593 coram_dtv_set_tuner(void *cookie, const struct dvb_frontend_parameters *params) 594 { 595 struct coram_softc *sc = cookie; 596 597 KASSERT(sc->sc_tuner != NULL); 598 mt2131_tune_dtv(sc->sc_tuner, params); 599 KASSERT(sc->sc_demod != NULL); 600 cx24227_set_modulation(sc->sc_demod, params->u.vsb.modulation); 601 602 return 0; /* XXX */ 603 } 604 605 static fe_status_t 606 coram_dtv_get_status(void *cookie) 607 { 608 return 0; 609 } 610 611 static uint16_t 612 coram_dtv_get_signal_strength(void *cookie) 613 { 614 return 0; 615 } 616 617 static uint16_t 618 coram_dtv_get_snr(void *cookie) 619 { 620 return 0; 621 } 622 623 static int 624 coram_dtv_start_transfer(void *cookie) 625 { 626 struct coram_softc *sc = cookie; 627 628 device_printf(sc->sc_dev, "%s\n", __func__); 629 630 coram_mpeg_trigger(sc, sc->sc_tsbuf); 631 632 return 0; 633 } 634 635 static int 636 coram_dtv_stop_transfer(void *cookie) 637 { 638 struct coram_softc *sc = cookie; 639 640 device_printf(sc->sc_dev, "%s\n", __func__); 641 642 coram_mpeg_halt(sc); 643 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 644 645 return 0; 646 } 647 648 649 static int 650 coram_mpeg_reset(struct coram_softc *sc) 651 { 652 uint32_t v; 653 654 v = (uint32_t)-1; 655 656 /* hold RISC in reset */ 657 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, 0); 658 659 /* disable fifo + risc */ 660 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 661 662 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 663 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 0); 664 665 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, 0); 666 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, 0); 667 668 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 669 670 return 0; 671 } 672 673 static void * 674 coram_mpeg_malloc(struct coram_softc *sc, size_t size) 675 { 676 struct coram_dma *p; 677 int err; 678 679 p = kmem_alloc(sizeof(struct coram_dma), KM_SLEEP); 680 if ( p == NULL ) 681 return NULL; 682 err = coram_allocmem(sc, size, 16, p); 683 if (err) { 684 kmem_free(p, sizeof(struct coram_dma)); 685 return NULL; 686 } 687 688 p->next = sc->sc_dma; 689 sc->sc_dma = p; 690 691 return KERNADDR(p); 692 } 693 694 static int 695 coram_allocmem(struct coram_softc *sc, size_t size, size_t align, 696 struct coram_dma *p) 697 { 698 int err; 699 700 p->size = size; 701 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 702 p->segs, sizeof(p->segs) / sizeof(p->segs[0]), 703 &p->nsegs, BUS_DMA_NOWAIT); 704 if (err) 705 return err; 706 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 707 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 708 if (err) 709 goto free; 710 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 711 BUS_DMA_NOWAIT, &p->map); 712 if (err) 713 goto unmap; 714 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 715 BUS_DMA_NOWAIT); 716 if (err) 717 goto destroy; 718 719 return 0; 720 destroy: 721 bus_dmamap_destroy(sc->sc_dmat, p->map); 722 unmap: 723 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 724 free: 725 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 726 727 return err; 728 } 729 730 static int 731 coram_mpeg_halt(struct coram_softc *sc) 732 { 733 uint32_t v; 734 735 device_printf(sc->sc_dev, "%s\n", __func__); 736 737 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 738 739 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 740 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 741 v & __BIT(2)); 742 743 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 744 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 745 v & 0); 746 747 return 0; 748 } 749 750 static void 751 coram_mpeg_free(struct coram_softc *sc, void *addr) 752 { 753 struct coram_dma *p; 754 struct coram_dma **pp; 755 756 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) 757 if (KERNADDR(p) == addr) { 758 coram_freemem(sc, p); 759 *pp = p->next; 760 kmem_free(p, sizeof(struct coram_dma)); 761 return; 762 } 763 764 printf("%s: %p is already free\n", device_xname(sc->sc_dev), addr); 765 return; 766 } 767 768 static int 769 coram_freemem(struct coram_softc *sc, struct coram_dma *p) 770 { 771 bus_dmamap_unload(sc->sc_dmat, p->map); 772 bus_dmamap_destroy(sc->sc_dmat, p->map); 773 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 774 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 775 776 return 0; 777 } 778 779 static int 780 coram_mpeg_trigger(struct coram_softc *sc, void *buf) 781 { 782 struct coram_dma *p; 783 struct coram_sram_ch *ch; 784 uint32_t v; 785 786 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 787 788 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 789 continue; 790 if (p == NULL) { 791 printf("%s: coram_mpeg_trigger: bad addr %p\n", 792 device_xname(sc->sc_dev), buf); 793 return ENOENT; 794 } 795 796 /* disable fifo + risc */ 797 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 798 799 coram_risc_buffer(sc, CORAM_TS_PKTSIZE, 1); 800 coram_sram_ch_setup(sc, ch, CORAM_TS_PKTSIZE); 801 802 /* let me hope this bit is the same as on the 2388[0-3] */ 803 /* software reset */ 804 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 0x0040); 805 delay (100*1000); 806 807 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_LNGTH, CORAM_TS_PKTSIZE); 808 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_HW_SOP_CTL, 0x47 << 16 | 188 << 4); 809 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_TS_CLK_EN, 1); 810 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_VLD_MISC, 0); 811 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 12); 812 delay (100*1000); 813 814 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PAD_CTRL); 815 v &= ~0x4; /* Clear TS2_SOP_OE */ 816 bus_space_write_4(sc->sc_memt, sc->sc_memh, PAD_CTRL, v); 817 818 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 819 v |= 0x111111; 820 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, v); 821 822 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL); 823 v |= 0x11; /* Enable RISC controller and FIFO */ 824 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, v); 825 826 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2); 827 v |= __BIT(5); /* Enable RISC controller */ 828 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, v); 829 830 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 831 v |= 0x001f00; 832 v |= 0x04; 833 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, v); 834 835 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 836 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 837 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 838 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 839 delay(100*1000); 840 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 841 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 842 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 843 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 844 845 return 0; 846 } 847 848 static int 849 coram_risc_buffer(struct coram_softc *sc, uint32_t bpl, uint32_t lines) 850 { 851 uint32_t *rm; 852 uint32_t size; 853 854 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 855 size += 2; 856 857 if (sc->sc_riscbuf == NULL) { 858 return ENOMEM; 859 } 860 861 rm = (uint32_t *)sc->sc_riscbuf; 862 coram_risc_field(sc, rm, bpl); 863 864 return 0; 865 } 866 867 static int 868 coram_risc_field(struct coram_softc *sc, uint32_t *rm, uint32_t bpl) 869 { 870 struct coram_dma *p; 871 872 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 873 continue; 874 if (p == NULL) { 875 printf("%s: coram_risc_field: bad addr %p\n", 876 device_xname(sc->sc_dev), sc->sc_tsbuf); 877 return ENOENT; 878 } 879 880 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 881 882 rm = sc->sc_riscbuf; 883 884 /* htole32 will be done when program is copied to chip sram */ 885 886 /* XXX */ 887 *(rm++) = (CX_RISC_SYNC|0); 888 889 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 890 *(rm++) = (DMAADDR(p) + 0 * bpl); 891 *(rm++) = 0; /* high dword */ 892 893 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 894 *(rm++) = (DMAADDR(p) + 1 * bpl); 895 *(rm++) = 0; 896 897 *(rm++) = (CX_RISC_JUMP|1); 898 *(rm++) = (coram_sram_chs[CORAM_SRAM_CH6].csc_risc + 4); 899 *(rm++) = 0; 900 901 return 0; 902 } 903 904 static int 905 coram_sram_ch_setup(struct coram_softc *sc, struct coram_sram_ch *csc, 906 uint32_t bpl) 907 { 908 unsigned int i, lines; 909 uint32_t cdt; 910 911 /* XXX why round? */ 912 bpl = (bpl + 7) & ~7; 913 cdt = csc->csc_cdt; 914 lines = csc->csc_fifosz / bpl; 915 printf("%s %d lines\n", __func__, lines); 916 917 /* fill in CDT */ 918 for (i = 0; i < lines; i++) { 919 #if 1 920 printf("CDT ent %08x, %08x\n", cdt + (16 * i), 921 csc->csc_fifo + (bpl * i)); 922 #endif 923 bus_space_write_4(sc->sc_memt, sc->sc_memh, 924 cdt + (16 * i), csc->csc_fifo + (bpl * i)); 925 } 926 927 /* copy program */ 928 /* converts program to little endian as it goes into sram */ 929 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 930 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 931 932 /* fill in CMDS */ 933 bus_space_write_4(sc->sc_memt, sc->sc_memh, 934 csc->csc_cmds + CMDS_O_IRPC, csc->csc_risc); 935 bus_space_write_4(sc->sc_memt, sc->sc_memh, 936 csc->csc_cmds + CMDS_O_IRPC + 4, 0); 937 938 bus_space_write_4(sc->sc_memt, sc->sc_memh, 939 csc->csc_cmds + CMDS_O_CDTB, csc->csc_cdt); 940 bus_space_write_4(sc->sc_memt, sc->sc_memh, 941 csc->csc_cmds + CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 942 943 bus_space_write_4(sc->sc_memt, sc->sc_memh, 944 csc->csc_cmds + CMDS_O_IQB, csc->csc_iq); 945 bus_space_write_4(sc->sc_memt, sc->sc_memh, 946 csc->csc_cmds + CMDS_O_IQS, 947 CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 948 949 /* zero rest of CMDS */ 950 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x18, 0, 20); 951 952 bus_space_write_4(sc->sc_memt, sc->sc_memh, 953 csc->csc_ptr1, csc->csc_fifo); 954 bus_space_write_4(sc->sc_memt, sc->sc_memh, 955 csc->csc_ptr2, cdt); 956 bus_space_write_4(sc->sc_memt, sc->sc_memh, 957 csc->csc_cnt2, (lines * 16) >> 3); 958 bus_space_write_4(sc->sc_memt, sc->sc_memh, 959 csc->csc_cnt1, (bpl >> 3) - 1); 960 961 return 0; 962 } 963
Indexes created Tue Sep 23 14:10:03 GMT 2025