coram.c revision 1.10
1 /* $NetBSD: coram.c,v 1.10 2012/01/30 19:41:18 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: coram.c,v 1.10 2012/01/30 19:41:18 drochner Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 40 #include <dev/dtv/dtvif.h> 41 42 #include <dev/pci/cx23885reg.h> 43 #include <dev/pci/coramvar.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/i2c/i2cvar.h> 49 #include <dev/i2c/at24cxxvar.h> 50 51 #include <dev/i2c/cx24227var.h> 52 #include <dev/i2c/mt2131var.h> 53 54 /* #define CORAM_DEBUG */ 55 /* #define CORAM_ATTACH_I2C */ 56 57 static const struct coram_board coram_boards[] = { 58 { PCI_VENDOR_HAUPPAUGE, 0x7911, "Hauppauge HVR-1250" }, 59 }; 60 61 static int coram_match(device_t, cfdata_t, void *); 62 static void coram_attach(device_t, device_t, void *); 63 static int coram_detach(device_t, int); 64 static int coram_rescan(device_t, const char *, const int *); 65 static void coram_childdet(device_t, device_t); 66 static bool coram_resume(device_t, const pmf_qual_t *); 67 static int coram_intr(void *); 68 static const struct coram_board * coram_board_lookup(uint16_t, uint16_t); 69 70 static int coram_iic_exec(void *, i2c_op_t, i2c_addr_t, 71 const void *, size_t, void *, size_t, int); 72 static int coram_iic_acquire_bus(void *, int); 73 static void coram_iic_release_bus(void *, int); 74 static int coram_iic_read(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 75 const void *, size_t, void *, size_t, int); 76 static int coram_iic_write(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 77 const void *, size_t, void *, size_t, int); 78 79 static void coram_dtv_get_devinfo(void *, struct dvb_frontend_info *); 80 static int coram_dtv_open(void *, int); 81 static void coram_dtv_close(void *); 82 static int coram_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 83 static fe_status_t coram_dtv_get_status(void *); 84 static uint16_t coram_dtv_get_signal_strength(void *); 85 static uint16_t coram_dtv_get_snr(void *); 86 static int coram_dtv_start_transfer(void *, void (*)(void *, const struct dtv_payload *), void *); 87 static int coram_dtv_stop_transfer(void *); 88 89 static int coram_mpeg_attach(struct coram_softc *); 90 static int coram_mpeg_detach(struct coram_softc *, int); 91 static int coram_mpeg_reset(struct coram_softc *); 92 static void * coram_mpeg_malloc(struct coram_softc *, size_t); 93 static int coram_allocmem(struct coram_softc *, size_t, size_t, struct coram_dma *); 94 static void coram_mpeg_free(struct coram_softc *, void *); 95 static int coram_mpeg_halt(struct coram_softc *); 96 static int coram_freemem(struct coram_softc *, struct coram_dma *); 97 static int coram_mpeg_trigger(struct coram_softc *, void *); 98 static int coram_risc_buffer(struct coram_softc *, uint32_t, uint32_t); 99 static int coram_risc_field(struct coram_softc *, uint32_t *, uint32_t); 100 static int coram_sram_ch_setup(struct coram_softc *, struct coram_sram_ch *, uint32_t); 101 static int coram_mpeg_intr(struct coram_softc *); 102 103 CFATTACH_DECL2_NEW(coram, sizeof(struct coram_softc), 104 coram_match, coram_attach, coram_detach, NULL, 105 coram_rescan, coram_childdet); 106 107 #define CORAM_SRAM_CH6 0 108 109 #define CORAM_TS_PKTSIZE (188 * 8) 110 111 static struct coram_sram_ch coram_sram_chs[] = { 112 [CORAM_SRAM_CH6] = { 113 .csc_cmds= 0x10140, 114 .csc_iq = 0x10500, 115 .csc_iqsz = 0x40, 116 .csc_cdt = 0x10600, 117 .csc_cdtsz = 0x10, 118 .csc_fifo = 0x6000, 119 .csc_fifosz = 0x1000, 120 .csc_risc = 0x10800, 121 .csc_riscsz = 0x800, 122 .csc_ptr1 = DMA5_PTR1, 123 .csc_ptr2 = DMA5_PTR2, 124 .csc_cnt1 = DMA5_CNT1, 125 .csc_cnt2 = DMA5_CNT2, 126 }, 127 }; 128 129 static const struct dtv_hw_if coram_dtv_if = { 130 .get_devinfo = coram_dtv_get_devinfo, 131 .open = coram_dtv_open, 132 .close = coram_dtv_close, 133 .set_tuner = coram_dtv_set_tuner, 134 .get_status = coram_dtv_get_status, 135 .get_signal_strength = coram_dtv_get_signal_strength, 136 .get_snr = coram_dtv_get_snr, 137 .start_transfer = coram_dtv_start_transfer, 138 .stop_transfer = coram_dtv_stop_transfer, 139 }; 140 141 static int 142 coram_match(device_t parent, cfdata_t match, void *v) 143 { 144 const struct pci_attach_args *pa = v; 145 pcireg_t subid; 146 147 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 148 return 0; 149 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX23885) 150 return 0; 151 152 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 153 if (coram_board_lookup(PCI_VENDOR(subid), PCI_PRODUCT(subid)) == NULL) 154 return 0; 155 156 return 1; 157 } 158 159 static void 160 coram_attach(device_t parent, device_t self, void *v) 161 { 162 struct coram_softc *sc = device_private(self); 163 const struct pci_attach_args *pa = v; 164 pci_intr_handle_t ih; 165 pcireg_t reg; 166 const char *intrstr; 167 struct coram_iic_softc *cic; 168 uint32_t value; 169 int i; 170 #ifdef CORAM_ATTACH_I2C 171 struct i2cbus_attach_args iba; 172 #endif 173 174 sc->sc_dev = self; 175 176 pci_aprint_devinfo(pa, NULL); 177 178 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 179 sc->sc_board = coram_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)); 180 KASSERT(sc->sc_board != NULL); 181 182 if (pci_mapreg_map(pa, CX23885_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 183 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 184 aprint_error_dev(self, "couldn't map memory space\n"); 185 return; 186 } 187 188 sc->sc_dmat = pa->pa_dmat; 189 sc->sc_pc = pa->pa_pc; 190 191 if (pci_intr_map(pa, &ih)) { 192 aprint_error_dev(self, "couldn't map interrupt\n"); 193 return; 194 } 195 intrstr = pci_intr_string(pa->pa_pc, ih); 196 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_VM, 197 coram_intr, (void *)self); 198 if (sc->sc_ih == NULL) { 199 aprint_error_dev(self, "couldn't establish interrupt"); 200 if (intrstr != NULL) 201 aprint_error(" at %s", intrstr); 202 aprint_error("\n"); 203 return; 204 } 205 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 206 207 /* set master */ 208 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 209 reg |= PCI_COMMAND_MASTER_ENABLE; 210 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 211 212 /* I2C */ 213 for(i = 0; i < I2C_NUM; i++) { 214 cic = &sc->sc_iic[i]; 215 216 cic->cic_sc = sc; 217 if(bus_space_subregion(sc->sc_memt, sc->sc_memh, I2C_BASE + (I2C_SIZE * i), I2C_SIZE, &cic->cic_regh)) 218 panic("failed to subregion i2c"); 219 220 mutex_init(&cic->cic_busmutex, MUTEX_DRIVER, IPL_NONE); 221 cic->cic_i2c.ic_cookie = cic; 222 cic->cic_i2c.ic_acquire_bus = coram_iic_acquire_bus; 223 cic->cic_i2c.ic_release_bus = coram_iic_release_bus; 224 cic->cic_i2c.ic_exec = coram_iic_exec; 225 226 #ifdef CORAM_ATTACH_I2C 227 /* attach iic(4) */ 228 memset(&iba, 0, sizeof(iba)); 229 iba.iba_tag = &cic->cic_i2c; 230 iba.iba_type = I2C_TYPE_SMBUS; 231 cic->cic_i2cdev = config_found_ia(self, "i2cbus", 232 &iba, iicbus_print); 233 #endif 234 } 235 236 /* HVR1250 GPIO */ 237 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x110010); 238 #if 1 239 value &= ~0x00010001; 240 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 241 delay(5000); 242 #endif 243 value |= 0x00010001; 244 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 245 246 #if 0 247 int i; 248 uint8_t foo[256]; 249 uint8_t bar; 250 bar = 0; 251 // seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0, 256, foo, 256); 252 253 iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL); 254 iic_exec(&sc->sc_i2c, I2C_OP_READ_WITH_STOP, 0x50, &bar, 1, foo, 256, I2C_F_POLL); 255 iic_release_bus(&sc->sc_i2c, I2C_F_POLL); 256 257 printf("\n"); 258 for ( i = 0; i < 256; i++) { 259 if ( (i % 8) == 0 ) 260 printf("%02x: ", i); 261 262 printf("%02x", foo[i]); 263 264 if ( (i % 8) == 7 ) 265 printf("\n"); 266 else 267 printf(" "); 268 } 269 printf("\n"); 270 #endif 271 272 sc->sc_demod = cx24227_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x19); 273 if (sc->sc_demod == NULL) 274 aprint_error_dev(self, "couldn't open cx24227\n"); 275 sc->sc_tuner = mt2131_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x61); 276 if (sc->sc_tuner == NULL) 277 aprint_error_dev(self, "couldn't open mt2131\n"); 278 279 coram_mpeg_attach(sc); 280 281 if (!pmf_device_register(self, NULL, coram_resume)) 282 aprint_error_dev(self, "couldn't establish power handler\n"); 283 284 return; 285 } 286 287 static int 288 coram_detach(device_t self, int flags) 289 { 290 struct coram_softc *sc = device_private(self); 291 struct coram_iic_softc *cic; 292 unsigned int i; 293 int error; 294 295 error = coram_mpeg_detach(sc, flags); 296 if (error) 297 return error; 298 299 if (sc->sc_tuner) 300 mt2131_close(sc->sc_tuner); 301 if (sc->sc_demod) 302 cx24227_close(sc->sc_demod); 303 for (i = 0; i < I2C_NUM; i++) { 304 cic = &sc->sc_iic[i]; 305 if (cic->cic_i2cdev) 306 config_detach(cic->cic_i2cdev, flags); 307 mutex_destroy(&cic->cic_busmutex); 308 } 309 pmf_device_deregister(self); 310 311 if (sc->sc_mems) 312 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 313 if (sc->sc_ih) 314 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 315 316 return 0; 317 } 318 319 static int 320 coram_rescan(device_t self, const char *ifattr, const int *locs) 321 { 322 struct coram_softc *sc = device_private(self); 323 struct dtv_attach_args daa; 324 325 daa.hw = &coram_dtv_if; 326 daa.priv = sc; 327 328 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL) 329 sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus", 330 &daa, dtv_print); 331 332 return 0; 333 } 334 335 static void 336 coram_childdet(device_t self, device_t child) 337 { 338 struct coram_softc *sc = device_private(self); 339 struct coram_iic_softc *cic; 340 unsigned int i; 341 342 if (sc->sc_dtvdev == child) 343 sc->sc_dtvdev = NULL; 344 345 for (i = 0; i < I2C_NUM; i++) { 346 cic = &sc->sc_iic[i]; 347 if (cic->cic_i2cdev == child) 348 cic->cic_i2cdev = NULL; 349 } 350 } 351 352 static int 353 coram_intr(void *v) 354 { 355 device_t self = v; 356 struct coram_softc *sc; 357 uint32_t val; 358 359 sc = device_private(self); 360 361 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSTAT ); 362 if (val == 0) 363 return 0; /* not ours */ 364 365 /* vid c */ 366 if (val & __BIT(2)) 367 coram_mpeg_intr(sc); 368 369 if (val & ~__BIT(2)) 370 printf("%s %08x\n", __func__, val); 371 372 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, val); 373 374 return 1; 375 } 376 377 static const struct coram_board * 378 coram_board_lookup(uint16_t vendor, uint16_t product) 379 { 380 unsigned int i; 381 382 for (i = 0; i < __arraycount(coram_boards); i++) { 383 if (coram_boards[i].vendor == vendor && 384 coram_boards[i].product == product) { 385 return &coram_boards[i]; 386 } 387 } 388 389 return NULL; 390 } 391 392 #define CXDTV_TS_RISCI2 (1 << 4) 393 #define CXDTV_TS_RISCI1 (1 << 0) 394 395 #define CXDTV_TS_RISCI (CXDTV_TS_RISCI1|CXDTV_TS_RISCI2) 396 397 static int 398 coram_mpeg_intr(struct coram_softc *sc) 399 { 400 struct dtv_payload payload; 401 uint32_t s, m, v; 402 int i; 403 404 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT); 405 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 406 407 if ((s & m) == 0) 408 return 0; 409 410 if ( (s & ~CXDTV_TS_RISCI) != 0 ) { 411 printf("%s: unexpected TS IS %08x\n", 412 device_xname(sc->sc_dev), s); 413 414 printf("cmds:\n"); 415 for(i = 0; i < 20; i++) 416 { 417 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x10140 +(i*4)); 418 printf("%06x %08x\n", 0x10140+(i*4), v); 419 } 420 } 421 422 if (sc->sc_dtvsubmitcb == NULL) 423 goto done; 424 425 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 426 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 427 0, CORAM_TS_PKTSIZE, 428 BUS_DMASYNC_POSTREAD); 429 payload.data = KERNADDR(sc->sc_dma); 430 payload.size = CORAM_TS_PKTSIZE; 431 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 432 } 433 434 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 435 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 436 CORAM_TS_PKTSIZE, CORAM_TS_PKTSIZE, 437 BUS_DMASYNC_POSTREAD); 438 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CORAM_TS_PKTSIZE; 439 payload.size = CORAM_TS_PKTSIZE; 440 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 441 } 442 443 done: 444 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, s); 445 446 return 1; 447 } 448 449 static bool 450 coram_resume(device_t dv, const pmf_qual_t *qual) 451 { 452 struct coram_softc *sc; 453 sc = device_private(dv); 454 455 return true; 456 } 457 458 static int 459 coram_iic_acquire_bus(void *cookie, int flags) 460 { 461 struct coram_iic_softc *cic; 462 463 cic = cookie; 464 465 if (flags & I2C_F_POLL) { 466 while (mutex_tryenter(&cic->cic_busmutex) == 0) 467 delay(50); 468 return 0; 469 } 470 471 mutex_enter(&cic->cic_busmutex); 472 473 return 0; 474 } 475 476 static void 477 coram_iic_release_bus(void *cookie, int flags) 478 { 479 struct coram_iic_softc *cic; 480 481 cic = cookie; 482 483 mutex_exit(&cic->cic_busmutex); 484 485 return; 486 } 487 488 /* I2C Bus */ 489 490 #define I2C_ADDR 0x0000 491 #define I2C_WDATA 0x0004 492 #define I2C_CTRL 0x0008 493 #define I2C_RDATA 0x000c 494 #define I2C_STAT 0x0010 495 496 #define I2C_EXTEND (1 << 3) 497 #define I2C_NOSTOP (1 << 4) 498 499 static int 500 coram_iic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 501 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 502 { 503 struct coram_iic_softc *cic; 504 int ret; 505 506 cic = cookie; 507 508 if(cmdlen) { 509 ret = coram_iic_write(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 510 if(ret) 511 return ret; 512 } 513 514 if(len) { 515 ret = coram_iic_read(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 516 if(ret) 517 return ret; 518 } 519 520 521 return 0; 522 523 } 524 525 static int 526 coram_iic_read(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 527 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 528 { 529 uint8_t *rb; 530 uint32_t ctrl; 531 int bn; 532 533 rb = buf; 534 535 for ( bn = 0; bn < len; bn++) { 536 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2) | 1; 537 if ( bn < len - 1 ) 538 ctrl |= I2C_NOSTOP | I2C_EXTEND; 539 540 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addr<<25); 541 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 542 543 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 544 I2C_STAT) & 0x02)) { 545 delay(25); 546 } 547 if((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 548 I2C_STAT) & 0x01) == 0x00) { 549 // printf("%s %d no ack\n", __func__, bn); 550 return EIO; 551 } 552 553 rb[bn] = bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_RDATA); 554 555 } 556 557 return 0; 558 } 559 560 static int 561 coram_iic_write(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 562 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 563 { 564 const uint8_t *wb; 565 uint32_t wdata, addrreg, ctrl; 566 int bn; 567 568 wb = cmdbuf; 569 570 addrreg = (addr << 25) | wb[0]; 571 wdata = wb[0]; 572 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 573 574 if ( cmdlen > 1 ) 575 ctrl |= I2C_NOSTOP | I2C_EXTEND; 576 else if (len) 577 ctrl |= I2C_NOSTOP; 578 579 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 580 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 581 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 582 583 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 584 delay(25); } 585 586 for ( bn = 1; bn < cmdlen; bn++) { 587 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 588 wdata = wb[bn]; 589 590 if ( bn < cmdlen - 1 ) 591 ctrl |= I2C_NOSTOP | I2C_EXTEND; 592 else if (len) 593 ctrl |= I2C_NOSTOP; 594 595 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 596 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 597 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 598 599 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 600 delay(25); } 601 } 602 603 return 0; 604 } 605 606 static int 607 coram_mpeg_attach(struct coram_softc *sc) 608 { 609 struct coram_sram_ch *ch; 610 611 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 612 613 sc->sc_riscbufsz = ch->csc_riscsz; 614 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 615 616 if ( sc->sc_riscbuf == NULL ) 617 panic("riscbuf null"); 618 619 coram_mpeg_reset(sc); 620 621 sc->sc_tsbuf = NULL; 622 623 coram_rescan(sc->sc_dev, NULL, NULL); 624 625 return (sc->sc_dtvdev != NULL); 626 } 627 628 static int 629 coram_mpeg_detach(struct coram_softc *sc, int flags) 630 { 631 struct coram_sram_ch *ch = &coram_sram_chs[CORAM_SRAM_CH6]; 632 int error; 633 634 if (sc->sc_dtvdev) { 635 error = config_detach(sc->sc_dtvdev, flags); 636 if (error) 637 return error; 638 } 639 if (sc->sc_riscbuf) { 640 kmem_free(sc->sc_riscbuf, ch->csc_riscsz); 641 } 642 643 return 0; 644 } 645 646 static void 647 coram_dtv_get_devinfo(void *cookie, struct dvb_frontend_info *info) 648 { 649 struct coram_softc *sc = cookie; 650 651 memset(info, 0, sizeof(*info)); 652 strlcpy(info->name, sc->sc_board->name, sizeof(info->name)); 653 info->type = FE_ATSC; 654 info->frequency_min = 54000000; 655 info->frequency_max = 858000000; 656 info->frequency_stepsize = 62500; 657 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 658 } 659 660 static int 661 coram_dtv_open(void *cookie, int flags) 662 { 663 struct coram_softc *sc = cookie; 664 665 #ifdef CORAM_DEBUG 666 device_printf(sc->sc_dev, "%s\n", __func__); 667 #endif 668 669 //KASSERT(sc->sc_tsbuf == NULL); 670 671 if (sc->sc_tuner == NULL || sc->sc_demod == NULL) 672 return ENXIO; 673 674 coram_mpeg_reset(sc); 675 676 /* allocate two alternating DMA areas for MPEG TS packets */ 677 sc->sc_tsbuf = coram_mpeg_malloc(sc, CORAM_TS_PKTSIZE * 2); 678 679 if (sc->sc_tsbuf == NULL) 680 return ENOMEM; 681 682 return 0; 683 } 684 685 static void 686 coram_dtv_close(void *cookie) 687 { 688 struct coram_softc *sc = cookie; 689 690 #ifdef CORAM_DEBUG 691 device_printf(sc->sc_dev, "%s\n", __func__); 692 #endif 693 694 coram_mpeg_halt(sc); 695 696 if (sc->sc_tsbuf != NULL) { 697 coram_mpeg_free(sc, sc->sc_tsbuf); 698 sc->sc_tsbuf = NULL; 699 } 700 } 701 702 static int 703 coram_dtv_set_tuner(void *cookie, const struct dvb_frontend_parameters *params) 704 { 705 struct coram_softc *sc = cookie; 706 707 KASSERT(sc->sc_tuner != NULL); 708 mt2131_tune_dtv(sc->sc_tuner, params); 709 KASSERT(sc->sc_demod != NULL); 710 return cx24227_set_modulation(sc->sc_demod, params->u.vsb.modulation); 711 } 712 713 static fe_status_t 714 coram_dtv_get_status(void *cookie) 715 { 716 struct coram_softc *sc = cookie; 717 718 if (sc->sc_demod == NULL) 719 return ENXIO; 720 721 return cx24227_get_dtv_status(sc->sc_demod);; 722 } 723 724 static uint16_t 725 coram_dtv_get_signal_strength(void *cookie) 726 { 727 return 0; 728 } 729 730 static uint16_t 731 coram_dtv_get_snr(void *cookie) 732 { 733 return 0; 734 } 735 736 static int 737 coram_dtv_start_transfer(void *cookie, 738 void (*cb)(void *, const struct dtv_payload *), void *arg) 739 { 740 struct coram_softc *sc = cookie; 741 742 #ifdef CORAM_DEBUG 743 device_printf(sc->sc_dev, "%s\n", __func__); 744 #endif 745 746 sc->sc_dtvsubmitcb = cb; 747 sc->sc_dtvsubmitarg = arg; 748 749 coram_mpeg_trigger(sc, sc->sc_tsbuf); 750 751 return 0; 752 } 753 754 static int 755 coram_dtv_stop_transfer(void *cookie) 756 { 757 struct coram_softc *sc = cookie; 758 759 #ifdef CORAM_DEBUG 760 device_printf(sc->sc_dev, "%s\n", __func__); 761 #endif 762 763 coram_mpeg_halt(sc); 764 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 765 766 sc->sc_dtvsubmitcb = NULL; 767 sc->sc_dtvsubmitarg = NULL; 768 769 return 0; 770 } 771 772 773 static int 774 coram_mpeg_reset(struct coram_softc *sc) 775 { 776 uint32_t v; 777 778 v = (uint32_t)-1; 779 780 /* hold RISC in reset */ 781 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, 0); 782 783 /* disable fifo + risc */ 784 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 785 786 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 787 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 0); 788 789 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, 0); 790 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, 0); 791 792 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 793 794 return 0; 795 } 796 797 static void * 798 coram_mpeg_malloc(struct coram_softc *sc, size_t size) 799 { 800 struct coram_dma *p; 801 int err; 802 803 p = kmem_alloc(sizeof(struct coram_dma), KM_SLEEP); 804 if ( p == NULL ) 805 return NULL; 806 err = coram_allocmem(sc, size, 16, p); 807 if (err) { 808 kmem_free(p, sizeof(struct coram_dma)); 809 return NULL; 810 } 811 812 p->next = sc->sc_dma; 813 sc->sc_dma = p; 814 815 return KERNADDR(p); 816 } 817 818 static int 819 coram_allocmem(struct coram_softc *sc, size_t size, size_t align, 820 struct coram_dma *p) 821 { 822 int err; 823 824 p->size = size; 825 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 826 p->segs, sizeof(p->segs) / sizeof(p->segs[0]), 827 &p->nsegs, BUS_DMA_NOWAIT); 828 if (err) 829 return err; 830 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 831 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 832 if (err) 833 goto free; 834 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 835 BUS_DMA_NOWAIT, &p->map); 836 if (err) 837 goto unmap; 838 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 839 BUS_DMA_NOWAIT); 840 if (err) 841 goto destroy; 842 843 return 0; 844 destroy: 845 bus_dmamap_destroy(sc->sc_dmat, p->map); 846 unmap: 847 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 848 free: 849 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 850 851 return err; 852 } 853 854 static int 855 coram_mpeg_halt(struct coram_softc *sc) 856 { 857 uint32_t v; 858 859 #ifdef CORAM_DEBUG 860 device_printf(sc->sc_dev, "%s\n", __func__); 861 #endif 862 863 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 864 865 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 866 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 867 v & __BIT(2)); 868 869 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 870 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 871 v & 0); 872 873 return 0; 874 } 875 876 static void 877 coram_mpeg_free(struct coram_softc *sc, void *addr) 878 { 879 struct coram_dma *p; 880 struct coram_dma **pp; 881 882 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) 883 if (KERNADDR(p) == addr) { 884 coram_freemem(sc, p); 885 *pp = p->next; 886 kmem_free(p, sizeof(struct coram_dma)); 887 return; 888 } 889 890 printf("%s: %p is already free\n", device_xname(sc->sc_dev), addr); 891 return; 892 } 893 894 static int 895 coram_freemem(struct coram_softc *sc, struct coram_dma *p) 896 { 897 bus_dmamap_unload(sc->sc_dmat, p->map); 898 bus_dmamap_destroy(sc->sc_dmat, p->map); 899 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 900 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 901 902 return 0; 903 } 904 905 static int 906 coram_mpeg_trigger(struct coram_softc *sc, void *buf) 907 { 908 struct coram_dma *p; 909 struct coram_sram_ch *ch; 910 uint32_t v; 911 912 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 913 914 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 915 continue; 916 if (p == NULL) { 917 printf("%s: coram_mpeg_trigger: bad addr %p\n", 918 device_xname(sc->sc_dev), buf); 919 return ENOENT; 920 } 921 922 /* disable fifo + risc */ 923 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 924 925 coram_risc_buffer(sc, CORAM_TS_PKTSIZE, 1); 926 coram_sram_ch_setup(sc, ch, CORAM_TS_PKTSIZE); 927 928 /* let me hope this bit is the same as on the 2388[0-3] */ 929 /* software reset */ 930 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 0x0040); 931 delay (100*1000); 932 933 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_LNGTH, CORAM_TS_PKTSIZE); 934 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_HW_SOP_CTL, 0x47 << 16 | 188 << 4); 935 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_TS_CLK_EN, 1); 936 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_VLD_MISC, 0); 937 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 12); 938 delay (100*1000); 939 940 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PAD_CTRL); 941 v &= ~0x4; /* Clear TS2_SOP_OE */ 942 bus_space_write_4(sc->sc_memt, sc->sc_memh, PAD_CTRL, v); 943 944 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 945 v |= 0x111111; 946 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, v); 947 948 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL); 949 v |= 0x11; /* Enable RISC controller and FIFO */ 950 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, v); 951 952 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2); 953 v |= __BIT(5); /* Enable RISC controller */ 954 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, v); 955 956 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 957 v |= 0x001f00; 958 v |= 0x04; 959 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, v); 960 961 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 962 #ifdef CORAM_DEBUG 963 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 964 #endif 965 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 966 #ifdef CORAM_DEBUG 967 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 968 #endif 969 delay(100*1000); 970 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 971 #ifdef CORAM_DEBUG 972 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 973 #endif 974 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 975 #ifdef CORAM_DEBUG 976 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 977 #endif 978 979 return 0; 980 } 981 982 static int 983 coram_risc_buffer(struct coram_softc *sc, uint32_t bpl, uint32_t lines) 984 { 985 uint32_t *rm; 986 uint32_t size; 987 988 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 989 size += 2; 990 991 if (sc->sc_riscbuf == NULL) { 992 return ENOMEM; 993 } 994 995 rm = (uint32_t *)sc->sc_riscbuf; 996 coram_risc_field(sc, rm, bpl); 997 998 return 0; 999 } 1000 1001 static int 1002 coram_risc_field(struct coram_softc *sc, uint32_t *rm, uint32_t bpl) 1003 { 1004 struct coram_dma *p; 1005 1006 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 1007 continue; 1008 if (p == NULL) { 1009 printf("%s: coram_risc_field: bad addr %p\n", 1010 device_xname(sc->sc_dev), sc->sc_tsbuf); 1011 return ENOENT; 1012 } 1013 1014 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 1015 1016 rm = sc->sc_riscbuf; 1017 1018 /* htole32 will be done when program is copied to chip sram */ 1019 1020 /* XXX */ 1021 *(rm++) = (CX_RISC_SYNC|0); 1022 1023 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 1024 *(rm++) = (DMAADDR(p) + 0 * bpl); 1025 *(rm++) = 0; /* high dword */ 1026 1027 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 1028 *(rm++) = (DMAADDR(p) + 1 * bpl); 1029 *(rm++) = 0; 1030 1031 *(rm++) = (CX_RISC_JUMP|1); 1032 *(rm++) = (coram_sram_chs[CORAM_SRAM_CH6].csc_risc + 4); 1033 *(rm++) = 0; 1034 1035 return 0; 1036 } 1037 1038 static int 1039 coram_sram_ch_setup(struct coram_softc *sc, struct coram_sram_ch *csc, 1040 uint32_t bpl) 1041 { 1042 unsigned int i, lines; 1043 uint32_t cdt; 1044 1045 /* XXX why round? */ 1046 bpl = (bpl + 7) & ~7; 1047 cdt = csc->csc_cdt; 1048 lines = csc->csc_fifosz / bpl; 1049 #ifdef CORAM_DEBUG 1050 printf("%s %d lines\n", __func__, lines); 1051 #endif 1052 1053 /* fill in CDT */ 1054 for (i = 0; i < lines; i++) { 1055 #ifdef CORAM_DEBUG 1056 printf("CDT ent %08x, %08x\n", cdt + (16 * i), 1057 csc->csc_fifo + (bpl * i)); 1058 #endif 1059 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1060 cdt + (16 * i), csc->csc_fifo + (bpl * i)); 1061 } 1062 1063 /* copy program */ 1064 /* converts program to little endian as it goes into sram */ 1065 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 1066 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 1067 1068 /* fill in CMDS */ 1069 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1070 csc->csc_cmds + CMDS_O_IRPC, csc->csc_risc); 1071 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1072 csc->csc_cmds + CMDS_O_IRPC + 4, 0); 1073 1074 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1075 csc->csc_cmds + CMDS_O_CDTB, csc->csc_cdt); 1076 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1077 csc->csc_cmds + CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 1078 1079 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1080 csc->csc_cmds + CMDS_O_IQB, csc->csc_iq); 1081 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1082 csc->csc_cmds + CMDS_O_IQS, 1083 CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 1084 1085 /* zero rest of CMDS */ 1086 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x18, 0, 20); 1087 1088 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1089 csc->csc_ptr1, csc->csc_fifo); 1090 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1091 csc->csc_ptr2, cdt); 1092 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1093 csc->csc_cnt2, (lines * 16) >> 3); 1094 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1095 csc->csc_cnt1, (bpl >> 3) - 1); 1096 1097 return 0; 1098 } 1099 1100 MODULE(MODULE_CLASS_DRIVER, coram, "cx24227,mt2131,pci"); 1101 1102 #ifdef _MODULE 1103 #include "ioconf.c" 1104 #endif 1105 1106 static int 1107 coram_modcmd(modcmd_t cmd, void *v) 1108 { 1109 int error = 0; 1110 1111 switch (cmd) { 1112 case MODULE_CMD_INIT: 1113 #ifdef _MODULE 1114 error = config_init_component(cfdriver_ioconf_coram, 1115 cfattach_ioconf_coram, cfdata_ioconf_coram); 1116 #endif 1117 return error; 1118 case MODULE_CMD_FINI: 1119 #ifdef _MODULE 1120 error = config_fini_component(cfdriver_ioconf_coram, 1121 cfattach_ioconf_coram, cfdata_ioconf_coram); 1122 #endif 1123 return error; 1124 default: 1125 return ENOTTY; 1126 } 1127 } 1128
Indexes created Tue Sep 23 23:09:58 GMT 2025