coram.c revision 1.11
1 /* $NetBSD: coram.c,v 1.11 2012/10/29 12:59:43 chs Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: coram.c,v 1.11 2012/10/29 12:59:43 chs Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 40 #include <dev/dtv/dtvif.h> 41 42 #include <dev/pci/cx23885reg.h> 43 #include <dev/pci/coramvar.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/i2c/i2cvar.h> 49 #include <dev/i2c/at24cxxvar.h> 50 51 #include <dev/i2c/cx24227var.h> 52 #include <dev/i2c/mt2131var.h> 53 54 /* #define CORAM_DEBUG */ 55 /* #define CORAM_ATTACH_I2C */ 56 57 static const struct coram_board coram_boards[] = { 58 { PCI_VENDOR_HAUPPAUGE, 0x7911, "Hauppauge HVR-1250" }, 59 }; 60 61 static int coram_match(device_t, cfdata_t, void *); 62 static void coram_attach(device_t, device_t, void *); 63 static int coram_detach(device_t, int); 64 static int coram_rescan(device_t, const char *, const int *); 65 static void coram_childdet(device_t, device_t); 66 static bool coram_resume(device_t, const pmf_qual_t *); 67 static int coram_intr(void *); 68 static const struct coram_board * coram_board_lookup(uint16_t, uint16_t); 69 70 static int coram_iic_exec(void *, i2c_op_t, i2c_addr_t, 71 const void *, size_t, void *, size_t, int); 72 static int coram_iic_acquire_bus(void *, int); 73 static void coram_iic_release_bus(void *, int); 74 static int coram_iic_read(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 75 const void *, size_t, void *, size_t, int); 76 static int coram_iic_write(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 77 const void *, size_t, void *, size_t, int); 78 79 static void coram_dtv_get_devinfo(void *, struct dvb_frontend_info *); 80 static int coram_dtv_open(void *, int); 81 static void coram_dtv_close(void *); 82 static int coram_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 83 static fe_status_t coram_dtv_get_status(void *); 84 static uint16_t coram_dtv_get_signal_strength(void *); 85 static uint16_t coram_dtv_get_snr(void *); 86 static int coram_dtv_start_transfer(void *, void (*)(void *, const struct dtv_payload *), void *); 87 static int coram_dtv_stop_transfer(void *); 88 89 static int coram_mpeg_attach(struct coram_softc *); 90 static int coram_mpeg_detach(struct coram_softc *, int); 91 static int coram_mpeg_reset(struct coram_softc *); 92 static void * coram_mpeg_malloc(struct coram_softc *, size_t); 93 static int coram_allocmem(struct coram_softc *, size_t, size_t, struct coram_dma *); 94 static void coram_mpeg_free(struct coram_softc *, void *); 95 static int coram_mpeg_halt(struct coram_softc *); 96 static int coram_freemem(struct coram_softc *, struct coram_dma *); 97 static int coram_mpeg_trigger(struct coram_softc *, void *); 98 static int coram_risc_buffer(struct coram_softc *, uint32_t, uint32_t); 99 static int coram_risc_field(struct coram_softc *, uint32_t *, uint32_t); 100 static int coram_sram_ch_setup(struct coram_softc *, struct coram_sram_ch *, uint32_t); 101 static int coram_mpeg_intr(struct coram_softc *); 102 103 CFATTACH_DECL2_NEW(coram, sizeof(struct coram_softc), 104 coram_match, coram_attach, coram_detach, NULL, 105 coram_rescan, coram_childdet); 106 107 #define CORAM_SRAM_CH6 0 108 109 #define CORAM_TS_PKTSIZE (188 * 8) 110 111 static struct coram_sram_ch coram_sram_chs[] = { 112 [CORAM_SRAM_CH6] = { 113 .csc_cmds= 0x10140, 114 .csc_iq = 0x10500, 115 .csc_iqsz = 0x40, 116 .csc_cdt = 0x10600, 117 .csc_cdtsz = 0x10, 118 .csc_fifo = 0x6000, 119 .csc_fifosz = 0x1000, 120 .csc_risc = 0x10800, 121 .csc_riscsz = 0x800, 122 .csc_ptr1 = DMA5_PTR1, 123 .csc_ptr2 = DMA5_PTR2, 124 .csc_cnt1 = DMA5_CNT1, 125 .csc_cnt2 = DMA5_CNT2, 126 }, 127 }; 128 129 static const struct dtv_hw_if coram_dtv_if = { 130 .get_devinfo = coram_dtv_get_devinfo, 131 .open = coram_dtv_open, 132 .close = coram_dtv_close, 133 .set_tuner = coram_dtv_set_tuner, 134 .get_status = coram_dtv_get_status, 135 .get_signal_strength = coram_dtv_get_signal_strength, 136 .get_snr = coram_dtv_get_snr, 137 .start_transfer = coram_dtv_start_transfer, 138 .stop_transfer = coram_dtv_stop_transfer, 139 }; 140 141 static int 142 coram_match(device_t parent, cfdata_t match, void *v) 143 { 144 const struct pci_attach_args *pa = v; 145 pcireg_t subid; 146 147 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 148 return 0; 149 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX23885) 150 return 0; 151 152 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 153 if (coram_board_lookup(PCI_VENDOR(subid), PCI_PRODUCT(subid)) == NULL) 154 return 0; 155 156 return 1; 157 } 158 159 static void 160 coram_attach(device_t parent, device_t self, void *aux) 161 { 162 struct coram_softc *sc = device_private(self); 163 const struct pci_attach_args *pa = aux; 164 pci_intr_handle_t ih; 165 pcireg_t reg; 166 const char *intrstr; 167 struct coram_iic_softc *cic; 168 uint32_t value; 169 int i; 170 #ifdef CORAM_ATTACH_I2C 171 struct i2cbus_attach_args iba; 172 #endif 173 174 sc->sc_dev = self; 175 176 pci_aprint_devinfo(pa, NULL); 177 178 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 179 sc->sc_board = coram_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)); 180 KASSERT(sc->sc_board != NULL); 181 182 if (pci_mapreg_map(pa, CX23885_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 183 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 184 aprint_error_dev(self, "couldn't map memory space\n"); 185 return; 186 } 187 188 sc->sc_dmat = pa->pa_dmat; 189 sc->sc_pc = pa->pa_pc; 190 191 if (pci_intr_map(pa, &ih)) { 192 aprint_error_dev(self, "couldn't map interrupt\n"); 193 return; 194 } 195 intrstr = pci_intr_string(pa->pa_pc, ih); 196 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_VM, coram_intr, self); 197 if (sc->sc_ih == NULL) { 198 aprint_error_dev(self, "couldn't establish interrupt"); 199 if (intrstr != NULL) 200 aprint_error(" at %s", intrstr); 201 aprint_error("\n"); 202 return; 203 } 204 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 205 206 /* set master */ 207 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 208 reg |= PCI_COMMAND_MASTER_ENABLE; 209 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 210 211 /* I2C */ 212 for(i = 0; i < I2C_NUM; i++) { 213 cic = &sc->sc_iic[i]; 214 215 cic->cic_sc = sc; 216 if (bus_space_subregion(sc->sc_memt, sc->sc_memh, 217 I2C_BASE + (I2C_SIZE * i), I2C_SIZE, &cic->cic_regh)) 218 panic("failed to subregion i2c"); 219 220 mutex_init(&cic->cic_busmutex, MUTEX_DRIVER, IPL_NONE); 221 cic->cic_i2c.ic_cookie = cic; 222 cic->cic_i2c.ic_acquire_bus = coram_iic_acquire_bus; 223 cic->cic_i2c.ic_release_bus = coram_iic_release_bus; 224 cic->cic_i2c.ic_exec = coram_iic_exec; 225 226 #ifdef CORAM_ATTACH_I2C 227 /* attach iic(4) */ 228 memset(&iba, 0, sizeof(iba)); 229 iba.iba_tag = &cic->cic_i2c; 230 iba.iba_type = I2C_TYPE_SMBUS; 231 cic->cic_i2cdev = config_found_ia(self, "i2cbus", &iba, 232 iicbus_print); 233 #endif 234 } 235 236 /* HVR1250 GPIO */ 237 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x110010); 238 #if 1 239 value &= ~0x00010001; 240 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 241 delay(5000); 242 #endif 243 value |= 0x00010001; 244 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 245 246 #if 0 247 int i; 248 uint8_t foo[256]; 249 uint8_t bar; 250 bar = 0; 251 // seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0, 256, foo, 256); 252 253 iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL); 254 iic_exec(&sc->sc_i2c, I2C_OP_READ_WITH_STOP, 0x50, &bar, 1, foo, 256, 255 I2C_F_POLL); 256 iic_release_bus(&sc->sc_i2c, I2C_F_POLL); 257 258 printf("\n"); 259 for ( i = 0; i < 256; i++) { 260 if ( (i % 8) == 0 ) 261 printf("%02x: ", i); 262 263 printf("%02x", foo[i]); 264 265 if ( (i % 8) == 7 ) 266 printf("\n"); 267 else 268 printf(" "); 269 } 270 printf("\n"); 271 #endif 272 273 sc->sc_demod = cx24227_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x19); 274 if (sc->sc_demod == NULL) 275 aprint_error_dev(self, "couldn't open cx24227\n"); 276 sc->sc_tuner = mt2131_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x61); 277 if (sc->sc_tuner == NULL) 278 aprint_error_dev(self, "couldn't open mt2131\n"); 279 280 coram_mpeg_attach(sc); 281 282 if (!pmf_device_register(self, NULL, coram_resume)) 283 aprint_error_dev(self, "couldn't establish power handler\n"); 284 285 return; 286 } 287 288 static int 289 coram_detach(device_t self, int flags) 290 { 291 struct coram_softc *sc = device_private(self); 292 struct coram_iic_softc *cic; 293 unsigned int i; 294 int error; 295 296 error = coram_mpeg_detach(sc, flags); 297 if (error) 298 return error; 299 300 if (sc->sc_tuner) 301 mt2131_close(sc->sc_tuner); 302 if (sc->sc_demod) 303 cx24227_close(sc->sc_demod); 304 for (i = 0; i < I2C_NUM; i++) { 305 cic = &sc->sc_iic[i]; 306 if (cic->cic_i2cdev) 307 config_detach(cic->cic_i2cdev, flags); 308 mutex_destroy(&cic->cic_busmutex); 309 } 310 pmf_device_deregister(self); 311 312 if (sc->sc_mems) 313 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 314 if (sc->sc_ih) 315 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 316 317 return 0; 318 } 319 320 static int 321 coram_rescan(device_t self, const char *ifattr, const int *locs) 322 { 323 struct coram_softc *sc = device_private(self); 324 struct dtv_attach_args daa; 325 326 daa.hw = &coram_dtv_if; 327 daa.priv = sc; 328 329 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL) 330 sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus", 331 &daa, dtv_print); 332 333 return 0; 334 } 335 336 static void 337 coram_childdet(device_t self, device_t child) 338 { 339 struct coram_softc *sc = device_private(self); 340 struct coram_iic_softc *cic; 341 unsigned int i; 342 343 if (sc->sc_dtvdev == child) 344 sc->sc_dtvdev = NULL; 345 346 for (i = 0; i < I2C_NUM; i++) { 347 cic = &sc->sc_iic[i]; 348 if (cic->cic_i2cdev == child) 349 cic->cic_i2cdev = NULL; 350 } 351 } 352 353 static int 354 coram_intr(void *v) 355 { 356 device_t self = v; 357 struct coram_softc *sc; 358 uint32_t val; 359 360 sc = device_private(self); 361 362 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSTAT ); 363 if (val == 0) 364 return 0; /* not ours */ 365 366 /* vid c */ 367 if (val & __BIT(2)) 368 coram_mpeg_intr(sc); 369 370 if (val & ~__BIT(2)) 371 printf("%s %08x\n", __func__, val); 372 373 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, val); 374 375 return 1; 376 } 377 378 static const struct coram_board * 379 coram_board_lookup(uint16_t vendor, uint16_t product) 380 { 381 unsigned int i; 382 383 for (i = 0; i < __arraycount(coram_boards); i++) { 384 if (coram_boards[i].vendor == vendor && 385 coram_boards[i].product == product) { 386 return &coram_boards[i]; 387 } 388 } 389 390 return NULL; 391 } 392 393 #define CXDTV_TS_RISCI2 (1 << 4) 394 #define CXDTV_TS_RISCI1 (1 << 0) 395 396 #define CXDTV_TS_RISCI (CXDTV_TS_RISCI1|CXDTV_TS_RISCI2) 397 398 static int 399 coram_mpeg_intr(struct coram_softc *sc) 400 { 401 struct dtv_payload payload; 402 uint32_t s, m, v; 403 int i; 404 405 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT); 406 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 407 408 if ((s & m) == 0) 409 return 0; 410 411 if ( (s & ~CXDTV_TS_RISCI) != 0 ) { 412 printf("%s: unexpected TS IS %08x\n", 413 device_xname(sc->sc_dev), s); 414 415 printf("cmds:\n"); 416 for(i = 0; i < 20; i++) 417 { 418 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x10140 +(i*4)); 419 printf("%06x %08x\n", 0x10140+(i*4), v); 420 } 421 } 422 423 if (sc->sc_dtvsubmitcb == NULL) 424 goto done; 425 426 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 427 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 428 0, CORAM_TS_PKTSIZE, 429 BUS_DMASYNC_POSTREAD); 430 payload.data = KERNADDR(sc->sc_dma); 431 payload.size = CORAM_TS_PKTSIZE; 432 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 433 } 434 435 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 436 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 437 CORAM_TS_PKTSIZE, CORAM_TS_PKTSIZE, 438 BUS_DMASYNC_POSTREAD); 439 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CORAM_TS_PKTSIZE; 440 payload.size = CORAM_TS_PKTSIZE; 441 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 442 } 443 444 done: 445 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, s); 446 447 return 1; 448 } 449 450 static bool 451 coram_resume(device_t dv, const pmf_qual_t *qual) 452 { 453 struct coram_softc *sc; 454 sc = device_private(dv); 455 456 return true; 457 } 458 459 static int 460 coram_iic_acquire_bus(void *cookie, int flags) 461 { 462 struct coram_iic_softc *cic; 463 464 cic = cookie; 465 466 if (flags & I2C_F_POLL) { 467 while (mutex_tryenter(&cic->cic_busmutex) == 0) 468 delay(50); 469 return 0; 470 } 471 472 mutex_enter(&cic->cic_busmutex); 473 474 return 0; 475 } 476 477 static void 478 coram_iic_release_bus(void *cookie, int flags) 479 { 480 struct coram_iic_softc *cic; 481 482 cic = cookie; 483 484 mutex_exit(&cic->cic_busmutex); 485 486 return; 487 } 488 489 /* I2C Bus */ 490 491 #define I2C_ADDR 0x0000 492 #define I2C_WDATA 0x0004 493 #define I2C_CTRL 0x0008 494 #define I2C_RDATA 0x000c 495 #define I2C_STAT 0x0010 496 497 #define I2C_EXTEND (1 << 3) 498 #define I2C_NOSTOP (1 << 4) 499 500 static int 501 coram_iic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 502 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 503 { 504 struct coram_iic_softc *cic; 505 int ret; 506 507 cic = cookie; 508 509 if(cmdlen) { 510 ret = coram_iic_write(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 511 if(ret) 512 return ret; 513 } 514 515 if(len) { 516 ret = coram_iic_read(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 517 if(ret) 518 return ret; 519 } 520 521 522 return 0; 523 524 } 525 526 static int 527 coram_iic_read(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 528 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 529 { 530 uint8_t *rb; 531 uint32_t ctrl; 532 int bn; 533 534 rb = buf; 535 536 for ( bn = 0; bn < len; bn++) { 537 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2) | 1; 538 if ( bn < len - 1 ) 539 ctrl |= I2C_NOSTOP | I2C_EXTEND; 540 541 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addr<<25); 542 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 543 544 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 545 I2C_STAT) & 0x02)) { 546 delay(25); 547 } 548 if((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 549 I2C_STAT) & 0x01) == 0x00) { 550 // printf("%s %d no ack\n", __func__, bn); 551 return EIO; 552 } 553 554 rb[bn] = bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_RDATA); 555 556 } 557 558 return 0; 559 } 560 561 static int 562 coram_iic_write(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 563 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 564 { 565 const uint8_t *wb; 566 uint32_t wdata, addrreg, ctrl; 567 int bn; 568 569 wb = cmdbuf; 570 571 addrreg = (addr << 25) | wb[0]; 572 wdata = wb[0]; 573 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 574 575 if ( cmdlen > 1 ) 576 ctrl |= I2C_NOSTOP | I2C_EXTEND; 577 else if (len) 578 ctrl |= I2C_NOSTOP; 579 580 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 581 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 582 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 583 584 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 585 delay(25); } 586 587 for ( bn = 1; bn < cmdlen; bn++) { 588 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 589 wdata = wb[bn]; 590 591 if ( bn < cmdlen - 1 ) 592 ctrl |= I2C_NOSTOP | I2C_EXTEND; 593 else if (len) 594 ctrl |= I2C_NOSTOP; 595 596 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 597 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 598 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 599 600 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 601 delay(25); } 602 } 603 604 return 0; 605 } 606 607 static int 608 coram_mpeg_attach(struct coram_softc *sc) 609 { 610 struct coram_sram_ch *ch; 611 612 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 613 614 sc->sc_riscbufsz = ch->csc_riscsz; 615 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 616 617 if ( sc->sc_riscbuf == NULL ) 618 panic("riscbuf null"); 619 620 coram_mpeg_reset(sc); 621 622 sc->sc_tsbuf = NULL; 623 624 coram_rescan(sc->sc_dev, NULL, NULL); 625 626 return (sc->sc_dtvdev != NULL); 627 } 628 629 static int 630 coram_mpeg_detach(struct coram_softc *sc, int flags) 631 { 632 struct coram_sram_ch *ch = &coram_sram_chs[CORAM_SRAM_CH6]; 633 int error; 634 635 if (sc->sc_dtvdev) { 636 error = config_detach(sc->sc_dtvdev, flags); 637 if (error) 638 return error; 639 } 640 if (sc->sc_riscbuf) { 641 kmem_free(sc->sc_riscbuf, ch->csc_riscsz); 642 } 643 644 return 0; 645 } 646 647 static void 648 coram_dtv_get_devinfo(void *cookie, struct dvb_frontend_info *info) 649 { 650 struct coram_softc *sc = cookie; 651 652 memset(info, 0, sizeof(*info)); 653 strlcpy(info->name, sc->sc_board->name, sizeof(info->name)); 654 info->type = FE_ATSC; 655 info->frequency_min = 54000000; 656 info->frequency_max = 858000000; 657 info->frequency_stepsize = 62500; 658 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 659 } 660 661 static int 662 coram_dtv_open(void *cookie, int flags) 663 { 664 struct coram_softc *sc = cookie; 665 666 #ifdef CORAM_DEBUG 667 device_printf(sc->sc_dev, "%s\n", __func__); 668 #endif 669 670 //KASSERT(sc->sc_tsbuf == NULL); 671 672 if (sc->sc_tuner == NULL || sc->sc_demod == NULL) 673 return ENXIO; 674 675 coram_mpeg_reset(sc); 676 677 /* allocate two alternating DMA areas for MPEG TS packets */ 678 sc->sc_tsbuf = coram_mpeg_malloc(sc, CORAM_TS_PKTSIZE * 2); 679 680 if (sc->sc_tsbuf == NULL) 681 return ENOMEM; 682 683 return 0; 684 } 685 686 static void 687 coram_dtv_close(void *cookie) 688 { 689 struct coram_softc *sc = cookie; 690 691 #ifdef CORAM_DEBUG 692 device_printf(sc->sc_dev, "%s\n", __func__); 693 #endif 694 695 coram_mpeg_halt(sc); 696 697 if (sc->sc_tsbuf != NULL) { 698 coram_mpeg_free(sc, sc->sc_tsbuf); 699 sc->sc_tsbuf = NULL; 700 } 701 } 702 703 static int 704 coram_dtv_set_tuner(void *cookie, const struct dvb_frontend_parameters *params) 705 { 706 struct coram_softc *sc = cookie; 707 708 KASSERT(sc->sc_tuner != NULL); 709 mt2131_tune_dtv(sc->sc_tuner, params); 710 KASSERT(sc->sc_demod != NULL); 711 return cx24227_set_modulation(sc->sc_demod, params->u.vsb.modulation); 712 } 713 714 static fe_status_t 715 coram_dtv_get_status(void *cookie) 716 { 717 struct coram_softc *sc = cookie; 718 719 if (sc->sc_demod == NULL) 720 return ENXIO; 721 722 return cx24227_get_dtv_status(sc->sc_demod);; 723 } 724 725 static uint16_t 726 coram_dtv_get_signal_strength(void *cookie) 727 { 728 return 0; 729 } 730 731 static uint16_t 732 coram_dtv_get_snr(void *cookie) 733 { 734 return 0; 735 } 736 737 static int 738 coram_dtv_start_transfer(void *cookie, 739 void (*cb)(void *, const struct dtv_payload *), void *arg) 740 { 741 struct coram_softc *sc = cookie; 742 743 #ifdef CORAM_DEBUG 744 device_printf(sc->sc_dev, "%s\n", __func__); 745 #endif 746 747 sc->sc_dtvsubmitcb = cb; 748 sc->sc_dtvsubmitarg = arg; 749 750 coram_mpeg_trigger(sc, sc->sc_tsbuf); 751 752 return 0; 753 } 754 755 static int 756 coram_dtv_stop_transfer(void *cookie) 757 { 758 struct coram_softc *sc = cookie; 759 760 #ifdef CORAM_DEBUG 761 device_printf(sc->sc_dev, "%s\n", __func__); 762 #endif 763 764 coram_mpeg_halt(sc); 765 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 766 767 sc->sc_dtvsubmitcb = NULL; 768 sc->sc_dtvsubmitarg = NULL; 769 770 return 0; 771 } 772 773 774 static int 775 coram_mpeg_reset(struct coram_softc *sc) 776 { 777 uint32_t v; 778 779 v = (uint32_t)-1; 780 781 /* hold RISC in reset */ 782 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, 0); 783 784 /* disable fifo + risc */ 785 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 786 787 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 788 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 0); 789 790 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, 0); 791 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, 0); 792 793 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 794 795 return 0; 796 } 797 798 static void * 799 coram_mpeg_malloc(struct coram_softc *sc, size_t size) 800 { 801 struct coram_dma *p; 802 int err; 803 804 p = kmem_alloc(sizeof(struct coram_dma), KM_SLEEP); 805 if ( p == NULL ) 806 return NULL; 807 err = coram_allocmem(sc, size, 16, p); 808 if (err) { 809 kmem_free(p, sizeof(struct coram_dma)); 810 return NULL; 811 } 812 813 p->next = sc->sc_dma; 814 sc->sc_dma = p; 815 816 return KERNADDR(p); 817 } 818 819 static int 820 coram_allocmem(struct coram_softc *sc, size_t size, size_t align, 821 struct coram_dma *p) 822 { 823 int err; 824 825 p->size = size; 826 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 827 p->segs, sizeof(p->segs) / sizeof(p->segs[0]), 828 &p->nsegs, BUS_DMA_NOWAIT); 829 if (err) 830 return err; 831 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 832 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 833 if (err) 834 goto free; 835 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 836 BUS_DMA_NOWAIT, &p->map); 837 if (err) 838 goto unmap; 839 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 840 BUS_DMA_NOWAIT); 841 if (err) 842 goto destroy; 843 844 return 0; 845 destroy: 846 bus_dmamap_destroy(sc->sc_dmat, p->map); 847 unmap: 848 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 849 free: 850 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 851 852 return err; 853 } 854 855 static int 856 coram_mpeg_halt(struct coram_softc *sc) 857 { 858 uint32_t v; 859 860 #ifdef CORAM_DEBUG 861 device_printf(sc->sc_dev, "%s\n", __func__); 862 #endif 863 864 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 865 866 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 867 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 868 v & __BIT(2)); 869 870 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 871 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 872 v & 0); 873 874 return 0; 875 } 876 877 static void 878 coram_mpeg_free(struct coram_softc *sc, void *addr) 879 { 880 struct coram_dma *p; 881 struct coram_dma **pp; 882 883 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) 884 if (KERNADDR(p) == addr) { 885 coram_freemem(sc, p); 886 *pp = p->next; 887 kmem_free(p, sizeof(struct coram_dma)); 888 return; 889 } 890 891 printf("%s: %p is already free\n", device_xname(sc->sc_dev), addr); 892 return; 893 } 894 895 static int 896 coram_freemem(struct coram_softc *sc, struct coram_dma *p) 897 { 898 bus_dmamap_unload(sc->sc_dmat, p->map); 899 bus_dmamap_destroy(sc->sc_dmat, p->map); 900 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 901 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 902 903 return 0; 904 } 905 906 static int 907 coram_mpeg_trigger(struct coram_softc *sc, void *buf) 908 { 909 struct coram_dma *p; 910 struct coram_sram_ch *ch; 911 uint32_t v; 912 913 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 914 915 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 916 continue; 917 if (p == NULL) { 918 printf("%s: coram_mpeg_trigger: bad addr %p\n", 919 device_xname(sc->sc_dev), buf); 920 return ENOENT; 921 } 922 923 /* disable fifo + risc */ 924 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 925 926 coram_risc_buffer(sc, CORAM_TS_PKTSIZE, 1); 927 coram_sram_ch_setup(sc, ch, CORAM_TS_PKTSIZE); 928 929 /* let me hope this bit is the same as on the 2388[0-3] */ 930 /* software reset */ 931 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 0x0040); 932 delay (100*1000); 933 934 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_LNGTH, CORAM_TS_PKTSIZE); 935 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_HW_SOP_CTL, 0x47 << 16 | 188 << 4); 936 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_TS_CLK_EN, 1); 937 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_VLD_MISC, 0); 938 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 12); 939 delay (100*1000); 940 941 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PAD_CTRL); 942 v &= ~0x4; /* Clear TS2_SOP_OE */ 943 bus_space_write_4(sc->sc_memt, sc->sc_memh, PAD_CTRL, v); 944 945 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 946 v |= 0x111111; 947 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, v); 948 949 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL); 950 v |= 0x11; /* Enable RISC controller and FIFO */ 951 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, v); 952 953 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2); 954 v |= __BIT(5); /* Enable RISC controller */ 955 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, v); 956 957 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 958 v |= 0x001f00; 959 v |= 0x04; 960 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, v); 961 962 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 963 #ifdef CORAM_DEBUG 964 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 965 #endif 966 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 967 #ifdef CORAM_DEBUG 968 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 969 #endif 970 delay(100*1000); 971 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 972 #ifdef CORAM_DEBUG 973 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 974 #endif 975 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 976 #ifdef CORAM_DEBUG 977 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 978 #endif 979 980 return 0; 981 } 982 983 static int 984 coram_risc_buffer(struct coram_softc *sc, uint32_t bpl, uint32_t lines) 985 { 986 uint32_t *rm; 987 uint32_t size; 988 989 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 990 size += 2; 991 992 if (sc->sc_riscbuf == NULL) { 993 return ENOMEM; 994 } 995 996 rm = (uint32_t *)sc->sc_riscbuf; 997 coram_risc_field(sc, rm, bpl); 998 999 return 0; 1000 } 1001 1002 static int 1003 coram_risc_field(struct coram_softc *sc, uint32_t *rm, uint32_t bpl) 1004 { 1005 struct coram_dma *p; 1006 1007 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 1008 continue; 1009 if (p == NULL) { 1010 printf("%s: coram_risc_field: bad addr %p\n", 1011 device_xname(sc->sc_dev), sc->sc_tsbuf); 1012 return ENOENT; 1013 } 1014 1015 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 1016 1017 rm = sc->sc_riscbuf; 1018 1019 /* htole32 will be done when program is copied to chip sram */ 1020 1021 /* XXX */ 1022 *(rm++) = (CX_RISC_SYNC|0); 1023 1024 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 1025 *(rm++) = (DMAADDR(p) + 0 * bpl); 1026 *(rm++) = 0; /* high dword */ 1027 1028 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 1029 *(rm++) = (DMAADDR(p) + 1 * bpl); 1030 *(rm++) = 0; 1031 1032 *(rm++) = (CX_RISC_JUMP|1); 1033 *(rm++) = (coram_sram_chs[CORAM_SRAM_CH6].csc_risc + 4); 1034 *(rm++) = 0; 1035 1036 return 0; 1037 } 1038 1039 static int 1040 coram_sram_ch_setup(struct coram_softc *sc, struct coram_sram_ch *csc, 1041 uint32_t bpl) 1042 { 1043 unsigned int i, lines; 1044 uint32_t cdt; 1045 1046 /* XXX why round? */ 1047 bpl = (bpl + 7) & ~7; 1048 cdt = csc->csc_cdt; 1049 lines = csc->csc_fifosz / bpl; 1050 #ifdef CORAM_DEBUG 1051 printf("%s %d lines\n", __func__, lines); 1052 #endif 1053 1054 /* fill in CDT */ 1055 for (i = 0; i < lines; i++) { 1056 #ifdef CORAM_DEBUG 1057 printf("CDT ent %08x, %08x\n", cdt + (16 * i), 1058 csc->csc_fifo + (bpl * i)); 1059 #endif 1060 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1061 cdt + (16 * i), csc->csc_fifo + (bpl * i)); 1062 } 1063 1064 /* copy program */ 1065 /* converts program to little endian as it goes into sram */ 1066 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 1067 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 1068 1069 /* fill in CMDS */ 1070 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1071 csc->csc_cmds + CMDS_O_IRPC, csc->csc_risc); 1072 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1073 csc->csc_cmds + CMDS_O_IRPC + 4, 0); 1074 1075 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1076 csc->csc_cmds + CMDS_O_CDTB, csc->csc_cdt); 1077 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1078 csc->csc_cmds + CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 1079 1080 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1081 csc->csc_cmds + CMDS_O_IQB, csc->csc_iq); 1082 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1083 csc->csc_cmds + CMDS_O_IQS, 1084 CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 1085 1086 /* zero rest of CMDS */ 1087 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x18, 0, 20); 1088 1089 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1090 csc->csc_ptr1, csc->csc_fifo); 1091 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1092 csc->csc_ptr2, cdt); 1093 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1094 csc->csc_cnt2, (lines * 16) >> 3); 1095 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1096 csc->csc_cnt1, (bpl >> 3) - 1); 1097 1098 return 0; 1099 } 1100 1101 MODULE(MODULE_CLASS_DRIVER, coram, "cx24227,mt2131,pci"); 1102 1103 #ifdef _MODULE 1104 #include "ioconf.c" 1105 #endif 1106 1107 static int 1108 coram_modcmd(modcmd_t cmd, void *v) 1109 { 1110 int error = 0; 1111 1112 switch (cmd) { 1113 case MODULE_CMD_INIT: 1114 #ifdef _MODULE 1115 error = config_init_component(cfdriver_ioconf_coram, 1116 cfattach_ioconf_coram, cfdata_ioconf_coram); 1117 #endif 1118 return error; 1119 case MODULE_CMD_FINI: 1120 #ifdef _MODULE 1121 error = config_fini_component(cfdriver_ioconf_coram, 1122 cfattach_ioconf_coram, cfdata_ioconf_coram); 1123 #endif 1124 return error; 1125 default: 1126 return ENOTTY; 1127 } 1128 } 1129
Indexes created Wed Sep 24 05:09:52 GMT 2025