coram.c revision 1.16
1 /* $NetBSD: coram.c,v 1.16 2018/12/09 11:14:01 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: coram.c,v 1.16 2018/12/09 11:14:01 jdolecek Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 40 #include <dev/dtv/dtvif.h> 41 42 #include <dev/pci/cx23885reg.h> 43 #include <dev/pci/coramvar.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/i2c/i2cvar.h> 49 #include <dev/i2c/at24cxxvar.h> 50 51 #include <dev/i2c/cx24227var.h> 52 #include <dev/i2c/mt2131var.h> 53 54 /* #define CORAM_DEBUG */ 55 /* #define CORAM_ATTACH_I2C */ 56 57 static const struct coram_board coram_boards[] = { 58 { PCI_VENDOR_HAUPPAUGE, 0x7911, "Hauppauge HVR-1250" }, 59 }; 60 61 static int coram_match(device_t, cfdata_t, void *); 62 static void coram_attach(device_t, device_t, void *); 63 static int coram_detach(device_t, int); 64 static int coram_rescan(device_t, const char *, const int *); 65 static void coram_childdet(device_t, device_t); 66 static bool coram_resume(device_t, const pmf_qual_t *); 67 static int coram_intr(void *); 68 static const struct coram_board * coram_board_lookup(uint16_t, uint16_t); 69 70 static int coram_iic_exec(void *, i2c_op_t, i2c_addr_t, 71 const void *, size_t, void *, size_t, int); 72 static int coram_iic_acquire_bus(void *, int); 73 static void coram_iic_release_bus(void *, int); 74 static int coram_iic_read(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 75 const void *, size_t, void *, size_t, int); 76 static int coram_iic_write(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 77 const void *, size_t, void *, size_t, int); 78 79 static void coram_dtv_get_devinfo(void *, struct dvb_frontend_info *); 80 static int coram_dtv_open(void *, int); 81 static void coram_dtv_close(void *); 82 static int coram_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 83 static fe_status_t coram_dtv_get_status(void *); 84 static uint16_t coram_dtv_get_signal_strength(void *); 85 static uint16_t coram_dtv_get_snr(void *); 86 static int coram_dtv_start_transfer(void *, void (*)(void *, const struct dtv_payload *), void *); 87 static int coram_dtv_stop_transfer(void *); 88 89 static int coram_mpeg_attach(struct coram_softc *); 90 static int coram_mpeg_detach(struct coram_softc *, int); 91 static int coram_mpeg_reset(struct coram_softc *); 92 static void * coram_mpeg_malloc(struct coram_softc *, size_t); 93 static int coram_allocmem(struct coram_softc *, size_t, size_t, struct coram_dma *); 94 static void coram_mpeg_free(struct coram_softc *, void *); 95 static int coram_mpeg_halt(struct coram_softc *); 96 static int coram_freemem(struct coram_softc *, struct coram_dma *); 97 static int coram_mpeg_trigger(struct coram_softc *, void *); 98 static int coram_risc_buffer(struct coram_softc *, uint32_t, uint32_t); 99 static int coram_risc_field(struct coram_softc *, uint32_t *, uint32_t); 100 static int coram_sram_ch_setup(struct coram_softc *, struct coram_sram_ch *, uint32_t); 101 static int coram_mpeg_intr(struct coram_softc *); 102 103 CFATTACH_DECL2_NEW(coram, sizeof(struct coram_softc), 104 coram_match, coram_attach, coram_detach, NULL, 105 coram_rescan, coram_childdet); 106 107 #define CORAM_SRAM_CH6 0 108 109 #define CORAM_TS_PKTSIZE (188 * 8) 110 111 static struct coram_sram_ch coram_sram_chs[] = { 112 [CORAM_SRAM_CH6] = { 113 .csc_cmds= 0x10140, 114 .csc_iq = 0x10500, 115 .csc_iqsz = 0x40, 116 .csc_cdt = 0x10600, 117 .csc_cdtsz = 0x10, 118 .csc_fifo = 0x6000, 119 .csc_fifosz = 0x1000, 120 .csc_risc = 0x10800, 121 .csc_riscsz = 0x800, 122 .csc_ptr1 = DMA5_PTR1, 123 .csc_ptr2 = DMA5_PTR2, 124 .csc_cnt1 = DMA5_CNT1, 125 .csc_cnt2 = DMA5_CNT2, 126 }, 127 }; 128 129 static const struct dtv_hw_if coram_dtv_if = { 130 .get_devinfo = coram_dtv_get_devinfo, 131 .open = coram_dtv_open, 132 .close = coram_dtv_close, 133 .set_tuner = coram_dtv_set_tuner, 134 .get_status = coram_dtv_get_status, 135 .get_signal_strength = coram_dtv_get_signal_strength, 136 .get_snr = coram_dtv_get_snr, 137 .start_transfer = coram_dtv_start_transfer, 138 .stop_transfer = coram_dtv_stop_transfer, 139 }; 140 141 static int 142 coram_match(device_t parent, cfdata_t match, void *v) 143 { 144 const struct pci_attach_args *pa = v; 145 pcireg_t subid; 146 147 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 148 return 0; 149 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX23885) 150 return 0; 151 152 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 153 if (coram_board_lookup(PCI_VENDOR(subid), PCI_PRODUCT(subid)) == NULL) 154 return 0; 155 156 return 1; 157 } 158 159 static void 160 coram_attach(device_t parent, device_t self, void *aux) 161 { 162 struct coram_softc *sc = device_private(self); 163 const struct pci_attach_args *pa = aux; 164 pci_intr_handle_t ih; 165 pcireg_t reg; 166 const char *intrstr; 167 struct coram_iic_softc *cic; 168 uint32_t value; 169 int i; 170 #ifdef CORAM_ATTACH_I2C 171 struct i2cbus_attach_args iba; 172 #endif 173 char intrbuf[PCI_INTRSTR_LEN]; 174 175 sc->sc_dev = self; 176 177 pci_aprint_devinfo(pa, NULL); 178 179 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 180 sc->sc_board = coram_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)); 181 KASSERT(sc->sc_board != NULL); 182 183 if (pci_mapreg_map(pa, CX23885_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 184 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 185 aprint_error_dev(self, "couldn't map memory space\n"); 186 return; 187 } 188 189 sc->sc_dmat = pa->pa_dmat; 190 sc->sc_pc = pa->pa_pc; 191 192 if (pci_intr_map(pa, &ih)) { 193 aprint_error_dev(self, "couldn't map interrupt\n"); 194 return; 195 } 196 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 197 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_VM, coram_intr, 198 self, device_xname(self)); 199 if (sc->sc_ih == NULL) { 200 aprint_error_dev(self, "couldn't establish interrupt"); 201 if (intrstr != NULL) 202 aprint_error(" at %s", intrstr); 203 aprint_error("\n"); 204 return; 205 } 206 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 207 208 /* set master */ 209 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 210 reg |= PCI_COMMAND_MASTER_ENABLE; 211 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 212 213 /* I2C */ 214 for(i = 0; i < I2C_NUM; i++) { 215 cic = &sc->sc_iic[i]; 216 217 cic->cic_sc = sc; 218 if (bus_space_subregion(sc->sc_memt, sc->sc_memh, 219 I2C_BASE + (I2C_SIZE * i), I2C_SIZE, &cic->cic_regh)) 220 panic("failed to subregion i2c"); 221 222 mutex_init(&cic->cic_busmutex, MUTEX_DRIVER, IPL_NONE); 223 cic->cic_i2c.ic_cookie = cic; 224 cic->cic_i2c.ic_acquire_bus = coram_iic_acquire_bus; 225 cic->cic_i2c.ic_release_bus = coram_iic_release_bus; 226 cic->cic_i2c.ic_exec = coram_iic_exec; 227 228 #ifdef CORAM_ATTACH_I2C 229 /* attach iic(4) */ 230 memset(&iba, 0, sizeof(iba)); 231 iba.iba_tag = &cic->cic_i2c; 232 iba.iba_type = I2C_TYPE_SMBUS; 233 cic->cic_i2cdev = config_found_ia(self, "i2cbus", &iba, 234 iicbus_print); 235 #endif 236 } 237 238 /* HVR1250 GPIO */ 239 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x110010); 240 #if 1 241 value &= ~0x00010001; 242 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 243 delay(5000); 244 #endif 245 value |= 0x00010001; 246 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 247 248 #if 0 249 int i; 250 uint8_t foo[256]; 251 uint8_t bar; 252 bar = 0; 253 // seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0, 256, foo, 256); 254 255 iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL); 256 iic_exec(&sc->sc_i2c, I2C_OP_READ_WITH_STOP, 0x50, &bar, 1, foo, 256, 257 I2C_F_POLL); 258 iic_release_bus(&sc->sc_i2c, I2C_F_POLL); 259 260 printf("\n"); 261 for ( i = 0; i < 256; i++) { 262 if ( (i % 8) == 0 ) 263 printf("%02x: ", i); 264 265 printf("%02x", foo[i]); 266 267 if ( (i % 8) == 7 ) 268 printf("\n"); 269 else 270 printf(" "); 271 } 272 printf("\n"); 273 #endif 274 275 sc->sc_demod = cx24227_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x19); 276 if (sc->sc_demod == NULL) 277 aprint_error_dev(self, "couldn't open cx24227\n"); 278 sc->sc_tuner = mt2131_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x61); 279 if (sc->sc_tuner == NULL) 280 aprint_error_dev(self, "couldn't open mt2131\n"); 281 282 coram_mpeg_attach(sc); 283 284 if (!pmf_device_register(self, NULL, coram_resume)) 285 aprint_error_dev(self, "couldn't establish power handler\n"); 286 287 return; 288 } 289 290 static int 291 coram_detach(device_t self, int flags) 292 { 293 struct coram_softc *sc = device_private(self); 294 struct coram_iic_softc *cic; 295 unsigned int i; 296 int error; 297 298 error = coram_mpeg_detach(sc, flags); 299 if (error) 300 return error; 301 302 if (sc->sc_tuner) 303 mt2131_close(sc->sc_tuner); 304 if (sc->sc_demod) 305 cx24227_close(sc->sc_demod); 306 for (i = 0; i < I2C_NUM; i++) { 307 cic = &sc->sc_iic[i]; 308 if (cic->cic_i2cdev) 309 config_detach(cic->cic_i2cdev, flags); 310 mutex_destroy(&cic->cic_busmutex); 311 } 312 pmf_device_deregister(self); 313 314 if (sc->sc_mems) 315 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 316 if (sc->sc_ih) 317 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 318 319 return 0; 320 } 321 322 static int 323 coram_rescan(device_t self, const char *ifattr, const int *locs) 324 { 325 struct coram_softc *sc = device_private(self); 326 struct dtv_attach_args daa; 327 328 daa.hw = &coram_dtv_if; 329 daa.priv = sc; 330 331 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL) 332 sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus", 333 &daa, dtv_print); 334 335 return 0; 336 } 337 338 static void 339 coram_childdet(device_t self, device_t child) 340 { 341 struct coram_softc *sc = device_private(self); 342 struct coram_iic_softc *cic; 343 unsigned int i; 344 345 if (sc->sc_dtvdev == child) 346 sc->sc_dtvdev = NULL; 347 348 for (i = 0; i < I2C_NUM; i++) { 349 cic = &sc->sc_iic[i]; 350 if (cic->cic_i2cdev == child) 351 cic->cic_i2cdev = NULL; 352 } 353 } 354 355 static int 356 coram_intr(void *v) 357 { 358 device_t self = v; 359 struct coram_softc *sc; 360 uint32_t val; 361 362 sc = device_private(self); 363 364 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSTAT ); 365 if (val == 0) 366 return 0; /* not ours */ 367 368 /* vid c */ 369 if (val & __BIT(2)) 370 coram_mpeg_intr(sc); 371 372 if (val & ~__BIT(2)) 373 printf("%s %08x\n", __func__, val); 374 375 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, val); 376 377 return 1; 378 } 379 380 static const struct coram_board * 381 coram_board_lookup(uint16_t vendor, uint16_t product) 382 { 383 unsigned int i; 384 385 for (i = 0; i < __arraycount(coram_boards); i++) { 386 if (coram_boards[i].vendor == vendor && 387 coram_boards[i].product == product) { 388 return &coram_boards[i]; 389 } 390 } 391 392 return NULL; 393 } 394 395 #define CXDTV_TS_RISCI2 (1 << 4) 396 #define CXDTV_TS_RISCI1 (1 << 0) 397 398 #define CXDTV_TS_RISCI (CXDTV_TS_RISCI1|CXDTV_TS_RISCI2) 399 400 static int 401 coram_mpeg_intr(struct coram_softc *sc) 402 { 403 struct dtv_payload payload; 404 uint32_t s, m, v; 405 int i; 406 407 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT); 408 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 409 410 if ((s & m) == 0) 411 return 0; 412 413 if ( (s & ~CXDTV_TS_RISCI) != 0 ) { 414 printf("%s: unexpected TS IS %08x\n", 415 device_xname(sc->sc_dev), s); 416 417 printf("cmds:\n"); 418 for(i = 0; i < 20; i++) 419 { 420 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x10140 +(i*4)); 421 printf("%06x %08x\n", 0x10140+(i*4), v); 422 } 423 } 424 425 if (sc->sc_dtvsubmitcb == NULL) 426 goto done; 427 428 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 429 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 430 0, CORAM_TS_PKTSIZE, 431 BUS_DMASYNC_POSTREAD); 432 payload.data = KERNADDR(sc->sc_dma); 433 payload.size = CORAM_TS_PKTSIZE; 434 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 435 } 436 437 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 438 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 439 CORAM_TS_PKTSIZE, CORAM_TS_PKTSIZE, 440 BUS_DMASYNC_POSTREAD); 441 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CORAM_TS_PKTSIZE; 442 payload.size = CORAM_TS_PKTSIZE; 443 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 444 } 445 446 done: 447 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, s); 448 449 return 1; 450 } 451 452 static bool 453 coram_resume(device_t dv, const pmf_qual_t *qual) 454 { 455 return true; 456 } 457 458 static int 459 coram_iic_acquire_bus(void *cookie, int flags) 460 { 461 struct coram_iic_softc *cic; 462 463 cic = cookie; 464 465 if (flags & I2C_F_POLL) { 466 while (mutex_tryenter(&cic->cic_busmutex) == 0) 467 delay(50); 468 return 0; 469 } 470 471 mutex_enter(&cic->cic_busmutex); 472 473 return 0; 474 } 475 476 static void 477 coram_iic_release_bus(void *cookie, int flags) 478 { 479 struct coram_iic_softc *cic; 480 481 cic = cookie; 482 483 mutex_exit(&cic->cic_busmutex); 484 485 return; 486 } 487 488 /* I2C Bus */ 489 490 #define I2C_ADDR 0x0000 491 #define I2C_WDATA 0x0004 492 #define I2C_CTRL 0x0008 493 #define I2C_RDATA 0x000c 494 #define I2C_STAT 0x0010 495 496 #define I2C_EXTEND (1 << 3) 497 #define I2C_NOSTOP (1 << 4) 498 499 static int 500 coram_iic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 501 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 502 { 503 struct coram_iic_softc *cic; 504 int ret; 505 506 cic = cookie; 507 508 if(cmdlen) { 509 ret = coram_iic_write(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 510 if(ret) 511 return ret; 512 } 513 514 if(len) { 515 ret = coram_iic_read(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 516 if(ret) 517 return ret; 518 } 519 520 521 return 0; 522 523 } 524 525 static int 526 coram_iic_read(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 527 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 528 { 529 uint8_t *rb; 530 uint32_t ctrl; 531 int bn; 532 533 rb = buf; 534 535 for ( bn = 0; bn < len; bn++) { 536 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2) | 1; 537 if ( bn < len - 1 ) 538 ctrl |= I2C_NOSTOP | I2C_EXTEND; 539 540 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addr<<25); 541 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 542 543 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 544 I2C_STAT) & 0x02)) { 545 delay(25); 546 } 547 if((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 548 I2C_STAT) & 0x01) == 0x00) { 549 // printf("%s %d no ack\n", __func__, bn); 550 return EIO; 551 } 552 553 rb[bn] = bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_RDATA); 554 555 } 556 557 return 0; 558 } 559 560 static int 561 coram_iic_write(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 562 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 563 { 564 const uint8_t *wb; 565 uint32_t wdata, addrreg, ctrl; 566 int bn; 567 568 wb = cmdbuf; 569 570 addrreg = (addr << 25) | wb[0]; 571 wdata = wb[0]; 572 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 573 574 if ( cmdlen > 1 ) 575 ctrl |= I2C_NOSTOP | I2C_EXTEND; 576 else if (len) 577 ctrl |= I2C_NOSTOP; 578 579 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 580 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 581 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 582 583 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 584 delay(25); } 585 586 for ( bn = 1; bn < cmdlen; bn++) { 587 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 588 wdata = wb[bn]; 589 590 if ( bn < cmdlen - 1 ) 591 ctrl |= I2C_NOSTOP | I2C_EXTEND; 592 else if (len) 593 ctrl |= I2C_NOSTOP; 594 595 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 596 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 597 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 598 599 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 600 delay(25); } 601 } 602 603 return 0; 604 } 605 606 static int 607 coram_mpeg_attach(struct coram_softc *sc) 608 { 609 struct coram_sram_ch *ch; 610 611 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 612 613 sc->sc_riscbufsz = ch->csc_riscsz; 614 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 615 616 coram_mpeg_reset(sc); 617 618 sc->sc_tsbuf = NULL; 619 620 coram_rescan(sc->sc_dev, NULL, NULL); 621 622 return (sc->sc_dtvdev != NULL); 623 } 624 625 static int 626 coram_mpeg_detach(struct coram_softc *sc, int flags) 627 { 628 struct coram_sram_ch *ch = &coram_sram_chs[CORAM_SRAM_CH6]; 629 int error; 630 631 if (sc->sc_dtvdev) { 632 error = config_detach(sc->sc_dtvdev, flags); 633 if (error) 634 return error; 635 } 636 if (sc->sc_riscbuf) { 637 kmem_free(sc->sc_riscbuf, ch->csc_riscsz); 638 } 639 640 return 0; 641 } 642 643 static void 644 coram_dtv_get_devinfo(void *cookie, struct dvb_frontend_info *info) 645 { 646 struct coram_softc *sc = cookie; 647 648 memset(info, 0, sizeof(*info)); 649 strlcpy(info->name, sc->sc_board->name, sizeof(info->name)); 650 info->type = FE_ATSC; 651 info->frequency_min = 54000000; 652 info->frequency_max = 858000000; 653 info->frequency_stepsize = 62500; 654 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 655 } 656 657 static int 658 coram_dtv_open(void *cookie, int flags) 659 { 660 struct coram_softc *sc = cookie; 661 662 #ifdef CORAM_DEBUG 663 device_printf(sc->sc_dev, "%s\n", __func__); 664 #endif 665 666 //KASSERT(sc->sc_tsbuf == NULL); 667 668 if (sc->sc_tuner == NULL || sc->sc_demod == NULL) 669 return ENXIO; 670 671 coram_mpeg_reset(sc); 672 673 /* allocate two alternating DMA areas for MPEG TS packets */ 674 sc->sc_tsbuf = coram_mpeg_malloc(sc, CORAM_TS_PKTSIZE * 2); 675 676 if (sc->sc_tsbuf == NULL) 677 return ENOMEM; 678 679 return 0; 680 } 681 682 static void 683 coram_dtv_close(void *cookie) 684 { 685 struct coram_softc *sc = cookie; 686 687 #ifdef CORAM_DEBUG 688 device_printf(sc->sc_dev, "%s\n", __func__); 689 #endif 690 691 coram_mpeg_halt(sc); 692 693 if (sc->sc_tsbuf != NULL) { 694 coram_mpeg_free(sc, sc->sc_tsbuf); 695 sc->sc_tsbuf = NULL; 696 } 697 } 698 699 static int 700 coram_dtv_set_tuner(void *cookie, const struct dvb_frontend_parameters *params) 701 { 702 struct coram_softc *sc = cookie; 703 704 KASSERT(sc->sc_tuner != NULL); 705 mt2131_tune_dtv(sc->sc_tuner, params); 706 KASSERT(sc->sc_demod != NULL); 707 return cx24227_set_modulation(sc->sc_demod, params->u.vsb.modulation); 708 } 709 710 static fe_status_t 711 coram_dtv_get_status(void *cookie) 712 { 713 struct coram_softc *sc = cookie; 714 715 if (sc->sc_demod == NULL) 716 return ENXIO; 717 718 return cx24227_get_dtv_status(sc->sc_demod); 719 } 720 721 static uint16_t 722 coram_dtv_get_signal_strength(void *cookie) 723 { 724 return 0; 725 } 726 727 static uint16_t 728 coram_dtv_get_snr(void *cookie) 729 { 730 return 0; 731 } 732 733 static int 734 coram_dtv_start_transfer(void *cookie, 735 void (*cb)(void *, const struct dtv_payload *), void *arg) 736 { 737 struct coram_softc *sc = cookie; 738 739 #ifdef CORAM_DEBUG 740 device_printf(sc->sc_dev, "%s\n", __func__); 741 #endif 742 743 sc->sc_dtvsubmitcb = cb; 744 sc->sc_dtvsubmitarg = arg; 745 746 coram_mpeg_trigger(sc, sc->sc_tsbuf); 747 748 return 0; 749 } 750 751 static int 752 coram_dtv_stop_transfer(void *cookie) 753 { 754 struct coram_softc *sc = cookie; 755 756 #ifdef CORAM_DEBUG 757 device_printf(sc->sc_dev, "%s\n", __func__); 758 #endif 759 760 coram_mpeg_halt(sc); 761 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 762 763 sc->sc_dtvsubmitcb = NULL; 764 sc->sc_dtvsubmitarg = NULL; 765 766 return 0; 767 } 768 769 770 static int 771 coram_mpeg_reset(struct coram_softc *sc) 772 { 773 /* hold RISC in reset */ 774 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, 0); 775 776 /* disable fifo + risc */ 777 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 778 779 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 780 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 0); 781 782 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, 0); 783 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, 0); 784 785 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 786 787 return 0; 788 } 789 790 static void * 791 coram_mpeg_malloc(struct coram_softc *sc, size_t size) 792 { 793 struct coram_dma *p; 794 int err; 795 796 p = kmem_alloc(sizeof(struct coram_dma), KM_SLEEP); 797 err = coram_allocmem(sc, size, 16, p); 798 if (err) { 799 kmem_free(p, sizeof(struct coram_dma)); 800 return NULL; 801 } 802 803 p->next = sc->sc_dma; 804 sc->sc_dma = p; 805 806 return KERNADDR(p); 807 } 808 809 static int 810 coram_allocmem(struct coram_softc *sc, size_t size, size_t align, 811 struct coram_dma *p) 812 { 813 int err; 814 815 p->size = size; 816 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 817 p->segs, sizeof(p->segs) / sizeof(p->segs[0]), 818 &p->nsegs, BUS_DMA_NOWAIT); 819 if (err) 820 return err; 821 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 822 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 823 if (err) 824 goto free; 825 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 826 BUS_DMA_NOWAIT, &p->map); 827 if (err) 828 goto unmap; 829 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 830 BUS_DMA_NOWAIT); 831 if (err) 832 goto destroy; 833 834 return 0; 835 destroy: 836 bus_dmamap_destroy(sc->sc_dmat, p->map); 837 unmap: 838 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 839 free: 840 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 841 842 return err; 843 } 844 845 static int 846 coram_mpeg_halt(struct coram_softc *sc) 847 { 848 uint32_t v; 849 850 #ifdef CORAM_DEBUG 851 device_printf(sc->sc_dev, "%s\n", __func__); 852 #endif 853 854 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 855 856 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 857 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 858 v & __BIT(2)); 859 860 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 861 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 862 v & 0); 863 864 return 0; 865 } 866 867 static void 868 coram_mpeg_free(struct coram_softc *sc, void *addr) 869 { 870 struct coram_dma *p; 871 struct coram_dma **pp; 872 873 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) 874 if (KERNADDR(p) == addr) { 875 coram_freemem(sc, p); 876 *pp = p->next; 877 kmem_free(p, sizeof(struct coram_dma)); 878 return; 879 } 880 881 printf("%s: %p is already free\n", device_xname(sc->sc_dev), addr); 882 return; 883 } 884 885 static int 886 coram_freemem(struct coram_softc *sc, struct coram_dma *p) 887 { 888 bus_dmamap_unload(sc->sc_dmat, p->map); 889 bus_dmamap_destroy(sc->sc_dmat, p->map); 890 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 891 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 892 893 return 0; 894 } 895 896 static int 897 coram_mpeg_trigger(struct coram_softc *sc, void *buf) 898 { 899 struct coram_dma *p; 900 struct coram_sram_ch *ch; 901 uint32_t v; 902 903 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 904 905 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 906 continue; 907 if (p == NULL) { 908 printf("%s: coram_mpeg_trigger: bad addr %p\n", 909 device_xname(sc->sc_dev), buf); 910 return ENOENT; 911 } 912 913 /* disable fifo + risc */ 914 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 915 916 coram_risc_buffer(sc, CORAM_TS_PKTSIZE, 1); 917 coram_sram_ch_setup(sc, ch, CORAM_TS_PKTSIZE); 918 919 /* let me hope this bit is the same as on the 2388[0-3] */ 920 /* software reset */ 921 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 0x0040); 922 delay (100*1000); 923 924 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_LNGTH, CORAM_TS_PKTSIZE); 925 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_HW_SOP_CTL, 0x47 << 16 | 188 << 4); 926 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_TS_CLK_EN, 1); 927 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_VLD_MISC, 0); 928 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 12); 929 delay (100*1000); 930 931 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PAD_CTRL); 932 v &= ~0x4; /* Clear TS2_SOP_OE */ 933 bus_space_write_4(sc->sc_memt, sc->sc_memh, PAD_CTRL, v); 934 935 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 936 v |= 0x111111; 937 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, v); 938 939 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL); 940 v |= 0x11; /* Enable RISC controller and FIFO */ 941 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, v); 942 943 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2); 944 v |= __BIT(5); /* Enable RISC controller */ 945 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, v); 946 947 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 948 v |= 0x001f00; 949 v |= 0x04; 950 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, v); 951 952 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 953 #ifdef CORAM_DEBUG 954 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 955 #endif 956 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 957 #ifdef CORAM_DEBUG 958 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 959 #endif 960 delay(100*1000); 961 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 962 #ifdef CORAM_DEBUG 963 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 964 #endif 965 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 966 #ifdef CORAM_DEBUG 967 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 968 #endif 969 970 return 0; 971 } 972 973 static int 974 coram_risc_buffer(struct coram_softc *sc, uint32_t bpl, uint32_t lines) 975 { 976 uint32_t *rm; 977 uint32_t size; 978 979 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 980 size += 2; 981 982 if (sc->sc_riscbuf == NULL) { 983 return ENOMEM; 984 } 985 986 rm = (uint32_t *)sc->sc_riscbuf; 987 coram_risc_field(sc, rm, bpl); 988 989 return 0; 990 } 991 992 static int 993 coram_risc_field(struct coram_softc *sc, uint32_t *rm, uint32_t bpl) 994 { 995 struct coram_dma *p; 996 997 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 998 continue; 999 if (p == NULL) { 1000 printf("%s: coram_risc_field: bad addr %p\n", 1001 device_xname(sc->sc_dev), sc->sc_tsbuf); 1002 return ENOENT; 1003 } 1004 1005 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 1006 1007 rm = sc->sc_riscbuf; 1008 1009 /* htole32 will be done when program is copied to chip sram */ 1010 1011 /* XXX */ 1012 *(rm++) = (CX_RISC_SYNC|0); 1013 1014 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 1015 *(rm++) = (DMAADDR(p) + 0 * bpl); 1016 *(rm++) = 0; /* high dword */ 1017 1018 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 1019 *(rm++) = (DMAADDR(p) + 1 * bpl); 1020 *(rm++) = 0; 1021 1022 *(rm++) = (CX_RISC_JUMP|1); 1023 *(rm++) = (coram_sram_chs[CORAM_SRAM_CH6].csc_risc + 4); 1024 *(rm++) = 0; 1025 1026 return 0; 1027 } 1028 1029 static int 1030 coram_sram_ch_setup(struct coram_softc *sc, struct coram_sram_ch *csc, 1031 uint32_t bpl) 1032 { 1033 unsigned int i, lines; 1034 uint32_t cdt; 1035 1036 /* XXX why round? */ 1037 bpl = (bpl + 7) & ~7; 1038 cdt = csc->csc_cdt; 1039 lines = csc->csc_fifosz / bpl; 1040 #ifdef CORAM_DEBUG 1041 printf("%s %d lines\n", __func__, lines); 1042 #endif 1043 1044 /* fill in CDT */ 1045 for (i = 0; i < lines; i++) { 1046 #ifdef CORAM_DEBUG 1047 printf("CDT ent %08x, %08x\n", cdt + (16 * i), 1048 csc->csc_fifo + (bpl * i)); 1049 #endif 1050 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1051 cdt + (16 * i), csc->csc_fifo + (bpl * i)); 1052 } 1053 1054 /* copy program */ 1055 /* converts program to little endian as it goes into sram */ 1056 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 1057 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 1058 1059 /* fill in CMDS */ 1060 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1061 csc->csc_cmds + CMDS_O_IRPC, csc->csc_risc); 1062 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1063 csc->csc_cmds + CMDS_O_IRPC + 4, 0); 1064 1065 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1066 csc->csc_cmds + CMDS_O_CDTB, csc->csc_cdt); 1067 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1068 csc->csc_cmds + CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 1069 1070 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1071 csc->csc_cmds + CMDS_O_IQB, csc->csc_iq); 1072 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1073 csc->csc_cmds + CMDS_O_IQS, 1074 CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 1075 1076 /* zero rest of CMDS */ 1077 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x18, 0, 20); 1078 1079 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1080 csc->csc_ptr1, csc->csc_fifo); 1081 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1082 csc->csc_ptr2, cdt); 1083 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1084 csc->csc_cnt2, (lines * 16) >> 3); 1085 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1086 csc->csc_cnt1, (bpl >> 3) - 1); 1087 1088 return 0; 1089 } 1090 1091 MODULE(MODULE_CLASS_DRIVER, coram, "cx24227,mt2131,pci"); 1092 1093 #ifdef _MODULE 1094 #include "ioconf.c" 1095 #endif 1096 1097 static int 1098 coram_modcmd(modcmd_t cmd, void *v) 1099 { 1100 int error = 0; 1101 1102 switch (cmd) { 1103 case MODULE_CMD_INIT: 1104 #ifdef _MODULE 1105 error = config_init_component(cfdriver_ioconf_coram, 1106 cfattach_ioconf_coram, cfdata_ioconf_coram); 1107 #endif 1108 return error; 1109 case MODULE_CMD_FINI: 1110 #ifdef _MODULE 1111 error = config_fini_component(cfdriver_ioconf_coram, 1112 cfattach_ioconf_coram, cfdata_ioconf_coram); 1113 #endif 1114 return error; 1115 default: 1116 return ENOTTY; 1117 } 1118 } 1119
Indexes created Wed Sep 24 05:09:52 GMT 2025