coram.c revision 1.19
1 /* $NetBSD: coram.c,v 1.19 2021/04/24 23:36:57 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: coram.c,v 1.19 2021/04/24 23:36:57 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 40 #include <dev/dtv/dtvif.h> 41 42 #include <dev/pci/cx23885reg.h> 43 #include <dev/pci/coramvar.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/i2c/i2cvar.h> 49 #include <dev/i2c/at24cxxvar.h> 50 51 #include <dev/i2c/cx24227var.h> 52 #include <dev/i2c/mt2131var.h> 53 54 /* #define CORAM_DEBUG */ 55 /* #define CORAM_ATTACH_I2C */ 56 57 static const struct coram_board coram_boards[] = { 58 { PCI_VENDOR_HAUPPAUGE, 0x7911, "Hauppauge HVR-1250" }, 59 }; 60 61 static int coram_match(device_t, cfdata_t, void *); 62 static void coram_attach(device_t, device_t, void *); 63 static int coram_detach(device_t, int); 64 static int coram_rescan(device_t, const char *, const int *); 65 static void coram_childdet(device_t, device_t); 66 static bool coram_resume(device_t, const pmf_qual_t *); 67 static int coram_intr(void *); 68 static const struct coram_board * coram_board_lookup(uint16_t, uint16_t); 69 70 static int coram_iic_exec(void *, i2c_op_t, i2c_addr_t, 71 const void *, size_t, void *, size_t, int); 72 static int coram_iic_read(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 73 const void *, size_t, void *, size_t, int); 74 static int coram_iic_write(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 75 const void *, size_t, void *, size_t, int); 76 77 static void coram_dtv_get_devinfo(void *, struct dvb_frontend_info *); 78 static int coram_dtv_open(void *, int); 79 static void coram_dtv_close(void *); 80 static int coram_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 81 static fe_status_t coram_dtv_get_status(void *); 82 static uint16_t coram_dtv_get_signal_strength(void *); 83 static uint16_t coram_dtv_get_snr(void *); 84 static int coram_dtv_start_transfer(void *, void (*)(void *, const struct dtv_payload *), void *); 85 static int coram_dtv_stop_transfer(void *); 86 87 static int coram_mpeg_attach(struct coram_softc *); 88 static int coram_mpeg_detach(struct coram_softc *, int); 89 static int coram_mpeg_reset(struct coram_softc *); 90 static void * coram_mpeg_malloc(struct coram_softc *, size_t); 91 static int coram_allocmem(struct coram_softc *, size_t, size_t, struct coram_dma *); 92 static void coram_mpeg_free(struct coram_softc *, void *); 93 static int coram_mpeg_halt(struct coram_softc *); 94 static int coram_freemem(struct coram_softc *, struct coram_dma *); 95 static int coram_mpeg_trigger(struct coram_softc *, void *); 96 static int coram_risc_buffer(struct coram_softc *, uint32_t, uint32_t); 97 static int coram_risc_field(struct coram_softc *, uint32_t *, uint32_t); 98 static int coram_sram_ch_setup(struct coram_softc *, struct coram_sram_ch *, uint32_t); 99 static int coram_mpeg_intr(struct coram_softc *); 100 101 CFATTACH_DECL2_NEW(coram, sizeof(struct coram_softc), 102 coram_match, coram_attach, coram_detach, NULL, 103 coram_rescan, coram_childdet); 104 105 #define CORAM_SRAM_CH6 0 106 107 #define CORAM_TS_PKTSIZE (188 * 8) 108 109 static struct coram_sram_ch coram_sram_chs[] = { 110 [CORAM_SRAM_CH6] = { 111 .csc_cmds= 0x10140, 112 .csc_iq = 0x10500, 113 .csc_iqsz = 0x40, 114 .csc_cdt = 0x10600, 115 .csc_cdtsz = 0x10, 116 .csc_fifo = 0x6000, 117 .csc_fifosz = 0x1000, 118 .csc_risc = 0x10800, 119 .csc_riscsz = 0x800, 120 .csc_ptr1 = DMA5_PTR1, 121 .csc_ptr2 = DMA5_PTR2, 122 .csc_cnt1 = DMA5_CNT1, 123 .csc_cnt2 = DMA5_CNT2, 124 }, 125 }; 126 127 static const struct dtv_hw_if coram_dtv_if = { 128 .get_devinfo = coram_dtv_get_devinfo, 129 .open = coram_dtv_open, 130 .close = coram_dtv_close, 131 .set_tuner = coram_dtv_set_tuner, 132 .get_status = coram_dtv_get_status, 133 .get_signal_strength = coram_dtv_get_signal_strength, 134 .get_snr = coram_dtv_get_snr, 135 .start_transfer = coram_dtv_start_transfer, 136 .stop_transfer = coram_dtv_stop_transfer, 137 }; 138 139 static int 140 coram_match(device_t parent, cfdata_t match, void *v) 141 { 142 const struct pci_attach_args *pa = v; 143 pcireg_t subid; 144 145 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 146 return 0; 147 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX23885) 148 return 0; 149 150 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 151 if (coram_board_lookup(PCI_VENDOR(subid), PCI_PRODUCT(subid)) == NULL) 152 return 0; 153 154 return 1; 155 } 156 157 static void 158 coram_attach(device_t parent, device_t self, void *aux) 159 { 160 struct coram_softc *sc = device_private(self); 161 const struct pci_attach_args *pa = aux; 162 pci_intr_handle_t ih; 163 pcireg_t reg; 164 const char *intrstr; 165 struct coram_iic_softc *cic; 166 uint32_t value; 167 int i; 168 #ifdef CORAM_ATTACH_I2C 169 struct i2cbus_attach_args iba; 170 #endif 171 char intrbuf[PCI_INTRSTR_LEN]; 172 173 sc->sc_dev = self; 174 175 pci_aprint_devinfo(pa, NULL); 176 177 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 178 sc->sc_board = coram_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)); 179 KASSERT(sc->sc_board != NULL); 180 181 if (pci_mapreg_map(pa, CX23885_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 182 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 183 aprint_error_dev(self, "couldn't map memory space\n"); 184 return; 185 } 186 187 sc->sc_dmat = pa->pa_dmat; 188 sc->sc_pc = pa->pa_pc; 189 190 if (pci_intr_map(pa, &ih)) { 191 aprint_error_dev(self, "couldn't map interrupt\n"); 192 return; 193 } 194 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 195 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_VM, coram_intr, 196 self, device_xname(self)); 197 if (sc->sc_ih == NULL) { 198 aprint_error_dev(self, "couldn't establish interrupt"); 199 if (intrstr != NULL) 200 aprint_error(" at %s", intrstr); 201 aprint_error("\n"); 202 return; 203 } 204 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 205 206 /* set master */ 207 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 208 reg |= PCI_COMMAND_MASTER_ENABLE; 209 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 210 211 /* I2C */ 212 for(i = 0; i < I2C_NUM; i++) { 213 cic = &sc->sc_iic[i]; 214 215 cic->cic_sc = sc; 216 if (bus_space_subregion(sc->sc_memt, sc->sc_memh, 217 I2C_BASE + (I2C_SIZE * i), I2C_SIZE, &cic->cic_regh)) 218 panic("failed to subregion i2c"); 219 220 iic_tag_init(&cic->cic_i2c); 221 cic->cic_i2c.ic_cookie = cic; 222 cic->cic_i2c.ic_exec = coram_iic_exec; 223 224 #ifdef CORAM_ATTACH_I2C 225 /* attach iic(4) */ 226 memset(&iba, 0, sizeof(iba)); 227 iba.iba_tag = &cic->cic_i2c; 228 cic->cic_i2cdev = config_found(self, &iba, iicbus_print, 229 CFARG_IATTR, "i2cbus", 230 CFARG_EOL); 231 #endif 232 } 233 234 /* HVR1250 GPIO */ 235 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x110010); 236 #if 1 237 value &= ~0x00010001; 238 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 239 delay(5000); 240 #endif 241 value |= 0x00010001; 242 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 243 244 #if 0 245 int i; 246 uint8_t foo[256]; 247 uint8_t bar; 248 bar = 0; 249 // seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0, 256, foo, 256); 250 251 iic_acquire_bus(&sc->sc_i2c, 0); 252 iic_exec(&sc->sc_i2c, I2C_OP_READ_WITH_STOP, 0x50, &bar, 1, foo, 256, 253 0); 254 iic_release_bus(&sc->sc_i2c, 0); 255 256 printf("\n"); 257 for ( i = 0; i < 256; i++) { 258 if ( (i % 8) == 0 ) 259 printf("%02x: ", i); 260 261 printf("%02x", foo[i]); 262 263 if ( (i % 8) == 7 ) 264 printf("\n"); 265 else 266 printf(" "); 267 } 268 printf("\n"); 269 #endif 270 271 sc->sc_demod = cx24227_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x19); 272 if (sc->sc_demod == NULL) 273 aprint_error_dev(self, "couldn't open cx24227\n"); 274 sc->sc_tuner = mt2131_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x61); 275 if (sc->sc_tuner == NULL) 276 aprint_error_dev(self, "couldn't open mt2131\n"); 277 278 coram_mpeg_attach(sc); 279 280 if (!pmf_device_register(self, NULL, coram_resume)) 281 aprint_error_dev(self, "couldn't establish power handler\n"); 282 283 return; 284 } 285 286 static int 287 coram_detach(device_t self, int flags) 288 { 289 struct coram_softc *sc = device_private(self); 290 struct coram_iic_softc *cic; 291 unsigned int i; 292 int error; 293 294 error = coram_mpeg_detach(sc, flags); 295 if (error) 296 return error; 297 298 if (sc->sc_tuner) 299 mt2131_close(sc->sc_tuner); 300 if (sc->sc_demod) 301 cx24227_close(sc->sc_demod); 302 for (i = 0; i < I2C_NUM; i++) { 303 cic = &sc->sc_iic[i]; 304 if (cic->cic_i2cdev) 305 config_detach(cic->cic_i2cdev, flags); 306 iic_tag_fini(&cic->cic_i2c); 307 } 308 pmf_device_deregister(self); 309 310 if (sc->sc_mems) 311 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 312 if (sc->sc_ih) 313 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 314 315 return 0; 316 } 317 318 static int 319 coram_rescan(device_t self, const char *ifattr, const int *locs) 320 { 321 struct coram_softc *sc = device_private(self); 322 struct dtv_attach_args daa; 323 324 daa.hw = &coram_dtv_if; 325 daa.priv = sc; 326 327 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL) 328 sc->sc_dtvdev = config_found(sc->sc_dev, &daa, dtv_print, 329 CFARG_IATTR, "dtvbus", 330 CFARG_EOL); 331 332 return 0; 333 } 334 335 static void 336 coram_childdet(device_t self, device_t child) 337 { 338 struct coram_softc *sc = device_private(self); 339 struct coram_iic_softc *cic; 340 unsigned int i; 341 342 if (sc->sc_dtvdev == child) 343 sc->sc_dtvdev = NULL; 344 345 for (i = 0; i < I2C_NUM; i++) { 346 cic = &sc->sc_iic[i]; 347 if (cic->cic_i2cdev == child) 348 cic->cic_i2cdev = NULL; 349 } 350 } 351 352 static int 353 coram_intr(void *v) 354 { 355 device_t self = v; 356 struct coram_softc *sc; 357 uint32_t val; 358 359 sc = device_private(self); 360 361 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSTAT ); 362 if (val == 0) 363 return 0; /* not ours */ 364 365 /* vid c */ 366 if (val & __BIT(2)) 367 coram_mpeg_intr(sc); 368 369 if (val & ~__BIT(2)) 370 printf("%s %08x\n", __func__, val); 371 372 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, val); 373 374 return 1; 375 } 376 377 static const struct coram_board * 378 coram_board_lookup(uint16_t vendor, uint16_t product) 379 { 380 unsigned int i; 381 382 for (i = 0; i < __arraycount(coram_boards); i++) { 383 if (coram_boards[i].vendor == vendor && 384 coram_boards[i].product == product) { 385 return &coram_boards[i]; 386 } 387 } 388 389 return NULL; 390 } 391 392 #define CXDTV_TS_RISCI2 (1 << 4) 393 #define CXDTV_TS_RISCI1 (1 << 0) 394 395 #define CXDTV_TS_RISCI (CXDTV_TS_RISCI1|CXDTV_TS_RISCI2) 396 397 static int 398 coram_mpeg_intr(struct coram_softc *sc) 399 { 400 struct dtv_payload payload; 401 uint32_t s, m, v; 402 int i; 403 404 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT); 405 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 406 407 if ((s & m) == 0) 408 return 0; 409 410 if ( (s & ~CXDTV_TS_RISCI) != 0 ) { 411 printf("%s: unexpected TS IS %08x\n", 412 device_xname(sc->sc_dev), s); 413 414 printf("cmds:\n"); 415 for(i = 0; i < 20; i++) 416 { 417 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x10140 +(i*4)); 418 printf("%06x %08x\n", 0x10140+(i*4), v); 419 } 420 } 421 422 if (sc->sc_dtvsubmitcb == NULL) 423 goto done; 424 425 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 426 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 427 0, CORAM_TS_PKTSIZE, 428 BUS_DMASYNC_POSTREAD); 429 payload.data = KERNADDR(sc->sc_dma); 430 payload.size = CORAM_TS_PKTSIZE; 431 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 432 } 433 434 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 435 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 436 CORAM_TS_PKTSIZE, CORAM_TS_PKTSIZE, 437 BUS_DMASYNC_POSTREAD); 438 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CORAM_TS_PKTSIZE; 439 payload.size = CORAM_TS_PKTSIZE; 440 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 441 } 442 443 done: 444 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, s); 445 446 return 1; 447 } 448 449 static bool 450 coram_resume(device_t dv, const pmf_qual_t *qual) 451 { 452 return true; 453 } 454 455 /* I2C Bus */ 456 457 #define I2C_ADDR 0x0000 458 #define I2C_WDATA 0x0004 459 #define I2C_CTRL 0x0008 460 #define I2C_RDATA 0x000c 461 #define I2C_STAT 0x0010 462 463 #define I2C_EXTEND (1 << 3) 464 #define I2C_NOSTOP (1 << 4) 465 466 static int 467 coram_iic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 468 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 469 { 470 struct coram_iic_softc *cic; 471 int ret; 472 473 cic = cookie; 474 475 if(cmdlen) { 476 ret = coram_iic_write(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 477 if(ret) 478 return ret; 479 } 480 481 if(len) { 482 ret = coram_iic_read(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 483 if(ret) 484 return ret; 485 } 486 487 488 return 0; 489 490 } 491 492 static int 493 coram_iic_read(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 494 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 495 { 496 uint8_t *rb; 497 uint32_t ctrl; 498 int bn; 499 500 rb = buf; 501 502 for ( bn = 0; bn < len; bn++) { 503 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2) | 1; 504 if ( bn < len - 1 ) 505 ctrl |= I2C_NOSTOP | I2C_EXTEND; 506 507 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addr<<25); 508 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 509 510 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 511 I2C_STAT) & 0x02)) { 512 delay(25); 513 } 514 if((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 515 I2C_STAT) & 0x01) == 0x00) { 516 // printf("%s %d no ack\n", __func__, bn); 517 return EIO; 518 } 519 520 rb[bn] = bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_RDATA); 521 522 } 523 524 return 0; 525 } 526 527 static int 528 coram_iic_write(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 529 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 530 { 531 const uint8_t *wb; 532 uint32_t wdata, addrreg, ctrl; 533 int bn; 534 535 wb = cmdbuf; 536 537 addrreg = (addr << 25) | wb[0]; 538 wdata = wb[0]; 539 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 540 541 if ( cmdlen > 1 ) 542 ctrl |= I2C_NOSTOP | I2C_EXTEND; 543 else if (len) 544 ctrl |= I2C_NOSTOP; 545 546 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 547 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 548 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 549 550 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 551 delay(25); } 552 553 for ( bn = 1; bn < cmdlen; bn++) { 554 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 555 wdata = wb[bn]; 556 557 if ( bn < cmdlen - 1 ) 558 ctrl |= I2C_NOSTOP | I2C_EXTEND; 559 else if (len) 560 ctrl |= I2C_NOSTOP; 561 562 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 563 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 564 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 565 566 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 567 delay(25); } 568 } 569 570 return 0; 571 } 572 573 static int 574 coram_mpeg_attach(struct coram_softc *sc) 575 { 576 struct coram_sram_ch *ch; 577 578 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 579 580 sc->sc_riscbufsz = ch->csc_riscsz; 581 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 582 583 coram_mpeg_reset(sc); 584 585 sc->sc_tsbuf = NULL; 586 587 coram_rescan(sc->sc_dev, NULL, NULL); 588 589 return (sc->sc_dtvdev != NULL); 590 } 591 592 static int 593 coram_mpeg_detach(struct coram_softc *sc, int flags) 594 { 595 struct coram_sram_ch *ch = &coram_sram_chs[CORAM_SRAM_CH6]; 596 int error; 597 598 if (sc->sc_dtvdev) { 599 error = config_detach(sc->sc_dtvdev, flags); 600 if (error) 601 return error; 602 } 603 if (sc->sc_riscbuf) { 604 kmem_free(sc->sc_riscbuf, ch->csc_riscsz); 605 } 606 607 return 0; 608 } 609 610 static void 611 coram_dtv_get_devinfo(void *cookie, struct dvb_frontend_info *info) 612 { 613 struct coram_softc *sc = cookie; 614 615 memset(info, 0, sizeof(*info)); 616 strlcpy(info->name, sc->sc_board->name, sizeof(info->name)); 617 info->type = FE_ATSC; 618 info->frequency_min = 54000000; 619 info->frequency_max = 858000000; 620 info->frequency_stepsize = 62500; 621 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 622 } 623 624 static int 625 coram_dtv_open(void *cookie, int flags) 626 { 627 struct coram_softc *sc = cookie; 628 629 #ifdef CORAM_DEBUG 630 device_printf(sc->sc_dev, "%s\n", __func__); 631 #endif 632 633 //KASSERT(sc->sc_tsbuf == NULL); 634 635 if (sc->sc_tuner == NULL || sc->sc_demod == NULL) 636 return ENXIO; 637 638 coram_mpeg_reset(sc); 639 640 /* allocate two alternating DMA areas for MPEG TS packets */ 641 sc->sc_tsbuf = coram_mpeg_malloc(sc, CORAM_TS_PKTSIZE * 2); 642 643 if (sc->sc_tsbuf == NULL) 644 return ENOMEM; 645 646 return 0; 647 } 648 649 static void 650 coram_dtv_close(void *cookie) 651 { 652 struct coram_softc *sc = cookie; 653 654 #ifdef CORAM_DEBUG 655 device_printf(sc->sc_dev, "%s\n", __func__); 656 #endif 657 658 coram_mpeg_halt(sc); 659 660 if (sc->sc_tsbuf != NULL) { 661 coram_mpeg_free(sc, sc->sc_tsbuf); 662 sc->sc_tsbuf = NULL; 663 } 664 } 665 666 static int 667 coram_dtv_set_tuner(void *cookie, const struct dvb_frontend_parameters *params) 668 { 669 struct coram_softc *sc = cookie; 670 671 KASSERT(sc->sc_tuner != NULL); 672 mt2131_tune_dtv(sc->sc_tuner, params); 673 KASSERT(sc->sc_demod != NULL); 674 return cx24227_set_modulation(sc->sc_demod, params->u.vsb.modulation); 675 } 676 677 static fe_status_t 678 coram_dtv_get_status(void *cookie) 679 { 680 struct coram_softc *sc = cookie; 681 682 if (sc->sc_demod == NULL) 683 return ENXIO; 684 685 return cx24227_get_dtv_status(sc->sc_demod); 686 } 687 688 static uint16_t 689 coram_dtv_get_signal_strength(void *cookie) 690 { 691 return 0; 692 } 693 694 static uint16_t 695 coram_dtv_get_snr(void *cookie) 696 { 697 return 0; 698 } 699 700 static int 701 coram_dtv_start_transfer(void *cookie, 702 void (*cb)(void *, const struct dtv_payload *), void *arg) 703 { 704 struct coram_softc *sc = cookie; 705 706 #ifdef CORAM_DEBUG 707 device_printf(sc->sc_dev, "%s\n", __func__); 708 #endif 709 710 sc->sc_dtvsubmitcb = cb; 711 sc->sc_dtvsubmitarg = arg; 712 713 coram_mpeg_trigger(sc, sc->sc_tsbuf); 714 715 return 0; 716 } 717 718 static int 719 coram_dtv_stop_transfer(void *cookie) 720 { 721 struct coram_softc *sc = cookie; 722 723 #ifdef CORAM_DEBUG 724 device_printf(sc->sc_dev, "%s\n", __func__); 725 #endif 726 727 coram_mpeg_halt(sc); 728 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 729 730 sc->sc_dtvsubmitcb = NULL; 731 sc->sc_dtvsubmitarg = NULL; 732 733 return 0; 734 } 735 736 737 static int 738 coram_mpeg_reset(struct coram_softc *sc) 739 { 740 /* hold RISC in reset */ 741 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, 0); 742 743 /* disable fifo + risc */ 744 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 745 746 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 747 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 0); 748 749 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, 0); 750 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, 0); 751 752 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 753 754 return 0; 755 } 756 757 static void * 758 coram_mpeg_malloc(struct coram_softc *sc, size_t size) 759 { 760 struct coram_dma *p; 761 int err; 762 763 p = kmem_alloc(sizeof(struct coram_dma), KM_SLEEP); 764 err = coram_allocmem(sc, size, 16, p); 765 if (err) { 766 kmem_free(p, sizeof(struct coram_dma)); 767 return NULL; 768 } 769 770 p->next = sc->sc_dma; 771 sc->sc_dma = p; 772 773 return KERNADDR(p); 774 } 775 776 static int 777 coram_allocmem(struct coram_softc *sc, size_t size, size_t align, 778 struct coram_dma *p) 779 { 780 int err; 781 782 p->size = size; 783 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 784 p->segs, sizeof(p->segs) / sizeof(p->segs[0]), 785 &p->nsegs, BUS_DMA_NOWAIT); 786 if (err) 787 return err; 788 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 789 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 790 if (err) 791 goto free; 792 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 793 BUS_DMA_NOWAIT, &p->map); 794 if (err) 795 goto unmap; 796 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 797 BUS_DMA_NOWAIT); 798 if (err) 799 goto destroy; 800 801 return 0; 802 destroy: 803 bus_dmamap_destroy(sc->sc_dmat, p->map); 804 unmap: 805 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 806 free: 807 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 808 809 return err; 810 } 811 812 static int 813 coram_mpeg_halt(struct coram_softc *sc) 814 { 815 uint32_t v; 816 817 #ifdef CORAM_DEBUG 818 device_printf(sc->sc_dev, "%s\n", __func__); 819 #endif 820 821 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 822 823 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 824 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 825 v & __BIT(2)); 826 827 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 828 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 829 v & 0); 830 831 return 0; 832 } 833 834 static void 835 coram_mpeg_free(struct coram_softc *sc, void *addr) 836 { 837 struct coram_dma *p; 838 struct coram_dma **pp; 839 840 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) 841 if (KERNADDR(p) == addr) { 842 coram_freemem(sc, p); 843 *pp = p->next; 844 kmem_free(p, sizeof(struct coram_dma)); 845 return; 846 } 847 848 printf("%s: %p is already free\n", device_xname(sc->sc_dev), addr); 849 return; 850 } 851 852 static int 853 coram_freemem(struct coram_softc *sc, struct coram_dma *p) 854 { 855 bus_dmamap_unload(sc->sc_dmat, p->map); 856 bus_dmamap_destroy(sc->sc_dmat, p->map); 857 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 858 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 859 860 return 0; 861 } 862 863 static int 864 coram_mpeg_trigger(struct coram_softc *sc, void *buf) 865 { 866 struct coram_dma *p; 867 struct coram_sram_ch *ch; 868 uint32_t v; 869 870 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 871 872 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 873 continue; 874 if (p == NULL) { 875 printf("%s: coram_mpeg_trigger: bad addr %p\n", 876 device_xname(sc->sc_dev), buf); 877 return ENOENT; 878 } 879 880 /* disable fifo + risc */ 881 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 882 883 coram_risc_buffer(sc, CORAM_TS_PKTSIZE, 1); 884 coram_sram_ch_setup(sc, ch, CORAM_TS_PKTSIZE); 885 886 /* let me hope this bit is the same as on the 2388[0-3] */ 887 /* software reset */ 888 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 0x0040); 889 delay (100*1000); 890 891 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_LNGTH, CORAM_TS_PKTSIZE); 892 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_HW_SOP_CTL, 0x47 << 16 | 188 << 4); 893 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_TS_CLK_EN, 1); 894 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_VLD_MISC, 0); 895 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 12); 896 delay (100*1000); 897 898 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PAD_CTRL); 899 v &= ~0x4; /* Clear TS2_SOP_OE */ 900 bus_space_write_4(sc->sc_memt, sc->sc_memh, PAD_CTRL, v); 901 902 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 903 v |= 0x111111; 904 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, v); 905 906 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL); 907 v |= 0x11; /* Enable RISC controller and FIFO */ 908 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, v); 909 910 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2); 911 v |= __BIT(5); /* Enable RISC controller */ 912 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, v); 913 914 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 915 v |= 0x001f00; 916 v |= 0x04; 917 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, v); 918 919 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 920 #ifdef CORAM_DEBUG 921 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 922 #endif 923 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 924 #ifdef CORAM_DEBUG 925 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 926 #endif 927 delay(100*1000); 928 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 929 #ifdef CORAM_DEBUG 930 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 931 #endif 932 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 933 #ifdef CORAM_DEBUG 934 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 935 #endif 936 937 return 0; 938 } 939 940 static int 941 coram_risc_buffer(struct coram_softc *sc, uint32_t bpl, uint32_t lines) 942 { 943 uint32_t *rm; 944 uint32_t size; 945 946 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 947 size += 2; 948 949 if (sc->sc_riscbuf == NULL) { 950 return ENOMEM; 951 } 952 953 rm = (uint32_t *)sc->sc_riscbuf; 954 coram_risc_field(sc, rm, bpl); 955 956 return 0; 957 } 958 959 static int 960 coram_risc_field(struct coram_softc *sc, uint32_t *rm, uint32_t bpl) 961 { 962 struct coram_dma *p; 963 964 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 965 continue; 966 if (p == NULL) { 967 printf("%s: coram_risc_field: bad addr %p\n", 968 device_xname(sc->sc_dev), sc->sc_tsbuf); 969 return ENOENT; 970 } 971 972 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 973 974 rm = sc->sc_riscbuf; 975 976 /* htole32 will be done when program is copied to chip sram */ 977 978 /* XXX */ 979 *(rm++) = (CX_RISC_SYNC|0); 980 981 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 982 *(rm++) = (DMAADDR(p) + 0 * bpl); 983 *(rm++) = 0; /* high dword */ 984 985 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 986 *(rm++) = (DMAADDR(p) + 1 * bpl); 987 *(rm++) = 0; 988 989 *(rm++) = (CX_RISC_JUMP|1); 990 *(rm++) = (coram_sram_chs[CORAM_SRAM_CH6].csc_risc + 4); 991 *(rm++) = 0; 992 993 return 0; 994 } 995 996 static int 997 coram_sram_ch_setup(struct coram_softc *sc, struct coram_sram_ch *csc, 998 uint32_t bpl) 999 { 1000 unsigned int i, lines; 1001 uint32_t cdt; 1002 1003 /* XXX why round? */ 1004 bpl = (bpl + 7) & ~7; 1005 cdt = csc->csc_cdt; 1006 lines = csc->csc_fifosz / bpl; 1007 #ifdef CORAM_DEBUG 1008 printf("%s %d lines\n", __func__, lines); 1009 #endif 1010 1011 /* fill in CDT */ 1012 for (i = 0; i < lines; i++) { 1013 #ifdef CORAM_DEBUG 1014 printf("CDT ent %08x, %08x\n", cdt + (16 * i), 1015 csc->csc_fifo + (bpl * i)); 1016 #endif 1017 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1018 cdt + (16 * i), csc->csc_fifo + (bpl * i)); 1019 } 1020 1021 /* copy program */ 1022 /* converts program to little endian as it goes into sram */ 1023 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 1024 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 1025 1026 /* fill in CMDS */ 1027 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1028 csc->csc_cmds + CMDS_O_IRPC, csc->csc_risc); 1029 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1030 csc->csc_cmds + CMDS_O_IRPC + 4, 0); 1031 1032 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1033 csc->csc_cmds + CMDS_O_CDTB, csc->csc_cdt); 1034 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1035 csc->csc_cmds + CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 1036 1037 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1038 csc->csc_cmds + CMDS_O_IQB, csc->csc_iq); 1039 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1040 csc->csc_cmds + CMDS_O_IQS, 1041 CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 1042 1043 /* zero rest of CMDS */ 1044 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x18, 0, 20); 1045 1046 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1047 csc->csc_ptr1, csc->csc_fifo); 1048 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1049 csc->csc_ptr2, cdt); 1050 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1051 csc->csc_cnt2, (lines * 16) >> 3); 1052 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1053 csc->csc_cnt1, (bpl >> 3) - 1); 1054 1055 return 0; 1056 } 1057 1058 MODULE(MODULE_CLASS_DRIVER, coram, "cx24227,mt2131,pci"); 1059 1060 #ifdef _MODULE 1061 #include "ioconf.c" 1062 #endif 1063 1064 static int 1065 coram_modcmd(modcmd_t cmd, void *v) 1066 { 1067 int error = 0; 1068 1069 switch (cmd) { 1070 case MODULE_CMD_INIT: 1071 #ifdef _MODULE 1072 error = config_init_component(cfdriver_ioconf_coram, 1073 cfattach_ioconf_coram, cfdata_ioconf_coram); 1074 #endif 1075 return error; 1076 case MODULE_CMD_FINI: 1077 #ifdef _MODULE 1078 error = config_fini_component(cfdriver_ioconf_coram, 1079 cfattach_ioconf_coram, cfdata_ioconf_coram); 1080 #endif 1081 return error; 1082 default: 1083 return ENOTTY; 1084 } 1085 } 1086
Indexes created Wed Sep 24 05:09:52 GMT 2025