coram.c revision 1.5
1 /* $NetBSD: coram.c,v 1.5 2011/08/06 11:37:56 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: coram.c,v 1.5 2011/08/06 11:37:56 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 40 #include <dev/dtv/dtvif.h> 41 42 #include <dev/pci/cx23885reg.h> 43 #include <dev/pci/coramvar.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/i2c/i2cvar.h> 49 #include <dev/i2c/at24cxxvar.h> 50 51 #include <dev/i2c/cx24227var.h> 52 #include <dev/i2c/mt2131var.h> 53 54 /* #define CORAM_DEBUG */ 55 /* #define CORAM_ATTACH_I2C */ 56 57 static int coram_match(device_t, cfdata_t, void *); 58 static void coram_attach(device_t, device_t, void *); 59 static int coram_detach(device_t, int); 60 static void coram_childdet(device_t, device_t); 61 static bool coram_resume(device_t, const pmf_qual_t *); 62 static int coram_intr(void *); 63 64 static int coram_iic_exec(void *, i2c_op_t, i2c_addr_t, 65 const void *, size_t, void *, size_t, int); 66 static int coram_iic_acquire_bus(void *, int); 67 static void coram_iic_release_bus(void *, int); 68 static int coram_iic_read(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 69 const void *, size_t, void *, size_t, int); 70 static int coram_iic_write(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 71 const void *, size_t, void *, size_t, int); 72 73 static void coram_dtv_get_devinfo(void *, struct dvb_frontend_info *); 74 static int coram_dtv_open(void *, int); 75 static void coram_dtv_close(void *); 76 static int coram_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 77 static fe_status_t coram_dtv_get_status(void *); 78 static uint16_t coram_dtv_get_signal_strength(void *); 79 static uint16_t coram_dtv_get_snr(void *); 80 static int coram_dtv_start_transfer(void *); 81 static int coram_dtv_stop_transfer(void *); 82 83 static int coram_mpeg_attach(struct coram_softc *); 84 static int coram_mpeg_detach(struct coram_softc *, int); 85 static int coram_mpeg_reset(struct coram_softc *); 86 static void * coram_mpeg_malloc(struct coram_softc *, size_t); 87 static int coram_allocmem(struct coram_softc *, size_t, size_t, struct coram_dma *); 88 static void coram_mpeg_free(struct coram_softc *, void *); 89 static int coram_mpeg_halt(struct coram_softc *); 90 static int coram_freemem(struct coram_softc *, struct coram_dma *); 91 static int coram_mpeg_trigger(struct coram_softc *, void *); 92 static int coram_risc_buffer(struct coram_softc *, uint32_t, uint32_t); 93 static int coram_risc_field(struct coram_softc *, uint32_t *, uint32_t); 94 static int coram_sram_ch_setup(struct coram_softc *, struct coram_sram_ch *, uint32_t); 95 static int coram_mpeg_intr(struct coram_softc *); 96 97 CFATTACH_DECL2_NEW(coram, sizeof(struct coram_softc), 98 coram_match, coram_attach, coram_detach, NULL, NULL, coram_childdet); 99 100 #define CORAM_SRAM_CH6 0 101 102 #define CORAM_TS_PKTSIZE (188 * 8) 103 104 static struct coram_sram_ch coram_sram_chs[] = { 105 [CORAM_SRAM_CH6] = { 106 .csc_cmds= 0x10140, 107 .csc_iq = 0x10500, 108 .csc_iqsz = 0x40, 109 .csc_cdt = 0x10600, 110 .csc_cdtsz = 0x10, 111 .csc_fifo = 0x6000, 112 .csc_fifosz = 0x1000, 113 .csc_risc = 0x10800, 114 .csc_riscsz = 0x800, 115 .csc_ptr1 = DMA5_PTR1, 116 .csc_ptr2 = DMA5_PTR2, 117 .csc_cnt1 = DMA5_CNT1, 118 .csc_cnt2 = DMA5_CNT2, 119 }, 120 }; 121 122 //#define PCI_PRODUCT_CONEXANT_CX23885 0x8852 123 124 static const struct dtv_hw_if coram_dtv_if = { 125 .get_devinfo = coram_dtv_get_devinfo, 126 .open = coram_dtv_open, 127 .close = coram_dtv_close, 128 .set_tuner = coram_dtv_set_tuner, 129 .get_status = coram_dtv_get_status, 130 .get_signal_strength = coram_dtv_get_signal_strength, 131 .get_snr = coram_dtv_get_snr, 132 .start_transfer = coram_dtv_start_transfer, 133 .stop_transfer = coram_dtv_stop_transfer, 134 }; 135 136 static int 137 coram_match(device_t parent, cfdata_t match, void *v) 138 { 139 const struct pci_attach_args *pa = v; 140 141 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 142 return 0; 143 144 switch (PCI_PRODUCT(pa->pa_id)) { 145 case PCI_PRODUCT_CONEXANT_CX23885: 146 return 1; 147 } 148 149 /* XXX only match supported boards */ 150 151 return 0; 152 } 153 154 static void 155 coram_attach(device_t parent, device_t self, void *v) 156 { 157 struct coram_softc *sc; 158 const struct pci_attach_args *pa = v; 159 pci_intr_handle_t ih; 160 pcireg_t reg; 161 const char *intrstr; 162 char devinfo[76]; 163 struct coram_iic_softc *cic; 164 uint32_t value; 165 int i; 166 #ifdef CORAM_ATTACH_I2C 167 struct i2cbus_attach_args iba; 168 #endif 169 170 sc = device_private(self); 171 172 sc->sc_dev = self; 173 174 aprint_naive("\n"); 175 176 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 177 178 sc->sc_vendor = PCI_VENDOR(reg); 179 sc->sc_product = PCI_PRODUCT(reg); 180 181 pci_devinfo(reg, pa->pa_class, 0, devinfo, sizeof(devinfo)); 182 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 183 184 if (pci_mapreg_map(pa, CX23885_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 185 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 186 aprint_error_dev(self, "couldn't map memory space\n"); 187 return; 188 } 189 190 sc->sc_dmat = pa->pa_dmat; 191 sc->sc_pc = pa->pa_pc; 192 193 if (pci_intr_map(pa, &ih)) { 194 aprint_error_dev(self, "couldn't map interrupt\n"); 195 return; 196 } 197 intrstr = pci_intr_string(pa->pa_pc, ih); 198 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_VM, 199 coram_intr, (void *)self); 200 if (sc->sc_ih == NULL) { 201 aprint_error_dev(self, "couldn't establish interrupt"); 202 if (intrstr != NULL) 203 aprint_error(" at %s", intrstr); 204 aprint_error("\n"); 205 return; 206 } 207 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 208 209 /* set master */ 210 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 211 reg |= PCI_COMMAND_MASTER_ENABLE; 212 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 213 214 /* I2C */ 215 for(i = 0; i < I2C_NUM; i++) { 216 cic = &sc->sc_iic[i]; 217 218 cic->cic_sc = sc; 219 if(bus_space_subregion(sc->sc_memt, sc->sc_memh, I2C_BASE + (I2C_SIZE * i), I2C_SIZE, &cic->cic_regh)) 220 panic("failed to subregion i2c"); 221 222 mutex_init(&cic->cic_busmutex, MUTEX_DRIVER, IPL_NONE); 223 cic->cic_i2c.ic_cookie = cic; 224 cic->cic_i2c.ic_acquire_bus = coram_iic_acquire_bus; 225 cic->cic_i2c.ic_release_bus = coram_iic_release_bus; 226 cic->cic_i2c.ic_exec = coram_iic_exec; 227 228 #ifdef CORAM_ATTACH_I2C 229 /* attach iic(4) */ 230 memset(&iba, 0, sizeof(iba)); 231 iba.iba_tag = &cic->cic_i2c; 232 iba.iba_type = I2C_TYPE_SMBUS; 233 cic->cic_i2cdev = config_found_ia(self, "i2cbus", 234 &iba, iicbus_print); 235 #endif 236 } 237 238 /* HVR1250 GPIO */ 239 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x110010); 240 #if 1 241 value &= ~0x00010001; 242 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 243 delay(5000); 244 #endif 245 value |= 0x00010001; 246 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 247 248 #if 0 249 int i; 250 uint8_t foo[256]; 251 uint8_t bar; 252 bar = 0; 253 // seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0, 256, foo, 256); 254 255 iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL); 256 iic_exec(&sc->sc_i2c, I2C_OP_READ_WITH_STOP, 0x50, &bar, 1, foo, 256, I2C_F_POLL); 257 iic_release_bus(&sc->sc_i2c, I2C_F_POLL); 258 259 printf("\n"); 260 for ( i = 0; i < 256; i++) { 261 if ( (i % 8) == 0 ) 262 printf("%02x: ", i); 263 264 printf("%02x", foo[i]); 265 266 if ( (i % 8) == 7 ) 267 printf("\n"); 268 else 269 printf(" "); 270 } 271 printf("\n"); 272 #endif 273 274 sc->sc_demod = cx24227_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x19); 275 if (sc->sc_demod == NULL) 276 aprint_error_dev(self, "couldn't open cx24227\n"); 277 sc->sc_tuner = mt2131_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x61); 278 if (sc->sc_tuner == NULL) 279 aprint_error_dev(self, "couldn't open mt2131\n"); 280 281 coram_mpeg_attach(sc); 282 283 if (!pmf_device_register(self, NULL, coram_resume)) 284 aprint_error_dev(self, "couldn't establish power handler\n"); 285 286 return; 287 } 288 289 static int 290 coram_detach(device_t self, int flags) 291 { 292 struct coram_softc *sc = device_private(self); 293 struct coram_iic_softc *cic; 294 unsigned int i; 295 int error; 296 297 error = coram_mpeg_detach(sc, flags); 298 if (error) 299 return error; 300 301 if (sc->sc_tuner) 302 mt2131_close(sc->sc_tuner); 303 if (sc->sc_demod) 304 cx24227_close(sc->sc_demod); 305 for (i = 0; i < I2C_NUM; i++) { 306 cic = &sc->sc_iic[i]; 307 if (cic->cic_i2cdev) 308 config_detach(cic->cic_i2cdev, flags); 309 mutex_destroy(&cic->cic_busmutex); 310 } 311 pmf_device_deregister(self); 312 313 if (sc->sc_mems) 314 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 315 if (sc->sc_ih) 316 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 317 318 return 0; 319 } 320 321 static void 322 coram_childdet(device_t self, device_t child) 323 { 324 struct coram_softc *sc = device_private(self); 325 struct coram_iic_softc *cic; 326 unsigned int i; 327 328 if (sc->sc_dtvdev == child) 329 sc->sc_dtvdev = NULL; 330 331 for (i = 0; i < I2C_NUM; i++) { 332 cic = &sc->sc_iic[i]; 333 if (cic->cic_i2cdev == child) 334 cic->cic_i2cdev = NULL; 335 } 336 } 337 338 static int 339 coram_intr(void *v) 340 { 341 device_t self = v; 342 struct coram_softc *sc; 343 uint32_t val; 344 345 sc = device_private(self); 346 347 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSTAT ); 348 if (val == 0) 349 return 0; /* not ours */ 350 351 /* vid c */ 352 if (val & __BIT(2)) 353 coram_mpeg_intr(sc); 354 355 if (val & ~__BIT(2)) 356 printf("%s %08x\n", __func__, val); 357 358 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, val); 359 360 return 1; 361 } 362 363 #define CXDTV_TS_RISCI2 (1 << 4) 364 #define CXDTV_TS_RISCI1 (1 << 0) 365 366 #define CXDTV_TS_RISCI (CXDTV_TS_RISCI1|CXDTV_TS_RISCI2) 367 368 static int 369 coram_mpeg_intr(struct coram_softc *sc) 370 { 371 struct dtv_payload payload; 372 uint32_t s, m, v; 373 int i; 374 375 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT); 376 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 377 378 if ((s & m) == 0) 379 return 0; 380 381 if ( (s & ~CXDTV_TS_RISCI) != 0 ) { 382 printf("%s: unexpected TS IS %08x\n", 383 device_xname(sc->sc_dev), s); 384 385 printf("cmds:\n"); 386 for(i = 0; i < 20; i++) 387 { 388 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x10140 +(i*4)); 389 printf("%06x %08x\n", 0x10140+(i*4), v); 390 } 391 } 392 393 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 394 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 395 0, CORAM_TS_PKTSIZE, 396 BUS_DMASYNC_POSTREAD); 397 payload.data = KERNADDR(sc->sc_dma); 398 payload.size = CORAM_TS_PKTSIZE; 399 dtv_submit_payload(sc->sc_dtvdev, &payload); 400 } 401 402 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 403 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 404 CORAM_TS_PKTSIZE, CORAM_TS_PKTSIZE, 405 BUS_DMASYNC_POSTREAD); 406 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CORAM_TS_PKTSIZE; 407 payload.size = CORAM_TS_PKTSIZE; 408 dtv_submit_payload(sc->sc_dtvdev, &payload); 409 } 410 411 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, s); 412 413 return 1; 414 } 415 416 static bool 417 coram_resume(device_t dv, const pmf_qual_t *qual) 418 { 419 struct coram_softc *sc; 420 sc = device_private(dv); 421 422 return true; 423 } 424 425 static int 426 coram_iic_acquire_bus(void *cookie, int flags) 427 { 428 struct coram_iic_softc *cic; 429 430 cic = cookie; 431 432 if (flags & I2C_F_POLL) { 433 while (mutex_tryenter(&cic->cic_busmutex) == 0) 434 delay(50); 435 return 0; 436 } 437 438 mutex_enter(&cic->cic_busmutex); 439 440 return 0; 441 } 442 443 static void 444 coram_iic_release_bus(void *cookie, int flags) 445 { 446 struct coram_iic_softc *cic; 447 448 cic = cookie; 449 450 mutex_exit(&cic->cic_busmutex); 451 452 return; 453 } 454 455 /* I2C Bus */ 456 457 #define I2C_ADDR 0x0000 458 #define I2C_WDATA 0x0004 459 #define I2C_CTRL 0x0008 460 #define I2C_RDATA 0x000c 461 #define I2C_STAT 0x0010 462 463 #define I2C_EXTEND (1 << 3) 464 #define I2C_NOSTOP (1 << 4) 465 466 static int 467 coram_iic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 468 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 469 { 470 struct coram_iic_softc *cic; 471 int ret; 472 473 cic = cookie; 474 475 if(cmdlen) { 476 ret = coram_iic_write(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 477 if(ret) 478 return ret; 479 } 480 481 if(len) { 482 ret = coram_iic_read(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 483 if(ret) 484 return ret; 485 } 486 487 488 return 0; 489 490 } 491 492 static int 493 coram_iic_read(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 494 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 495 { 496 uint8_t *rb; 497 uint32_t ctrl; 498 int bn; 499 500 rb = buf; 501 502 for ( bn = 0; bn < len; bn++) { 503 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2) | 1; 504 if ( bn < len - 1 ) 505 ctrl |= I2C_NOSTOP | I2C_EXTEND; 506 507 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addr<<25); 508 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 509 510 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 511 I2C_STAT) & 0x02)) { 512 delay(25); 513 } 514 if((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 515 I2C_STAT) & 0x01) == 0x00) { 516 // printf("%s %d no ack\n", __func__, bn); 517 return EIO; 518 } 519 520 rb[bn] = bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_RDATA); 521 522 } 523 524 return 0; 525 } 526 527 static int 528 coram_iic_write(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 529 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 530 { 531 const uint8_t *wb; 532 uint32_t wdata, addrreg, ctrl; 533 int bn; 534 535 wb = cmdbuf; 536 537 addrreg = (addr << 25) | wb[0]; 538 wdata = wb[0]; 539 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 540 541 if ( cmdlen > 1 ) 542 ctrl |= I2C_NOSTOP | I2C_EXTEND; 543 else if (len) 544 ctrl |= I2C_NOSTOP; 545 546 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 547 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 548 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 549 550 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 551 delay(25); } 552 553 for ( bn = 1; bn < cmdlen; bn++) { 554 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 555 wdata = wb[bn]; 556 557 if ( bn < cmdlen - 1 ) 558 ctrl |= I2C_NOSTOP | I2C_EXTEND; 559 else if (len) 560 ctrl |= I2C_NOSTOP; 561 562 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 563 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 564 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 565 566 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 567 delay(25); } 568 } 569 570 return 0; 571 } 572 573 static int 574 coram_mpeg_attach(struct coram_softc *sc) 575 { 576 struct dtv_attach_args daa; 577 struct coram_sram_ch *ch; 578 579 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 580 581 sc->sc_riscbufsz = ch->csc_riscsz; 582 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 583 584 if ( sc->sc_riscbuf == NULL ) 585 panic("riscbuf null"); 586 587 coram_mpeg_reset(sc); 588 589 daa.hw = &coram_dtv_if; 590 daa.priv = sc; 591 592 sc->sc_tsbuf = NULL; 593 594 sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus", &daa, dtv_print); 595 596 return (sc->sc_dtvdev != NULL); 597 } 598 599 static int 600 coram_mpeg_detach(struct coram_softc *sc, int flags) 601 { 602 struct coram_sram_ch *ch = &coram_sram_chs[CORAM_SRAM_CH6]; 603 int error; 604 605 if (sc->sc_dtvdev) { 606 error = config_detach(sc->sc_dtvdev, flags); 607 if (error) 608 return error; 609 } 610 if (sc->sc_riscbuf) { 611 kmem_free(sc->sc_riscbuf, ch->csc_riscsz); 612 } 613 614 return 0; 615 } 616 617 static void 618 coram_dtv_get_devinfo(void *cookie, struct dvb_frontend_info *info) 619 { 620 memset(info, 0, sizeof(*info)); 621 strlcpy(info->name, "CX23885", sizeof(info->name)); 622 info->type = FE_ATSC; 623 info->frequency_min = 54000000; 624 info->frequency_max = 858000000; 625 info->frequency_stepsize = 62500; 626 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 627 } 628 629 static int 630 coram_dtv_open(void *cookie, int flags) 631 { 632 struct coram_softc *sc = cookie; 633 634 #ifdef CORAM_DEBUG 635 device_printf(sc->sc_dev, "%s\n", __func__); 636 #endif 637 638 //KASSERT(sc->sc_tsbuf == NULL); 639 640 if (sc->sc_tuner == NULL || sc->sc_demod == NULL) 641 return ENXIO; 642 643 coram_mpeg_reset(sc); 644 645 /* allocate two alternating DMA areas for MPEG TS packets */ 646 sc->sc_tsbuf = coram_mpeg_malloc(sc, CORAM_TS_PKTSIZE * 2); 647 648 if (sc->sc_tsbuf == NULL) 649 return ENOMEM; 650 651 return 0; 652 } 653 654 static void 655 coram_dtv_close(void *cookie) 656 { 657 struct coram_softc *sc = cookie; 658 659 #ifdef CORAM_DEBUG 660 device_printf(sc->sc_dev, "%s\n", __func__); 661 #endif 662 663 coram_mpeg_halt(sc); 664 665 if (sc->sc_tsbuf != NULL) { 666 coram_mpeg_free(sc, sc->sc_tsbuf); 667 sc->sc_tsbuf = NULL; 668 } 669 } 670 671 static int 672 coram_dtv_set_tuner(void *cookie, const struct dvb_frontend_parameters *params) 673 { 674 struct coram_softc *sc = cookie; 675 676 KASSERT(sc->sc_tuner != NULL); 677 mt2131_tune_dtv(sc->sc_tuner, params); 678 KASSERT(sc->sc_demod != NULL); 679 return cx24227_set_modulation(sc->sc_demod, params->u.vsb.modulation); 680 } 681 682 static fe_status_t 683 coram_dtv_get_status(void *cookie) 684 { 685 struct coram_softc *sc = cookie; 686 687 if (sc->sc_demod == NULL) 688 return ENXIO; 689 690 return cx24227_get_dtv_status(sc->sc_demod);; 691 } 692 693 static uint16_t 694 coram_dtv_get_signal_strength(void *cookie) 695 { 696 return 0; 697 } 698 699 static uint16_t 700 coram_dtv_get_snr(void *cookie) 701 { 702 return 0; 703 } 704 705 static int 706 coram_dtv_start_transfer(void *cookie) 707 { 708 struct coram_softc *sc = cookie; 709 710 #ifdef CORAM_DEBUG 711 device_printf(sc->sc_dev, "%s\n", __func__); 712 #endif 713 714 coram_mpeg_trigger(sc, sc->sc_tsbuf); 715 716 return 0; 717 } 718 719 static int 720 coram_dtv_stop_transfer(void *cookie) 721 { 722 struct coram_softc *sc = cookie; 723 724 #ifdef CORAM_DEBUG 725 device_printf(sc->sc_dev, "%s\n", __func__); 726 #endif 727 728 coram_mpeg_halt(sc); 729 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 730 731 return 0; 732 } 733 734 735 static int 736 coram_mpeg_reset(struct coram_softc *sc) 737 { 738 uint32_t v; 739 740 v = (uint32_t)-1; 741 742 /* hold RISC in reset */ 743 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, 0); 744 745 /* disable fifo + risc */ 746 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 747 748 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 749 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 0); 750 751 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, 0); 752 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, 0); 753 754 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 755 756 return 0; 757 } 758 759 static void * 760 coram_mpeg_malloc(struct coram_softc *sc, size_t size) 761 { 762 struct coram_dma *p; 763 int err; 764 765 p = kmem_alloc(sizeof(struct coram_dma), KM_SLEEP); 766 if ( p == NULL ) 767 return NULL; 768 err = coram_allocmem(sc, size, 16, p); 769 if (err) { 770 kmem_free(p, sizeof(struct coram_dma)); 771 return NULL; 772 } 773 774 p->next = sc->sc_dma; 775 sc->sc_dma = p; 776 777 return KERNADDR(p); 778 } 779 780 static int 781 coram_allocmem(struct coram_softc *sc, size_t size, size_t align, 782 struct coram_dma *p) 783 { 784 int err; 785 786 p->size = size; 787 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 788 p->segs, sizeof(p->segs) / sizeof(p->segs[0]), 789 &p->nsegs, BUS_DMA_NOWAIT); 790 if (err) 791 return err; 792 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 793 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 794 if (err) 795 goto free; 796 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 797 BUS_DMA_NOWAIT, &p->map); 798 if (err) 799 goto unmap; 800 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 801 BUS_DMA_NOWAIT); 802 if (err) 803 goto destroy; 804 805 return 0; 806 destroy: 807 bus_dmamap_destroy(sc->sc_dmat, p->map); 808 unmap: 809 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 810 free: 811 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 812 813 return err; 814 } 815 816 static int 817 coram_mpeg_halt(struct coram_softc *sc) 818 { 819 uint32_t v; 820 821 #ifdef CORAM_DEBUG 822 device_printf(sc->sc_dev, "%s\n", __func__); 823 #endif 824 825 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 826 827 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 828 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 829 v & __BIT(2)); 830 831 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 832 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 833 v & 0); 834 835 return 0; 836 } 837 838 static void 839 coram_mpeg_free(struct coram_softc *sc, void *addr) 840 { 841 struct coram_dma *p; 842 struct coram_dma **pp; 843 844 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) 845 if (KERNADDR(p) == addr) { 846 coram_freemem(sc, p); 847 *pp = p->next; 848 kmem_free(p, sizeof(struct coram_dma)); 849 return; 850 } 851 852 printf("%s: %p is already free\n", device_xname(sc->sc_dev), addr); 853 return; 854 } 855 856 static int 857 coram_freemem(struct coram_softc *sc, struct coram_dma *p) 858 { 859 bus_dmamap_unload(sc->sc_dmat, p->map); 860 bus_dmamap_destroy(sc->sc_dmat, p->map); 861 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 862 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 863 864 return 0; 865 } 866 867 static int 868 coram_mpeg_trigger(struct coram_softc *sc, void *buf) 869 { 870 struct coram_dma *p; 871 struct coram_sram_ch *ch; 872 uint32_t v; 873 874 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 875 876 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 877 continue; 878 if (p == NULL) { 879 printf("%s: coram_mpeg_trigger: bad addr %p\n", 880 device_xname(sc->sc_dev), buf); 881 return ENOENT; 882 } 883 884 /* disable fifo + risc */ 885 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 886 887 coram_risc_buffer(sc, CORAM_TS_PKTSIZE, 1); 888 coram_sram_ch_setup(sc, ch, CORAM_TS_PKTSIZE); 889 890 /* let me hope this bit is the same as on the 2388[0-3] */ 891 /* software reset */ 892 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 0x0040); 893 delay (100*1000); 894 895 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_LNGTH, CORAM_TS_PKTSIZE); 896 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_HW_SOP_CTL, 0x47 << 16 | 188 << 4); 897 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_TS_CLK_EN, 1); 898 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_VLD_MISC, 0); 899 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 12); 900 delay (100*1000); 901 902 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PAD_CTRL); 903 v &= ~0x4; /* Clear TS2_SOP_OE */ 904 bus_space_write_4(sc->sc_memt, sc->sc_memh, PAD_CTRL, v); 905 906 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 907 v |= 0x111111; 908 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, v); 909 910 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL); 911 v |= 0x11; /* Enable RISC controller and FIFO */ 912 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, v); 913 914 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2); 915 v |= __BIT(5); /* Enable RISC controller */ 916 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, v); 917 918 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 919 v |= 0x001f00; 920 v |= 0x04; 921 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, v); 922 923 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 924 #ifdef CORAM_DEBUG 925 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 926 #endif 927 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 928 #ifdef CORAM_DEBUG 929 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 930 #endif 931 delay(100*1000); 932 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 933 #ifdef CORAM_DEBUG 934 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 935 #endif 936 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 937 #ifdef CORAM_DEBUG 938 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 939 #endif 940 941 return 0; 942 } 943 944 static int 945 coram_risc_buffer(struct coram_softc *sc, uint32_t bpl, uint32_t lines) 946 { 947 uint32_t *rm; 948 uint32_t size; 949 950 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 951 size += 2; 952 953 if (sc->sc_riscbuf == NULL) { 954 return ENOMEM; 955 } 956 957 rm = (uint32_t *)sc->sc_riscbuf; 958 coram_risc_field(sc, rm, bpl); 959 960 return 0; 961 } 962 963 static int 964 coram_risc_field(struct coram_softc *sc, uint32_t *rm, uint32_t bpl) 965 { 966 struct coram_dma *p; 967 968 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 969 continue; 970 if (p == NULL) { 971 printf("%s: coram_risc_field: bad addr %p\n", 972 device_xname(sc->sc_dev), sc->sc_tsbuf); 973 return ENOENT; 974 } 975 976 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 977 978 rm = sc->sc_riscbuf; 979 980 /* htole32 will be done when program is copied to chip sram */ 981 982 /* XXX */ 983 *(rm++) = (CX_RISC_SYNC|0); 984 985 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 986 *(rm++) = (DMAADDR(p) + 0 * bpl); 987 *(rm++) = 0; /* high dword */ 988 989 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 990 *(rm++) = (DMAADDR(p) + 1 * bpl); 991 *(rm++) = 0; 992 993 *(rm++) = (CX_RISC_JUMP|1); 994 *(rm++) = (coram_sram_chs[CORAM_SRAM_CH6].csc_risc + 4); 995 *(rm++) = 0; 996 997 return 0; 998 } 999 1000 static int 1001 coram_sram_ch_setup(struct coram_softc *sc, struct coram_sram_ch *csc, 1002 uint32_t bpl) 1003 { 1004 unsigned int i, lines; 1005 uint32_t cdt; 1006 1007 /* XXX why round? */ 1008 bpl = (bpl + 7) & ~7; 1009 cdt = csc->csc_cdt; 1010 lines = csc->csc_fifosz / bpl; 1011 #ifdef CORAM_DEBUG 1012 printf("%s %d lines\n", __func__, lines); 1013 #endif 1014 1015 /* fill in CDT */ 1016 for (i = 0; i < lines; i++) { 1017 #ifdef CORAM_DEBUG 1018 printf("CDT ent %08x, %08x\n", cdt + (16 * i), 1019 csc->csc_fifo + (bpl * i)); 1020 #endif 1021 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1022 cdt + (16 * i), csc->csc_fifo + (bpl * i)); 1023 } 1024 1025 /* copy program */ 1026 /* converts program to little endian as it goes into sram */ 1027 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 1028 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 1029 1030 /* fill in CMDS */ 1031 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1032 csc->csc_cmds + CMDS_O_IRPC, csc->csc_risc); 1033 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1034 csc->csc_cmds + CMDS_O_IRPC + 4, 0); 1035 1036 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1037 csc->csc_cmds + CMDS_O_CDTB, csc->csc_cdt); 1038 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1039 csc->csc_cmds + CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 1040 1041 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1042 csc->csc_cmds + CMDS_O_IQB, csc->csc_iq); 1043 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1044 csc->csc_cmds + CMDS_O_IQS, 1045 CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 1046 1047 /* zero rest of CMDS */ 1048 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x18, 0, 20); 1049 1050 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1051 csc->csc_ptr1, csc->csc_fifo); 1052 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1053 csc->csc_ptr2, cdt); 1054 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1055 csc->csc_cnt2, (lines * 16) >> 3); 1056 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1057 csc->csc_cnt1, (bpl >> 3) - 1); 1058 1059 return 0; 1060 } 1061 1062 MODULE(MODULE_CLASS_DRIVER, coram, "dtv,cx24227,mt2131"); 1063 1064 #ifdef _MODULE 1065 #include "ioconf.c" 1066 #endif 1067 1068 static int 1069 coram_modcmd(modcmd_t cmd, void *v) 1070 { 1071 int error = 0; 1072 1073 switch (cmd) { 1074 case MODULE_CMD_INIT: 1075 #ifdef _MODULE 1076 error = config_init_component(cfdriver_ioconf_coram, 1077 cfattach_ioconf_coram, cfdata_ioconf_coram); 1078 #endif 1079 return error; 1080 case MODULE_CMD_FINI: 1081 #ifdef _MODULE 1082 error = config_fini_component(cfdriver_ioconf_coram, 1083 cfattach_ioconf_coram, cfdata_ioconf_coram); 1084 #endif 1085 return error; 1086 default: 1087 return ENOTTY; 1088 } 1089 } 1090
Indexes created Sat Sep 27 14:09:57 GMT 2025