cs4280.c revision 1.7.2.3
1 1.7.2.3 bouyer /* $NetBSD: cs4280.c,v 1.7.2.3 2000/12/08 09:12:31 bouyer Exp $ */ 2 1.7.2.2 bouyer 3 1.7.2.2 bouyer /* 4 1.7.2.2 bouyer * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 1.7.2.2 bouyer * 6 1.7.2.2 bouyer * Redistribution and use in source and binary forms, with or without 7 1.7.2.2 bouyer * modification, are permitted provided that the following conditions 8 1.7.2.2 bouyer * are met: 9 1.7.2.2 bouyer * 1. Redistributions of source code must retain the above copyright 10 1.7.2.2 bouyer * notice, this list of conditions and the following disclaimer. 11 1.7.2.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright 12 1.7.2.2 bouyer * notice, this list of conditions and the following disclaimer in the 13 1.7.2.2 bouyer * documentation and/or other materials provided with the distribution. 14 1.7.2.2 bouyer * 3. All advertising materials mentioning features or use of this software 15 1.7.2.2 bouyer * must display the following acknowledgement: 16 1.7.2.2 bouyer * This product includes software developed by Tatoku Ogaito 17 1.7.2.2 bouyer * for the NetBSD Project. 18 1.7.2.2 bouyer * 4. The name of the author may not be used to endorse or promote products 19 1.7.2.2 bouyer * derived from this software without specific prior written permission 20 1.7.2.2 bouyer * 21 1.7.2.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 1.7.2.2 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 1.7.2.2 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 1.7.2.2 bouyer * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 1.7.2.2 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 1.7.2.2 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 1.7.2.2 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 1.7.2.2 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 1.7.2.2 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 1.7.2.2 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1.7.2.2 bouyer */ 32 1.7.2.2 bouyer 33 1.7.2.2 bouyer /* 34 1.7.2.2 bouyer * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 1.7.2.2 bouyer * Data sheets can be found 36 1.7.2.2 bouyer * http://www.cirrus.com/ftp/pubs/4280.pdf 37 1.7.2.2 bouyer * http://www.cirrus.com/ftp/pubs/4297.pdf 38 1.7.2.2 bouyer * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 1.7.2.2 bouyer * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 1.7.2.2 bouyer * 41 1.7.2.2 bouyer * Note: CS4610 + CS423x ISA codec should be worked with 42 1.7.2.2 bouyer * wss* at pnpbios? 43 1.7.2.2 bouyer * 44 1.7.2.2 bouyer */ 45 1.7.2.2 bouyer 46 1.7.2.2 bouyer /* 47 1.7.2.2 bouyer * TODO 48 1.7.2.2 bouyer * Joystick support 49 1.7.2.2 bouyer */ 50 1.7.2.2 bouyer 51 1.7.2.2 bouyer #if defined(CS4280_DEBUG) 52 1.7.2.2 bouyer #define DPRINTF(x) if (cs4280debug) printf x 53 1.7.2.2 bouyer #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 54 1.7.2.2 bouyer int cs4280debug = 0; 55 1.7.2.2 bouyer #else 56 1.7.2.2 bouyer #define DPRINTF(x) 57 1.7.2.2 bouyer #define DPRINTFN(n,x) 58 1.7.2.2 bouyer #endif 59 1.7.2.2 bouyer 60 1.7.2.2 bouyer #include "midi.h" 61 1.7.2.2 bouyer 62 1.7.2.2 bouyer #include <sys/param.h> 63 1.7.2.2 bouyer #include <sys/systm.h> 64 1.7.2.2 bouyer #include <sys/kernel.h> 65 1.7.2.2 bouyer #include <sys/fcntl.h> 66 1.7.2.2 bouyer #include <sys/malloc.h> 67 1.7.2.2 bouyer #include <sys/device.h> 68 1.7.2.2 bouyer #include <sys/types.h> 69 1.7.2.2 bouyer #include <sys/systm.h> 70 1.7.2.2 bouyer 71 1.7.2.2 bouyer #include <dev/pci/pcidevs.h> 72 1.7.2.2 bouyer #include <dev/pci/pcivar.h> 73 1.7.2.2 bouyer #include <dev/pci/cs4280reg.h> 74 1.7.2.2 bouyer #include <dev/pci/cs4280_image.h> 75 1.7.2.2 bouyer 76 1.7.2.2 bouyer #include <sys/audioio.h> 77 1.7.2.2 bouyer #include <dev/audio_if.h> 78 1.7.2.2 bouyer #include <dev/midi_if.h> 79 1.7.2.2 bouyer #include <dev/mulaw.h> 80 1.7.2.2 bouyer #include <dev/auconv.h> 81 1.7.2.2 bouyer 82 1.7.2.2 bouyer #include <dev/ic/ac97reg.h> 83 1.7.2.2 bouyer #include <dev/ic/ac97var.h> 84 1.7.2.2 bouyer 85 1.7.2.2 bouyer #include <machine/bus.h> 86 1.7.2.2 bouyer #include <machine/bswap.h> 87 1.7.2.2 bouyer 88 1.7.2.2 bouyer #define CSCC_PCI_BA0 0x10 89 1.7.2.2 bouyer #define CSCC_PCI_BA1 0x14 90 1.7.2.2 bouyer 91 1.7.2.2 bouyer struct cs4280_dma { 92 1.7.2.2 bouyer bus_dmamap_t map; 93 1.7.2.2 bouyer caddr_t addr; /* real dma buffer */ 94 1.7.2.2 bouyer caddr_t dum; /* dummy buffer for audio driver */ 95 1.7.2.2 bouyer bus_dma_segment_t segs[1]; 96 1.7.2.2 bouyer int nsegs; 97 1.7.2.2 bouyer size_t size; 98 1.7.2.2 bouyer struct cs4280_dma *next; 99 1.7.2.2 bouyer }; 100 1.7.2.2 bouyer #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 101 1.7.2.2 bouyer #define BUFADDR(p) ((void *)((p)->dum)) 102 1.7.2.2 bouyer #define KERNADDR(p) ((void *)((p)->addr)) 103 1.7.2.2 bouyer 104 1.7.2.2 bouyer /* 105 1.7.2.2 bouyer * Software state 106 1.7.2.2 bouyer */ 107 1.7.2.2 bouyer struct cs4280_softc { 108 1.7.2.2 bouyer struct device sc_dev; 109 1.7.2.2 bouyer 110 1.7.2.2 bouyer pci_intr_handle_t * sc_ih; 111 1.7.2.2 bouyer 112 1.7.2.2 bouyer /* I/O (BA0) */ 113 1.7.2.2 bouyer bus_space_tag_t ba0t; 114 1.7.2.2 bouyer bus_space_handle_t ba0h; 115 1.7.2.2 bouyer 116 1.7.2.2 bouyer /* BA1 */ 117 1.7.2.2 bouyer bus_space_tag_t ba1t; 118 1.7.2.2 bouyer bus_space_handle_t ba1h; 119 1.7.2.2 bouyer 120 1.7.2.2 bouyer /* DMA */ 121 1.7.2.2 bouyer bus_dma_tag_t sc_dmatag; 122 1.7.2.2 bouyer struct cs4280_dma *sc_dmas; 123 1.7.2.2 bouyer 124 1.7.2.2 bouyer void (*sc_pintr)(void *); /* dma completion intr handler */ 125 1.7.2.2 bouyer void *sc_parg; /* arg for sc_intr() */ 126 1.7.2.2 bouyer char *sc_ps, *sc_pe, *sc_pn; 127 1.7.2.2 bouyer int sc_pcount; 128 1.7.2.2 bouyer int sc_pi; 129 1.7.2.2 bouyer struct cs4280_dma *sc_pdma; 130 1.7.2.2 bouyer char *sc_pbuf; 131 1.7.2.2 bouyer #ifdef DIAGNOSTIC 132 1.7.2.2 bouyer char sc_prun; 133 1.7.2.2 bouyer #endif 134 1.7.2.2 bouyer 135 1.7.2.2 bouyer void (*sc_rintr)(void *); /* dma completion intr handler */ 136 1.7.2.2 bouyer void *sc_rarg; /* arg for sc_intr() */ 137 1.7.2.2 bouyer char *sc_rs, *sc_re, *sc_rn; 138 1.7.2.2 bouyer int sc_rcount; 139 1.7.2.2 bouyer int sc_ri; 140 1.7.2.2 bouyer struct cs4280_dma *sc_rdma; 141 1.7.2.2 bouyer char *sc_rbuf; 142 1.7.2.2 bouyer int sc_rparam; /* record format */ 143 1.7.2.2 bouyer #ifdef DIAGNOSTIC 144 1.7.2.2 bouyer char sc_rrun; 145 1.7.2.2 bouyer #endif 146 1.7.2.2 bouyer 147 1.7.2.2 bouyer #if NMIDI > 0 148 1.7.2.2 bouyer void (*sc_iintr)(void *, int); /* midi input ready handler */ 149 1.7.2.2 bouyer void (*sc_ointr)(void *); /* midi output ready handler */ 150 1.7.2.2 bouyer void *sc_arg; 151 1.7.2.2 bouyer #endif 152 1.7.2.2 bouyer 153 1.7.2.2 bouyer u_int32_t pctl; 154 1.7.2.2 bouyer u_int32_t cctl; 155 1.7.2.2 bouyer 156 1.7.2.2 bouyer struct ac97_codec_if *codec_if; 157 1.7.2.2 bouyer struct ac97_host_if host_if; 158 1.7.2.2 bouyer 159 1.7.2.2 bouyer char sc_suspend; 160 1.7.2.2 bouyer void *sc_powerhook; /* Power Hook */ 161 1.7.2.2 bouyer u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 162 1.7.2.2 bouyer }; 163 1.7.2.2 bouyer 164 1.7.2.2 bouyer #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 165 1.7.2.2 bouyer #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 166 1.7.2.2 bouyer #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 167 1.7.2.2 bouyer #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 168 1.7.2.2 bouyer 169 1.7.2.2 bouyer int cs4280_match __P((struct device *, struct cfdata *, void *)); 170 1.7.2.2 bouyer void cs4280_attach __P((struct device *, struct device *, void *)); 171 1.7.2.2 bouyer int cs4280_intr __P((void *)); 172 1.7.2.2 bouyer void cs4280_reset __P((void *)); 173 1.7.2.2 bouyer int cs4280_download_image __P((struct cs4280_softc *)); 174 1.7.2.2 bouyer 175 1.7.2.2 bouyer int cs4280_download(struct cs4280_softc *, u_int32_t *, u_int32_t, u_int32_t); 176 1.7.2.2 bouyer int cs4280_allocmem __P((struct cs4280_softc *, size_t, size_t, 177 1.7.2.2 bouyer struct cs4280_dma *)); 178 1.7.2.2 bouyer int cs4280_freemem __P((struct cs4280_softc *, struct cs4280_dma *)); 179 1.7.2.2 bouyer 180 1.7.2.2 bouyer #ifdef CS4280_DEBUG 181 1.7.2.2 bouyer int cs4280_check_images __P((struct cs4280_softc *)); 182 1.7.2.2 bouyer int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 183 1.7.2.2 bouyer u_int32_t); 184 1.7.2.2 bouyer #endif 185 1.7.2.2 bouyer 186 1.7.2.2 bouyer struct cfattach clcs_ca = { 187 1.7.2.2 bouyer sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 188 1.7.2.2 bouyer }; 189 1.7.2.2 bouyer 190 1.7.2.2 bouyer int cs4280_init __P((struct cs4280_softc *, int)); 191 1.7.2.2 bouyer int cs4280_open __P((void *, int)); 192 1.7.2.2 bouyer void cs4280_close __P((void *)); 193 1.7.2.2 bouyer 194 1.7.2.2 bouyer int cs4280_query_encoding __P((void *, struct audio_encoding *)); 195 1.7.2.2 bouyer int cs4280_set_params __P((void *, int, int, struct audio_params *, struct audio_params *)); 196 1.7.2.2 bouyer int cs4280_round_blocksize __P((void *, int)); 197 1.7.2.2 bouyer 198 1.7.2.2 bouyer int cs4280_halt_output __P((void *)); 199 1.7.2.2 bouyer int cs4280_halt_input __P((void *)); 200 1.7.2.2 bouyer 201 1.7.2.2 bouyer int cs4280_getdev __P((void *, struct audio_device *)); 202 1.7.2.2 bouyer 203 1.7.2.2 bouyer int cs4280_mixer_set_port __P((void *, mixer_ctrl_t *)); 204 1.7.2.2 bouyer int cs4280_mixer_get_port __P((void *, mixer_ctrl_t *)); 205 1.7.2.2 bouyer int cs4280_query_devinfo __P((void *addr, mixer_devinfo_t *dip)); 206 1.7.2.2 bouyer void *cs4280_malloc __P((void *, int, size_t, int, int)); 207 1.7.2.2 bouyer void cs4280_free __P((void *, void *, int)); 208 1.7.2.2 bouyer size_t cs4280_round_buffersize __P((void *, int, size_t)); 209 1.7.2.2 bouyer paddr_t cs4280_mappage __P((void *, void *, off_t, int)); 210 1.7.2.2 bouyer int cs4280_get_props __P((void *)); 211 1.7.2.2 bouyer int cs4280_trigger_output __P((void *, void *, void *, int, void (*)(void *), 212 1.7.2.2 bouyer void *, struct audio_params *)); 213 1.7.2.2 bouyer int cs4280_trigger_input __P((void *, void *, void *, int, void (*)(void *), 214 1.7.2.2 bouyer void *, struct audio_params *)); 215 1.7.2.2 bouyer 216 1.7.2.2 bouyer 217 1.7.2.2 bouyer void cs4280_set_dac_rate __P((struct cs4280_softc *, int )); 218 1.7.2.2 bouyer void cs4280_set_adc_rate __P((struct cs4280_softc *, int )); 219 1.7.2.2 bouyer int cs4280_get_portnum_by_name __P((struct cs4280_softc *, char *, char *, 220 1.7.2.2 bouyer char *)); 221 1.7.2.2 bouyer int cs4280_src_wait __P((struct cs4280_softc *)); 222 1.7.2.2 bouyer int cs4280_attach_codec __P((void *sc, struct ac97_codec_if *)); 223 1.7.2.2 bouyer int cs4280_read_codec __P((void *sc, u_int8_t a, u_int16_t *d)); 224 1.7.2.2 bouyer int cs4280_write_codec __P((void *sc, u_int8_t a, u_int16_t d)); 225 1.7.2.2 bouyer void cs4280_reset_codec __P((void *sc)); 226 1.7.2.2 bouyer 227 1.7.2.2 bouyer void cs4280_power __P((int, void *)); 228 1.7.2.2 bouyer 229 1.7.2.2 bouyer void cs4280_clear_fifos __P((struct cs4280_softc *)); 230 1.7.2.2 bouyer 231 1.7.2.2 bouyer #if NMIDI > 0 232 1.7.2.2 bouyer void cs4280_midi_close __P((void*)); 233 1.7.2.2 bouyer void cs4280_midi_getinfo __P((void *, struct midi_info *)); 234 1.7.2.2 bouyer int cs4280_midi_open __P((void *, int, void (*)(void *, int), 235 1.7.2.2 bouyer void (*)(void *), void *)); 236 1.7.2.2 bouyer int cs4280_midi_output __P((void *, int)); 237 1.7.2.2 bouyer #endif 238 1.7.2.2 bouyer 239 1.7.2.2 bouyer struct audio_hw_if cs4280_hw_if = { 240 1.7.2.2 bouyer cs4280_open, 241 1.7.2.2 bouyer cs4280_close, 242 1.7.2.2 bouyer NULL, 243 1.7.2.2 bouyer cs4280_query_encoding, 244 1.7.2.2 bouyer cs4280_set_params, 245 1.7.2.2 bouyer cs4280_round_blocksize, 246 1.7.2.2 bouyer NULL, 247 1.7.2.2 bouyer NULL, 248 1.7.2.2 bouyer NULL, 249 1.7.2.2 bouyer NULL, 250 1.7.2.2 bouyer NULL, 251 1.7.2.2 bouyer cs4280_halt_output, 252 1.7.2.2 bouyer cs4280_halt_input, 253 1.7.2.2 bouyer NULL, 254 1.7.2.2 bouyer cs4280_getdev, 255 1.7.2.2 bouyer NULL, 256 1.7.2.2 bouyer cs4280_mixer_set_port, 257 1.7.2.2 bouyer cs4280_mixer_get_port, 258 1.7.2.2 bouyer cs4280_query_devinfo, 259 1.7.2.2 bouyer cs4280_malloc, 260 1.7.2.2 bouyer cs4280_free, 261 1.7.2.2 bouyer cs4280_round_buffersize, 262 1.7.2.2 bouyer cs4280_mappage, 263 1.7.2.2 bouyer cs4280_get_props, 264 1.7.2.2 bouyer cs4280_trigger_output, 265 1.7.2.2 bouyer cs4280_trigger_input, 266 1.7.2.2 bouyer }; 267 1.7.2.2 bouyer 268 1.7.2.2 bouyer #if NMIDI > 0 269 1.7.2.2 bouyer struct midi_hw_if cs4280_midi_hw_if = { 270 1.7.2.2 bouyer cs4280_midi_open, 271 1.7.2.2 bouyer cs4280_midi_close, 272 1.7.2.2 bouyer cs4280_midi_output, 273 1.7.2.2 bouyer cs4280_midi_getinfo, 274 1.7.2.2 bouyer 0, 275 1.7.2.2 bouyer }; 276 1.7.2.2 bouyer #endif 277 1.7.2.2 bouyer 278 1.7.2.2 bouyer 279 1.7.2.2 bouyer 280 1.7.2.2 bouyer struct audio_device cs4280_device = { 281 1.7.2.2 bouyer "CS4280", 282 1.7.2.2 bouyer "", 283 1.7.2.2 bouyer "cs4280" 284 1.7.2.2 bouyer }; 285 1.7.2.2 bouyer 286 1.7.2.2 bouyer 287 1.7.2.2 bouyer int 288 1.7.2.2 bouyer cs4280_match(parent, match, aux) 289 1.7.2.2 bouyer struct device *parent; 290 1.7.2.2 bouyer struct cfdata *match; 291 1.7.2.2 bouyer void *aux; 292 1.7.2.2 bouyer { 293 1.7.2.2 bouyer struct pci_attach_args *pa = (struct pci_attach_args *)aux; 294 1.7.2.2 bouyer 295 1.7.2.2 bouyer if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 296 1.7.2.2 bouyer return (0); 297 1.7.2.2 bouyer if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 298 1.7.2.2 bouyer #if 0 /* I can't confirm */ 299 1.7.2.2 bouyer || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 300 1.7.2.2 bouyer #endif 301 1.7.2.2 bouyer ) 302 1.7.2.2 bouyer return (1); 303 1.7.2.2 bouyer return (0); 304 1.7.2.2 bouyer } 305 1.7.2.2 bouyer 306 1.7.2.2 bouyer int 307 1.7.2.2 bouyer cs4280_read_codec(sc_, add, data) 308 1.7.2.2 bouyer void *sc_; 309 1.7.2.2 bouyer u_int8_t add; 310 1.7.2.2 bouyer u_int16_t *data; 311 1.7.2.2 bouyer { 312 1.7.2.2 bouyer struct cs4280_softc *sc = sc_; 313 1.7.2.2 bouyer int n; 314 1.7.2.2 bouyer 315 1.7.2.2 bouyer DPRINTFN(5,("read_codec: add=0x%02x ", add)); 316 1.7.2.2 bouyer /* 317 1.7.2.2 bouyer * Make sure that there is not data sitting around from a preivous 318 1.7.2.2 bouyer * uncompleted access. 319 1.7.2.2 bouyer */ 320 1.7.2.2 bouyer BA0READ4(sc, CS4280_ACSDA); 321 1.7.2.2 bouyer 322 1.7.2.2 bouyer /* Set up AC97 control registers. */ 323 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCAD, add); 324 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCDA, 0); 325 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCTL, 326 1.7.2.2 bouyer ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 327 1.7.2.2 bouyer 328 1.7.2.2 bouyer if (cs4280_src_wait(sc) < 0) { 329 1.7.2.2 bouyer printf("%s: AC97 read prob. (DCV!=0) for add=0x%0x\n", 330 1.7.2.2 bouyer sc->sc_dev.dv_xname, add); 331 1.7.2.2 bouyer return (1); 332 1.7.2.2 bouyer } 333 1.7.2.2 bouyer 334 1.7.2.2 bouyer /* wait for valid status bit is active */ 335 1.7.2.2 bouyer n = 0; 336 1.7.2.2 bouyer while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 337 1.7.2.2 bouyer delay(1); 338 1.7.2.2 bouyer while (++n > 1000) { 339 1.7.2.2 bouyer printf("%s: AC97 read fail (VSTS==0) for add=0x%0x\n", 340 1.7.2.2 bouyer sc->sc_dev.dv_xname, add); 341 1.7.2.2 bouyer return (1); 342 1.7.2.2 bouyer } 343 1.7.2.2 bouyer } 344 1.7.2.2 bouyer *data = BA0READ4(sc, CS4280_ACSDA); 345 1.7.2.2 bouyer DPRINTFN(5,("data=0x%04x\n", *data)); 346 1.7.2.2 bouyer return (0); 347 1.7.2.2 bouyer } 348 1.7.2.2 bouyer 349 1.7.2.2 bouyer int 350 1.7.2.2 bouyer cs4280_write_codec(sc_, add, data) 351 1.7.2.2 bouyer void *sc_; 352 1.7.2.2 bouyer u_int8_t add; 353 1.7.2.2 bouyer u_int16_t data; 354 1.7.2.2 bouyer { 355 1.7.2.2 bouyer struct cs4280_softc *sc = sc_; 356 1.7.2.2 bouyer 357 1.7.2.2 bouyer DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 358 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCAD, add); 359 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCDA, data); 360 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCTL, 361 1.7.2.2 bouyer ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 362 1.7.2.2 bouyer 363 1.7.2.2 bouyer if (cs4280_src_wait(sc) < 0) { 364 1.7.2.2 bouyer printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 365 1.7.2.2 bouyer "0x%04x\n", sc->sc_dev.dv_xname, add, data); 366 1.7.2.2 bouyer return (1); 367 1.7.2.2 bouyer } 368 1.7.2.2 bouyer return (0); 369 1.7.2.2 bouyer } 370 1.7.2.2 bouyer 371 1.7.2.2 bouyer int 372 1.7.2.2 bouyer cs4280_src_wait(sc) 373 1.7.2.2 bouyer struct cs4280_softc *sc; 374 1.7.2.2 bouyer { 375 1.7.2.2 bouyer int n; 376 1.7.2.2 bouyer n = 0; 377 1.7.2.2 bouyer while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 378 1.7.2.2 bouyer delay(1000); 379 1.7.2.2 bouyer while (++n > 1000) 380 1.7.2.2 bouyer return (-1); 381 1.7.2.2 bouyer } 382 1.7.2.2 bouyer return (0); 383 1.7.2.2 bouyer } 384 1.7.2.2 bouyer 385 1.7.2.2 bouyer 386 1.7.2.2 bouyer void 387 1.7.2.2 bouyer cs4280_set_adc_rate(sc, rate) 388 1.7.2.2 bouyer struct cs4280_softc *sc; 389 1.7.2.2 bouyer int rate; 390 1.7.2.2 bouyer { 391 1.7.2.2 bouyer /* calculate capture rate: 392 1.7.2.2 bouyer * 393 1.7.2.2 bouyer * capture_coefficient_increment = -round(rate*128*65536/48000; 394 1.7.2.2 bouyer * capture_phase_increment = floor(48000*65536*1024/rate); 395 1.7.2.2 bouyer * cx = round(48000*65536*1024 - capture_phase_increment*rate); 396 1.7.2.2 bouyer * cy = floor(cx/200); 397 1.7.2.2 bouyer * capture_sample_rate_correction = cx - 200*cy; 398 1.7.2.2 bouyer * capture_delay = ceil(24*48000/rate); 399 1.7.2.2 bouyer * capture_num_triplets = floor(65536*rate/24000); 400 1.7.2.2 bouyer * capture_group_length = 24000/GCD(rate, 24000); 401 1.7.2.2 bouyer * where GCD means "Greatest Common Divisor". 402 1.7.2.2 bouyer * 403 1.7.2.2 bouyer * capture_coefficient_increment, capture_phase_increment and 404 1.7.2.2 bouyer * capture_num_triplets are 32-bit signed quantities. 405 1.7.2.2 bouyer * capture_sample_rate_correction and capture_group_length are 406 1.7.2.2 bouyer * 16-bit signed quantities. 407 1.7.2.2 bouyer * capture_delay is a 14-bit unsigned quantity. 408 1.7.2.2 bouyer */ 409 1.7.2.2 bouyer u_int32_t cci,cpi,cnt,cx,cy, tmp1; 410 1.7.2.2 bouyer u_int16_t csrc, cgl, cdlay; 411 1.7.2.2 bouyer 412 1.7.2.2 bouyer /* XXX 413 1.7.2.2 bouyer * Even though, embedded_audio_spec says capture rate range 11025 to 414 1.7.2.2 bouyer * 48000, dhwiface.cpp says, 415 1.7.2.2 bouyer * 416 1.7.2.2 bouyer * "We can only decimate by up to a factor of 1/9th the hardware rate. 417 1.7.2.2 bouyer * Return an error if an attempt is made to stray outside that limit." 418 1.7.2.2 bouyer * 419 1.7.2.2 bouyer * so assume range as 48000/9 to 48000 420 1.7.2.2 bouyer */ 421 1.7.2.2 bouyer 422 1.7.2.2 bouyer if (rate < 8000) 423 1.7.2.2 bouyer rate = 8000; 424 1.7.2.2 bouyer if (rate > 48000) 425 1.7.2.2 bouyer rate = 48000; 426 1.7.2.2 bouyer 427 1.7.2.2 bouyer cx = rate << 16; 428 1.7.2.2 bouyer cci = cx / 48000; 429 1.7.2.2 bouyer cx -= cci * 48000; 430 1.7.2.2 bouyer cx <<= 7; 431 1.7.2.2 bouyer cci <<= 7; 432 1.7.2.2 bouyer cci += cx / 48000; 433 1.7.2.2 bouyer cci = - cci; 434 1.7.2.2 bouyer 435 1.7.2.2 bouyer cx = 48000 << 16; 436 1.7.2.2 bouyer cpi = cx / rate; 437 1.7.2.2 bouyer cx -= cpi * rate; 438 1.7.2.2 bouyer cx <<= 10; 439 1.7.2.2 bouyer cpi <<= 10; 440 1.7.2.2 bouyer cy = cx / rate; 441 1.7.2.2 bouyer cpi += cy; 442 1.7.2.2 bouyer cx -= cy * rate; 443 1.7.2.2 bouyer 444 1.7.2.2 bouyer cy = cx / 200; 445 1.7.2.2 bouyer csrc = cx - 200*cy; 446 1.7.2.2 bouyer 447 1.7.2.2 bouyer cdlay = ((48000 * 24) + rate - 1) / rate; 448 1.7.2.2 bouyer #if 0 449 1.7.2.2 bouyer cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 450 1.7.2.2 bouyer #endif 451 1.7.2.2 bouyer 452 1.7.2.2 bouyer cnt = rate << 16; 453 1.7.2.2 bouyer cnt /= 24000; 454 1.7.2.2 bouyer 455 1.7.2.2 bouyer cgl = 1; 456 1.7.2.2 bouyer for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 457 1.7.2.2 bouyer if (((rate / tmp1) * tmp1) != rate) 458 1.7.2.2 bouyer cgl *= 2; 459 1.7.2.2 bouyer } 460 1.7.2.2 bouyer if (((rate / 3) * 3) != rate) 461 1.7.2.2 bouyer cgl *= 3; 462 1.7.2.2 bouyer for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 463 1.7.2.2 bouyer if (((rate / tmp1) * tmp1) != rate) 464 1.7.2.2 bouyer cgl *= 5; 465 1.7.2.2 bouyer } 466 1.7.2.2 bouyer #if 0 467 1.7.2.2 bouyer /* XXX what manual says */ 468 1.7.2.2 bouyer tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 469 1.7.2.2 bouyer tmp1 |= csrc<<16; 470 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CSRC, tmp1); 471 1.7.2.2 bouyer #else 472 1.7.2.2 bouyer /* suggested by cs461x.c (ALSA driver) */ 473 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 474 1.7.2.2 bouyer #endif 475 1.7.2.2 bouyer 476 1.7.2.2 bouyer #if 0 477 1.7.2.2 bouyer /* I am confused. The sample rate calculation section says 478 1.7.2.2 bouyer * cci *is* 32-bit signed quantity but in the parameter description 479 1.7.2.2 bouyer * section, CCI only assigned 16bit. 480 1.7.2.2 bouyer * I believe size of the variable. 481 1.7.2.2 bouyer */ 482 1.7.2.2 bouyer tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 483 1.7.2.2 bouyer tmp1 |= cci<<16; 484 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CCI, tmp1); 485 1.7.2.2 bouyer #else 486 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CCI, cci); 487 1.7.2.2 bouyer #endif 488 1.7.2.2 bouyer 489 1.7.2.2 bouyer tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 490 1.7.2.2 bouyer tmp1 |= cdlay <<18; 491 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CD, tmp1); 492 1.7.2.2 bouyer 493 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CPI, cpi); 494 1.7.2.2 bouyer 495 1.7.2.2 bouyer tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 496 1.7.2.2 bouyer tmp1 |= cgl; 497 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CGL, tmp1); 498 1.7.2.2 bouyer 499 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CNT, cnt); 500 1.7.2.2 bouyer 501 1.7.2.2 bouyer tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 502 1.7.2.2 bouyer tmp1 |= cgl; 503 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CGC, tmp1); 504 1.7.2.2 bouyer } 505 1.7.2.2 bouyer 506 1.7.2.2 bouyer void 507 1.7.2.2 bouyer cs4280_set_dac_rate(sc, rate) 508 1.7.2.2 bouyer struct cs4280_softc *sc; 509 1.7.2.2 bouyer int rate; 510 1.7.2.2 bouyer { 511 1.7.2.2 bouyer /* 512 1.7.2.2 bouyer * playback rate may range from 8000Hz to 48000Hz 513 1.7.2.2 bouyer * 514 1.7.2.2 bouyer * play_phase_increment = floor(rate*65536*1024/48000) 515 1.7.2.2 bouyer * px = round(rate*65536*1024 - play_phase_incremnt*48000) 516 1.7.2.2 bouyer * py=floor(px/200) 517 1.7.2.2 bouyer * play_sample_rate_correction = px - 200*py 518 1.7.2.2 bouyer * 519 1.7.2.2 bouyer * play_phase_increment is a 32bit signed quantity. 520 1.7.2.2 bouyer * play_sample_rate_correction is a 16bit signed quantity. 521 1.7.2.2 bouyer */ 522 1.7.2.2 bouyer int32_t ppi; 523 1.7.2.2 bouyer int16_t psrc; 524 1.7.2.2 bouyer u_int32_t px, py; 525 1.7.2.2 bouyer 526 1.7.2.2 bouyer if (rate < 8000) 527 1.7.2.2 bouyer rate = 8000; 528 1.7.2.2 bouyer if (rate > 48000) 529 1.7.2.2 bouyer rate = 48000; 530 1.7.2.2 bouyer px = rate << 16; 531 1.7.2.2 bouyer ppi = px/48000; 532 1.7.2.2 bouyer px -= ppi*48000; 533 1.7.2.2 bouyer ppi <<= 10; 534 1.7.2.2 bouyer px <<= 10; 535 1.7.2.2 bouyer py = px / 48000; 536 1.7.2.2 bouyer ppi += py; 537 1.7.2.2 bouyer px -= py*48000; 538 1.7.2.2 bouyer py = px/200; 539 1.7.2.2 bouyer px -= py*200; 540 1.7.2.2 bouyer psrc = px; 541 1.7.2.2 bouyer #if 0 542 1.7.2.2 bouyer /* what manual says */ 543 1.7.2.2 bouyer px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 544 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PSRC, 545 1.7.2.2 bouyer ( ((psrc<<16) & PSRC_MASK) | px )); 546 1.7.2.2 bouyer #else 547 1.7.2.2 bouyer /* suggested by cs461x.c (ALSA driver) */ 548 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 549 1.7.2.2 bouyer #endif 550 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PPI, ppi); 551 1.7.2.2 bouyer } 552 1.7.2.2 bouyer 553 1.7.2.2 bouyer void 554 1.7.2.2 bouyer cs4280_attach(parent, self, aux) 555 1.7.2.2 bouyer struct device *parent; 556 1.7.2.2 bouyer struct device *self; 557 1.7.2.2 bouyer void *aux; 558 1.7.2.2 bouyer { 559 1.7.2.2 bouyer struct cs4280_softc *sc = (struct cs4280_softc *)self; 560 1.7.2.2 bouyer struct pci_attach_args *pa = (struct pci_attach_args *)aux; 561 1.7.2.2 bouyer pci_chipset_tag_t pc = pa->pa_pc; 562 1.7.2.2 bouyer char const *intrstr; 563 1.7.2.2 bouyer pci_intr_handle_t ih; 564 1.7.2.2 bouyer pcireg_t csr; 565 1.7.2.2 bouyer char devinfo[256]; 566 1.7.2.2 bouyer mixer_ctrl_t ctl; 567 1.7.2.2 bouyer u_int32_t mem; 568 1.7.2.2 bouyer 569 1.7.2.2 bouyer pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 570 1.7.2.2 bouyer printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 571 1.7.2.2 bouyer 572 1.7.2.2 bouyer /* Map I/O register */ 573 1.7.2.2 bouyer if (pci_mapreg_map(pa, CSCC_PCI_BA0, 574 1.7.2.2 bouyer PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 575 1.7.2.2 bouyer &sc->ba0t, &sc->ba0h, NULL, NULL)) { 576 1.7.2.2 bouyer printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 577 1.7.2.2 bouyer return; 578 1.7.2.2 bouyer } 579 1.7.2.2 bouyer if (pci_mapreg_map(pa, CSCC_PCI_BA1, 580 1.7.2.2 bouyer PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 581 1.7.2.2 bouyer &sc->ba1t, &sc->ba1h, NULL, NULL)) { 582 1.7.2.2 bouyer printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 583 1.7.2.2 bouyer return; 584 1.7.2.2 bouyer } 585 1.7.2.2 bouyer 586 1.7.2.2 bouyer sc->sc_dmatag = pa->pa_dmat; 587 1.7.2.2 bouyer 588 1.7.2.2 bouyer /* Enable the device (set bus master flag) */ 589 1.7.2.2 bouyer csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 590 1.7.2.2 bouyer pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 591 1.7.2.2 bouyer csr | PCI_COMMAND_MASTER_ENABLE); 592 1.7.2.2 bouyer 593 1.7.2.2 bouyer /* LATENCY_TIMER setting */ 594 1.7.2.2 bouyer mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 595 1.7.2.2 bouyer if ( PCI_LATTIMER(mem) < 32 ) { 596 1.7.2.2 bouyer mem &= 0xffff00ff; 597 1.7.2.2 bouyer mem |= 0x00002000; 598 1.7.2.2 bouyer pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 599 1.7.2.2 bouyer } 600 1.7.2.2 bouyer 601 1.7.2.2 bouyer /* Map and establish the interrupt. */ 602 1.7.2.2 bouyer if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 603 1.7.2.2 bouyer pa->pa_intrline, &ih)) { 604 1.7.2.2 bouyer printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 605 1.7.2.2 bouyer return; 606 1.7.2.2 bouyer } 607 1.7.2.2 bouyer intrstr = pci_intr_string(pc, ih); 608 1.7.2.2 bouyer 609 1.7.2.2 bouyer sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 610 1.7.2.2 bouyer if (sc->sc_ih == NULL) { 611 1.7.2.2 bouyer printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 612 1.7.2.2 bouyer if (intrstr != NULL) 613 1.7.2.2 bouyer printf(" at %s", intrstr); 614 1.7.2.2 bouyer printf("\n"); 615 1.7.2.2 bouyer return; 616 1.7.2.2 bouyer } 617 1.7.2.2 bouyer printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 618 1.7.2.2 bouyer 619 1.7.2.2 bouyer /* Initialization */ 620 1.7.2.2 bouyer if(cs4280_init(sc, 1) != 0) 621 1.7.2.2 bouyer return; 622 1.7.2.2 bouyer 623 1.7.2.2 bouyer /* AC 97 attachement */ 624 1.7.2.2 bouyer sc->host_if.arg = sc; 625 1.7.2.2 bouyer sc->host_if.attach = cs4280_attach_codec; 626 1.7.2.2 bouyer sc->host_if.read = cs4280_read_codec; 627 1.7.2.2 bouyer sc->host_if.write = cs4280_write_codec; 628 1.7.2.2 bouyer sc->host_if.reset = cs4280_reset_codec; 629 1.7.2.2 bouyer 630 1.7.2.2 bouyer if (ac97_attach(&sc->host_if) != 0) { 631 1.7.2.2 bouyer printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 632 1.7.2.2 bouyer return; 633 1.7.2.2 bouyer } 634 1.7.2.2 bouyer 635 1.7.2.2 bouyer /* Turn mute off of DAC, CD and master volumes by default */ 636 1.7.2.2 bouyer ctl.type = AUDIO_MIXER_ENUM; 637 1.7.2.2 bouyer ctl.un.ord = 0; /* off */ 638 1.7.2.2 bouyer 639 1.7.2.2 bouyer ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 640 1.7.2.2 bouyer AudioNmaster, AudioNmute); 641 1.7.2.2 bouyer cs4280_mixer_set_port(sc, &ctl); 642 1.7.2.2 bouyer 643 1.7.2.2 bouyer ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 644 1.7.2.2 bouyer AudioNdac, AudioNmute); 645 1.7.2.2 bouyer cs4280_mixer_set_port(sc, &ctl); 646 1.7.2.2 bouyer 647 1.7.2.2 bouyer ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 648 1.7.2.2 bouyer AudioNcd, AudioNmute); 649 1.7.2.2 bouyer cs4280_mixer_set_port(sc, &ctl); 650 1.7.2.2 bouyer 651 1.7.2.2 bouyer audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 652 1.7.2.2 bouyer 653 1.7.2.2 bouyer #if NMIDI > 0 654 1.7.2.2 bouyer midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 655 1.7.2.2 bouyer #endif 656 1.7.2.2 bouyer sc->sc_suspend = PWR_RESUME; 657 1.7.2.2 bouyer sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 658 1.7.2.2 bouyer } 659 1.7.2.2 bouyer 660 1.7.2.2 bouyer int 661 1.7.2.2 bouyer cs4280_intr(p) 662 1.7.2.2 bouyer void *p; 663 1.7.2.2 bouyer { 664 1.7.2.2 bouyer /* 665 1.7.2.2 bouyer * XXX 666 1.7.2.2 bouyer * 667 1.7.2.2 bouyer * Since CS4280 has only 4kB dma buffer and 668 1.7.2.2 bouyer * interrupt occurs every 2kB block, I create dummy buffer 669 1.7.2.2 bouyer * which returns to audio driver and actual dma buffer 670 1.7.2.2 bouyer * using in DMA transfer. 671 1.7.2.2 bouyer * 672 1.7.2.2 bouyer * 673 1.7.2.2 bouyer * ring buffer in audio.c is pointed by BUFADDR 674 1.7.2.2 bouyer * <------ ring buffer size == 64kB ------> 675 1.7.2.2 bouyer * <-----> blksize == 2048*(sc->sc_[pr]count) kB 676 1.7.2.2 bouyer * |= = = =|= = = =|= = = =|= = = =|= = = =| 677 1.7.2.2 bouyer * | | | | | | <- call audio_intp every 678 1.7.2.2 bouyer * sc->sc_[pr]_count time. 679 1.7.2.2 bouyer * 680 1.7.2.2 bouyer * actual dma buffer is pointed by KERNADDR 681 1.7.2.2 bouyer * <-> dma buffer size = 4kB 682 1.7.2.2 bouyer * |= =| 683 1.7.2.2 bouyer * 684 1.7.2.2 bouyer * 685 1.7.2.2 bouyer */ 686 1.7.2.2 bouyer struct cs4280_softc *sc = p; 687 1.7.2.2 bouyer u_int32_t intr, mem; 688 1.7.2.2 bouyer char * empty_dma; 689 1.7.2.2 bouyer 690 1.7.2.2 bouyer /* grab interrupt register then clear it */ 691 1.7.2.2 bouyer intr = BA0READ4(sc, CS4280_HISR); 692 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 693 1.7.2.2 bouyer 694 1.7.2.2 bouyer /* not for me */ 695 1.7.2.2 bouyer if((intr & HISR_INTENA) == 0 ) 696 1.7.2.2 bouyer return 0; 697 1.7.2.2 bouyer 698 1.7.2.2 bouyer /* Playback Interrupt */ 699 1.7.2.2 bouyer if (intr & HISR_PINT) { 700 1.7.2.2 bouyer mem = BA1READ4(sc, CS4280_PFIE); 701 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 702 1.7.2.2 bouyer if (sc->sc_pintr) { 703 1.7.2.2 bouyer if ((sc->sc_pi%sc->sc_pcount) == 0) 704 1.7.2.2 bouyer sc->sc_pintr(sc->sc_parg); 705 1.7.2.2 bouyer } else { 706 1.7.2.2 bouyer printf("unexpected play intr\n"); 707 1.7.2.2 bouyer } 708 1.7.2.2 bouyer /* copy buffer */ 709 1.7.2.2 bouyer ++sc->sc_pi; 710 1.7.2.2 bouyer empty_dma = sc->sc_pdma->addr; 711 1.7.2.2 bouyer if (sc->sc_pi&1) 712 1.7.2.2 bouyer empty_dma += CS4280_ICHUNK; 713 1.7.2.2 bouyer memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 714 1.7.2.2 bouyer sc->sc_pn += CS4280_ICHUNK; 715 1.7.2.2 bouyer if (sc->sc_pn >= sc->sc_pe) 716 1.7.2.2 bouyer sc->sc_pn = sc->sc_ps; 717 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PFIE, mem); 718 1.7.2.2 bouyer } 719 1.7.2.2 bouyer /* Capture Interrupt */ 720 1.7.2.2 bouyer if (intr & HISR_CINT) { 721 1.7.2.2 bouyer int i; 722 1.7.2.2 bouyer int16_t rdata; 723 1.7.2.2 bouyer 724 1.7.2.2 bouyer mem = BA1READ4(sc, CS4280_CIE); 725 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 726 1.7.2.2 bouyer ++sc->sc_ri; 727 1.7.2.2 bouyer empty_dma = sc->sc_rdma->addr; 728 1.7.2.2 bouyer if ((sc->sc_ri&1) == 0) 729 1.7.2.2 bouyer empty_dma += CS4280_ICHUNK; 730 1.7.2.2 bouyer 731 1.7.2.2 bouyer /* 732 1.7.2.2 bouyer * XXX 733 1.7.2.2 bouyer * I think this audio data conversion should be 734 1.7.2.2 bouyer * happend in upper layer, but I put this here 735 1.7.2.2 bouyer * since there is no conversion function available. 736 1.7.2.2 bouyer */ 737 1.7.2.2 bouyer switch(sc->sc_rparam) { 738 1.7.2.2 bouyer case CF_16BIT_STEREO: 739 1.7.2.2 bouyer /* just copy it */ 740 1.7.2.2 bouyer memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 741 1.7.2.2 bouyer sc->sc_rn += CS4280_ICHUNK; 742 1.7.2.2 bouyer break; 743 1.7.2.2 bouyer case CF_16BIT_MONO: 744 1.7.2.2 bouyer for (i = 0; i < 512; i++) { 745 1.7.2.2 bouyer rdata = *((int16_t *)empty_dma)++>>1; 746 1.7.2.2 bouyer rdata += *((int16_t *)empty_dma)++>>1; 747 1.7.2.2 bouyer *((int16_t *)sc->sc_rn)++ = rdata; 748 1.7.2.2 bouyer } 749 1.7.2.2 bouyer break; 750 1.7.2.2 bouyer case CF_8BIT_STEREO: 751 1.7.2.2 bouyer for (i = 0; i < 512; i++) { 752 1.7.2.2 bouyer rdata = *((int16_t*)empty_dma)++; 753 1.7.2.2 bouyer *sc->sc_rn++ = rdata >> 8; 754 1.7.2.2 bouyer rdata = *((int16_t*)empty_dma)++; 755 1.7.2.2 bouyer *sc->sc_rn++ = rdata >> 8; 756 1.7.2.2 bouyer } 757 1.7.2.2 bouyer break; 758 1.7.2.2 bouyer case CF_8BIT_MONO: 759 1.7.2.2 bouyer for (i = 0; i < 512; i++) { 760 1.7.2.2 bouyer rdata = *((int16_t*)empty_dma)++ >>1; 761 1.7.2.2 bouyer rdata += *((int16_t*)empty_dma)++ >>1; 762 1.7.2.2 bouyer *sc->sc_rn++ = rdata >>8; 763 1.7.2.2 bouyer } 764 1.7.2.2 bouyer break; 765 1.7.2.2 bouyer default: 766 1.7.2.2 bouyer /* Should not reach here */ 767 1.7.2.2 bouyer printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 768 1.7.2.2 bouyer } 769 1.7.2.2 bouyer if (sc->sc_rn >= sc->sc_re) 770 1.7.2.2 bouyer sc->sc_rn = sc->sc_rs; 771 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CIE, mem); 772 1.7.2.2 bouyer if (sc->sc_rintr) { 773 1.7.2.2 bouyer if ((sc->sc_ri%(sc->sc_rcount)) == 0) 774 1.7.2.2 bouyer sc->sc_rintr(sc->sc_rarg); 775 1.7.2.2 bouyer } else { 776 1.7.2.2 bouyer printf("unexpected record intr\n"); 777 1.7.2.2 bouyer } 778 1.7.2.2 bouyer } 779 1.7.2.2 bouyer 780 1.7.2.2 bouyer #if NMIDI > 0 781 1.7.2.2 bouyer /* Midi port Interrupt */ 782 1.7.2.2 bouyer if (intr & HISR_MIDI) { 783 1.7.2.2 bouyer int data; 784 1.7.2.2 bouyer 785 1.7.2.2 bouyer DPRINTF(("i: %d: ", 786 1.7.2.2 bouyer BA0READ4(sc, CS4280_MIDSR))); 787 1.7.2.2 bouyer /* Read the received data */ 788 1.7.2.2 bouyer while ((sc->sc_iintr != NULL) && 789 1.7.2.2 bouyer ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 790 1.7.2.2 bouyer data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 791 1.7.2.2 bouyer DPRINTF(("r:%x\n",data)); 792 1.7.2.2 bouyer sc->sc_iintr(sc->sc_arg, data); 793 1.7.2.2 bouyer } 794 1.7.2.2 bouyer 795 1.7.2.2 bouyer /* Write the data */ 796 1.7.2.2 bouyer #if 1 797 1.7.2.2 bouyer /* XXX: 798 1.7.2.2 bouyer * It seems "Transmit Buffer Full" never activate until EOI 799 1.7.2.2 bouyer * is deliverd. Shall I throw EOI top of this routine ? 800 1.7.2.2 bouyer */ 801 1.7.2.2 bouyer if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 802 1.7.2.2 bouyer DPRINTF(("w: ")); 803 1.7.2.2 bouyer if (sc->sc_ointr != NULL) 804 1.7.2.2 bouyer sc->sc_ointr(sc->sc_arg); 805 1.7.2.2 bouyer } 806 1.7.2.2 bouyer #else 807 1.7.2.2 bouyer while ((sc->sc_ointr != NULL) && 808 1.7.2.2 bouyer ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 809 1.7.2.2 bouyer DPRINTF(("w: ")); 810 1.7.2.2 bouyer sc->sc_ointr(sc->sc_arg); 811 1.7.2.2 bouyer } 812 1.7.2.2 bouyer #endif 813 1.7.2.2 bouyer DPRINTF(("\n")); 814 1.7.2.2 bouyer } 815 1.7.2.2 bouyer #endif 816 1.7.2.2 bouyer 817 1.7.2.2 bouyer return (1); 818 1.7.2.2 bouyer } 819 1.7.2.2 bouyer 820 1.7.2.2 bouyer 821 1.7.2.2 bouyer /* Download Proceessor Code and Data image */ 822 1.7.2.2 bouyer 823 1.7.2.2 bouyer int 824 1.7.2.2 bouyer cs4280_download(sc, src, offset, len) 825 1.7.2.2 bouyer struct cs4280_softc *sc; 826 1.7.2.2 bouyer u_int32_t *src; 827 1.7.2.2 bouyer u_int32_t offset, len; 828 1.7.2.2 bouyer { 829 1.7.2.2 bouyer u_int32_t ctr; 830 1.7.2.2 bouyer 831 1.7.2.2 bouyer #ifdef CS4280_DEBUG 832 1.7.2.2 bouyer u_int32_t con, data; 833 1.7.2.2 bouyer u_int8_t c0,c1,c2,c3; 834 1.7.2.2 bouyer #endif 835 1.7.2.2 bouyer if ((offset&3) || (len&3)) 836 1.7.2.2 bouyer return (-1); 837 1.7.2.2 bouyer 838 1.7.2.2 bouyer len /= sizeof(u_int32_t); 839 1.7.2.2 bouyer for (ctr = 0; ctr < len; ctr++) { 840 1.7.2.2 bouyer /* XXX: 841 1.7.2.2 bouyer * I cannot confirm this is the right thing or not 842 1.7.2.2 bouyer * on BIG-ENDIAN machines. 843 1.7.2.2 bouyer */ 844 1.7.2.2 bouyer BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 845 1.7.2.2 bouyer #ifdef CS4280_DEBUG 846 1.7.2.2 bouyer data = htole32(*(src+ctr)); 847 1.7.2.2 bouyer c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 848 1.7.2.2 bouyer c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 849 1.7.2.2 bouyer c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 850 1.7.2.2 bouyer c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 851 1.7.2.2 bouyer con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 852 1.7.2.2 bouyer if (data != con ) { 853 1.7.2.2 bouyer printf("0x%06x: write=0x%08x read=0x%08x\n", 854 1.7.2.2 bouyer offset+ctr*4, data, con); 855 1.7.2.2 bouyer return (-1); 856 1.7.2.2 bouyer } 857 1.7.2.2 bouyer #endif 858 1.7.2.2 bouyer } 859 1.7.2.2 bouyer return (0); 860 1.7.2.2 bouyer } 861 1.7.2.2 bouyer 862 1.7.2.2 bouyer int 863 1.7.2.2 bouyer cs4280_download_image(sc) 864 1.7.2.2 bouyer struct cs4280_softc *sc; 865 1.7.2.2 bouyer { 866 1.7.2.2 bouyer int idx, err; 867 1.7.2.2 bouyer u_int32_t offset = 0; 868 1.7.2.2 bouyer 869 1.7.2.2 bouyer err = 0; 870 1.7.2.2 bouyer for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 871 1.7.2.2 bouyer err = cs4280_download(sc, &BA1Struct.map[offset], 872 1.7.2.2 bouyer BA1Struct.memory[idx].offset, 873 1.7.2.2 bouyer BA1Struct.memory[idx].size); 874 1.7.2.2 bouyer if (err != 0) { 875 1.7.2.2 bouyer printf("%s: load_image failed at %d\n", 876 1.7.2.2 bouyer sc->sc_dev.dv_xname, idx); 877 1.7.2.2 bouyer return (-1); 878 1.7.2.2 bouyer } 879 1.7.2.2 bouyer offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 880 1.7.2.2 bouyer } 881 1.7.2.2 bouyer return (err); 882 1.7.2.2 bouyer } 883 1.7.2.2 bouyer 884 1.7.2.2 bouyer #ifdef CS4280_DEBUG 885 1.7.2.2 bouyer int 886 1.7.2.2 bouyer cs4280_checkimage(sc, src, offset, len) 887 1.7.2.2 bouyer struct cs4280_softc *sc; 888 1.7.2.2 bouyer u_int32_t *src; 889 1.7.2.2 bouyer u_int32_t offset, len; 890 1.7.2.2 bouyer { 891 1.7.2.2 bouyer u_int32_t ctr, data; 892 1.7.2.2 bouyer int err = 0; 893 1.7.2.2 bouyer 894 1.7.2.2 bouyer if ((offset&3) || (len&3)) 895 1.7.2.2 bouyer return -1; 896 1.7.2.2 bouyer 897 1.7.2.2 bouyer len /= sizeof(u_int32_t); 898 1.7.2.2 bouyer for (ctr = 0; ctr < len; ctr++) { 899 1.7.2.2 bouyer /* I cannot confirm this is the right thing 900 1.7.2.2 bouyer * on BIG-ENDIAN machines 901 1.7.2.2 bouyer */ 902 1.7.2.2 bouyer data = BA1READ4(sc, offset+ctr*4); 903 1.7.2.2 bouyer if (data != htole32(*(src+ctr))) { 904 1.7.2.2 bouyer printf("0x%06x: 0x%08x(0x%08x)\n", 905 1.7.2.2 bouyer offset+ctr*4, data, *(src+ctr)); 906 1.7.2.2 bouyer *(src+ctr) = data; 907 1.7.2.2 bouyer ++err; 908 1.7.2.2 bouyer } 909 1.7.2.2 bouyer } 910 1.7.2.2 bouyer return (err); 911 1.7.2.2 bouyer } 912 1.7.2.2 bouyer 913 1.7.2.2 bouyer int 914 1.7.2.2 bouyer cs4280_check_images(sc) 915 1.7.2.2 bouyer struct cs4280_softc *sc; 916 1.7.2.2 bouyer { 917 1.7.2.2 bouyer int idx, err; 918 1.7.2.2 bouyer u_int32_t offset = 0; 919 1.7.2.2 bouyer 920 1.7.2.2 bouyer err = 0; 921 1.7.2.2 bouyer /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 922 1.7.2.2 bouyer for (idx = 0; idx < 1; ++idx) { 923 1.7.2.2 bouyer err = cs4280_checkimage(sc, &BA1Struct.map[offset], 924 1.7.2.2 bouyer BA1Struct.memory[idx].offset, 925 1.7.2.2 bouyer BA1Struct.memory[idx].size); 926 1.7.2.2 bouyer if (err != 0) { 927 1.7.2.2 bouyer printf("%s: check_image failed at %d\n", 928 1.7.2.2 bouyer sc->sc_dev.dv_xname, idx); 929 1.7.2.2 bouyer } 930 1.7.2.2 bouyer offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 931 1.7.2.2 bouyer } 932 1.7.2.2 bouyer return (err); 933 1.7.2.2 bouyer } 934 1.7.2.2 bouyer 935 1.7.2.2 bouyer #endif 936 1.7.2.2 bouyer 937 1.7.2.2 bouyer int 938 1.7.2.2 bouyer cs4280_attach_codec(sc_, codec_if) 939 1.7.2.2 bouyer void *sc_; 940 1.7.2.2 bouyer struct ac97_codec_if *codec_if; 941 1.7.2.2 bouyer { 942 1.7.2.2 bouyer struct cs4280_softc *sc = sc_; 943 1.7.2.2 bouyer 944 1.7.2.2 bouyer sc->codec_if = codec_if; 945 1.7.2.2 bouyer return (0); 946 1.7.2.2 bouyer } 947 1.7.2.2 bouyer 948 1.7.2.2 bouyer void 949 1.7.2.2 bouyer cs4280_reset_codec(sc_) 950 1.7.2.2 bouyer void *sc_; 951 1.7.2.2 bouyer { 952 1.7.2.2 bouyer struct cs4280_softc *sc = sc_; 953 1.7.2.2 bouyer int n; 954 1.7.2.2 bouyer 955 1.7.2.2 bouyer /* Reset codec */ 956 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCTL, 0); 957 1.7.2.2 bouyer delay(100); /* delay 100us */ 958 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 959 1.7.2.2 bouyer 960 1.7.2.2 bouyer /* 961 1.7.2.2 bouyer * It looks like we do the following procedure, too 962 1.7.2.2 bouyer */ 963 1.7.2.2 bouyer 964 1.7.2.2 bouyer /* Enable AC-link sync generation */ 965 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 966 1.7.2.2 bouyer delay(50*1000); /* XXX delay 50ms */ 967 1.7.2.2 bouyer 968 1.7.2.2 bouyer /* Assert valid frame signal */ 969 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 970 1.7.2.2 bouyer 971 1.7.2.2 bouyer /* Wait for valid AC97 input slot */ 972 1.7.2.2 bouyer n = 0; 973 1.7.2.2 bouyer while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 974 1.7.2.2 bouyer delay(1000); 975 1.7.2.2 bouyer if (++n > 1000) { 976 1.7.2.2 bouyer printf("reset_codec: AC97 inputs slot ready timeout\n"); 977 1.7.2.2 bouyer return; 978 1.7.2.2 bouyer } 979 1.7.2.2 bouyer } 980 1.7.2.2 bouyer } 981 1.7.2.2 bouyer 982 1.7.2.2 bouyer 983 1.7.2.2 bouyer /* Processor Soft Reset */ 984 1.7.2.2 bouyer void 985 1.7.2.2 bouyer cs4280_reset(sc_) 986 1.7.2.2 bouyer void *sc_; 987 1.7.2.2 bouyer { 988 1.7.2.2 bouyer struct cs4280_softc *sc = sc_; 989 1.7.2.2 bouyer 990 1.7.2.2 bouyer /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 991 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 992 1.7.2.2 bouyer delay(100); 993 1.7.2.2 bouyer /* Clear RSTSP bit in SPCR */ 994 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_SPCR, 0); 995 1.7.2.2 bouyer /* enable DMA reqest */ 996 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 997 1.7.2.2 bouyer } 998 1.7.2.2 bouyer 999 1.7.2.2 bouyer int 1000 1.7.2.2 bouyer cs4280_open(addr, flags) 1001 1.7.2.2 bouyer void *addr; 1002 1.7.2.2 bouyer int flags; 1003 1.7.2.2 bouyer { 1004 1.7.2.2 bouyer return (0); 1005 1.7.2.2 bouyer } 1006 1.7.2.2 bouyer 1007 1.7.2.2 bouyer void 1008 1.7.2.2 bouyer cs4280_close(addr) 1009 1.7.2.2 bouyer void *addr; 1010 1.7.2.2 bouyer { 1011 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1012 1.7.2.2 bouyer 1013 1.7.2.2 bouyer cs4280_halt_output(sc); 1014 1.7.2.2 bouyer cs4280_halt_input(sc); 1015 1.7.2.2 bouyer 1016 1.7.2.2 bouyer sc->sc_pintr = 0; 1017 1.7.2.2 bouyer sc->sc_rintr = 0; 1018 1.7.2.2 bouyer } 1019 1.7.2.2 bouyer 1020 1.7.2.2 bouyer int 1021 1.7.2.2 bouyer cs4280_query_encoding(addr, fp) 1022 1.7.2.2 bouyer void *addr; 1023 1.7.2.2 bouyer struct audio_encoding *fp; 1024 1.7.2.2 bouyer { 1025 1.7.2.2 bouyer switch (fp->index) { 1026 1.7.2.2 bouyer case 0: 1027 1.7.2.2 bouyer strcpy(fp->name, AudioEulinear); 1028 1.7.2.2 bouyer fp->encoding = AUDIO_ENCODING_ULINEAR; 1029 1.7.2.2 bouyer fp->precision = 8; 1030 1.7.2.2 bouyer fp->flags = 0; 1031 1.7.2.2 bouyer break; 1032 1.7.2.2 bouyer case 1: 1033 1.7.2.2 bouyer strcpy(fp->name, AudioEmulaw); 1034 1.7.2.2 bouyer fp->encoding = AUDIO_ENCODING_ULAW; 1035 1.7.2.2 bouyer fp->precision = 8; 1036 1.7.2.2 bouyer fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1037 1.7.2.2 bouyer break; 1038 1.7.2.2 bouyer case 2: 1039 1.7.2.2 bouyer strcpy(fp->name, AudioEalaw); 1040 1.7.2.2 bouyer fp->encoding = AUDIO_ENCODING_ALAW; 1041 1.7.2.2 bouyer fp->precision = 8; 1042 1.7.2.2 bouyer fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1043 1.7.2.2 bouyer break; 1044 1.7.2.2 bouyer case 3: 1045 1.7.2.2 bouyer strcpy(fp->name, AudioEslinear); 1046 1.7.2.2 bouyer fp->encoding = AUDIO_ENCODING_SLINEAR; 1047 1.7.2.2 bouyer fp->precision = 8; 1048 1.7.2.2 bouyer fp->flags = 0; 1049 1.7.2.2 bouyer break; 1050 1.7.2.2 bouyer case 4: 1051 1.7.2.2 bouyer strcpy(fp->name, AudioEslinear_le); 1052 1.7.2.2 bouyer fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1053 1.7.2.2 bouyer fp->precision = 16; 1054 1.7.2.2 bouyer fp->flags = 0; 1055 1.7.2.2 bouyer break; 1056 1.7.2.2 bouyer case 5: 1057 1.7.2.2 bouyer strcpy(fp->name, AudioEulinear_le); 1058 1.7.2.2 bouyer fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1059 1.7.2.2 bouyer fp->precision = 16; 1060 1.7.2.2 bouyer fp->flags = 0; 1061 1.7.2.2 bouyer break; 1062 1.7.2.2 bouyer case 6: 1063 1.7.2.2 bouyer strcpy(fp->name, AudioEslinear_be); 1064 1.7.2.2 bouyer fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1065 1.7.2.2 bouyer fp->precision = 16; 1066 1.7.2.2 bouyer fp->flags = 0; 1067 1.7.2.2 bouyer break; 1068 1.7.2.2 bouyer case 7: 1069 1.7.2.2 bouyer strcpy(fp->name, AudioEulinear_be); 1070 1.7.2.2 bouyer fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1071 1.7.2.2 bouyer fp->precision = 16; 1072 1.7.2.2 bouyer fp->flags = 0; 1073 1.7.2.2 bouyer break; 1074 1.7.2.2 bouyer default: 1075 1.7.2.2 bouyer return (EINVAL); 1076 1.7.2.2 bouyer } 1077 1.7.2.2 bouyer return (0); 1078 1.7.2.2 bouyer } 1079 1.7.2.2 bouyer 1080 1.7.2.2 bouyer int 1081 1.7.2.2 bouyer cs4280_set_params(addr, setmode, usemode, play, rec) 1082 1.7.2.2 bouyer void *addr; 1083 1.7.2.2 bouyer int setmode, usemode; 1084 1.7.2.2 bouyer struct audio_params *play, *rec; 1085 1.7.2.2 bouyer { 1086 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1087 1.7.2.2 bouyer struct audio_params *p; 1088 1.7.2.2 bouyer int mode; 1089 1.7.2.2 bouyer 1090 1.7.2.2 bouyer for (mode = AUMODE_RECORD; mode != -1; 1091 1.7.2.2 bouyer mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1092 1.7.2.2 bouyer if ((setmode & mode) == 0) 1093 1.7.2.2 bouyer continue; 1094 1.7.2.2 bouyer 1095 1.7.2.2 bouyer p = mode == AUMODE_PLAY ? play : rec; 1096 1.7.2.2 bouyer 1097 1.7.2.2 bouyer if (p == play) { 1098 1.7.2.2 bouyer DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1099 1.7.2.2 bouyer p->sample_rate, p->precision, p->channels)); 1100 1.7.2.2 bouyer /* play back data format may be 8- or 16-bit and 1101 1.7.2.2 bouyer * either stereo or mono. 1102 1.7.2.2 bouyer * playback rate may range from 8000Hz to 48000Hz 1103 1.7.2.2 bouyer */ 1104 1.7.2.2 bouyer if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1105 1.7.2.2 bouyer (p->precision != 8 && p->precision != 16) || 1106 1.7.2.2 bouyer (p->channels != 1 && p->channels != 2) ) { 1107 1.7.2.2 bouyer return (EINVAL); 1108 1.7.2.2 bouyer } 1109 1.7.2.2 bouyer } else { 1110 1.7.2.2 bouyer DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1111 1.7.2.2 bouyer p->sample_rate, p->precision, p->channels)); 1112 1.7.2.2 bouyer /* capture data format must be 16bit stereo 1113 1.7.2.2 bouyer * and sample rate range from 11025Hz to 48000Hz. 1114 1.7.2.2 bouyer * 1115 1.7.2.2 bouyer * XXX: it looks like to work with 8000Hz, 1116 1.7.2.2 bouyer * although data sheets say lower limit is 1117 1.7.2.2 bouyer * 11025 Hz. 1118 1.7.2.2 bouyer */ 1119 1.7.2.2 bouyer 1120 1.7.2.2 bouyer if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1121 1.7.2.2 bouyer (p->precision != 8 && p->precision != 16) || 1122 1.7.2.2 bouyer (p->channels != 1 && p->channels != 2) ) { 1123 1.7.2.2 bouyer return (EINVAL); 1124 1.7.2.2 bouyer } 1125 1.7.2.2 bouyer } 1126 1.7.2.2 bouyer p->factor = 1; 1127 1.7.2.2 bouyer p->sw_code = 0; 1128 1.7.2.2 bouyer 1129 1.7.2.2 bouyer /* capturing data is slinear */ 1130 1.7.2.2 bouyer switch (p->encoding) { 1131 1.7.2.2 bouyer case AUDIO_ENCODING_SLINEAR_BE: 1132 1.7.2.2 bouyer if (mode == AUMODE_RECORD) { 1133 1.7.2.2 bouyer if (p->precision == 16) 1134 1.7.2.2 bouyer p->sw_code = swap_bytes; 1135 1.7.2.2 bouyer } 1136 1.7.2.2 bouyer break; 1137 1.7.2.2 bouyer case AUDIO_ENCODING_SLINEAR_LE: 1138 1.7.2.2 bouyer break; 1139 1.7.2.2 bouyer case AUDIO_ENCODING_ULINEAR_BE: 1140 1.7.2.2 bouyer if (mode == AUMODE_RECORD) { 1141 1.7.2.2 bouyer if (p->precision == 16) 1142 1.7.2.2 bouyer p->sw_code = change_sign16_swap_bytes_le; 1143 1.7.2.2 bouyer else 1144 1.7.2.2 bouyer p->sw_code = change_sign8; 1145 1.7.2.2 bouyer } 1146 1.7.2.2 bouyer break; 1147 1.7.2.2 bouyer case AUDIO_ENCODING_ULINEAR_LE: 1148 1.7.2.2 bouyer if (mode == AUMODE_RECORD) { 1149 1.7.2.2 bouyer if (p->precision == 16) 1150 1.7.2.2 bouyer p->sw_code = change_sign16_le; 1151 1.7.2.2 bouyer else 1152 1.7.2.2 bouyer p->sw_code = change_sign8; 1153 1.7.2.2 bouyer } 1154 1.7.2.2 bouyer break; 1155 1.7.2.2 bouyer case AUDIO_ENCODING_ULAW: 1156 1.7.2.2 bouyer if (mode == AUMODE_PLAY) { 1157 1.7.2.2 bouyer p->factor = 2; 1158 1.7.2.2 bouyer p->sw_code = mulaw_to_slinear16_le; 1159 1.7.2.2 bouyer } else { 1160 1.7.2.2 bouyer p->sw_code = slinear8_to_mulaw; 1161 1.7.2.2 bouyer } 1162 1.7.2.2 bouyer break; 1163 1.7.2.2 bouyer case AUDIO_ENCODING_ALAW: 1164 1.7.2.2 bouyer if (mode == AUMODE_PLAY) { 1165 1.7.2.2 bouyer p->factor = 2; 1166 1.7.2.2 bouyer p->sw_code = alaw_to_slinear16_le; 1167 1.7.2.2 bouyer } else { 1168 1.7.2.2 bouyer p->sw_code = slinear8_to_alaw; 1169 1.7.2.2 bouyer } 1170 1.7.2.2 bouyer break; 1171 1.7.2.2 bouyer default: 1172 1.7.2.2 bouyer return (EINVAL); 1173 1.7.2.2 bouyer } 1174 1.7.2.2 bouyer } 1175 1.7.2.2 bouyer 1176 1.7.2.2 bouyer /* set sample rate */ 1177 1.7.2.2 bouyer cs4280_set_dac_rate(sc, play->sample_rate); 1178 1.7.2.2 bouyer cs4280_set_adc_rate(sc, rec->sample_rate); 1179 1.7.2.2 bouyer return (0); 1180 1.7.2.2 bouyer } 1181 1.7.2.2 bouyer 1182 1.7.2.2 bouyer int 1183 1.7.2.2 bouyer cs4280_round_blocksize(hdl, blk) 1184 1.7.2.2 bouyer void *hdl; 1185 1.7.2.2 bouyer int blk; 1186 1.7.2.2 bouyer { 1187 1.7.2.2 bouyer return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1188 1.7.2.2 bouyer } 1189 1.7.2.2 bouyer 1190 1.7.2.2 bouyer size_t 1191 1.7.2.2 bouyer cs4280_round_buffersize(addr, direction, size) 1192 1.7.2.2 bouyer void *addr; 1193 1.7.2.2 bouyer int direction; 1194 1.7.2.2 bouyer size_t size; 1195 1.7.2.2 bouyer { 1196 1.7.2.2 bouyer /* although real dma buffer size is 4KB, 1197 1.7.2.2 bouyer * let the audio.c driver use a larger buffer. 1198 1.7.2.2 bouyer * ( suggested by Lennart Augustsson. ) 1199 1.7.2.2 bouyer */ 1200 1.7.2.2 bouyer return (size); 1201 1.7.2.2 bouyer } 1202 1.7.2.2 bouyer 1203 1.7.2.2 bouyer int 1204 1.7.2.2 bouyer cs4280_get_props(hdl) 1205 1.7.2.2 bouyer void *hdl; 1206 1.7.2.2 bouyer { 1207 1.7.2.2 bouyer return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1208 1.7.2.2 bouyer #ifdef notyet 1209 1.7.2.2 bouyer /* XXX 1210 1.7.2.2 bouyer * How can I mmap ? 1211 1.7.2.2 bouyer */ 1212 1.7.2.2 bouyer AUDIO_PROP_MMAP 1213 1.7.2.2 bouyer #endif 1214 1.7.2.2 bouyer 1215 1.7.2.2 bouyer } 1216 1.7.2.2 bouyer 1217 1.7.2.2 bouyer int 1218 1.7.2.2 bouyer cs4280_mixer_get_port(addr, cp) 1219 1.7.2.2 bouyer void *addr; 1220 1.7.2.2 bouyer mixer_ctrl_t *cp; 1221 1.7.2.2 bouyer { 1222 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1223 1.7.2.2 bouyer 1224 1.7.2.2 bouyer return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1225 1.7.2.2 bouyer } 1226 1.7.2.2 bouyer 1227 1.7.2.2 bouyer paddr_t 1228 1.7.2.2 bouyer cs4280_mappage(addr, mem, off, prot) 1229 1.7.2.2 bouyer void *addr; 1230 1.7.2.2 bouyer void *mem; 1231 1.7.2.2 bouyer off_t off; 1232 1.7.2.2 bouyer int prot; 1233 1.7.2.2 bouyer { 1234 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1235 1.7.2.2 bouyer struct cs4280_dma *p; 1236 1.7.2.2 bouyer 1237 1.7.2.2 bouyer if (off < 0) 1238 1.7.2.2 bouyer return (-1); 1239 1.7.2.2 bouyer for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1240 1.7.2.2 bouyer ; 1241 1.7.2.2 bouyer if (!p) { 1242 1.7.2.2 bouyer DPRINTF(("cs4280_mappage: bad buffer address\n")); 1243 1.7.2.2 bouyer return (-1); 1244 1.7.2.2 bouyer } 1245 1.7.2.2 bouyer return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1246 1.7.2.2 bouyer off, prot, BUS_DMA_WAITOK)); 1247 1.7.2.2 bouyer } 1248 1.7.2.2 bouyer 1249 1.7.2.2 bouyer 1250 1.7.2.2 bouyer int 1251 1.7.2.2 bouyer cs4280_query_devinfo(addr, dip) 1252 1.7.2.2 bouyer void *addr; 1253 1.7.2.2 bouyer mixer_devinfo_t *dip; 1254 1.7.2.2 bouyer { 1255 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1256 1.7.2.2 bouyer 1257 1.7.2.2 bouyer return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1258 1.7.2.2 bouyer } 1259 1.7.2.2 bouyer 1260 1.7.2.2 bouyer int 1261 1.7.2.2 bouyer cs4280_get_portnum_by_name(sc, class, device, qualifier) 1262 1.7.2.2 bouyer struct cs4280_softc *sc; 1263 1.7.2.2 bouyer char *class, *device, *qualifier; 1264 1.7.2.2 bouyer { 1265 1.7.2.2 bouyer return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1266 1.7.2.2 bouyer device, qualifier)); 1267 1.7.2.2 bouyer } 1268 1.7.2.2 bouyer 1269 1.7.2.2 bouyer int 1270 1.7.2.2 bouyer cs4280_halt_output(addr) 1271 1.7.2.2 bouyer void *addr; 1272 1.7.2.2 bouyer { 1273 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1274 1.7.2.2 bouyer u_int32_t mem; 1275 1.7.2.2 bouyer 1276 1.7.2.2 bouyer mem = BA1READ4(sc, CS4280_PCTL); 1277 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1278 1.7.2.2 bouyer #ifdef DIAGNOSTIC 1279 1.7.2.2 bouyer sc->sc_prun = 0; 1280 1.7.2.2 bouyer #endif 1281 1.7.2.2 bouyer return (0); 1282 1.7.2.2 bouyer } 1283 1.7.2.2 bouyer 1284 1.7.2.2 bouyer int 1285 1.7.2.2 bouyer cs4280_halt_input(addr) 1286 1.7.2.2 bouyer void *addr; 1287 1.7.2.2 bouyer { 1288 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1289 1.7.2.2 bouyer u_int32_t mem; 1290 1.7.2.2 bouyer 1291 1.7.2.2 bouyer mem = BA1READ4(sc, CS4280_CCTL); 1292 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1293 1.7.2.2 bouyer #ifdef DIAGNOSTIC 1294 1.7.2.2 bouyer sc->sc_rrun = 0; 1295 1.7.2.2 bouyer #endif 1296 1.7.2.2 bouyer return (0); 1297 1.7.2.2 bouyer } 1298 1.7.2.2 bouyer 1299 1.7.2.2 bouyer int 1300 1.7.2.2 bouyer cs4280_getdev(addr, retp) 1301 1.7.2.2 bouyer void *addr; 1302 1.7.2.2 bouyer struct audio_device *retp; 1303 1.7.2.2 bouyer { 1304 1.7.2.2 bouyer *retp = cs4280_device; 1305 1.7.2.2 bouyer return (0); 1306 1.7.2.2 bouyer } 1307 1.7.2.2 bouyer 1308 1.7.2.2 bouyer int 1309 1.7.2.2 bouyer cs4280_mixer_set_port(addr, cp) 1310 1.7.2.2 bouyer void *addr; 1311 1.7.2.2 bouyer mixer_ctrl_t *cp; 1312 1.7.2.2 bouyer { 1313 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1314 1.7.2.2 bouyer int val; 1315 1.7.2.2 bouyer 1316 1.7.2.2 bouyer val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1317 1.7.2.2 bouyer DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1318 1.7.2.2 bouyer return (val); 1319 1.7.2.2 bouyer } 1320 1.7.2.2 bouyer 1321 1.7.2.2 bouyer 1322 1.7.2.2 bouyer int 1323 1.7.2.2 bouyer cs4280_freemem(sc, p) 1324 1.7.2.2 bouyer struct cs4280_softc *sc; 1325 1.7.2.2 bouyer struct cs4280_dma *p; 1326 1.7.2.2 bouyer { 1327 1.7.2.2 bouyer bus_dmamap_unload(sc->sc_dmatag, p->map); 1328 1.7.2.2 bouyer bus_dmamap_destroy(sc->sc_dmatag, p->map); 1329 1.7.2.2 bouyer bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1330 1.7.2.2 bouyer bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1331 1.7.2.2 bouyer return (0); 1332 1.7.2.2 bouyer } 1333 1.7.2.2 bouyer 1334 1.7.2.2 bouyer int 1335 1.7.2.2 bouyer cs4280_allocmem(sc, size, align, p) 1336 1.7.2.2 bouyer struct cs4280_softc *sc; 1337 1.7.2.2 bouyer size_t size; 1338 1.7.2.2 bouyer size_t align; 1339 1.7.2.2 bouyer struct cs4280_dma *p; 1340 1.7.2.2 bouyer { 1341 1.7.2.2 bouyer int error; 1342 1.7.2.2 bouyer 1343 1.7.2.2 bouyer /* XXX */ 1344 1.7.2.2 bouyer p->size = size; 1345 1.7.2.2 bouyer error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1346 1.7.2.2 bouyer p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1347 1.7.2.2 bouyer &p->nsegs, BUS_DMA_NOWAIT); 1348 1.7.2.2 bouyer if (error) { 1349 1.7.2.2 bouyer printf("%s: unable to allocate dma, error=%d\n", 1350 1.7.2.2 bouyer sc->sc_dev.dv_xname, error); 1351 1.7.2.2 bouyer return (error); 1352 1.7.2.2 bouyer } 1353 1.7.2.2 bouyer 1354 1.7.2.2 bouyer error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1355 1.7.2.2 bouyer &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1356 1.7.2.2 bouyer if (error) { 1357 1.7.2.2 bouyer printf("%s: unable to map dma, error=%d\n", 1358 1.7.2.2 bouyer sc->sc_dev.dv_xname, error); 1359 1.7.2.2 bouyer goto free; 1360 1.7.2.2 bouyer } 1361 1.7.2.2 bouyer 1362 1.7.2.2 bouyer error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1363 1.7.2.2 bouyer 0, BUS_DMA_NOWAIT, &p->map); 1364 1.7.2.2 bouyer if (error) { 1365 1.7.2.2 bouyer printf("%s: unable to create dma map, error=%d\n", 1366 1.7.2.2 bouyer sc->sc_dev.dv_xname, error); 1367 1.7.2.2 bouyer goto unmap; 1368 1.7.2.2 bouyer } 1369 1.7.2.2 bouyer 1370 1.7.2.2 bouyer error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1371 1.7.2.2 bouyer BUS_DMA_NOWAIT); 1372 1.7.2.2 bouyer if (error) { 1373 1.7.2.2 bouyer printf("%s: unable to load dma map, error=%d\n", 1374 1.7.2.2 bouyer sc->sc_dev.dv_xname, error); 1375 1.7.2.2 bouyer goto destroy; 1376 1.7.2.2 bouyer } 1377 1.7.2.2 bouyer return (0); 1378 1.7.2.2 bouyer 1379 1.7.2.2 bouyer destroy: 1380 1.7.2.2 bouyer bus_dmamap_destroy(sc->sc_dmatag, p->map); 1381 1.7.2.2 bouyer unmap: 1382 1.7.2.2 bouyer bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1383 1.7.2.2 bouyer free: 1384 1.7.2.2 bouyer bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1385 1.7.2.2 bouyer return (error); 1386 1.7.2.2 bouyer } 1387 1.7.2.2 bouyer 1388 1.7.2.2 bouyer 1389 1.7.2.2 bouyer void * 1390 1.7.2.2 bouyer cs4280_malloc(addr, direction, size, pool, flags) 1391 1.7.2.2 bouyer void *addr; 1392 1.7.2.2 bouyer int direction; 1393 1.7.2.2 bouyer size_t size; 1394 1.7.2.2 bouyer int pool, flags; 1395 1.7.2.2 bouyer { 1396 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1397 1.7.2.2 bouyer struct cs4280_dma *p; 1398 1.7.2.2 bouyer caddr_t q; 1399 1.7.2.2 bouyer int error; 1400 1.7.2.2 bouyer 1401 1.7.2.2 bouyer DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1402 1.7.2.2 bouyer q = malloc(size, pool, flags); 1403 1.7.2.2 bouyer if (!q) 1404 1.7.2.2 bouyer return (0); 1405 1.7.2.2 bouyer p = malloc(sizeof(*p), pool, flags); 1406 1.7.2.2 bouyer if (!p) { 1407 1.7.2.2 bouyer free(q,pool); 1408 1.7.2.2 bouyer return (0); 1409 1.7.2.2 bouyer } 1410 1.7.2.2 bouyer /* 1411 1.7.2.2 bouyer * cs4280 has fixed 4kB buffer 1412 1.7.2.2 bouyer */ 1413 1.7.2.2 bouyer error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1414 1.7.2.2 bouyer 1415 1.7.2.2 bouyer if (error) { 1416 1.7.2.2 bouyer free(q, pool); 1417 1.7.2.2 bouyer free(p, pool); 1418 1.7.2.2 bouyer return (0); 1419 1.7.2.2 bouyer } 1420 1.7.2.2 bouyer 1421 1.7.2.2 bouyer p->next = sc->sc_dmas; 1422 1.7.2.2 bouyer sc->sc_dmas = p; 1423 1.7.2.2 bouyer p->dum = q; /* return to audio driver */ 1424 1.7.2.2 bouyer 1425 1.7.2.2 bouyer return (p->dum); 1426 1.7.2.2 bouyer } 1427 1.7.2.2 bouyer 1428 1.7.2.2 bouyer void 1429 1.7.2.2 bouyer cs4280_free(addr, ptr, pool) 1430 1.7.2.2 bouyer void *addr; 1431 1.7.2.2 bouyer void *ptr; 1432 1.7.2.2 bouyer int pool; 1433 1.7.2.2 bouyer { 1434 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1435 1.7.2.2 bouyer struct cs4280_dma **pp, *p; 1436 1.7.2.2 bouyer 1437 1.7.2.2 bouyer for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1438 1.7.2.2 bouyer if (BUFADDR(p) == ptr) { 1439 1.7.2.2 bouyer cs4280_freemem(sc, p); 1440 1.7.2.2 bouyer *pp = p->next; 1441 1.7.2.2 bouyer free(p->dum, pool); 1442 1.7.2.2 bouyer free(p, pool); 1443 1.7.2.2 bouyer return; 1444 1.7.2.2 bouyer } 1445 1.7.2.2 bouyer } 1446 1.7.2.2 bouyer } 1447 1.7.2.2 bouyer 1448 1.7.2.2 bouyer int 1449 1.7.2.2 bouyer cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1450 1.7.2.2 bouyer void *addr; 1451 1.7.2.2 bouyer void *start, *end; 1452 1.7.2.2 bouyer int blksize; 1453 1.7.2.2 bouyer void (*intr) __P((void *)); 1454 1.7.2.2 bouyer void *arg; 1455 1.7.2.2 bouyer struct audio_params *param; 1456 1.7.2.2 bouyer { 1457 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1458 1.7.2.2 bouyer u_int32_t pfie, pctl, mem, pdtc; 1459 1.7.2.2 bouyer struct cs4280_dma *p; 1460 1.7.2.2 bouyer 1461 1.7.2.2 bouyer #ifdef DIAGNOSTIC 1462 1.7.2.2 bouyer if (sc->sc_prun) 1463 1.7.2.2 bouyer printf("cs4280_trigger_output: already running\n"); 1464 1.7.2.2 bouyer sc->sc_prun = 1; 1465 1.7.2.2 bouyer #endif 1466 1.7.2.2 bouyer 1467 1.7.2.2 bouyer DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1468 1.7.2.2 bouyer "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1469 1.7.2.2 bouyer sc->sc_pintr = intr; 1470 1.7.2.2 bouyer sc->sc_parg = arg; 1471 1.7.2.2 bouyer 1472 1.7.2.2 bouyer /* stop playback DMA */ 1473 1.7.2.2 bouyer mem = BA1READ4(sc, CS4280_PCTL); 1474 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1475 1.7.2.2 bouyer 1476 1.7.2.2 bouyer /* setup PDTC */ 1477 1.7.2.2 bouyer pdtc = BA1READ4(sc, CS4280_PDTC); 1478 1.7.2.2 bouyer pdtc &= ~PDTC_MASK; 1479 1.7.2.2 bouyer pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1480 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PDTC, pdtc); 1481 1.7.2.2 bouyer 1482 1.7.2.2 bouyer DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1483 1.7.2.2 bouyer param->precision, param->factor, param->channels, 1484 1.7.2.2 bouyer param->encoding)); 1485 1.7.2.2 bouyer for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1486 1.7.2.2 bouyer ; 1487 1.7.2.2 bouyer if (p == NULL) { 1488 1.7.2.2 bouyer printf("cs4280_trigger_output: bad addr %p\n", start); 1489 1.7.2.2 bouyer return (EINVAL); 1490 1.7.2.2 bouyer } 1491 1.7.2.2 bouyer if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1492 1.7.2.2 bouyer printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1493 1.7.2.2 bouyer "4kB align\n", DMAADDR(p)); 1494 1.7.2.2 bouyer return (EINVAL); 1495 1.7.2.2 bouyer } 1496 1.7.2.2 bouyer 1497 1.7.2.2 bouyer sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1498 1.7.2.2 bouyer sc->sc_ps = (char *)start; 1499 1.7.2.2 bouyer sc->sc_pe = (char *)end; 1500 1.7.2.2 bouyer sc->sc_pdma = p; 1501 1.7.2.2 bouyer sc->sc_pbuf = KERNADDR(p); 1502 1.7.2.2 bouyer sc->sc_pi = 0; 1503 1.7.2.2 bouyer sc->sc_pn = sc->sc_ps; 1504 1.7.2.2 bouyer if (blksize >= CS4280_DCHUNK) { 1505 1.7.2.2 bouyer sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1506 1.7.2.2 bouyer memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1507 1.7.2.2 bouyer ++sc->sc_pi; 1508 1.7.2.2 bouyer } else { 1509 1.7.2.2 bouyer sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1510 1.7.2.2 bouyer memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1511 1.7.2.2 bouyer } 1512 1.7.2.2 bouyer 1513 1.7.2.2 bouyer /* initiate playback dma */ 1514 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1515 1.7.2.2 bouyer 1516 1.7.2.2 bouyer /* set PFIE */ 1517 1.7.2.2 bouyer pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1518 1.7.2.2 bouyer 1519 1.7.2.2 bouyer if (param->precision * param->factor == 8) 1520 1.7.2.2 bouyer pfie |= PFIE_8BIT; 1521 1.7.2.2 bouyer if (param->channels == 1) 1522 1.7.2.2 bouyer pfie |= PFIE_MONO; 1523 1.7.2.2 bouyer 1524 1.7.2.2 bouyer if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1525 1.7.2.2 bouyer param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1526 1.7.2.2 bouyer pfie |= PFIE_SWAPPED; 1527 1.7.2.2 bouyer if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1528 1.7.2.2 bouyer param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1529 1.7.2.2 bouyer pfie |= PFIE_UNSIGNED; 1530 1.7.2.2 bouyer 1531 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1532 1.7.2.2 bouyer 1533 1.7.2.2 bouyer cs4280_set_dac_rate(sc, param->sample_rate); 1534 1.7.2.2 bouyer 1535 1.7.2.2 bouyer pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1536 1.7.2.2 bouyer pctl |= sc->pctl; 1537 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PCTL, pctl); 1538 1.7.2.2 bouyer return (0); 1539 1.7.2.2 bouyer } 1540 1.7.2.2 bouyer 1541 1.7.2.2 bouyer int 1542 1.7.2.2 bouyer cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1543 1.7.2.2 bouyer void *addr; 1544 1.7.2.2 bouyer void *start, *end; 1545 1.7.2.2 bouyer int blksize; 1546 1.7.2.2 bouyer void (*intr) __P((void *)); 1547 1.7.2.2 bouyer void *arg; 1548 1.7.2.2 bouyer struct audio_params *param; 1549 1.7.2.2 bouyer { 1550 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1551 1.7.2.2 bouyer u_int32_t cctl, cie; 1552 1.7.2.2 bouyer struct cs4280_dma *p; 1553 1.7.2.2 bouyer 1554 1.7.2.2 bouyer #ifdef DIAGNOSTIC 1555 1.7.2.2 bouyer if (sc->sc_rrun) 1556 1.7.2.2 bouyer printf("cs4280_trigger_input: already running\n"); 1557 1.7.2.2 bouyer sc->sc_rrun = 1; 1558 1.7.2.2 bouyer #endif 1559 1.7.2.2 bouyer DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1560 1.7.2.2 bouyer "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1561 1.7.2.2 bouyer sc->sc_rintr = intr; 1562 1.7.2.2 bouyer sc->sc_rarg = arg; 1563 1.7.2.2 bouyer 1564 1.7.2.2 bouyer sc->sc_ri = 0; 1565 1.7.2.2 bouyer sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1566 1.7.2.2 bouyer sc->sc_rs = (char *)start; 1567 1.7.2.2 bouyer sc->sc_re = (char *)end; 1568 1.7.2.2 bouyer sc->sc_rn = sc->sc_rs; 1569 1.7.2.2 bouyer 1570 1.7.2.2 bouyer /* setup format information for internal converter */ 1571 1.7.2.2 bouyer sc->sc_rparam = 0; 1572 1.7.2.2 bouyer if (param->precision == 8) { 1573 1.7.2.2 bouyer sc->sc_rparam += CF_8BIT; 1574 1.7.2.2 bouyer sc->sc_rcount <<= 1; 1575 1.7.2.2 bouyer } 1576 1.7.2.2 bouyer if (param->channels == 1) { 1577 1.7.2.2 bouyer sc->sc_rparam += CF_MONO; 1578 1.7.2.2 bouyer sc->sc_rcount <<= 1; 1579 1.7.2.2 bouyer } 1580 1.7.2.2 bouyer 1581 1.7.2.2 bouyer /* stop capture DMA */ 1582 1.7.2.2 bouyer cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1583 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CCTL, cctl); 1584 1.7.2.2 bouyer 1585 1.7.2.2 bouyer for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1586 1.7.2.2 bouyer ; 1587 1.7.2.2 bouyer if (!p) { 1588 1.7.2.2 bouyer printf("cs4280_trigger_input: bad addr %p\n", start); 1589 1.7.2.2 bouyer return (EINVAL); 1590 1.7.2.2 bouyer } 1591 1.7.2.2 bouyer if (DMAADDR(p) % CS4280_DALIGN != 0) { 1592 1.7.2.2 bouyer printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1593 1.7.2.2 bouyer "4kB align\n", DMAADDR(p)); 1594 1.7.2.2 bouyer return (EINVAL); 1595 1.7.2.2 bouyer } 1596 1.7.2.2 bouyer sc->sc_rdma = p; 1597 1.7.2.2 bouyer sc->sc_rbuf = KERNADDR(p); 1598 1.7.2.2 bouyer 1599 1.7.2.2 bouyer /* initiate capture dma */ 1600 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1601 1.7.2.2 bouyer 1602 1.7.2.2 bouyer /* set CIE */ 1603 1.7.2.2 bouyer cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1604 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1605 1.7.2.2 bouyer 1606 1.7.2.2 bouyer cs4280_set_adc_rate(sc, param->sample_rate); 1607 1.7.2.2 bouyer 1608 1.7.2.2 bouyer cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1609 1.7.2.2 bouyer cctl |= sc->cctl; 1610 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CCTL, cctl); 1611 1.7.2.2 bouyer return (0); 1612 1.7.2.2 bouyer } 1613 1.7.2.2 bouyer 1614 1.7.2.2 bouyer int 1615 1.7.2.2 bouyer cs4280_init(sc, init) 1616 1.7.2.2 bouyer struct cs4280_softc *sc; 1617 1.7.2.2 bouyer int init; 1618 1.7.2.2 bouyer { 1619 1.7.2.2 bouyer int n; 1620 1.7.2.2 bouyer u_int32_t mem; 1621 1.7.2.2 bouyer 1622 1.7.2.2 bouyer /* Start PLL out in known state */ 1623 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_CLKCR1, 0); 1624 1.7.2.2 bouyer /* Start serial ports out in known state */ 1625 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_SERMC1, 0); 1626 1.7.2.2 bouyer 1627 1.7.2.2 bouyer /* Specify type of CODEC */ 1628 1.7.2.2 bouyer /* XXX should not be here */ 1629 1.7.2.2 bouyer #define SERACC_CODEC_TYPE_1_03 1630 1.7.2.2 bouyer #ifdef SERACC_CODEC_TYPE_1_03 1631 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1632 1.7.2.2 bouyer #else 1633 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1634 1.7.2.2 bouyer #endif 1635 1.7.2.2 bouyer 1636 1.7.2.2 bouyer /* Reset codec */ 1637 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCTL, 0); 1638 1.7.2.2 bouyer delay(100); /* delay 100us */ 1639 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1640 1.7.2.2 bouyer 1641 1.7.2.2 bouyer /* Enable AC-link sync generation */ 1642 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1643 1.7.2.2 bouyer delay(50*1000); /* delay 50ms */ 1644 1.7.2.2 bouyer 1645 1.7.2.2 bouyer /* Set the serial port timing configuration */ 1646 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1647 1.7.2.2 bouyer 1648 1.7.2.2 bouyer /* Setup clock control */ 1649 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1650 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1651 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1652 1.7.2.2 bouyer 1653 1.7.2.2 bouyer /* Power up the PLL */ 1654 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1655 1.7.2.2 bouyer delay(50*1000); /* delay 50ms */ 1656 1.7.2.2 bouyer 1657 1.7.2.2 bouyer /* Turn on clock */ 1658 1.7.2.2 bouyer mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1659 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_CLKCR1, mem); 1660 1.7.2.2 bouyer 1661 1.7.2.2 bouyer /* Set the serial port FIFO pointer to the 1662 1.7.2.2 bouyer * first sample in FIFO. (not documented) */ 1663 1.7.2.2 bouyer cs4280_clear_fifos(sc); 1664 1.7.2.2 bouyer 1665 1.7.2.2 bouyer #if 0 1666 1.7.2.2 bouyer /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1667 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_SERBSP, 0); 1668 1.7.2.2 bouyer #endif 1669 1.7.2.2 bouyer 1670 1.7.2.2 bouyer /* Configure the serial port */ 1671 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1672 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1673 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1674 1.7.2.2 bouyer 1675 1.7.2.2 bouyer /* Wait for CODEC ready */ 1676 1.7.2.2 bouyer n = 0; 1677 1.7.2.2 bouyer while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1678 1.7.2.2 bouyer delay(125); 1679 1.7.2.2 bouyer if (++n > 1000) { 1680 1.7.2.2 bouyer printf("%s: codec ready timeout\n", 1681 1.7.2.2 bouyer sc->sc_dev.dv_xname); 1682 1.7.2.2 bouyer return(1); 1683 1.7.2.2 bouyer } 1684 1.7.2.2 bouyer } 1685 1.7.2.2 bouyer 1686 1.7.2.2 bouyer /* Assert valid frame signal */ 1687 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1688 1.7.2.2 bouyer 1689 1.7.2.2 bouyer /* Wait for valid AC97 input slot */ 1690 1.7.2.2 bouyer n = 0; 1691 1.7.2.2 bouyer while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1692 1.7.2.2 bouyer (ACISV_ISV3 | ACISV_ISV4)) { 1693 1.7.2.2 bouyer delay(1000); 1694 1.7.2.2 bouyer if (++n > 1000) { 1695 1.7.2.2 bouyer printf("AC97 inputs slot ready timeout\n"); 1696 1.7.2.2 bouyer return(1); 1697 1.7.2.2 bouyer } 1698 1.7.2.2 bouyer } 1699 1.7.2.2 bouyer 1700 1.7.2.2 bouyer /* Set AC97 output slot valid signals */ 1701 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1702 1.7.2.2 bouyer 1703 1.7.2.2 bouyer /* reset the processor */ 1704 1.7.2.2 bouyer cs4280_reset(sc); 1705 1.7.2.2 bouyer 1706 1.7.2.2 bouyer /* Download the image to the processor */ 1707 1.7.2.2 bouyer if (cs4280_download_image(sc) != 0) { 1708 1.7.2.2 bouyer printf("%s: image download error\n", sc->sc_dev.dv_xname); 1709 1.7.2.2 bouyer return(1); 1710 1.7.2.2 bouyer } 1711 1.7.2.2 bouyer 1712 1.7.2.2 bouyer /* Save playback parameter and then write zero. 1713 1.7.2.2 bouyer * this ensures that DMA doesn't immediately occur upon 1714 1.7.2.2 bouyer * starting the processor core 1715 1.7.2.2 bouyer */ 1716 1.7.2.2 bouyer mem = BA1READ4(sc, CS4280_PCTL); 1717 1.7.2.2 bouyer sc->pctl = mem & PCTL_MASK; /* save startup value */ 1718 1.7.2.2 bouyer cs4280_halt_output(sc); 1719 1.7.2.2 bouyer 1720 1.7.2.2 bouyer /* Save capture parameter and then write zero. 1721 1.7.2.2 bouyer * this ensures that DMA doesn't immediately occur upon 1722 1.7.2.2 bouyer * starting the processor core 1723 1.7.2.2 bouyer */ 1724 1.7.2.2 bouyer mem = BA1READ4(sc, CS4280_CCTL); 1725 1.7.2.2 bouyer sc->cctl = mem & CCTL_MASK; /* save startup value */ 1726 1.7.2.2 bouyer cs4280_halt_input(sc); 1727 1.7.2.2 bouyer 1728 1.7.2.2 bouyer /* Processor Startup Procedure */ 1729 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1730 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1731 1.7.2.2 bouyer 1732 1.7.2.2 bouyer /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1733 1.7.2.2 bouyer n = 0; 1734 1.7.2.2 bouyer while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1735 1.7.2.2 bouyer delay(10); 1736 1.7.2.2 bouyer if (++n > 1000) { 1737 1.7.2.2 bouyer printf("SPCR 1->0 transition timeout\n"); 1738 1.7.2.2 bouyer return(1); 1739 1.7.2.2 bouyer } 1740 1.7.2.2 bouyer } 1741 1.7.2.2 bouyer 1742 1.7.2.2 bouyer n = 0; 1743 1.7.2.2 bouyer while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1744 1.7.2.2 bouyer delay(10); 1745 1.7.2.2 bouyer if (++n > 1000) { 1746 1.7.2.2 bouyer printf("SPCS 0->1 transition timeout\n"); 1747 1.7.2.2 bouyer return(1); 1748 1.7.2.2 bouyer } 1749 1.7.2.2 bouyer } 1750 1.7.2.2 bouyer /* Processor is now running !!! */ 1751 1.7.2.2 bouyer 1752 1.7.2.2 bouyer /* Setup volume */ 1753 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1754 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1755 1.7.2.2 bouyer 1756 1.7.2.2 bouyer /* Interrupt enable */ 1757 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1758 1.7.2.2 bouyer 1759 1.7.2.2 bouyer /* playback interrupt enable */ 1760 1.7.2.2 bouyer mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1761 1.7.2.2 bouyer mem |= PFIE_PI_ENABLE; 1762 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_PFIE, mem); 1763 1.7.2.2 bouyer /* capture interrupt enable */ 1764 1.7.2.2 bouyer mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1765 1.7.2.2 bouyer mem |= CIE_CI_ENABLE; 1766 1.7.2.2 bouyer BA1WRITE4(sc, CS4280_CIE, mem); 1767 1.7.2.2 bouyer 1768 1.7.2.2 bouyer #if NMIDI > 0 1769 1.7.2.2 bouyer /* Reset midi port */ 1770 1.7.2.2 bouyer mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1771 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1772 1.7.2.2 bouyer DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1773 1.7.2.2 bouyer /* midi interrupt enable */ 1774 1.7.2.2 bouyer mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1775 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_MIDCR, mem); 1776 1.7.2.2 bouyer #endif 1777 1.7.2.2 bouyer return(0); 1778 1.7.2.2 bouyer } 1779 1.7.2.2 bouyer 1780 1.7.2.2 bouyer void 1781 1.7.2.2 bouyer cs4280_power(why, v) 1782 1.7.2.2 bouyer int why; 1783 1.7.2.2 bouyer void *v; 1784 1.7.2.2 bouyer { 1785 1.7.2.2 bouyer struct cs4280_softc *sc = (struct cs4280_softc *)v; 1786 1.7.2.2 bouyer int i; 1787 1.7.2.2 bouyer 1788 1.7.2.2 bouyer DPRINTF(("%s: cs4280_power why=%d\n", 1789 1.7.2.2 bouyer sc->sc_dev.dv_xname, why)); 1790 1.7.2.3 bouyer switch (why) { 1791 1.7.2.3 bouyer case PWR_SUSPEND: 1792 1.7.2.3 bouyer case PWR_STANDBY: 1793 1.7.2.2 bouyer sc->sc_suspend = why; 1794 1.7.2.2 bouyer 1795 1.7.2.2 bouyer cs4280_halt_output(sc); 1796 1.7.2.2 bouyer cs4280_halt_input(sc); 1797 1.7.2.2 bouyer /* Save AC97 registers */ 1798 1.7.2.2 bouyer for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1799 1.7.2.2 bouyer if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1800 1.7.2.2 bouyer continue; 1801 1.7.2.2 bouyer cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i]); 1802 1.7.2.2 bouyer } 1803 1.7.2.2 bouyer /* should I powerdown here ? */ 1804 1.7.2.2 bouyer cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1805 1.7.2.3 bouyer break; 1806 1.7.2.3 bouyer case PWR_RESUME: 1807 1.7.2.2 bouyer if (sc->sc_suspend == PWR_RESUME) { 1808 1.7.2.2 bouyer printf("cs4280_power: odd, resume without suspend.\n"); 1809 1.7.2.2 bouyer sc->sc_suspend = why; 1810 1.7.2.2 bouyer return; 1811 1.7.2.2 bouyer } 1812 1.7.2.2 bouyer sc->sc_suspend = why; 1813 1.7.2.2 bouyer cs4280_init(sc, 0); 1814 1.7.2.2 bouyer cs4280_reset_codec(sc); 1815 1.7.2.2 bouyer 1816 1.7.2.2 bouyer /* restore ac97 registers */ 1817 1.7.2.2 bouyer for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1818 1.7.2.2 bouyer if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1819 1.7.2.2 bouyer continue; 1820 1.7.2.2 bouyer cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]); 1821 1.7.2.2 bouyer } 1822 1.7.2.3 bouyer break; 1823 1.7.2.3 bouyer case PWR_SOFTSUSPEND: 1824 1.7.2.3 bouyer case PWR_SOFTSTANDBY: 1825 1.7.2.3 bouyer case PWR_SOFTRESUME: 1826 1.7.2.3 bouyer break; 1827 1.7.2.2 bouyer } 1828 1.7.2.2 bouyer } 1829 1.7.2.2 bouyer 1830 1.7.2.2 bouyer void 1831 1.7.2.2 bouyer cs4280_clear_fifos(sc) 1832 1.7.2.2 bouyer struct cs4280_softc *sc; 1833 1.7.2.2 bouyer { 1834 1.7.2.2 bouyer int pd = 0, cnt, n; 1835 1.7.2.2 bouyer u_int32_t mem; 1836 1.7.2.2 bouyer 1837 1.7.2.2 bouyer /* 1838 1.7.2.2 bouyer * If device power down, power up the device and keep power down 1839 1.7.2.2 bouyer * state. 1840 1.7.2.2 bouyer */ 1841 1.7.2.2 bouyer mem = BA0READ4(sc, CS4280_CLKCR1); 1842 1.7.2.2 bouyer if (!(mem & CLKCR1_SWCE)) { 1843 1.7.2.2 bouyer printf("cs4280_clear_fifo: power down found.\n"); 1844 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1845 1.7.2.2 bouyer pd = 1; 1846 1.7.2.2 bouyer } 1847 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_SERBWP, 0); 1848 1.7.2.2 bouyer for (cnt = 0; cnt < 256; cnt++) { 1849 1.7.2.2 bouyer n = 0; 1850 1.7.2.2 bouyer while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1851 1.7.2.2 bouyer delay(1000); 1852 1.7.2.2 bouyer if (++n > 1000) { 1853 1.7.2.2 bouyer printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1854 1.7.2.2 bouyer break; 1855 1.7.2.2 bouyer } 1856 1.7.2.2 bouyer } 1857 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_SERBAD, cnt); 1858 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1859 1.7.2.2 bouyer } 1860 1.7.2.2 bouyer if (pd) 1861 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_CLKCR1, mem); 1862 1.7.2.2 bouyer } 1863 1.7.2.2 bouyer 1864 1.7.2.2 bouyer #if NMIDI > 0 1865 1.7.2.2 bouyer int 1866 1.7.2.2 bouyer cs4280_midi_open(addr, flags, iintr, ointr, arg) 1867 1.7.2.2 bouyer void *addr; 1868 1.7.2.2 bouyer int flags; 1869 1.7.2.2 bouyer void (*iintr)__P((void *, int)); 1870 1.7.2.2 bouyer void (*ointr)__P((void *)); 1871 1.7.2.2 bouyer void *arg; 1872 1.7.2.2 bouyer { 1873 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1874 1.7.2.2 bouyer u_int32_t mem; 1875 1.7.2.2 bouyer 1876 1.7.2.2 bouyer DPRINTF(("midi_open\n")); 1877 1.7.2.2 bouyer sc->sc_iintr = iintr; 1878 1.7.2.2 bouyer sc->sc_ointr = ointr; 1879 1.7.2.2 bouyer sc->sc_arg = arg; 1880 1.7.2.2 bouyer 1881 1.7.2.2 bouyer /* midi interrupt enable */ 1882 1.7.2.2 bouyer mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1883 1.7.2.2 bouyer mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1884 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_MIDCR, mem); 1885 1.7.2.2 bouyer #ifdef CS4280_DEBUG 1886 1.7.2.2 bouyer if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1887 1.7.2.2 bouyer DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1888 1.7.2.2 bouyer return(EINVAL); 1889 1.7.2.2 bouyer } 1890 1.7.2.2 bouyer DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1891 1.7.2.2 bouyer #endif 1892 1.7.2.2 bouyer return (0); 1893 1.7.2.2 bouyer } 1894 1.7.2.2 bouyer 1895 1.7.2.2 bouyer void 1896 1.7.2.2 bouyer cs4280_midi_close(addr) 1897 1.7.2.2 bouyer void *addr; 1898 1.7.2.2 bouyer { 1899 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1900 1.7.2.2 bouyer u_int32_t mem; 1901 1.7.2.2 bouyer 1902 1.7.2.2 bouyer DPRINTF(("midi_close\n")); 1903 1.7.2.2 bouyer mem = BA0READ4(sc, CS4280_MIDCR); 1904 1.7.2.2 bouyer mem &= ~MIDCR_MASK; 1905 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_MIDCR, mem); 1906 1.7.2.2 bouyer 1907 1.7.2.2 bouyer sc->sc_iintr = 0; 1908 1.7.2.2 bouyer sc->sc_ointr = 0; 1909 1.7.2.2 bouyer } 1910 1.7.2.2 bouyer 1911 1.7.2.2 bouyer int 1912 1.7.2.2 bouyer cs4280_midi_output(addr, d) 1913 1.7.2.2 bouyer void *addr; 1914 1.7.2.2 bouyer int d; 1915 1.7.2.2 bouyer { 1916 1.7.2.2 bouyer struct cs4280_softc *sc = addr; 1917 1.7.2.2 bouyer u_int32_t mem; 1918 1.7.2.2 bouyer int x; 1919 1.7.2.2 bouyer 1920 1.7.2.2 bouyer for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1921 1.7.2.2 bouyer if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1922 1.7.2.2 bouyer mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1923 1.7.2.2 bouyer mem |= d & MIDWP_MASK; 1924 1.7.2.2 bouyer DPRINTFN(5,("midi_output d=0x%08x",d)); 1925 1.7.2.2 bouyer BA0WRITE4(sc, CS4280_MIDWP, mem); 1926 1.7.2.2 bouyer #ifdef DIAGNOSTIC 1927 1.7.2.2 bouyer if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1928 1.7.2.2 bouyer DPRINTF(("Bad write data: %d %d", 1929 1.7.2.2 bouyer mem, BA0READ4(sc, CS4280_MIDWP))); 1930 1.7.2.2 bouyer return(EIO); 1931 1.7.2.2 bouyer } 1932 1.7.2.2 bouyer #endif 1933 1.7.2.2 bouyer return (0); 1934 1.7.2.2 bouyer } 1935 1.7.2.2 bouyer delay(MIDI_BUSY_DELAY); 1936 1.7.2.2 bouyer } 1937 1.7.2.2 bouyer return (EIO); 1938 1.7.2.2 bouyer } 1939 1.7.2.2 bouyer 1940 1.7.2.2 bouyer void 1941 1.7.2.2 bouyer cs4280_midi_getinfo(addr, mi) 1942 1.7.2.2 bouyer void *addr; 1943 1.7.2.2 bouyer struct midi_info *mi; 1944 1.7.2.2 bouyer { 1945 1.7.2.2 bouyer mi->name = "CS4280 MIDI UART"; 1946 1.7.2.2 bouyer mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1947 1.7.2.2 bouyer } 1948 1.7.2.2 bouyer 1949 1.7.2.2 bouyer #endif 1950
Indexes created Fri Oct 03 02:09:57 GMT 2025