cs4280.c revision 1.1.2.1
1 /* $NetBSD: cs4280.c,v 1.1.2.1 1999/12/27 18:35:14 wrstuden Exp $ */ 2 /* $Tera: cs4280.c,v 1.24 1999/12/13 15:24:04 tacha Exp $ */ 3 4 /* 5 * Copyright (c) 1999 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Cirrus Logic CS4280 (and maybe CS461x) driver. 36 * Data sheets can be found 37 * http://www.cirrus.com/ftp/pubs/4280.pdf 38 * http://www.cirrus.com/ftp/pubs/4297.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 41 */ 42 43 /* 44 * TODO 45 * Implement MIDI 46 * Joystick support 47 */ 48 49 #ifdef CS4280_DEBUG 50 #define MIDI_READY 51 #endif 52 53 #ifdef MIDI_READY 54 #include "midi.h" 55 #endif 56 57 #if defined(CS4280_DEBUG) 58 #define DPRINTF(x) if (cs4280debug) printf x 59 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 60 int cs4280debug = 0; 61 #else 62 #define DPRINTF(x) 63 #define DPRINTFN(n,x) 64 #endif 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/fcntl.h> 70 #include <sys/malloc.h> 71 #include <sys/device.h> 72 #include <sys/types.h> 73 #include <sys/systm.h> 74 75 #include <dev/pci/pcidevs.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/cs4280reg.h> 78 #include <dev/pci/cs4280_image.h> 79 80 #include <sys/audioio.h> 81 #include <dev/audio_if.h> 82 #include <dev/midi_if.h> 83 #include <dev/mulaw.h> 84 #include <dev/auconv.h> 85 #include <dev/ic/ac97.h> 86 87 #include <machine/bus.h> 88 #include <machine/bswap.h> 89 90 #define CSCC_PCI_BA0 0x10 91 #define CSCC_PCI_BA1 0x14 92 93 struct cs4280_dma { 94 bus_dmamap_t map; 95 caddr_t addr; /* real dma buffer */ 96 caddr_t dum; /* dummy buffer for audio driver */ 97 bus_dma_segment_t segs[1]; 98 int nsegs; 99 size_t size; 100 struct cs4280_dma *next; 101 }; 102 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 103 #define BUFADDR(p) ((void *)((p)->dum)) 104 #define KERNADDR(p) ((void *)((p)->addr)) 105 106 /* 107 * Software state 108 */ 109 struct cs4280_softc { 110 struct device sc_dev; 111 112 pci_intr_handle_t * sc_ih; 113 114 /* I/O (BA0) */ 115 bus_space_tag_t ba0t; 116 bus_space_handle_t ba0h; 117 118 /* BA1 */ 119 bus_space_tag_t ba1t; 120 bus_space_handle_t ba1h; 121 122 /* DMA */ 123 bus_dma_tag_t sc_dmatag; 124 struct cs4280_dma *sc_dmas; 125 126 void (*sc_pintr)(void *); /* dma completion intr handler */ 127 void *sc_parg; /* arg for sc_intr() */ 128 char *sc_ps, *sc_pe, *sc_pn; 129 int sc_pcount; 130 int sc_pi; 131 struct cs4280_dma *sc_pdma; 132 char *sc_pbuf; 133 #ifdef DIAGNOSTIC 134 char sc_prun; 135 #endif 136 137 void (*sc_rintr)(void *); /* dma completion intr handler */ 138 void *sc_rarg; /* arg for sc_intr() */ 139 char *sc_rs, *sc_re, *sc_rn; 140 int sc_rcount; 141 int sc_ri; 142 struct cs4280_dma *sc_rdma; 143 char *sc_rbuf; 144 int sc_rparam; /* record format */ 145 #ifdef DIAGNOSTIC 146 char sc_rrun; 147 #endif 148 149 #if NMIDI > 0 150 void (*sc_iintr)(void *, int); /* midi input ready handler */ 151 void (*sc_ointr)(void *); /* midi output ready handler */ 152 void *sc_arg; 153 #endif 154 155 u_int32_t pctl; 156 u_int32_t cctl; 157 158 struct ac97_codec_if *codec_if; 159 struct ac97_host_if host_if; 160 161 char sc_suspend; 162 void *sc_powerhook; /* Power Hook */ 163 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 164 }; 165 166 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 167 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 168 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 169 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 170 171 int cs4280_match __P((struct device *, struct cfdata *, void *)); 172 void cs4280_attach __P((struct device *, struct device *, void *)); 173 int cs4280_intr __P((void *)); 174 void cs4280_reset __P((void *)); 175 int cs4280_download_image __P((struct cs4280_softc *)); 176 177 int cs4280_download(struct cs4280_softc *, u_int32_t *, u_int32_t, u_int32_t); 178 int cs4280_allocmem __P((struct cs4280_softc *, size_t, size_t, 179 struct cs4280_dma *)); 180 int cs4280_freemem __P((struct cs4280_softc *, struct cs4280_dma *)); 181 182 #ifdef CS4280_DEBUG 183 int cs4280_check_images __P((struct cs4280_softc *)); 184 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 185 u_int32_t); 186 #endif 187 188 struct cfattach clcs_ca = { 189 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 190 }; 191 192 void cs4280_init __P((struct cs4280_softc *, int)); 193 int cs4280_open __P((void *, int)); 194 void cs4280_close __P((void *)); 195 196 int cs4280_query_encoding __P((void *, struct audio_encoding *)); 197 int cs4280_set_params __P((void *, int, int, struct audio_params *, struct audio_params *)); 198 int cs4280_round_blocksize __P((void *, int)); 199 200 int cs4280_halt_output __P((void *)); 201 int cs4280_halt_input __P((void *)); 202 203 int cs4280_getdev __P((void *, struct audio_device *)); 204 205 int cs4280_mixer_set_port __P((void *, mixer_ctrl_t *)); 206 int cs4280_mixer_get_port __P((void *, mixer_ctrl_t *)); 207 int cs4280_query_devinfo __P((void *addr, mixer_devinfo_t *dip)); 208 void *cs4280_malloc __P((void *, int, size_t, int, int)); 209 void cs4280_free __P((void *, void *, int)); 210 size_t cs4280_round_buffersize __P((void *, int, size_t)); 211 int cs4280_mappage __P((void *, void *, int, int)); 212 int cs4280_get_props __P((void *)); 213 int cs4280_trigger_output __P((void *, void *, void *, int, void (*)(void *), 214 void *, struct audio_params *)); 215 int cs4280_trigger_input __P((void *, void *, void *, int, void (*)(void *), 216 void *, struct audio_params *)); 217 218 219 void cs4280_set_dac_rate __P((struct cs4280_softc *, int )); 220 void cs4280_set_adc_rate __P((struct cs4280_softc *, int )); 221 int cs4280_get_portnum_by_name __P((struct cs4280_softc *, char *, char *, 222 char *)); 223 int cs4280_src_wait __P((struct cs4280_softc *)); 224 int cs4280_attach_codec __P((void *sc, struct ac97_codec_if *)); 225 int cs4280_read_codec __P((void *sc, u_int8_t a, u_int16_t *d)); 226 int cs4280_write_codec __P((void *sc, u_int8_t a, u_int16_t d)); 227 void cs4280_reset_codec __P((void *sc)); 228 229 void cs4280_power __P((int, void *)); 230 231 #ifdef NEED_CLEAR_FIFOS 232 void cs4280_clear_fifos __P((struct cs4280_softc *)); 233 #endif 234 235 #if NMIDI > 0 236 void cs4280_midi_close __P((void*)); 237 void cs4280_midi_getinfo __P((void *, struct midi_info *)); 238 int cs4280_midi_open __P((void *, int, void (*)(void *, int), 239 void (*)(void *), void *)); 240 int cs4280_midi_output __P((void *, int)); 241 #endif 242 243 struct audio_hw_if cs4280_hw_if = { 244 cs4280_open, 245 cs4280_close, 246 NULL, 247 cs4280_query_encoding, 248 cs4280_set_params, 249 cs4280_round_blocksize, 250 NULL, 251 NULL, 252 NULL, 253 NULL, 254 NULL, 255 cs4280_halt_output, 256 cs4280_halt_input, 257 NULL, 258 cs4280_getdev, 259 NULL, 260 cs4280_mixer_set_port, 261 cs4280_mixer_get_port, 262 cs4280_query_devinfo, 263 cs4280_malloc, 264 cs4280_free, 265 cs4280_round_buffersize, 266 cs4280_mappage, 267 cs4280_get_props, 268 cs4280_trigger_output, 269 cs4280_trigger_input, 270 }; 271 272 #if NMIDI > 0 273 struct midi_hw_if cs4280_midi_hw_if = { 274 cs4280_midi_open, 275 cs4280_midi_close, 276 cs4280_midi_output, 277 cs4280_midi_getinfo, 278 0, 279 }; 280 #endif 281 282 283 284 struct audio_device cs4280_device = { 285 "CS4280", 286 "", 287 "cs4280" 288 }; 289 290 291 int 292 cs4280_match(parent, match, aux) 293 struct device *parent; 294 struct cfdata *match; 295 void *aux; 296 { 297 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 298 299 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 300 return (0); 301 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 302 #if 0 /* I can't confirm */ 303 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 304 #endif 305 306 ) { 307 return (1); 308 } 309 return (0); 310 } 311 312 int 313 cs4280_read_codec(sc_, add, data) 314 void *sc_; 315 u_int8_t add; 316 u_int16_t *data; 317 { 318 struct cs4280_softc *sc = sc_; 319 int n; 320 321 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 322 /* 323 * Make sure that there is not data sitting around from a preivous 324 * uncompleted access. 325 */ 326 BA0READ4(sc, CS4280_ACSDA); 327 328 /* Set up AC97 control registers. */ 329 BA0WRITE4(sc, CS4280_ACCAD, add); 330 BA0WRITE4(sc, CS4280_ACCDA, 0); 331 BA0WRITE4(sc, CS4280_ACCTL, 332 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 333 334 if (cs4280_src_wait(sc) < 0) { 335 printf("%s: AC97 read prob. (DCV!=0) for add=0x%0x\n", 336 sc->sc_dev.dv_xname, add); 337 return (1); 338 } 339 340 /* wait for valid status bit is active */ 341 n = 0; 342 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 343 delay(1); 344 while (++n > 1000) { 345 printf("%s: AC97 read fail (VSTS==0) for add=0x%0x\n", 346 sc->sc_dev.dv_xname, add); 347 return (1); 348 } 349 } 350 *data = BA0READ4(sc, CS4280_ACSDA); 351 DPRINTFN(5,("data=0x%04x\n", *data)); 352 return (0); 353 } 354 355 int 356 cs4280_write_codec(sc_, add, data) 357 void *sc_; 358 u_int8_t add; 359 u_int16_t data; 360 { 361 struct cs4280_softc *sc = sc_; 362 363 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 364 BA0WRITE4(sc, CS4280_ACCAD, add); 365 BA0WRITE4(sc, CS4280_ACCDA, data); 366 BA0WRITE4(sc, CS4280_ACCTL, 367 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 368 369 if (cs4280_src_wait(sc) < 0) { 370 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 371 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 372 return (1); 373 } 374 return (0); 375 } 376 377 int 378 cs4280_src_wait(sc) 379 struct cs4280_softc *sc; 380 { 381 int n; 382 n = 0; 383 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 384 delay(1000); 385 while (++n > 1000) 386 return (-1); 387 } 388 return (0); 389 } 390 391 392 void 393 cs4280_set_adc_rate(sc, rate) 394 struct cs4280_softc *sc; 395 int rate; 396 { 397 /* calculate capture rate: 398 * 399 * capture_coefficient_increment = -round(rate*128*65536/48000; 400 * capture_phase_increment = floor(48000*65536*1024/rate); 401 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 402 * cy = floor(cx/200); 403 * capture_sample_rate_correction = cx - 200*cy; 404 * capture_delay = ceil(24*48000/rate); 405 * capture_num_triplets = floor(65536*rate/24000); 406 * capture_group_length = 24000/GCD(rate, 24000); 407 * where GCD means "Greatest Common Divisor". 408 * 409 * capture_coefficient_increment, capture_phase_increment and 410 * capture_num_triplets are 32-bit signed quantities. 411 * capture_sample_rate_correction and capture_group_length are 412 * 16-bit signed quantities. 413 * capture_delay is a 14-bit unsigned quantity. 414 */ 415 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 416 u_int16_t csrc, cgl, cdlay; 417 418 /* XXX 419 * Even though, embedded_audio_spec says capture rate range 11025 to 420 * 48000, dhwiface.cpp says, 421 * 422 * "We can only decimate by up to a factor of 1/9th the hardware rate. 423 * Return an error if an attempt is made to stray outside that limit." 424 * 425 * so assume range as 48000/9 to 48000 426 */ 427 428 if (rate < 8000) 429 rate = 8000; 430 if (rate > 48000) 431 rate = 48000; 432 433 cx = rate << 16; 434 cci = cx / 48000; 435 cx -= cci * 48000; 436 cx <<= 7; 437 cci <<= 7; 438 cci += cx / 48000; 439 cci = - cci; 440 441 cx = 48000 << 16; 442 cpi = cx / rate; 443 cx -= cpi * rate; 444 cx <<= 10; 445 cpi <<= 10; 446 cy = cx / rate; 447 cpi += cy; 448 cx -= cy * rate; 449 450 cy = cx / 200; 451 csrc = cx - 200*cy; 452 453 cdlay = ((48000 * 24) + rate - 1) / rate; 454 #if 0 455 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 456 #endif 457 458 cnt = rate << 16; 459 cnt /= 24000; 460 461 cgl = 1; 462 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 463 if (((rate / tmp1) * tmp1) != rate) 464 cgl *= 2; 465 } 466 if (((rate / 3) * 3) != rate) 467 cgl *= 3; 468 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 469 if (((rate / tmp1) * tmp1) != rate) 470 cgl *= 5; 471 } 472 #if 0 473 /* XXX what manual says */ 474 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 475 tmp1 |= csrc<<16; 476 BA1WRITE4(sc, CS4280_CSRC, tmp1); 477 #else 478 /* suggested by cs461x.c (ALSA driver) */ 479 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 480 #endif 481 482 #if 0 483 /* I am confused. The sample rate calculation section says 484 * cci *is* 32-bit signed quantity but in the parameter description 485 * section, CCI only assigned 16bit. 486 * I believe size of the variable. 487 */ 488 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 489 tmp1 |= cci<<16; 490 BA1WRITE4(sc, CS4280_CCI, tmp1); 491 #else 492 BA1WRITE4(sc, CS4280_CCI, cci); 493 #endif 494 495 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 496 tmp1 |= cdlay <<18; 497 BA1WRITE4(sc, CS4280_CD, tmp1); 498 499 BA1WRITE4(sc, CS4280_CPI, cpi); 500 501 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 502 tmp1 |= cgl; 503 BA1WRITE4(sc, CS4280_CGL, tmp1); 504 505 BA1WRITE4(sc, CS4280_CNT, cnt); 506 507 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 508 tmp1 |= cgl; 509 BA1WRITE4(sc, CS4280_CGC, tmp1); 510 } 511 512 void 513 cs4280_set_dac_rate(sc, rate) 514 struct cs4280_softc *sc; 515 int rate; 516 { 517 /* 518 * playback rate may range from 8000Hz to 48000Hz 519 * 520 * play_phase_increment = floor(rate*65536*1024/48000) 521 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 522 * py=floor(px/200) 523 * play_sample_rate_correction = px - 200*py 524 * 525 * play_phase_increment is a 32bit signed quantity. 526 * play_sample_rate_correction is a 16bit signed quantity. 527 */ 528 int32_t ppi; 529 int16_t psrc; 530 u_int32_t px, py; 531 532 if (rate < 8000) 533 rate = 8000; 534 if (rate > 48000) 535 rate = 48000; 536 px = rate << 16; 537 ppi = px/48000; 538 px -= ppi*48000; 539 ppi <<= 10; 540 px <<= 10; 541 py = px / 48000; 542 ppi += py; 543 px -= py*48000; 544 py = px/200; 545 px -= py*200; 546 psrc = px; 547 #if 0 548 /* what manual says */ 549 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 550 BA1WRITE4(sc, CS4280_PSRC, 551 ( ((psrc<<16) & PSRC_MASK) | px )); 552 #else 553 /* suggested by cs461x.c (ALSA driver) */ 554 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 555 #endif 556 BA1WRITE4(sc, CS4280_PPI, ppi); 557 } 558 559 void 560 cs4280_attach(parent, self, aux) 561 struct device *parent; 562 struct device *self; 563 void *aux; 564 { 565 struct cs4280_softc *sc = (struct cs4280_softc *)self; 566 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 567 pci_chipset_tag_t pc = pa->pa_pc; 568 char const *intrstr; 569 pci_intr_handle_t ih; 570 pcireg_t csr; 571 char devinfo[256]; 572 mixer_ctrl_t ctl; 573 u_int32_t mem; 574 575 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 576 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 577 578 /* Map I/O register */ 579 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 580 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 581 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 582 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 583 return; 584 } 585 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 586 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 587 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 588 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 589 return; 590 } 591 592 sc->sc_dmatag = pa->pa_dmat; 593 594 /* Enable the device (set bus master flag) */ 595 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 596 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 597 csr | PCI_COMMAND_MASTER_ENABLE); 598 599 /* LATENCY_TIMER setting */ 600 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 601 if ( PCI_LATTIMER(mem) < 32 ) { 602 mem &= 0xffff00ff; 603 mem |= 0x00002000; 604 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 605 } 606 607 /* Map and establish the interrupt. */ 608 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 609 pa->pa_intrline, &ih)) { 610 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 611 return; 612 } 613 intrstr = pci_intr_string(pc, ih); 614 615 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 616 if (sc->sc_ih == NULL) { 617 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 618 if (intrstr != NULL) 619 printf(" at %s", intrstr); 620 printf("\n"); 621 return; 622 } 623 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 624 625 /* Initialization */ 626 cs4280_init(sc, 1); 627 628 /* AC 97 attachement */ 629 sc->host_if.arg = sc; 630 sc->host_if.attach = cs4280_attach_codec; 631 sc->host_if.read = cs4280_read_codec; 632 sc->host_if.write = cs4280_write_codec; 633 sc->host_if.reset = cs4280_reset_codec; 634 635 if (ac97_attach(&sc->host_if) != 0) { 636 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 637 return; 638 } 639 640 /* Turn mute off of DAC, CD and master volumes by default */ 641 ctl.type = AUDIO_MIXER_ENUM; 642 ctl.un.ord = 0; /* off */ 643 644 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 645 AudioNmaster, AudioNmute); 646 cs4280_mixer_set_port(sc, &ctl); 647 648 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 649 AudioNdac, AudioNmute); 650 cs4280_mixer_set_port(sc, &ctl); 651 652 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 653 AudioNcd, AudioNmute); 654 cs4280_mixer_set_port(sc, &ctl); 655 656 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 657 #if NMIDI > 0 658 /* Reset midi port */ 659 mem = BA0READ4(sc, CS4280_MIDCR) & 0xffffffc0; 660 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 661 662 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 663 #endif 664 sc->sc_suspend = PWR_RESUME; 665 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 666 } 667 668 int 669 cs4280_intr(p) 670 void *p; 671 { 672 /* 673 * XXX 674 * 675 * Since CS4280 has only 4kB dma buffer and 676 * interrupt occurs every 2kB block, I create dummy buffer 677 * which returns to audio driver and actual dma buffer 678 * using in DMA transfer. 679 * 680 * 681 * ring buffer in audio.c is pointed by BUFADDR 682 * <------ ring buffer size == 64kB ------> 683 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 684 * |= = = =|= = = =|= = = =|= = = =|= = = =| 685 * | | | | | | <- call audio_intp every 686 * sc->sc_[pr]_count time. 687 * 688 * actual dma buffer is pointed by KERNADDR 689 * <-> dma buffer size = 4kB 690 * |= =| 691 * 692 * 693 */ 694 struct cs4280_softc *sc = p; 695 u_int32_t intr, mem; 696 char * empty_dma; 697 698 intr = BA0READ4(sc, CS4280_HISR); 699 700 if ((intr & HISR_INTENA) == 0) { 701 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 702 return (0); 703 } 704 705 /* Playback Interrupt */ 706 if (intr & HISR_PINT) { 707 mem = BA1READ4(sc, CS4280_PFIE); 708 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 709 if (sc->sc_pintr) { 710 if ((sc->sc_pi%sc->sc_pcount) == 0) 711 sc->sc_pintr(sc->sc_parg); 712 } else { 713 printf("unexpected play intr\n"); 714 } 715 /* copy buffer */ 716 ++sc->sc_pi; 717 empty_dma = sc->sc_pdma->addr; 718 if (sc->sc_pi&1) 719 empty_dma += CS4280_ICHUNK; 720 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 721 sc->sc_pn += CS4280_ICHUNK; 722 if (sc->sc_pn >= sc->sc_pe) 723 sc->sc_pn = sc->sc_ps; 724 BA1WRITE4(sc, CS4280_PFIE, mem); 725 } 726 /* Capture Interrupt */ 727 if (intr & HISR_CINT) { 728 int i; 729 int16_t rdata; 730 731 mem = BA1READ4(sc, CS4280_CIE); 732 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 733 ++sc->sc_ri; 734 empty_dma = sc->sc_rdma->addr; 735 if ((sc->sc_ri&1) == 0) 736 empty_dma += CS4280_ICHUNK; 737 738 /* 739 * XXX 740 * I think this audio data conversion should be 741 * happend in upper layer, but I put this here 742 * since there is no conversion function available. 743 */ 744 switch(sc->sc_rparam) { 745 case CF_16BIT_STEREO: 746 /* just copy it */ 747 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 748 sc->sc_rn += CS4280_ICHUNK; 749 break; 750 case CF_16BIT_MONO: 751 for (i = 0; i < 512; i++) { 752 rdata = *((int16_t *)empty_dma)++>>1; 753 rdata += *((int16_t *)empty_dma)++>>1; 754 *((int16_t *)sc->sc_rn)++ = rdata; 755 } 756 break; 757 case CF_8BIT_STEREO: 758 for (i = 0; i < 512; i++) { 759 rdata = *((int16_t*)empty_dma)++; 760 *sc->sc_rn++ = rdata >> 8; 761 rdata = *((int16_t*)empty_dma)++; 762 *sc->sc_rn++ = rdata >> 8; 763 } 764 break; 765 case CF_8BIT_MONO: 766 for (i = 0; i < 512; i++) { 767 rdata = *((int16_t*)empty_dma)++ >>1; 768 rdata += *((int16_t*)empty_dma)++ >>1; 769 *sc->sc_rn++ = rdata >>8; 770 } 771 break; 772 default: 773 /* Should not reach here */ 774 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 775 776 } 777 if (sc->sc_rn >= sc->sc_re) 778 sc->sc_rn = sc->sc_rs; 779 BA1WRITE4(sc, CS4280_CIE, mem); 780 if (sc->sc_rintr) { 781 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 782 sc->sc_rintr(sc->sc_rarg); 783 } else { 784 printf("unexpected record intr\n"); 785 } 786 } 787 788 #if NMIDI > 0 789 /* Midi port Interrupt */ 790 if (intr & HISR_MIDI) { 791 u_int32_t data; 792 do { 793 mem = BA0READ4(sc, CS4280_MIDSR); 794 DPRINTF(("cs4280_intr HISR_MIDI: mem=0x%x\n", mem)); 795 if (!(mem & MIDSR_TBF)) { 796 if (sc->sc_ointr != NULL) { 797 DPRINTF(("call sc_ointr(%p)\n", 798 sc->sc_ointr)); 799 sc->sc_ointr(sc->sc_arg); 800 } 801 } 802 if (!(mem & MIDSR_RBE)) { 803 data = BA0READ4(sc, CS4280_MIDRP); 804 if (sc->sc_iintr != NULL) { 805 DPRINTF(("call sc_iintr(%p) data=0x" 806 "%x\n", sc->sc_iintr, data)); 807 sc->sc_iintr(sc->sc_arg, data); 808 } 809 } 810 } while ((mem & MIDSR_TBF) || !(mem & MIDSR_RBE)); 811 } 812 #endif 813 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 814 return (0); 815 } 816 817 818 /* Download Proceessor Code and Data image */ 819 820 int 821 cs4280_download(sc, src, offset, len) 822 struct cs4280_softc *sc; 823 u_int32_t *src; 824 u_int32_t offset, len; 825 { 826 u_int32_t ctr; 827 828 #ifdef CS4280_DEBUG 829 u_int32_t con, data; 830 u_int8_t c0,c1,c2,c3; 831 #endif 832 if ((offset&3) || (len&3)) { 833 return (-1); 834 } 835 len /= sizeof(u_int32_t); 836 for (ctr = 0; ctr < len; ctr++) { 837 /* XXX: 838 * I cannot confirm this is the right thing or not 839 * on BIG-ENDIAN machines. 840 */ 841 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 842 #ifdef CS4280_DEBUG 843 data = htole32(*(src+ctr)); 844 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 845 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 846 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 847 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 848 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 849 if (data != con ) { 850 printf("0x%06x: write=0x%08x read=0x%08x\n", 851 offset+ctr*4, data, con); 852 return (-1); 853 } 854 #endif 855 } 856 return (0); 857 } 858 859 int 860 cs4280_download_image(sc) 861 struct cs4280_softc *sc; 862 { 863 int idx, err; 864 u_int32_t offset = 0; 865 866 err = 0; 867 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 868 err = cs4280_download(sc, &BA1Struct.map[offset], 869 BA1Struct.memory[idx].offset, 870 BA1Struct.memory[idx].size); 871 if (err != 0) { 872 printf("%s: load_image failed at %d\n", 873 sc->sc_dev.dv_xname, idx); 874 return (-1); 875 } 876 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 877 } 878 return (err); 879 } 880 881 #ifdef CS4280_DEBUG 882 int 883 cs4280_checkimage(sc, src, offset, len) 884 struct cs4280_softc *sc; 885 u_int32_t *src; 886 u_int32_t offset, len; 887 { 888 u_int32_t ctr, data; 889 int err = 0; 890 891 if ((offset&3) || (len&3)) { 892 return -1; 893 } 894 len /= sizeof(u_int32_t); 895 for (ctr = 0; ctr < len; ctr++) { 896 /* I cannot confirm this is the right thing 897 * on BIG-ENDIAN machines 898 */ 899 data = BA1READ4(sc, offset+ctr*4); 900 if (data != htole32(*(src+ctr))) { 901 printf("0x%06x: 0x%08x(0x%08x)\n", 902 offset+ctr*4, data, *(src+ctr)); 903 *(src+ctr) = data; 904 ++err; 905 } 906 } 907 return (err); 908 } 909 910 int 911 cs4280_check_images(sc) 912 struct cs4280_softc *sc; 913 { 914 int idx, err; 915 u_int32_t offset = 0; 916 917 err = 0; 918 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 919 for (idx = 0; idx < 1; ++idx) { 920 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 921 BA1Struct.memory[idx].offset, 922 BA1Struct.memory[idx].size); 923 if (err != 0) { 924 printf("%s: check_image failed at %d\n", 925 sc->sc_dev.dv_xname, idx); 926 } 927 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 928 } 929 return (err); 930 } 931 932 #endif 933 934 int 935 cs4280_attach_codec(sc_, codec_if) 936 void *sc_; 937 struct ac97_codec_if *codec_if; 938 { 939 struct cs4280_softc *sc = sc_; 940 941 sc->codec_if = codec_if; 942 return (0); 943 } 944 945 void 946 cs4280_reset_codec(sc_) 947 void *sc_; 948 { 949 struct cs4280_softc *sc = sc_; 950 int n; 951 952 /* Reset codec */ 953 BA0WRITE4(sc, CS4280_ACCTL, 0); 954 delay(100); /* delay 100us */ 955 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 956 957 /* 958 * It looks like we do the following procedure, too 959 */ 960 961 /* Enable AC-link sync generation */ 962 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 963 delay(50*1000); /* XXX delay 50ms */ 964 965 /* Assert valid frame signal */ 966 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 967 968 /* Wait for valid AC97 input slot */ 969 n = 0; 970 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 971 delay(1000); 972 if (++n > 1000) { 973 printf("reset_codec: AC97 inputs slot ready timeout\n"); 974 return; 975 } 976 } 977 } 978 979 980 /* Processor Soft Reset */ 981 void 982 cs4280_reset(sc_) 983 void *sc_; 984 { 985 struct cs4280_softc *sc = sc_; 986 987 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 988 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 989 delay(100); 990 /* Clear RSTSP bit in SPCR */ 991 BA1WRITE4(sc, CS4280_SPCR, 0); 992 /* enable DMA reqest */ 993 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 994 } 995 996 int 997 cs4280_open(addr, flags) 998 void *addr; 999 int flags; 1000 { 1001 return (0); 1002 } 1003 1004 void 1005 cs4280_close(addr) 1006 void *addr; 1007 { 1008 struct cs4280_softc *sc = addr; 1009 1010 cs4280_halt_output(sc); 1011 cs4280_halt_input(sc); 1012 1013 sc->sc_pintr = 0; 1014 sc->sc_rintr = 0; 1015 } 1016 1017 int 1018 cs4280_query_encoding(addr, fp) 1019 void *addr; 1020 struct audio_encoding *fp; 1021 { 1022 switch (fp->index) { 1023 case 0: 1024 strcpy(fp->name, AudioEulinear); 1025 fp->encoding = AUDIO_ENCODING_ULINEAR; 1026 fp->precision = 8; 1027 fp->flags = 0; 1028 break; 1029 case 1: 1030 strcpy(fp->name, AudioEmulaw); 1031 fp->encoding = AUDIO_ENCODING_ULAW; 1032 fp->precision = 8; 1033 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1034 break; 1035 case 2: 1036 strcpy(fp->name, AudioEalaw); 1037 fp->encoding = AUDIO_ENCODING_ALAW; 1038 fp->precision = 8; 1039 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1040 break; 1041 case 3: 1042 strcpy(fp->name, AudioEslinear); 1043 fp->encoding = AUDIO_ENCODING_SLINEAR; 1044 fp->precision = 8; 1045 fp->flags = 0; 1046 break; 1047 case 4: 1048 strcpy(fp->name, AudioEslinear_le); 1049 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1050 fp->precision = 16; 1051 fp->flags = 0; 1052 break; 1053 case 5: 1054 strcpy(fp->name, AudioEulinear_le); 1055 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1056 fp->precision = 16; 1057 fp->flags = 0; 1058 break; 1059 case 6: 1060 strcpy(fp->name, AudioEslinear_be); 1061 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1062 fp->precision = 16; 1063 fp->flags = 0; 1064 break; 1065 case 7: 1066 strcpy(fp->name, AudioEulinear_be); 1067 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1068 fp->precision = 16; 1069 fp->flags = 0; 1070 break; 1071 default: 1072 return (EINVAL); 1073 } 1074 return (0); 1075 } 1076 1077 int 1078 cs4280_set_params(addr, setmode, usemode, play, rec) 1079 void *addr; 1080 int setmode, usemode; 1081 struct audio_params *play, *rec; 1082 { 1083 struct cs4280_softc *sc = addr; 1084 struct audio_params *p; 1085 int mode; 1086 1087 for (mode = AUMODE_RECORD; mode != -1; 1088 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1089 if ((setmode & mode) == 0) 1090 continue; 1091 1092 p = mode == AUMODE_PLAY ? play : rec; 1093 1094 if (p == play) { 1095 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1096 p->sample_rate, p->precision, p->channels)); 1097 /* play back data format may be 8- or 16-bit and 1098 * either stereo or mono. 1099 * playback rate may range from 8000Hz to 48000Hz 1100 */ 1101 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1102 (p->precision != 8 && p->precision != 16) || 1103 (p->channels != 1 && p->channels != 2) ) { 1104 return (EINVAL); 1105 } 1106 } else { 1107 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1108 p->sample_rate, p->precision, p->channels)); 1109 /* capture data format must be 16bit stereo 1110 * and sample rate range from 11025Hz to 48000Hz. 1111 * 1112 * XXX: it looks like to work with 8000Hz, 1113 * although data sheets say lower limit is 1114 * 11025 Hz. 1115 */ 1116 1117 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1118 (p->precision != 8 && p->precision != 16) || 1119 (p->channels != 1 && p->channels != 2) ) { 1120 return (EINVAL); 1121 } 1122 } 1123 p->factor = 1; 1124 p->sw_code = 0; 1125 1126 /* capturing data is slinear */ 1127 switch (p->encoding) { 1128 case AUDIO_ENCODING_SLINEAR_BE: 1129 if (mode == AUMODE_RECORD) { 1130 if (p->precision == 16) 1131 p->sw_code = swap_bytes; 1132 } 1133 break; 1134 case AUDIO_ENCODING_SLINEAR_LE: 1135 break; 1136 case AUDIO_ENCODING_ULINEAR_BE: 1137 if (mode == AUMODE_RECORD) { 1138 if (p->precision == 16) 1139 p->sw_code = change_sign16_swap_bytes_le; 1140 else 1141 p->sw_code = change_sign8; 1142 } 1143 break; 1144 case AUDIO_ENCODING_ULINEAR_LE: 1145 if (mode == AUMODE_RECORD) { 1146 if (p->precision == 16) 1147 p->sw_code = change_sign16_le; 1148 else 1149 p->sw_code = change_sign8; 1150 } 1151 break; 1152 case AUDIO_ENCODING_ULAW: 1153 if (mode == AUMODE_PLAY) { 1154 p->factor = 2; 1155 p->sw_code = mulaw_to_slinear16_le; 1156 } else { 1157 p->sw_code = slinear8_to_mulaw; 1158 } 1159 break; 1160 case AUDIO_ENCODING_ALAW: 1161 if (mode == AUMODE_PLAY) { 1162 p->factor = 2; 1163 p->sw_code = alaw_to_slinear16_le; 1164 } else { 1165 p->sw_code = slinear8_to_alaw; 1166 } 1167 break; 1168 default: 1169 return (EINVAL); 1170 } 1171 } 1172 1173 /* set sample rate */ 1174 cs4280_set_dac_rate(sc, play->sample_rate); 1175 cs4280_set_adc_rate(sc, rec->sample_rate); 1176 return (0); 1177 } 1178 1179 int 1180 cs4280_round_blocksize(hdl, blk) 1181 void *hdl; 1182 int blk; 1183 { 1184 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1185 } 1186 1187 size_t 1188 cs4280_round_buffersize(addr, direction, size) 1189 void *addr; 1190 int direction; 1191 size_t size; 1192 { 1193 /* although real dma buffer size is 4KB, 1194 * let the audio.c driver use a larger buffer. 1195 * ( suggested by Lennart Augustsson. ) 1196 */ 1197 return (size); 1198 } 1199 1200 int 1201 cs4280_get_props(hdl) 1202 void *hdl; 1203 { 1204 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1205 #ifdef notyet 1206 /* XXX 1207 * How can I mmap ? 1208 */ 1209 AUDIO_PROP_MMAP 1210 #endif 1211 1212 } 1213 1214 int 1215 cs4280_mixer_get_port(addr, cp) 1216 void *addr; 1217 mixer_ctrl_t *cp; 1218 { 1219 struct cs4280_softc *sc = addr; 1220 1221 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1222 } 1223 1224 int 1225 cs4280_mappage(addr, mem, off, prot) 1226 void *addr; 1227 void *mem; 1228 int off; 1229 int prot; 1230 { 1231 struct cs4280_softc *sc = addr; 1232 struct cs4280_dma *p; 1233 1234 if (off < 0) 1235 return (-1); 1236 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1237 ; 1238 if (!p) { 1239 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1240 return (-1); 1241 } 1242 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1243 off, prot, BUS_DMA_WAITOK)); 1244 } 1245 1246 1247 int 1248 cs4280_query_devinfo(addr, dip) 1249 void *addr; 1250 mixer_devinfo_t *dip; 1251 { 1252 struct cs4280_softc *sc = addr; 1253 1254 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1255 } 1256 1257 int 1258 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1259 struct cs4280_softc *sc; 1260 char *class, *device, *qualifier; 1261 { 1262 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1263 device, qualifier)); 1264 } 1265 1266 int 1267 cs4280_halt_output(addr) 1268 void *addr; 1269 { 1270 struct cs4280_softc *sc = addr; 1271 u_int32_t mem; 1272 1273 mem = BA1READ4(sc, CS4280_PCTL); 1274 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1275 #ifdef DIAGNOSTIC 1276 sc->sc_prun = 0; 1277 #endif 1278 return (0); 1279 } 1280 1281 int 1282 cs4280_halt_input(addr) 1283 void *addr; 1284 { 1285 struct cs4280_softc *sc = addr; 1286 u_int32_t mem; 1287 1288 mem = BA1READ4(sc, CS4280_CCTL); 1289 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1290 #ifdef DIAGNOSTIC 1291 sc->sc_rrun = 0; 1292 #endif 1293 return (0); 1294 } 1295 1296 int 1297 cs4280_getdev(addr, retp) 1298 void *addr; 1299 struct audio_device *retp; 1300 { 1301 *retp = cs4280_device; 1302 return (0); 1303 } 1304 1305 int 1306 cs4280_mixer_set_port(addr, cp) 1307 void *addr; 1308 mixer_ctrl_t *cp; 1309 { 1310 struct cs4280_softc *sc = addr; 1311 int val; 1312 1313 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1314 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1315 return (val); 1316 } 1317 1318 1319 int 1320 cs4280_freemem(sc, p) 1321 struct cs4280_softc *sc; 1322 struct cs4280_dma *p; 1323 { 1324 bus_dmamap_unload(sc->sc_dmatag, p->map); 1325 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1326 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1327 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1328 return (0); 1329 } 1330 1331 int 1332 cs4280_allocmem(sc, size, align, p) 1333 struct cs4280_softc *sc; 1334 size_t size; 1335 size_t align; 1336 struct cs4280_dma *p; 1337 { 1338 int error; 1339 1340 /* XXX */ 1341 p->size = size; 1342 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1343 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1344 &p->nsegs, BUS_DMA_NOWAIT); 1345 if (error) { 1346 printf("%s: unable to allocate dma, error=%d\n", 1347 sc->sc_dev.dv_xname, error); 1348 return (error); 1349 } 1350 1351 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1352 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1353 if (error) { 1354 printf("%s: unable to map dma, error=%d\n", 1355 sc->sc_dev.dv_xname, error); 1356 goto free; 1357 } 1358 1359 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1360 0, BUS_DMA_NOWAIT, &p->map); 1361 if (error) { 1362 printf("%s: unable to create dma map, error=%d\n", 1363 sc->sc_dev.dv_xname, error); 1364 goto unmap; 1365 } 1366 1367 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1368 BUS_DMA_NOWAIT); 1369 if (error) { 1370 printf("%s: unable to load dma map, error=%d\n", 1371 sc->sc_dev.dv_xname, error); 1372 goto destroy; 1373 } 1374 return (0); 1375 1376 destroy: 1377 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1378 unmap: 1379 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1380 free: 1381 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1382 return (error); 1383 } 1384 1385 1386 void * 1387 cs4280_malloc(addr, direction, size, pool, flags) 1388 void *addr; 1389 int direction; 1390 size_t size; 1391 int pool, flags; 1392 { 1393 struct cs4280_softc *sc = addr; 1394 struct cs4280_dma *p; 1395 caddr_t q; 1396 int error; 1397 1398 #if 0 1399 printf("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags); 1400 #endif 1401 q = malloc(size, pool, flags); 1402 if (!q) 1403 return (0); 1404 p = malloc(sizeof(*p), pool, flags); 1405 if (!p) { 1406 free(q,pool); 1407 return (0); 1408 } 1409 /* 1410 * cs4280 has fixed 4kB buffer 1411 */ 1412 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1413 1414 if (error) { 1415 free(q, pool); 1416 free(p, pool); 1417 return (0); 1418 } 1419 1420 p->next = sc->sc_dmas; 1421 sc->sc_dmas = p; 1422 p->dum = q; /* return to audio driver */ 1423 1424 return (p->dum); 1425 } 1426 1427 void 1428 cs4280_free(addr, ptr, pool) 1429 void *addr; 1430 void *ptr; 1431 int pool; 1432 { 1433 struct cs4280_softc *sc = addr; 1434 struct cs4280_dma **pp, *p; 1435 1436 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1437 if (BUFADDR(p) == ptr) { 1438 cs4280_freemem(sc, p); 1439 *pp = p->next; 1440 free(p->dum, pool); 1441 free(p, pool); 1442 return; 1443 } 1444 } 1445 } 1446 1447 int 1448 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1449 void *addr; 1450 void *start, *end; 1451 int blksize; 1452 void (*intr) __P((void *)); 1453 void *arg; 1454 struct audio_params *param; 1455 { 1456 struct cs4280_softc *sc = addr; 1457 u_int32_t pfie, pctl, mem, pdtc; 1458 struct cs4280_dma *p; 1459 1460 #ifdef DIAGNOSTIC 1461 if (sc->sc_prun) 1462 printf("cs4280_trigger_output: already running\n"); 1463 sc->sc_prun = 1; 1464 #endif 1465 1466 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1467 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1468 sc->sc_pintr = intr; 1469 sc->sc_parg = arg; 1470 1471 /* stop playback DMA */ 1472 mem = BA1READ4(sc, CS4280_PCTL); 1473 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1474 1475 /* setup PDTC */ 1476 pdtc = BA1READ4(sc, CS4280_PDTC); 1477 pdtc &= ~PDTC_MASK; 1478 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1479 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1480 1481 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1482 param->precision, param->factor, param->channels, 1483 param->encoding)); 1484 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1485 ; 1486 if (p == NULL) { 1487 printf("cs4280_trigger_output: bad addr %p\n", start); 1488 return (EINVAL); 1489 } 1490 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1491 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1492 "4kB align\n", DMAADDR(p)); 1493 return (EINVAL); 1494 } 1495 1496 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1497 sc->sc_ps = (char *)start; 1498 sc->sc_pe = (char *)end; 1499 sc->sc_pdma = p; 1500 sc->sc_pbuf = KERNADDR(p); 1501 sc->sc_pi = 0; 1502 sc->sc_pn = sc->sc_ps; 1503 if (blksize >= CS4280_DCHUNK) { 1504 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1505 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1506 ++sc->sc_pi; 1507 } else { 1508 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1509 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1510 } 1511 1512 /* initiate playback dma */ 1513 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1514 1515 /* set PFIE */ 1516 pfie = (BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK); 1517 1518 if (param->precision * param->factor == 8) 1519 pfie |= PFIE_8BIT; 1520 if (param->channels == 1) 1521 pfie |= PFIE_MONO; 1522 1523 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1524 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1525 pfie |= PFIE_SWAPPED; 1526 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1527 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1528 pfie |= PFIE_UNSIGNED; 1529 1530 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1531 1532 cs4280_set_dac_rate(sc, param->sample_rate); 1533 1534 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1535 pctl |= sc->pctl; 1536 BA1WRITE4(sc, CS4280_PCTL, pctl); 1537 return (0); 1538 } 1539 1540 int 1541 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1542 void *addr; 1543 void *start, *end; 1544 int blksize; 1545 void (*intr) __P((void *)); 1546 void *arg; 1547 struct audio_params *param; 1548 { 1549 struct cs4280_softc *sc = addr; 1550 u_int32_t cctl, cie; 1551 struct cs4280_dma *p; 1552 1553 #ifdef DIAGNOSTIC 1554 if (sc->sc_rrun) 1555 printf("cs4280_trigger_input: already running\n"); 1556 sc->sc_rrun = 1; 1557 #endif 1558 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1559 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1560 sc->sc_rintr = intr; 1561 sc->sc_rarg = arg; 1562 1563 sc->sc_ri = 0; 1564 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1565 sc->sc_rs = (char *)start; 1566 sc->sc_re = (char *)end; 1567 sc->sc_rn = sc->sc_rs; 1568 1569 /* setup format information for internal converter */ 1570 sc->sc_rparam = 0; 1571 if (param->precision == 8) { 1572 sc->sc_rparam += CF_8BIT; 1573 sc->sc_rcount <<= 1; 1574 } 1575 if (param->channels == 1) { 1576 sc->sc_rparam += CF_MONO; 1577 sc->sc_rcount <<= 1; 1578 } 1579 1580 /* stop capture DMA */ 1581 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1582 BA1WRITE4(sc, CS4280_CCTL, cctl); 1583 1584 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1585 ; 1586 if (!p) { 1587 printf("cs4280_trigger_input: bad addr %p\n", start); 1588 return (EINVAL); 1589 } 1590 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1591 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1592 "4kB align\n", DMAADDR(p)); 1593 return (EINVAL); 1594 } 1595 sc->sc_rdma = p; 1596 sc->sc_rbuf = KERNADDR(p); 1597 1598 /* initiate capture dma */ 1599 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1600 1601 /* set CIE */ 1602 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1603 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1604 1605 cs4280_set_adc_rate(sc, param->sample_rate); 1606 1607 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1608 cctl |= sc->cctl; 1609 BA1WRITE4(sc, CS4280_CCTL, cctl); 1610 return (0); 1611 } 1612 1613 void 1614 cs4280_init(sc, init) 1615 struct cs4280_softc *sc; 1616 int init; 1617 { 1618 int n; 1619 u_int32_t mem; 1620 1621 /* Start PLL out in known state */ 1622 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1623 /* Start serial ports out in known state */ 1624 BA0WRITE4(sc, CS4280_SERMC1, 0); 1625 1626 /* Specify type of CODEC */ 1627 /* XXX should no be here */ 1628 #define SERACC_CODEC_TYPE_1_03 1629 #ifdef SERACC_CODEC_TYPE_1_03 1630 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1631 #else 1632 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1633 #endif 1634 1635 /* Reset codec */ 1636 BA0WRITE4(sc, CS4280_ACCTL, 0); 1637 delay(100); /* delay 100us */ 1638 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1639 1640 /* Enable AC-link sync generation */ 1641 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN|ACCTL_RSTN); 1642 delay(50*1000); /* delay 50ms */ 1643 1644 /* Set the serial port timing configuration */ 1645 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1646 1647 /* Setup clock control */ 1648 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1649 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1650 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1651 1652 /* Power up the PLL */ 1653 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1654 delay(50*1000); /* delay 50ms */ 1655 1656 /* Turn on clock */ 1657 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE); 1658 1659 #ifdef NEED_CLEAR_FIFOS 1660 /* if we get beep sound, need clear fifo ? */ 1661 cs4280_clear_fifos(sc); 1662 #endif 1663 1664 /* Configure the serial port */ 1665 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1666 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1667 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1668 1669 /* Wait for CODEC ready */ 1670 n = 0; 1671 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY)) { 1672 delay(10); 1673 if (++n > 100) { 1674 printf("%s: codec ready timeout\n", 1675 sc->sc_dev.dv_xname); 1676 return; 1677 } 1678 } 1679 1680 /* Assert valid frame signal */ 1681 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM|ACCTL_ESYN|ACCTL_RSTN); 1682 1683 /* Wait for valid AC97 input slot */ 1684 n = 0; 1685 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 1686 delay(1000); 1687 if (++n > 1000) { 1688 printf("AC97 inputs slot ready timeout\n"); 1689 return; 1690 } 1691 } 1692 1693 /* Set AC97 output slot valid signals */ 1694 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1695 1696 /* reset the processor */ 1697 cs4280_reset(sc); 1698 1699 /* Download the image to the processor */ 1700 if (cs4280_download_image(sc) != 0) { 1701 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1702 return; 1703 } 1704 1705 /* Save playback parameter and then write zero. 1706 * this ensures that DMA doesn't immediately occur upon 1707 * starting the processor core 1708 */ 1709 mem = BA1READ4(sc, CS4280_PCTL); 1710 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1711 cs4280_halt_output(sc); 1712 1713 /* Save capture parameter and then write zero. 1714 * this ensures that DMA doesn't immediately occur upon 1715 * starting the processor core 1716 */ 1717 mem = BA1READ4(sc, CS4280_CCTL); 1718 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1719 cs4280_halt_input(sc); 1720 1721 /* Processor Startup Procedure */ 1722 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1723 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1724 1725 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1726 n = 0; 1727 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1728 delay(10); 1729 if (++n > 1000) { 1730 printf("SPCR 1->0 transition timeout\n"); 1731 return; 1732 } 1733 } 1734 1735 n = 0; 1736 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1737 delay(10); 1738 if (++n > 1000) { 1739 printf("SPCS 0->1 transition timeout\n"); 1740 return; 1741 } 1742 } 1743 /* Processor is now running !!! */ 1744 1745 /* Setup volume */ 1746 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1747 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1748 1749 /* Interrupt enable */ 1750 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1751 1752 /* playback interrupt enable */ 1753 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1754 mem |= PFIE_PI_ENABLE; 1755 BA1WRITE4(sc, CS4280_PFIE, mem); 1756 /* capture interrupt enable */ 1757 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1758 mem |= CIE_CI_ENABLE; 1759 BA1WRITE4(sc, CS4280_CIE, mem); 1760 1761 } 1762 1763 void 1764 cs4280_power(why, v) 1765 int why; 1766 void *v; 1767 { 1768 struct cs4280_softc *sc = (struct cs4280_softc *)v; 1769 int i; 1770 1771 DPRINTF(("%s: cs4280_power why=%d\n", 1772 sc->sc_dev.dv_xname, why)); 1773 if (why != PWR_RESUME) { 1774 sc->sc_suspend = why; 1775 1776 cs4280_halt_output(sc); 1777 cs4280_halt_input(sc); 1778 /* Save AC97 registers */ 1779 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1780 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1781 continue; 1782 cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i>>2]); 1783 } 1784 /* should I powerdown here ? */ 1785 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1786 } else { 1787 if (sc->sc_suspend == PWR_RESUME) { 1788 printf("cs4280_power: odd, resume without suspend.\n"); 1789 sc->sc_suspend = why; 1790 return; 1791 } 1792 sc->sc_suspend = why; 1793 cs4280_init(sc, 0); 1794 cs4280_reset_codec(sc); 1795 cs4280_write_codec(sc, AC97_REG_RESET, 0); /* Cold AC'97 Reset */ 1796 /* restore ac97 registers */ 1797 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1798 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1799 continue; 1800 cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]); 1801 } 1802 } 1803 } 1804 1805 #ifdef NEED_CLEAR_FIFOS 1806 void 1807 cs4280_clear_fifos(sc) 1808 struct cs4280_softc *sc; 1809 { 1810 int pd = 0, cnt, n; 1811 u_int32_t mem; 1812 1813 /* 1814 * If device power down, power up the device and keep power down 1815 * state. 1816 */ 1817 mem = BA0READ4(sc, CS4280_CLKCR1); 1818 if (!(mem & CLKCR1_SWCE)) { 1819 printf("cs4280_clear_fifo: power down found.\n"); 1820 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1821 pd = 1; 1822 } 1823 BA0WRITE4(sc, CS4280_SERBWP, 0); 1824 for (cnt = 0; cnt < 256; cnt++) { 1825 n = 0; 1826 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1827 delay(1000); 1828 if (++n > 1000) { 1829 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1830 break; 1831 } 1832 } 1833 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1834 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1835 } 1836 if (pd) 1837 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1838 } 1839 #endif 1840 1841 #if NMIDI > 0 1842 int 1843 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1844 void *addr; 1845 int flags; 1846 void (*iintr)__P((void *, int)); 1847 void (*ointr)__P((void *)); 1848 void *arg; 1849 { 1850 struct cs4280_softc *sc = addr; 1851 u_int32_t mem; 1852 1853 DPRINTF(("midi_open\n")); 1854 sc->sc_iintr = iintr; 1855 sc->sc_ointr = ointr; 1856 sc->sc_arg = arg; 1857 1858 mem = BA0READ4(sc, CS4280_MIDCR); 1859 mem &= ~MIDCR_MASK; 1860 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1861 BA0WRITE4(sc, CS4280_MIDCR, mem); 1862 1863 return (0); 1864 } 1865 1866 void 1867 cs4280_midi_close(addr) 1868 void *addr; 1869 { 1870 struct cs4280_softc *sc = addr; 1871 u_int32_t mem; 1872 1873 DPRINTF(("midi_close\n")); 1874 mem = BA0READ4(sc, CS4280_MIDCR); 1875 mem &= MIDCR_MASK; 1876 BA0WRITE4(sc, CS4280_MIDCR, mem); 1877 1878 sc->sc_iintr = 0; 1879 sc->sc_ointr = 0; 1880 } 1881 1882 int 1883 cs4280_midi_output(addr, d) 1884 void *addr; 1885 int d; 1886 { 1887 struct cs4280_softc *sc = addr; 1888 u_int32_t mem; 1889 int x; 1890 1891 DPRINTF(("midi_output d=0x%08x\n",d)); 1892 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1893 if (!(BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF)) { 1894 mem = BA0READ4(sc, CS4280_MIDWP); 1895 mem &= ~MIDWP_MASK; 1896 mem |= d; 1897 BA0WRITE4(sc, CS4280_MIDWP, mem); 1898 return (0); 1899 } 1900 delay(MIDI_BUSY_DELAY); 1901 } 1902 return (EIO); 1903 } 1904 1905 void 1906 cs4280_midi_getinfo(addr, mi) 1907 void *addr; 1908 struct midi_info *mi; 1909 { 1910 mi->name = "CS4280 MIDI UART"; 1911 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1912 } 1913 1914 #endif 1915
Indexes created Thu Oct 02 14:10:14 GMT 2025