cs4280.c revision 1.15.2.2
1 /* $NetBSD: cs4280.c,v 1.15.2.2 2001/10/08 20:11:11 nathanw Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include "midi.h" 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/fcntl.h> 60 #include <sys/malloc.h> 61 #include <sys/device.h> 62 #include <sys/proc.h> 63 #include <sys/types.h> 64 #include <sys/systm.h> 65 66 #include <dev/pci/pcidevs.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/cs4280reg.h> 69 #include <dev/pci/cs4280_image.h> 70 #include <dev/pci/cs428xreg.h> 71 72 #include <sys/audioio.h> 73 #include <dev/audio_if.h> 74 #include <dev/midi_if.h> 75 #include <dev/mulaw.h> 76 #include <dev/auconv.h> 77 78 #include <dev/ic/ac97reg.h> 79 #include <dev/ic/ac97var.h> 80 81 #include <dev/pci/cs428x.h> 82 83 #include <machine/bus.h> 84 #include <machine/bswap.h> 85 86 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 87 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 88 89 /* IF functions for audio driver */ 90 int cs4280_match(struct device *, struct cfdata *, void *); 91 void cs4280_attach(struct device *, struct device *, void *); 92 int cs4280_intr(void *); 93 int cs4280_query_encoding(void *, struct audio_encoding *); 94 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 95 int cs4280_halt_output(void *); 96 int cs4280_halt_input(void *); 97 int cs4280_getdev(void *, struct audio_device *); 98 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 99 void *, struct audio_params *); 100 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 101 void *, struct audio_params *); 102 103 void cs4280_reset_codec(void *); 104 105 /* For PowerHook */ 106 void cs4280_power(int, void *); 107 108 /* Internal functions */ 109 void cs4280_set_adc_rate(struct cs428x_softc *, int ); 110 void cs4280_set_dac_rate(struct cs428x_softc *, int ); 111 int cs4280_download(struct cs428x_softc *, const u_int32_t *, u_int32_t, u_int32_t); 112 int cs4280_download_image(struct cs428x_softc *); 113 void cs4280_reset(void *); 114 int cs4280_get_portnum_by_name(struct cs428x_softc *, char *, char *, char *); 115 int cs4280_init(struct cs428x_softc *, int); 116 void cs4280_clear_fifos(struct cs428x_softc *); 117 118 #if CS4280_DEBUG > 10 119 /* Thease two function is only for checking image loading is succeeded or not. */ 120 int cs4280_check_images(struct cs428x_softc *); 121 int cs4280_checkimage(struct cs428x_softc *, u_int32_t *, u_int32_t, u_int32_t); 122 #endif 123 124 struct audio_hw_if cs4280_hw_if = { 125 cs428x_open, 126 cs428x_close, 127 NULL, 128 cs4280_query_encoding, 129 cs4280_set_params, 130 cs428x_round_blocksize, 131 NULL, 132 NULL, 133 NULL, 134 NULL, 135 NULL, 136 cs4280_halt_output, 137 cs4280_halt_input, 138 NULL, 139 cs4280_getdev, 140 NULL, 141 cs428x_mixer_set_port, 142 cs428x_mixer_get_port, 143 cs428x_query_devinfo, 144 cs428x_malloc, 145 cs428x_free, 146 cs428x_round_buffersize, 147 cs428x_mappage, 148 cs428x_get_props, 149 cs4280_trigger_output, 150 cs4280_trigger_input, 151 NULL, 152 }; 153 154 #if NMIDI > 0 155 /* Midi Interface */ 156 int cs4280_midi_open(void *, int, void (*)(void *, int), 157 void (*)(void *), void *); 158 void cs4280_midi_close(void*); 159 int cs4280_midi_output(void *, int); 160 void cs4280_midi_getinfo(void *, struct midi_info *); 161 162 struct midi_hw_if cs4280_midi_hw_if = { 163 cs4280_midi_open, 164 cs4280_midi_close, 165 cs4280_midi_output, 166 cs4280_midi_getinfo, 167 0, 168 }; 169 #endif 170 171 struct cfattach clcs_ca = { 172 sizeof(struct cs428x_softc), cs4280_match, cs4280_attach 173 }; 174 175 struct audio_device cs4280_device = { 176 "CS4280", 177 "", 178 "cs4280" 179 }; 180 181 182 int 183 cs4280_match(parent, match, aux) 184 struct device *parent; 185 struct cfdata *match; 186 void *aux; 187 { 188 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 189 190 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 191 return 0; 192 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 193 #if 0 /* I can't confirm */ 194 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 195 #endif 196 ) 197 return 1; 198 return 0; 199 } 200 201 void 202 cs4280_attach(parent, self, aux) 203 struct device *parent; 204 struct device *self; 205 void *aux; 206 { 207 struct cs428x_softc *sc = (struct cs428x_softc *)self; 208 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 209 pci_chipset_tag_t pc = pa->pa_pc; 210 char const *intrstr; 211 pci_intr_handle_t ih; 212 pcireg_t reg; 213 char devinfo[256]; 214 mixer_ctrl_t ctl; 215 u_int32_t mem; 216 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 217 218 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 219 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 220 221 /* Map I/O register */ 222 if (pci_mapreg_map(pa, PCI_BA0, 223 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 224 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 225 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 226 return; 227 } 228 if (pci_mapreg_map(pa, PCI_BA1, 229 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 230 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 231 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 232 return; 233 } 234 235 sc->sc_dmatag = pa->pa_dmat; 236 237 /* Check and set Power State */ 238 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 239 &pci_pwrmgmt_cap_reg, 0)) { 240 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 241 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 242 pci_pwrmgmt_csr_reg); 243 DPRINTF(("%s: Power State is %d\n", 244 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 245 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 246 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 247 (reg & ~PCI_PMCSR_STATE_MASK) | 248 PCI_PMCSR_STATE_D0); 249 } 250 } 251 252 /* Enable the device (set bus master flag) */ 253 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 254 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 255 reg | PCI_COMMAND_MASTER_ENABLE); 256 257 /* LATENCY_TIMER setting */ 258 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 259 if ( PCI_LATTIMER(mem) < 32 ) { 260 mem &= 0xffff00ff; 261 mem |= 0x00002000; 262 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 263 } 264 265 /* Map and establish the interrupt. */ 266 if (pci_intr_map(pa, &ih)) { 267 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 268 return; 269 } 270 intrstr = pci_intr_string(pc, ih); 271 272 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 273 if (sc->sc_ih == NULL) { 274 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 275 if (intrstr != NULL) 276 printf(" at %s", intrstr); 277 printf("\n"); 278 return; 279 } 280 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 281 282 /* Initialization */ 283 if(cs4280_init(sc, 1) != 0) 284 return; 285 286 sc->type = TYPE_CS4280; 287 sc->halt_input = cs4280_halt_input; 288 sc->halt_output = cs4280_halt_output; 289 290 /* setup buffer related parameters */ 291 sc->dma_size = CS4280_DCHUNK; 292 sc->dma_align = CS4280_DALIGN; 293 sc->hw_blocksize = CS4280_ICHUNK; 294 295 /* AC 97 attachment */ 296 sc->host_if.arg = sc; 297 sc->host_if.attach = cs428x_attach_codec; 298 sc->host_if.read = cs428x_read_codec; 299 sc->host_if.write = cs428x_write_codec; 300 sc->host_if.reset = cs4280_reset_codec; 301 if (ac97_attach(&sc->host_if) != 0) { 302 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 303 return; 304 } 305 306 /* Turn mute off of DAC, CD and master volumes by default */ 307 ctl.type = AUDIO_MIXER_ENUM; 308 ctl.un.ord = 0; /* off */ 309 310 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 311 AudioNmaster, AudioNmute); 312 cs428x_mixer_set_port(sc, &ctl); 313 314 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 315 AudioNdac, AudioNmute); 316 cs428x_mixer_set_port(sc, &ctl); 317 318 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 319 AudioNcd, AudioNmute); 320 cs428x_mixer_set_port(sc, &ctl); 321 322 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 323 324 #if NMIDI > 0 325 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 326 #endif 327 328 sc->sc_suspend = PWR_RESUME; 329 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 330 } 331 332 /* Interrupt handling function */ 333 int 334 cs4280_intr(p) 335 void *p; 336 { 337 /* 338 * XXX 339 * 340 * Since CS4280 has only 4kB dma buffer and 341 * interrupt occurs every 2kB block, I create dummy buffer 342 * which returns to audio driver and actual dma buffer 343 * using in DMA transfer. 344 * 345 * 346 * ring buffer in audio.c is pointed by BUFADDR 347 * <------ ring buffer size == 64kB ------> 348 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 349 * |= = = =|= = = =|= = = =|= = = =|= = = =| 350 * | | | | | | <- call audio_intp every 351 * sc->sc_[pr]_count time. 352 * 353 * actual dma buffer is pointed by KERNADDR 354 * <-> dma buffer size = 4kB 355 * |= =| 356 * 357 * 358 */ 359 struct cs428x_softc *sc = p; 360 u_int32_t intr, mem; 361 char * empty_dma; 362 int handled = 0; 363 364 /* grab interrupt register then clear it */ 365 intr = BA0READ4(sc, CS4280_HISR); 366 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 367 368 /* Playback Interrupt */ 369 if (intr & HISR_PINT) { 370 handled = 1; 371 mem = BA1READ4(sc, CS4280_PFIE); 372 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 373 if (sc->sc_pintr) { 374 if ((sc->sc_pi%sc->sc_pcount) == 0) 375 sc->sc_pintr(sc->sc_parg); 376 } else { 377 printf("unexpected play intr\n"); 378 } 379 /* copy buffer */ 380 ++sc->sc_pi; 381 empty_dma = sc->sc_pdma->addr; 382 if (sc->sc_pi&1) 383 empty_dma += sc->hw_blocksize; 384 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 385 sc->sc_pn += sc->hw_blocksize; 386 if (sc->sc_pn >= sc->sc_pe) 387 sc->sc_pn = sc->sc_ps; 388 BA1WRITE4(sc, CS4280_PFIE, mem); 389 } 390 /* Capture Interrupt */ 391 if (intr & HISR_CINT) { 392 int i; 393 int16_t rdata; 394 395 handled = 1; 396 mem = BA1READ4(sc, CS4280_CIE); 397 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 398 ++sc->sc_ri; 399 empty_dma = sc->sc_rdma->addr; 400 if ((sc->sc_ri&1) == 0) 401 empty_dma += sc->hw_blocksize; 402 403 /* 404 * XXX 405 * I think this audio data conversion should be 406 * happend in upper layer, but I put this here 407 * since there is no conversion function available. 408 */ 409 switch(sc->sc_rparam) { 410 case CF_16BIT_STEREO: 411 /* just copy it */ 412 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 413 sc->sc_rn += sc->hw_blocksize; 414 break; 415 case CF_16BIT_MONO: 416 for (i = 0; i < 512; i++) { 417 rdata = *((int16_t *)empty_dma)++>>1; 418 rdata += *((int16_t *)empty_dma)++>>1; 419 *((int16_t *)sc->sc_rn)++ = rdata; 420 } 421 break; 422 case CF_8BIT_STEREO: 423 for (i = 0; i < 512; i++) { 424 rdata = *((int16_t*)empty_dma)++; 425 *sc->sc_rn++ = rdata >> 8; 426 rdata = *((int16_t*)empty_dma)++; 427 *sc->sc_rn++ = rdata >> 8; 428 } 429 break; 430 case CF_8BIT_MONO: 431 for (i = 0; i < 512; i++) { 432 rdata = *((int16_t*)empty_dma)++ >>1; 433 rdata += *((int16_t*)empty_dma)++ >>1; 434 *sc->sc_rn++ = rdata >>8; 435 } 436 break; 437 default: 438 /* Should not reach here */ 439 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 440 } 441 if (sc->sc_rn >= sc->sc_re) 442 sc->sc_rn = sc->sc_rs; 443 BA1WRITE4(sc, CS4280_CIE, mem); 444 if (sc->sc_rintr) { 445 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 446 sc->sc_rintr(sc->sc_rarg); 447 } else { 448 printf("unexpected record intr\n"); 449 } 450 } 451 452 #if NMIDI > 0 453 /* Midi port Interrupt */ 454 if (intr & HISR_MIDI) { 455 int data; 456 457 handled = 1; 458 DPRINTF(("i: %d: ", 459 BA0READ4(sc, CS4280_MIDSR))); 460 /* Read the received data */ 461 while ((sc->sc_iintr != NULL) && 462 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 463 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 464 DPRINTF(("r:%x\n",data)); 465 sc->sc_iintr(sc->sc_arg, data); 466 } 467 468 /* Write the data */ 469 #if 1 470 /* XXX: 471 * It seems "Transmit Buffer Full" never activate until EOI 472 * is deliverd. Shall I throw EOI top of this routine ? 473 */ 474 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 475 DPRINTF(("w: ")); 476 if (sc->sc_ointr != NULL) 477 sc->sc_ointr(sc->sc_arg); 478 } 479 #else 480 while ((sc->sc_ointr != NULL) && 481 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 482 DPRINTF(("w: ")); 483 sc->sc_ointr(sc->sc_arg); 484 } 485 #endif 486 DPRINTF(("\n")); 487 } 488 #endif 489 490 return handled; 491 } 492 493 int 494 cs4280_query_encoding(addr, fp) 495 void *addr; 496 struct audio_encoding *fp; 497 { 498 switch (fp->index) { 499 case 0: 500 strcpy(fp->name, AudioEulinear); 501 fp->encoding = AUDIO_ENCODING_ULINEAR; 502 fp->precision = 8; 503 fp->flags = 0; 504 break; 505 case 1: 506 strcpy(fp->name, AudioEmulaw); 507 fp->encoding = AUDIO_ENCODING_ULAW; 508 fp->precision = 8; 509 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 510 break; 511 case 2: 512 strcpy(fp->name, AudioEalaw); 513 fp->encoding = AUDIO_ENCODING_ALAW; 514 fp->precision = 8; 515 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 516 break; 517 case 3: 518 strcpy(fp->name, AudioEslinear); 519 fp->encoding = AUDIO_ENCODING_SLINEAR; 520 fp->precision = 8; 521 fp->flags = 0; 522 break; 523 case 4: 524 strcpy(fp->name, AudioEslinear_le); 525 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 526 fp->precision = 16; 527 fp->flags = 0; 528 break; 529 case 5: 530 strcpy(fp->name, AudioEulinear_le); 531 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 532 fp->precision = 16; 533 fp->flags = 0; 534 break; 535 case 6: 536 strcpy(fp->name, AudioEslinear_be); 537 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 538 fp->precision = 16; 539 fp->flags = 0; 540 break; 541 case 7: 542 strcpy(fp->name, AudioEulinear_be); 543 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 544 fp->precision = 16; 545 fp->flags = 0; 546 break; 547 default: 548 return EINVAL; 549 } 550 return 0; 551 } 552 553 int 554 cs4280_set_params(addr, setmode, usemode, play, rec) 555 void *addr; 556 int setmode, usemode; 557 struct audio_params *play, *rec; 558 { 559 struct cs428x_softc *sc = addr; 560 struct audio_params *p; 561 int mode; 562 563 for (mode = AUMODE_RECORD; mode != -1; 564 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 565 if ((setmode & mode) == 0) 566 continue; 567 568 p = mode == AUMODE_PLAY ? play : rec; 569 570 if (p == play) { 571 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 572 p->sample_rate, p->precision, p->channels)); 573 /* play back data format may be 8- or 16-bit and 574 * either stereo or mono. 575 * playback rate may range from 8000Hz to 48000Hz 576 */ 577 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 578 (p->precision != 8 && p->precision != 16) || 579 (p->channels != 1 && p->channels != 2) ) { 580 return EINVAL; 581 } 582 } else { 583 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 584 p->sample_rate, p->precision, p->channels)); 585 /* capture data format must be 16bit stereo 586 * and sample rate range from 11025Hz to 48000Hz. 587 * 588 * XXX: it looks like to work with 8000Hz, 589 * although data sheets say lower limit is 590 * 11025 Hz. 591 */ 592 593 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 594 (p->precision != 8 && p->precision != 16) || 595 (p->channels != 1 && p->channels != 2) ) { 596 return EINVAL; 597 } 598 } 599 p->factor = 1; 600 p->sw_code = 0; 601 602 /* capturing data is slinear */ 603 switch (p->encoding) { 604 case AUDIO_ENCODING_SLINEAR_BE: 605 if (mode == AUMODE_RECORD) { 606 if (p->precision == 16) 607 p->sw_code = swap_bytes; 608 } 609 break; 610 case AUDIO_ENCODING_SLINEAR_LE: 611 break; 612 case AUDIO_ENCODING_ULINEAR_BE: 613 if (mode == AUMODE_RECORD) { 614 if (p->precision == 16) 615 p->sw_code = change_sign16_swap_bytes_le; 616 else 617 p->sw_code = change_sign8; 618 } 619 break; 620 case AUDIO_ENCODING_ULINEAR_LE: 621 if (mode == AUMODE_RECORD) { 622 if (p->precision == 16) 623 p->sw_code = change_sign16_le; 624 else 625 p->sw_code = change_sign8; 626 } 627 break; 628 case AUDIO_ENCODING_ULAW: 629 if (mode == AUMODE_PLAY) { 630 p->factor = 2; 631 p->sw_code = mulaw_to_slinear16_le; 632 } else { 633 p->sw_code = slinear8_to_mulaw; 634 } 635 break; 636 case AUDIO_ENCODING_ALAW: 637 if (mode == AUMODE_PLAY) { 638 p->factor = 2; 639 p->sw_code = alaw_to_slinear16_le; 640 } else { 641 p->sw_code = slinear8_to_alaw; 642 } 643 break; 644 default: 645 return EINVAL; 646 } 647 } 648 649 /* set sample rate */ 650 cs4280_set_dac_rate(sc, play->sample_rate); 651 cs4280_set_adc_rate(sc, rec->sample_rate); 652 return 0; 653 } 654 655 int 656 cs4280_halt_output(addr) 657 void *addr; 658 { 659 struct cs428x_softc *sc = addr; 660 u_int32_t mem; 661 662 mem = BA1READ4(sc, CS4280_PCTL); 663 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 664 sc->sc_prun = 0; 665 return 0; 666 } 667 668 int 669 cs4280_halt_input(addr) 670 void *addr; 671 { 672 struct cs428x_softc *sc = addr; 673 u_int32_t mem; 674 675 mem = BA1READ4(sc, CS4280_CCTL); 676 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 677 sc->sc_rrun = 0; 678 return 0; 679 } 680 681 int 682 cs4280_getdev(addr, retp) 683 void *addr; 684 struct audio_device *retp; 685 { 686 *retp = cs4280_device; 687 return 0; 688 } 689 690 int 691 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 692 void *addr; 693 void *start, *end; 694 int blksize; 695 void (*intr) __P((void *)); 696 void *arg; 697 struct audio_params *param; 698 { 699 struct cs428x_softc *sc = addr; 700 u_int32_t pfie, pctl, pdtc; 701 struct cs428x_dma *p; 702 703 #ifdef DIAGNOSTIC 704 if (sc->sc_prun) 705 printf("cs4280_trigger_output: already running\n"); 706 #endif 707 sc->sc_prun = 1; 708 709 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 710 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 711 sc->sc_pintr = intr; 712 sc->sc_parg = arg; 713 714 /* stop playback DMA */ 715 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 716 717 /* setup PDTC */ 718 pdtc = BA1READ4(sc, CS4280_PDTC); 719 pdtc &= ~PDTC_MASK; 720 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 721 BA1WRITE4(sc, CS4280_PDTC, pdtc); 722 723 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 724 param->precision, param->factor, param->channels, 725 param->encoding)); 726 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 727 ; 728 if (p == NULL) { 729 printf("cs4280_trigger_output: bad addr %p\n", start); 730 return EINVAL; 731 } 732 if (DMAADDR(p) % sc->dma_align != 0 ) { 733 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 734 "4kB align\n", DMAADDR(p)); 735 return EINVAL; 736 } 737 738 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 739 sc->sc_ps = (char *)start; 740 sc->sc_pe = (char *)end; 741 sc->sc_pdma = p; 742 sc->sc_pbuf = KERNADDR(p); 743 sc->sc_pi = 0; 744 sc->sc_pn = sc->sc_ps; 745 if (blksize >= sc->dma_size) { 746 sc->sc_pn = sc->sc_ps + sc->dma_size; 747 memcpy(sc->sc_pbuf, start, sc->dma_size); 748 ++sc->sc_pi; 749 } else { 750 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 751 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 752 } 753 754 /* initiate playback dma */ 755 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 756 757 /* set PFIE */ 758 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 759 760 if (param->precision * param->factor == 8) 761 pfie |= PFIE_8BIT; 762 if (param->channels == 1) 763 pfie |= PFIE_MONO; 764 765 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 766 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 767 pfie |= PFIE_SWAPPED; 768 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 769 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 770 pfie |= PFIE_UNSIGNED; 771 772 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 773 774 sc->sc_prate = param->sample_rate; 775 cs4280_set_dac_rate(sc, param->sample_rate); 776 777 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 778 pctl |= sc->pctl; 779 BA1WRITE4(sc, CS4280_PCTL, pctl); 780 return 0; 781 } 782 783 int 784 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 785 void *addr; 786 void *start, *end; 787 int blksize; 788 void (*intr) __P((void *)); 789 void *arg; 790 struct audio_params *param; 791 { 792 struct cs428x_softc *sc = addr; 793 u_int32_t cctl, cie; 794 struct cs428x_dma *p; 795 796 #ifdef DIAGNOSTIC 797 if (sc->sc_rrun) 798 printf("cs4280_trigger_input: already running\n"); 799 #endif 800 sc->sc_rrun = 1; 801 802 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 803 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 804 sc->sc_rintr = intr; 805 sc->sc_rarg = arg; 806 807 /* stop capture DMA */ 808 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 809 810 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 811 ; 812 if (p == NULL) { 813 printf("cs4280_trigger_input: bad addr %p\n", start); 814 return EINVAL; 815 } 816 if (DMAADDR(p) % sc->dma_align != 0) { 817 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 818 "4kB align\n", DMAADDR(p)); 819 return EINVAL; 820 } 821 822 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 823 sc->sc_rs = (char *)start; 824 sc->sc_re = (char *)end; 825 sc->sc_rdma = p; 826 sc->sc_rbuf = KERNADDR(p); 827 sc->sc_ri = 0; 828 sc->sc_rn = sc->sc_rs; 829 830 /* initiate capture dma */ 831 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 832 833 /* setup format information for internal converter */ 834 sc->sc_rparam = 0; 835 if (param->precision == 8) { 836 sc->sc_rparam += CF_8BIT; 837 sc->sc_rcount <<= 1; 838 } 839 if (param->channels == 1) { 840 sc->sc_rparam += CF_MONO; 841 sc->sc_rcount <<= 1; 842 } 843 844 /* set CIE */ 845 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 846 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 847 848 sc->sc_rrate = param->sample_rate; 849 cs4280_set_adc_rate(sc, param->sample_rate); 850 851 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 852 cctl |= sc->cctl; 853 BA1WRITE4(sc, CS4280_CCTL, cctl); 854 return 0; 855 } 856 857 /* Power Hook */ 858 void 859 cs4280_power(why, v) 860 int why; 861 void *v; 862 { 863 struct cs428x_softc *sc = (struct cs428x_softc *)v; 864 static u_int32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 865 static u_int32_t cctl = 0, cba = 0, cie = 0; 866 867 DPRINTF(("%s: cs4280_power why=%d\n", 868 sc->sc_dev.dv_xname, why)); 869 switch (why) { 870 case PWR_SUSPEND: 871 case PWR_STANDBY: 872 sc->sc_suspend = why; 873 874 /* save current playback status */ 875 if ( sc->sc_prun ) { 876 pctl = BA1READ4(sc, CS4280_PCTL); 877 pfie = BA1READ4(sc, CS4280_PFIE); 878 pba = BA1READ4(sc, CS4280_PBA); 879 pdtc = BA1READ4(sc, CS4280_PDTC); 880 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 881 pctl, pfie, pba, pdtc)); 882 } 883 884 /* save current capture status */ 885 if ( sc->sc_rrun ) { 886 cctl = BA1READ4(sc, CS4280_CCTL); 887 cie = BA1READ4(sc, CS4280_CIE); 888 cba = BA1READ4(sc, CS4280_CBA); 889 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 890 cctl, cie, cba)); 891 } 892 893 /* Stop DMA */ 894 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 895 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 896 break; 897 case PWR_RESUME: 898 if (sc->sc_suspend == PWR_RESUME) { 899 printf("cs4280_power: odd, resume without suspend.\n"); 900 sc->sc_suspend = why; 901 return; 902 } 903 sc->sc_suspend = why; 904 cs4280_init(sc, 0); 905 cs4280_reset_codec(sc); 906 907 /* restore ac97 registers */ 908 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 909 910 /* restore DMA related status */ 911 if(sc->sc_prun) { 912 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 913 pctl, pfie, pba, pdtc)); 914 cs4280_set_dac_rate(sc, sc->sc_prate); 915 BA1WRITE4(sc, CS4280_PDTC, pdtc); 916 BA1WRITE4(sc, CS4280_PBA, pba); 917 BA1WRITE4(sc, CS4280_PFIE, pfie); 918 BA1WRITE4(sc, CS4280_PCTL, pctl); 919 } 920 921 if (sc->sc_rrun) { 922 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 923 cctl, cie, cba)); 924 cs4280_set_adc_rate(sc, sc->sc_rrate); 925 BA1WRITE4(sc, CS4280_CBA, cba); 926 BA1WRITE4(sc, CS4280_CIE, cie); 927 BA1WRITE4(sc, CS4280_CCTL, cctl); 928 } 929 break; 930 case PWR_SOFTSUSPEND: 931 case PWR_SOFTSTANDBY: 932 case PWR_SOFTRESUME: 933 break; 934 } 935 } 936 937 /* control AC97 codec */ 938 void 939 cs4280_reset_codec(void *addr) 940 { 941 struct cs428x_softc *sc; 942 int n; 943 944 sc = addr; 945 946 /* Reset codec */ 947 BA0WRITE4(sc, CS428X_ACCTL, 0); 948 delay(100); /* delay 100us */ 949 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 950 951 /* 952 * It looks like we do the following procedure, too 953 */ 954 955 /* Enable AC-link sync generation */ 956 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 957 delay(50*1000); /* XXX delay 50ms */ 958 959 /* Assert valid frame signal */ 960 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 961 962 /* Wait for valid AC97 input slot */ 963 n = 0; 964 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 965 (ACISV_ISV3 | ACISV_ISV4)) { 966 delay(1000); 967 if (++n > 1000) { 968 printf("reset_codec: AC97 inputs slot ready timeout\n"); 969 return; 970 } 971 } 972 } 973 974 975 /* Internal functions */ 976 977 void 978 cs4280_set_adc_rate(sc, rate) 979 struct cs428x_softc *sc; 980 int rate; 981 { 982 /* calculate capture rate: 983 * 984 * capture_coefficient_increment = -round(rate*128*65536/48000; 985 * capture_phase_increment = floor(48000*65536*1024/rate); 986 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 987 * cy = floor(cx/200); 988 * capture_sample_rate_correction = cx - 200*cy; 989 * capture_delay = ceil(24*48000/rate); 990 * capture_num_triplets = floor(65536*rate/24000); 991 * capture_group_length = 24000/GCD(rate, 24000); 992 * where GCD means "Greatest Common Divisor". 993 * 994 * capture_coefficient_increment, capture_phase_increment and 995 * capture_num_triplets are 32-bit signed quantities. 996 * capture_sample_rate_correction and capture_group_length are 997 * 16-bit signed quantities. 998 * capture_delay is a 14-bit unsigned quantity. 999 */ 1000 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 1001 u_int16_t csrc, cgl, cdlay; 1002 1003 /* XXX 1004 * Even though, embedded_audio_spec says capture rate range 11025 to 1005 * 48000, dhwiface.cpp says, 1006 * 1007 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1008 * Return an error if an attempt is made to stray outside that limit." 1009 * 1010 * so assume range as 48000/9 to 48000 1011 */ 1012 1013 if (rate < 8000) 1014 rate = 8000; 1015 if (rate > 48000) 1016 rate = 48000; 1017 1018 cx = rate << 16; 1019 cci = cx / 48000; 1020 cx -= cci * 48000; 1021 cx <<= 7; 1022 cci <<= 7; 1023 cci += cx / 48000; 1024 cci = - cci; 1025 1026 cx = 48000 << 16; 1027 cpi = cx / rate; 1028 cx -= cpi * rate; 1029 cx <<= 10; 1030 cpi <<= 10; 1031 cy = cx / rate; 1032 cpi += cy; 1033 cx -= cy * rate; 1034 1035 cy = cx / 200; 1036 csrc = cx - 200*cy; 1037 1038 cdlay = ((48000 * 24) + rate - 1) / rate; 1039 #if 0 1040 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1041 #endif 1042 1043 cnt = rate << 16; 1044 cnt /= 24000; 1045 1046 cgl = 1; 1047 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1048 if (((rate / tmp1) * tmp1) != rate) 1049 cgl *= 2; 1050 } 1051 if (((rate / 3) * 3) != rate) 1052 cgl *= 3; 1053 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1054 if (((rate / tmp1) * tmp1) != rate) 1055 cgl *= 5; 1056 } 1057 #if 0 1058 /* XXX what manual says */ 1059 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1060 tmp1 |= csrc<<16; 1061 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1062 #else 1063 /* suggested by cs461x.c (ALSA driver) */ 1064 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1065 #endif 1066 1067 #if 0 1068 /* I am confused. The sample rate calculation section says 1069 * cci *is* 32-bit signed quantity but in the parameter description 1070 * section, CCI only assigned 16bit. 1071 * I believe size of the variable. 1072 */ 1073 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1074 tmp1 |= cci<<16; 1075 BA1WRITE4(sc, CS4280_CCI, tmp1); 1076 #else 1077 BA1WRITE4(sc, CS4280_CCI, cci); 1078 #endif 1079 1080 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1081 tmp1 |= cdlay <<18; 1082 BA1WRITE4(sc, CS4280_CD, tmp1); 1083 1084 BA1WRITE4(sc, CS4280_CPI, cpi); 1085 1086 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1087 tmp1 |= cgl; 1088 BA1WRITE4(sc, CS4280_CGL, tmp1); 1089 1090 BA1WRITE4(sc, CS4280_CNT, cnt); 1091 1092 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1093 tmp1 |= cgl; 1094 BA1WRITE4(sc, CS4280_CGC, tmp1); 1095 } 1096 1097 void 1098 cs4280_set_dac_rate(sc, rate) 1099 struct cs428x_softc *sc; 1100 int rate; 1101 { 1102 /* 1103 * playback rate may range from 8000Hz to 48000Hz 1104 * 1105 * play_phase_increment = floor(rate*65536*1024/48000) 1106 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1107 * py=floor(px/200) 1108 * play_sample_rate_correction = px - 200*py 1109 * 1110 * play_phase_increment is a 32bit signed quantity. 1111 * play_sample_rate_correction is a 16bit signed quantity. 1112 */ 1113 int32_t ppi; 1114 int16_t psrc; 1115 u_int32_t px, py; 1116 1117 if (rate < 8000) 1118 rate = 8000; 1119 if (rate > 48000) 1120 rate = 48000; 1121 px = rate << 16; 1122 ppi = px/48000; 1123 px -= ppi*48000; 1124 ppi <<= 10; 1125 px <<= 10; 1126 py = px / 48000; 1127 ppi += py; 1128 px -= py*48000; 1129 py = px/200; 1130 px -= py*200; 1131 psrc = px; 1132 #if 0 1133 /* what manual says */ 1134 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1135 BA1WRITE4(sc, CS4280_PSRC, 1136 ( ((psrc<<16) & PSRC_MASK) | px )); 1137 #else 1138 /* suggested by cs461x.c (ALSA driver) */ 1139 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1140 #endif 1141 BA1WRITE4(sc, CS4280_PPI, ppi); 1142 } 1143 1144 /* Download Proceessor Code and Data image */ 1145 int 1146 cs4280_download(sc, src, offset, len) 1147 struct cs428x_softc *sc; 1148 const u_int32_t *src; 1149 u_int32_t offset, len; 1150 { 1151 u_int32_t ctr; 1152 1153 #if CS4280_DEBUG > 10 1154 u_int32_t con, data; 1155 u_int8_t c0,c1,c2,c3; 1156 #endif 1157 if ((offset&3) || (len&3)) 1158 return -1; 1159 1160 len /= sizeof(u_int32_t); 1161 for (ctr = 0; ctr < len; ctr++) { 1162 /* XXX: 1163 * I cannot confirm this is the right thing or not 1164 * on BIG-ENDIAN machines. 1165 */ 1166 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1167 #if CS4280_DEBUG > 10 1168 data = htole32(*(src+ctr)); 1169 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1170 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1171 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1172 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1173 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 1174 if (data != con ) { 1175 printf("0x%06x: write=0x%08x read=0x%08x\n", 1176 offset+ctr*4, data, con); 1177 return -1; 1178 } 1179 #endif 1180 } 1181 return 0; 1182 } 1183 1184 int 1185 cs4280_download_image(sc) 1186 struct cs428x_softc *sc; 1187 { 1188 int idx, err; 1189 u_int32_t offset = 0; 1190 1191 err = 0; 1192 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1193 err = cs4280_download(sc, &BA1Struct.map[offset], 1194 BA1Struct.memory[idx].offset, 1195 BA1Struct.memory[idx].size); 1196 if (err != 0) { 1197 printf("%s: load_image failed at %d\n", 1198 sc->sc_dev.dv_xname, idx); 1199 return -1; 1200 } 1201 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1202 } 1203 return err; 1204 } 1205 1206 /* Processor Soft Reset */ 1207 void 1208 cs4280_reset(sc_) 1209 void *sc_; 1210 { 1211 struct cs428x_softc *sc = sc_; 1212 1213 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1214 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1215 delay(100); 1216 /* Clear RSTSP bit in SPCR */ 1217 BA1WRITE4(sc, CS4280_SPCR, 0); 1218 /* enable DMA reqest */ 1219 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1220 } 1221 1222 int 1223 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1224 struct cs428x_softc *sc; 1225 char *class, *device, *qualifier; 1226 { 1227 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1228 device, qualifier)); 1229 } 1230 1231 int 1232 cs4280_init(sc, init) 1233 struct cs428x_softc *sc; 1234 int init; 1235 { 1236 int n; 1237 u_int32_t mem; 1238 1239 /* Start PLL out in known state */ 1240 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1241 /* Start serial ports out in known state */ 1242 BA0WRITE4(sc, CS4280_SERMC1, 0); 1243 1244 /* Specify type of CODEC */ 1245 /* XXX should not be here */ 1246 #define SERACC_CODEC_TYPE_1_03 1247 #ifdef SERACC_CODEC_TYPE_1_03 1248 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1249 #else 1250 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1251 #endif 1252 1253 /* Reset codec */ 1254 BA0WRITE4(sc, CS428X_ACCTL, 0); 1255 delay(100); /* delay 100us */ 1256 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1257 1258 /* Enable AC-link sync generation */ 1259 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1260 delay(50*1000); /* delay 50ms */ 1261 1262 /* Set the serial port timing configuration */ 1263 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1264 1265 /* Setup clock control */ 1266 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1267 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1268 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1269 1270 /* Power up the PLL */ 1271 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1272 delay(50*1000); /* delay 50ms */ 1273 1274 /* Turn on clock */ 1275 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1276 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1277 1278 /* Set the serial port FIFO pointer to the 1279 * first sample in FIFO. (not documented) */ 1280 cs4280_clear_fifos(sc); 1281 1282 #if 0 1283 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1284 BA0WRITE4(sc, CS4280_SERBSP, 0); 1285 #endif 1286 1287 /* Configure the serial port */ 1288 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1289 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1290 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1291 1292 /* Wait for CODEC ready */ 1293 n = 0; 1294 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1295 delay(125); 1296 if (++n > 1000) { 1297 printf("%s: codec ready timeout\n", 1298 sc->sc_dev.dv_xname); 1299 return(1); 1300 } 1301 } 1302 1303 /* Assert valid frame signal */ 1304 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1305 1306 /* Wait for valid AC97 input slot */ 1307 n = 0; 1308 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1309 (ACISV_ISV3 | ACISV_ISV4)) { 1310 delay(1000); 1311 if (++n > 1000) { 1312 printf("AC97 inputs slot ready timeout\n"); 1313 return(1); 1314 } 1315 } 1316 1317 /* Set AC97 output slot valid signals */ 1318 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1319 1320 /* reset the processor */ 1321 cs4280_reset(sc); 1322 1323 /* Download the image to the processor */ 1324 if (cs4280_download_image(sc) != 0) { 1325 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1326 return(1); 1327 } 1328 1329 /* Save playback parameter and then write zero. 1330 * this ensures that DMA doesn't immediately occur upon 1331 * starting the processor core 1332 */ 1333 mem = BA1READ4(sc, CS4280_PCTL); 1334 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1335 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1336 if (init != 0) 1337 sc->sc_prun = 0; 1338 1339 /* Save capture parameter and then write zero. 1340 * this ensures that DMA doesn't immediately occur upon 1341 * starting the processor core 1342 */ 1343 mem = BA1READ4(sc, CS4280_CCTL); 1344 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1345 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1346 if (init != 0) 1347 sc->sc_rrun = 0; 1348 1349 /* Processor Startup Procedure */ 1350 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1351 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1352 1353 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1354 n = 0; 1355 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1356 delay(10); 1357 if (++n > 1000) { 1358 printf("SPCR 1->0 transition timeout\n"); 1359 return(1); 1360 } 1361 } 1362 1363 n = 0; 1364 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1365 delay(10); 1366 if (++n > 1000) { 1367 printf("SPCS 0->1 transition timeout\n"); 1368 return(1); 1369 } 1370 } 1371 /* Processor is now running !!! */ 1372 1373 /* Setup volume */ 1374 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1375 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1376 1377 /* Interrupt enable */ 1378 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1379 1380 /* playback interrupt enable */ 1381 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1382 mem |= PFIE_PI_ENABLE; 1383 BA1WRITE4(sc, CS4280_PFIE, mem); 1384 /* capture interrupt enable */ 1385 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1386 mem |= CIE_CI_ENABLE; 1387 BA1WRITE4(sc, CS4280_CIE, mem); 1388 1389 #if NMIDI > 0 1390 /* Reset midi port */ 1391 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1392 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1393 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1394 /* midi interrupt enable */ 1395 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1396 BA0WRITE4(sc, CS4280_MIDCR, mem); 1397 #endif 1398 return(0); 1399 } 1400 1401 void 1402 cs4280_clear_fifos(sc) 1403 struct cs428x_softc *sc; 1404 { 1405 int pd = 0, cnt, n; 1406 u_int32_t mem; 1407 1408 /* 1409 * If device power down, power up the device and keep power down 1410 * state. 1411 */ 1412 mem = BA0READ4(sc, CS4280_CLKCR1); 1413 if (!(mem & CLKCR1_SWCE)) { 1414 printf("cs4280_clear_fifo: power down found.\n"); 1415 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1416 pd = 1; 1417 } 1418 BA0WRITE4(sc, CS4280_SERBWP, 0); 1419 for (cnt = 0; cnt < 256; cnt++) { 1420 n = 0; 1421 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1422 delay(1000); 1423 if (++n > 1000) { 1424 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1425 break; 1426 } 1427 } 1428 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1429 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1430 } 1431 if (pd) 1432 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1433 } 1434 1435 #if NMIDI > 0 1436 int 1437 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1438 void *addr; 1439 int flags; 1440 void (*iintr)__P((void *, int)); 1441 void (*ointr)__P((void *)); 1442 void *arg; 1443 { 1444 struct cs428x_softc *sc = addr; 1445 u_int32_t mem; 1446 1447 DPRINTF(("midi_open\n")); 1448 sc->sc_iintr = iintr; 1449 sc->sc_ointr = ointr; 1450 sc->sc_arg = arg; 1451 1452 /* midi interrupt enable */ 1453 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1454 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1455 BA0WRITE4(sc, CS4280_MIDCR, mem); 1456 #ifdef CS4280_DEBUG 1457 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1458 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1459 return(EINVAL); 1460 } 1461 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1462 #endif 1463 return 0; 1464 } 1465 1466 void 1467 cs4280_midi_close(addr) 1468 void *addr; 1469 { 1470 struct cs428x_softc *sc = addr; 1471 u_int32_t mem; 1472 1473 DPRINTF(("midi_close\n")); 1474 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1475 mem = BA0READ4(sc, CS4280_MIDCR); 1476 mem &= ~MIDCR_MASK; 1477 BA0WRITE4(sc, CS4280_MIDCR, mem); 1478 1479 sc->sc_iintr = 0; 1480 sc->sc_ointr = 0; 1481 } 1482 1483 int 1484 cs4280_midi_output(addr, d) 1485 void *addr; 1486 int d; 1487 { 1488 struct cs428x_softc *sc = addr; 1489 u_int32_t mem; 1490 int x; 1491 1492 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1493 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1494 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1495 mem |= d & MIDWP_MASK; 1496 DPRINTFN(5,("midi_output d=0x%08x",d)); 1497 BA0WRITE4(sc, CS4280_MIDWP, mem); 1498 #ifdef DIAGNOSTIC 1499 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1500 DPRINTF(("Bad write data: %d %d", 1501 mem, BA0READ4(sc, CS4280_MIDWP))); 1502 return(EIO); 1503 } 1504 #endif 1505 return 0; 1506 } 1507 delay(MIDI_BUSY_DELAY); 1508 } 1509 return (EIO); 1510 } 1511 1512 void 1513 cs4280_midi_getinfo(addr, mi) 1514 void *addr; 1515 struct midi_info *mi; 1516 { 1517 mi->name = "CS4280 MIDI UART"; 1518 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1519 } 1520 1521 #endif 1522 1523 /* DEBUG functions */ 1524 #if CS4280_DEBUG > 10 1525 int 1526 cs4280_checkimage(sc, src, offset, len) 1527 struct cs428x_softc *sc; 1528 u_int32_t *src; 1529 u_int32_t offset, len; 1530 { 1531 u_int32_t ctr, data; 1532 int err = 0; 1533 1534 if ((offset&3) || (len&3)) 1535 return -1; 1536 1537 len /= sizeof(u_int32_t); 1538 for (ctr = 0; ctr < len; ctr++) { 1539 /* I cannot confirm this is the right thing 1540 * on BIG-ENDIAN machines 1541 */ 1542 data = BA1READ4(sc, offset+ctr*4); 1543 if (data != htole32(*(src+ctr))) { 1544 printf("0x%06x: 0x%08x(0x%08x)\n", 1545 offset+ctr*4, data, *(src+ctr)); 1546 *(src+ctr) = data; 1547 ++err; 1548 } 1549 } 1550 return err; 1551 } 1552 1553 int 1554 cs4280_check_images(sc) 1555 struct cs428x_softc *sc; 1556 { 1557 int idx, err; 1558 u_int32_t offset = 0; 1559 1560 err = 0; 1561 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 1562 for (idx = 0; idx < 1; ++idx) { 1563 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1564 BA1Struct.memory[idx].offset, 1565 BA1Struct.memory[idx].size); 1566 if (err != 0) { 1567 printf("%s: check_image failed at %d\n", 1568 sc->sc_dev.dv_xname, idx); 1569 } 1570 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1571 } 1572 return err; 1573 } 1574 1575 #endif 1576
Indexes created Thu Oct 02 14:10:14 GMT 2025