cs4280.c revision 1.16.2.2
1 /* $NetBSD: cs4280.c,v 1.16.2.2 2002/06/23 17:47:34 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.16.2.2 2002/06/23 17:47:34 jdolecek Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <machine/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 int cs4280_match(struct device *, struct cfdata *, void *); 93 void cs4280_attach(struct device *, struct device *, void *); 94 int cs4280_intr(void *); 95 int cs4280_query_encoding(void *, struct audio_encoding *); 96 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 97 int cs4280_halt_output(void *); 98 int cs4280_halt_input(void *); 99 int cs4280_getdev(void *, struct audio_device *); 100 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 101 void *, struct audio_params *); 102 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 103 void *, struct audio_params *); 104 105 void cs4280_reset_codec(void *); 106 107 /* For PowerHook */ 108 void cs4280_power(int, void *); 109 110 /* Internal functions */ 111 void cs4280_set_adc_rate(struct cs428x_softc *, int ); 112 void cs4280_set_dac_rate(struct cs428x_softc *, int ); 113 int cs4280_download(struct cs428x_softc *, const u_int32_t *, u_int32_t, u_int32_t); 114 int cs4280_download_image(struct cs428x_softc *); 115 void cs4280_reset(void *); 116 int cs4280_get_portnum_by_name(struct cs428x_softc *, char *, char *, char *); 117 int cs4280_init(struct cs428x_softc *, int); 118 void cs4280_clear_fifos(struct cs428x_softc *); 119 120 #if CS4280_DEBUG > 10 121 /* Thease two function is only for checking image loading is succeeded or not. */ 122 int cs4280_check_images(struct cs428x_softc *); 123 int cs4280_checkimage(struct cs428x_softc *, u_int32_t *, u_int32_t, u_int32_t); 124 #endif 125 126 struct audio_hw_if cs4280_hw_if = { 127 cs428x_open, 128 cs428x_close, 129 NULL, 130 cs4280_query_encoding, 131 cs4280_set_params, 132 cs428x_round_blocksize, 133 NULL, 134 NULL, 135 NULL, 136 NULL, 137 NULL, 138 cs4280_halt_output, 139 cs4280_halt_input, 140 NULL, 141 cs4280_getdev, 142 NULL, 143 cs428x_mixer_set_port, 144 cs428x_mixer_get_port, 145 cs428x_query_devinfo, 146 cs428x_malloc, 147 cs428x_free, 148 cs428x_round_buffersize, 149 cs428x_mappage, 150 cs428x_get_props, 151 cs4280_trigger_output, 152 cs4280_trigger_input, 153 NULL, 154 }; 155 156 #if NMIDI > 0 157 /* Midi Interface */ 158 int cs4280_midi_open(void *, int, void (*)(void *, int), 159 void (*)(void *), void *); 160 void cs4280_midi_close(void*); 161 int cs4280_midi_output(void *, int); 162 void cs4280_midi_getinfo(void *, struct midi_info *); 163 164 struct midi_hw_if cs4280_midi_hw_if = { 165 cs4280_midi_open, 166 cs4280_midi_close, 167 cs4280_midi_output, 168 cs4280_midi_getinfo, 169 0, 170 }; 171 #endif 172 173 struct cfattach clcs_ca = { 174 sizeof(struct cs428x_softc), cs4280_match, cs4280_attach 175 }; 176 177 struct audio_device cs4280_device = { 178 "CS4280", 179 "", 180 "cs4280" 181 }; 182 183 184 int 185 cs4280_match(parent, match, aux) 186 struct device *parent; 187 struct cfdata *match; 188 void *aux; 189 { 190 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 191 192 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 193 return 0; 194 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 195 #if 0 /* I can't confirm */ 196 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 197 #endif 198 ) 199 return 1; 200 return 0; 201 } 202 203 void 204 cs4280_attach(parent, self, aux) 205 struct device *parent; 206 struct device *self; 207 void *aux; 208 { 209 struct cs428x_softc *sc = (struct cs428x_softc *)self; 210 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 211 pci_chipset_tag_t pc = pa->pa_pc; 212 char const *intrstr; 213 pci_intr_handle_t ih; 214 pcireg_t reg; 215 char devinfo[256]; 216 mixer_ctrl_t ctl; 217 u_int32_t mem; 218 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 219 220 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 221 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 222 223 /* Map I/O register */ 224 if (pci_mapreg_map(pa, PCI_BA0, 225 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 226 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 227 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 228 return; 229 } 230 if (pci_mapreg_map(pa, PCI_BA1, 231 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 232 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 233 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 234 return; 235 } 236 237 sc->sc_dmatag = pa->pa_dmat; 238 239 /* Check and set Power State */ 240 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 241 &pci_pwrmgmt_cap_reg, 0)) { 242 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 243 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 244 pci_pwrmgmt_csr_reg); 245 DPRINTF(("%s: Power State is %d\n", 246 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 247 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 248 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 249 (reg & ~PCI_PMCSR_STATE_MASK) | 250 PCI_PMCSR_STATE_D0); 251 } 252 } 253 254 /* Enable the device (set bus master flag) */ 255 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 256 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 257 reg | PCI_COMMAND_MASTER_ENABLE); 258 259 /* LATENCY_TIMER setting */ 260 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 261 if ( PCI_LATTIMER(mem) < 32 ) { 262 mem &= 0xffff00ff; 263 mem |= 0x00002000; 264 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 265 } 266 267 /* Map and establish the interrupt. */ 268 if (pci_intr_map(pa, &ih)) { 269 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 270 return; 271 } 272 intrstr = pci_intr_string(pc, ih); 273 274 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 275 if (sc->sc_ih == NULL) { 276 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 277 if (intrstr != NULL) 278 printf(" at %s", intrstr); 279 printf("\n"); 280 return; 281 } 282 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 283 284 /* Initialization */ 285 if(cs4280_init(sc, 1) != 0) 286 return; 287 288 sc->type = TYPE_CS4280; 289 sc->halt_input = cs4280_halt_input; 290 sc->halt_output = cs4280_halt_output; 291 292 /* setup buffer related parameters */ 293 sc->dma_size = CS4280_DCHUNK; 294 sc->dma_align = CS4280_DALIGN; 295 sc->hw_blocksize = CS4280_ICHUNK; 296 297 /* AC 97 attachment */ 298 sc->host_if.arg = sc; 299 sc->host_if.attach = cs428x_attach_codec; 300 sc->host_if.read = cs428x_read_codec; 301 sc->host_if.write = cs428x_write_codec; 302 sc->host_if.reset = cs4280_reset_codec; 303 if (ac97_attach(&sc->host_if) != 0) { 304 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 305 return; 306 } 307 308 /* Turn mute off of DAC, CD and master volumes by default */ 309 ctl.type = AUDIO_MIXER_ENUM; 310 ctl.un.ord = 0; /* off */ 311 312 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 313 AudioNmaster, AudioNmute); 314 cs428x_mixer_set_port(sc, &ctl); 315 316 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 317 AudioNdac, AudioNmute); 318 cs428x_mixer_set_port(sc, &ctl); 319 320 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 321 AudioNcd, AudioNmute); 322 cs428x_mixer_set_port(sc, &ctl); 323 324 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 325 326 #if NMIDI > 0 327 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 328 #endif 329 330 sc->sc_suspend = PWR_RESUME; 331 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 332 } 333 334 /* Interrupt handling function */ 335 int 336 cs4280_intr(p) 337 void *p; 338 { 339 /* 340 * XXX 341 * 342 * Since CS4280 has only 4kB dma buffer and 343 * interrupt occurs every 2kB block, I create dummy buffer 344 * which returns to audio driver and actual dma buffer 345 * using in DMA transfer. 346 * 347 * 348 * ring buffer in audio.c is pointed by BUFADDR 349 * <------ ring buffer size == 64kB ------> 350 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 351 * |= = = =|= = = =|= = = =|= = = =|= = = =| 352 * | | | | | | <- call audio_intp every 353 * sc->sc_[pr]_count time. 354 * 355 * actual dma buffer is pointed by KERNADDR 356 * <-> dma buffer size = 4kB 357 * |= =| 358 * 359 * 360 */ 361 struct cs428x_softc *sc = p; 362 u_int32_t intr, mem; 363 char * empty_dma; 364 int handled = 0; 365 366 /* grab interrupt register then clear it */ 367 intr = BA0READ4(sc, CS4280_HISR); 368 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 369 370 /* Playback Interrupt */ 371 if (intr & HISR_PINT) { 372 handled = 1; 373 mem = BA1READ4(sc, CS4280_PFIE); 374 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 375 if (sc->sc_pintr) { 376 if ((sc->sc_pi%sc->sc_pcount) == 0) 377 sc->sc_pintr(sc->sc_parg); 378 } else { 379 printf("unexpected play intr\n"); 380 } 381 /* copy buffer */ 382 ++sc->sc_pi; 383 empty_dma = sc->sc_pdma->addr; 384 if (sc->sc_pi&1) 385 empty_dma += sc->hw_blocksize; 386 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 387 sc->sc_pn += sc->hw_blocksize; 388 if (sc->sc_pn >= sc->sc_pe) 389 sc->sc_pn = sc->sc_ps; 390 BA1WRITE4(sc, CS4280_PFIE, mem); 391 } 392 /* Capture Interrupt */ 393 if (intr & HISR_CINT) { 394 int i; 395 int16_t rdata; 396 397 handled = 1; 398 mem = BA1READ4(sc, CS4280_CIE); 399 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 400 ++sc->sc_ri; 401 empty_dma = sc->sc_rdma->addr; 402 if ((sc->sc_ri&1) == 0) 403 empty_dma += sc->hw_blocksize; 404 405 /* 406 * XXX 407 * I think this audio data conversion should be 408 * happend in upper layer, but I put this here 409 * since there is no conversion function available. 410 */ 411 switch(sc->sc_rparam) { 412 case CF_16BIT_STEREO: 413 /* just copy it */ 414 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 415 sc->sc_rn += sc->hw_blocksize; 416 break; 417 case CF_16BIT_MONO: 418 for (i = 0; i < 512; i++) { 419 rdata = *((int16_t *)empty_dma)++>>1; 420 rdata += *((int16_t *)empty_dma)++>>1; 421 *((int16_t *)sc->sc_rn)++ = rdata; 422 } 423 break; 424 case CF_8BIT_STEREO: 425 for (i = 0; i < 512; i++) { 426 rdata = *((int16_t*)empty_dma)++; 427 *sc->sc_rn++ = rdata >> 8; 428 rdata = *((int16_t*)empty_dma)++; 429 *sc->sc_rn++ = rdata >> 8; 430 } 431 break; 432 case CF_8BIT_MONO: 433 for (i = 0; i < 512; i++) { 434 rdata = *((int16_t*)empty_dma)++ >>1; 435 rdata += *((int16_t*)empty_dma)++ >>1; 436 *sc->sc_rn++ = rdata >>8; 437 } 438 break; 439 default: 440 /* Should not reach here */ 441 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 442 } 443 if (sc->sc_rn >= sc->sc_re) 444 sc->sc_rn = sc->sc_rs; 445 BA1WRITE4(sc, CS4280_CIE, mem); 446 if (sc->sc_rintr) { 447 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 448 sc->sc_rintr(sc->sc_rarg); 449 } else { 450 printf("unexpected record intr\n"); 451 } 452 } 453 454 #if NMIDI > 0 455 /* Midi port Interrupt */ 456 if (intr & HISR_MIDI) { 457 int data; 458 459 handled = 1; 460 DPRINTF(("i: %d: ", 461 BA0READ4(sc, CS4280_MIDSR))); 462 /* Read the received data */ 463 while ((sc->sc_iintr != NULL) && 464 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 465 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 466 DPRINTF(("r:%x\n",data)); 467 sc->sc_iintr(sc->sc_arg, data); 468 } 469 470 /* Write the data */ 471 #if 1 472 /* XXX: 473 * It seems "Transmit Buffer Full" never activate until EOI 474 * is deliverd. Shall I throw EOI top of this routine ? 475 */ 476 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 477 DPRINTF(("w: ")); 478 if (sc->sc_ointr != NULL) 479 sc->sc_ointr(sc->sc_arg); 480 } 481 #else 482 while ((sc->sc_ointr != NULL) && 483 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 484 DPRINTF(("w: ")); 485 sc->sc_ointr(sc->sc_arg); 486 } 487 #endif 488 DPRINTF(("\n")); 489 } 490 #endif 491 492 return handled; 493 } 494 495 int 496 cs4280_query_encoding(addr, fp) 497 void *addr; 498 struct audio_encoding *fp; 499 { 500 switch (fp->index) { 501 case 0: 502 strcpy(fp->name, AudioEulinear); 503 fp->encoding = AUDIO_ENCODING_ULINEAR; 504 fp->precision = 8; 505 fp->flags = 0; 506 break; 507 case 1: 508 strcpy(fp->name, AudioEmulaw); 509 fp->encoding = AUDIO_ENCODING_ULAW; 510 fp->precision = 8; 511 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 512 break; 513 case 2: 514 strcpy(fp->name, AudioEalaw); 515 fp->encoding = AUDIO_ENCODING_ALAW; 516 fp->precision = 8; 517 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 518 break; 519 case 3: 520 strcpy(fp->name, AudioEslinear); 521 fp->encoding = AUDIO_ENCODING_SLINEAR; 522 fp->precision = 8; 523 fp->flags = 0; 524 break; 525 case 4: 526 strcpy(fp->name, AudioEslinear_le); 527 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 528 fp->precision = 16; 529 fp->flags = 0; 530 break; 531 case 5: 532 strcpy(fp->name, AudioEulinear_le); 533 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 534 fp->precision = 16; 535 fp->flags = 0; 536 break; 537 case 6: 538 strcpy(fp->name, AudioEslinear_be); 539 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 540 fp->precision = 16; 541 fp->flags = 0; 542 break; 543 case 7: 544 strcpy(fp->name, AudioEulinear_be); 545 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 546 fp->precision = 16; 547 fp->flags = 0; 548 break; 549 default: 550 return EINVAL; 551 } 552 return 0; 553 } 554 555 int 556 cs4280_set_params(addr, setmode, usemode, play, rec) 557 void *addr; 558 int setmode, usemode; 559 struct audio_params *play, *rec; 560 { 561 struct cs428x_softc *sc = addr; 562 struct audio_params *p; 563 int mode; 564 565 for (mode = AUMODE_RECORD; mode != -1; 566 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 567 if ((setmode & mode) == 0) 568 continue; 569 570 p = mode == AUMODE_PLAY ? play : rec; 571 572 if (p == play) { 573 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 574 p->sample_rate, p->precision, p->channels)); 575 /* play back data format may be 8- or 16-bit and 576 * either stereo or mono. 577 * playback rate may range from 8000Hz to 48000Hz 578 */ 579 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 580 (p->precision != 8 && p->precision != 16) || 581 (p->channels != 1 && p->channels != 2) ) { 582 return EINVAL; 583 } 584 } else { 585 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 586 p->sample_rate, p->precision, p->channels)); 587 /* capture data format must be 16bit stereo 588 * and sample rate range from 11025Hz to 48000Hz. 589 * 590 * XXX: it looks like to work with 8000Hz, 591 * although data sheets say lower limit is 592 * 11025 Hz. 593 */ 594 595 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 596 (p->precision != 8 && p->precision != 16) || 597 (p->channels != 1 && p->channels != 2) ) { 598 return EINVAL; 599 } 600 } 601 p->factor = 1; 602 p->sw_code = 0; 603 604 /* capturing data is slinear */ 605 switch (p->encoding) { 606 case AUDIO_ENCODING_SLINEAR_BE: 607 if (mode == AUMODE_RECORD) { 608 if (p->precision == 16) 609 p->sw_code = swap_bytes; 610 } 611 break; 612 case AUDIO_ENCODING_SLINEAR_LE: 613 break; 614 case AUDIO_ENCODING_ULINEAR_BE: 615 if (mode == AUMODE_RECORD) { 616 if (p->precision == 16) 617 p->sw_code = change_sign16_swap_bytes_le; 618 else 619 p->sw_code = change_sign8; 620 } 621 break; 622 case AUDIO_ENCODING_ULINEAR_LE: 623 if (mode == AUMODE_RECORD) { 624 if (p->precision == 16) 625 p->sw_code = change_sign16_le; 626 else 627 p->sw_code = change_sign8; 628 } 629 break; 630 case AUDIO_ENCODING_ULAW: 631 if (mode == AUMODE_PLAY) { 632 p->factor = 2; 633 p->sw_code = mulaw_to_slinear16_le; 634 } else { 635 p->sw_code = slinear8_to_mulaw; 636 } 637 break; 638 case AUDIO_ENCODING_ALAW: 639 if (mode == AUMODE_PLAY) { 640 p->factor = 2; 641 p->sw_code = alaw_to_slinear16_le; 642 } else { 643 p->sw_code = slinear8_to_alaw; 644 } 645 break; 646 default: 647 return EINVAL; 648 } 649 } 650 651 /* set sample rate */ 652 cs4280_set_dac_rate(sc, play->sample_rate); 653 cs4280_set_adc_rate(sc, rec->sample_rate); 654 return 0; 655 } 656 657 int 658 cs4280_halt_output(addr) 659 void *addr; 660 { 661 struct cs428x_softc *sc = addr; 662 u_int32_t mem; 663 664 mem = BA1READ4(sc, CS4280_PCTL); 665 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 666 sc->sc_prun = 0; 667 return 0; 668 } 669 670 int 671 cs4280_halt_input(addr) 672 void *addr; 673 { 674 struct cs428x_softc *sc = addr; 675 u_int32_t mem; 676 677 mem = BA1READ4(sc, CS4280_CCTL); 678 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 679 sc->sc_rrun = 0; 680 return 0; 681 } 682 683 int 684 cs4280_getdev(addr, retp) 685 void *addr; 686 struct audio_device *retp; 687 { 688 *retp = cs4280_device; 689 return 0; 690 } 691 692 int 693 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 694 void *addr; 695 void *start, *end; 696 int blksize; 697 void (*intr) __P((void *)); 698 void *arg; 699 struct audio_params *param; 700 { 701 struct cs428x_softc *sc = addr; 702 u_int32_t pfie, pctl, pdtc; 703 struct cs428x_dma *p; 704 705 #ifdef DIAGNOSTIC 706 if (sc->sc_prun) 707 printf("cs4280_trigger_output: already running\n"); 708 #endif 709 sc->sc_prun = 1; 710 711 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 712 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 713 sc->sc_pintr = intr; 714 sc->sc_parg = arg; 715 716 /* stop playback DMA */ 717 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 718 719 /* setup PDTC */ 720 pdtc = BA1READ4(sc, CS4280_PDTC); 721 pdtc &= ~PDTC_MASK; 722 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 723 BA1WRITE4(sc, CS4280_PDTC, pdtc); 724 725 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 726 param->precision, param->factor, param->channels, 727 param->encoding)); 728 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 729 ; 730 if (p == NULL) { 731 printf("cs4280_trigger_output: bad addr %p\n", start); 732 return EINVAL; 733 } 734 if (DMAADDR(p) % sc->dma_align != 0 ) { 735 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 736 "4kB align\n", (ulong)DMAADDR(p)); 737 return EINVAL; 738 } 739 740 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 741 sc->sc_ps = (char *)start; 742 sc->sc_pe = (char *)end; 743 sc->sc_pdma = p; 744 sc->sc_pbuf = KERNADDR(p); 745 sc->sc_pi = 0; 746 sc->sc_pn = sc->sc_ps; 747 if (blksize >= sc->dma_size) { 748 sc->sc_pn = sc->sc_ps + sc->dma_size; 749 memcpy(sc->sc_pbuf, start, sc->dma_size); 750 ++sc->sc_pi; 751 } else { 752 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 753 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 754 } 755 756 /* initiate playback dma */ 757 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 758 759 /* set PFIE */ 760 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 761 762 if (param->precision * param->factor == 8) 763 pfie |= PFIE_8BIT; 764 if (param->channels == 1) 765 pfie |= PFIE_MONO; 766 767 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 768 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 769 pfie |= PFIE_SWAPPED; 770 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 771 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 772 pfie |= PFIE_UNSIGNED; 773 774 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 775 776 sc->sc_prate = param->sample_rate; 777 cs4280_set_dac_rate(sc, param->sample_rate); 778 779 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 780 pctl |= sc->pctl; 781 BA1WRITE4(sc, CS4280_PCTL, pctl); 782 return 0; 783 } 784 785 int 786 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 787 void *addr; 788 void *start, *end; 789 int blksize; 790 void (*intr) __P((void *)); 791 void *arg; 792 struct audio_params *param; 793 { 794 struct cs428x_softc *sc = addr; 795 u_int32_t cctl, cie; 796 struct cs428x_dma *p; 797 798 #ifdef DIAGNOSTIC 799 if (sc->sc_rrun) 800 printf("cs4280_trigger_input: already running\n"); 801 #endif 802 sc->sc_rrun = 1; 803 804 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 805 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 806 sc->sc_rintr = intr; 807 sc->sc_rarg = arg; 808 809 /* stop capture DMA */ 810 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 811 812 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 813 ; 814 if (p == NULL) { 815 printf("cs4280_trigger_input: bad addr %p\n", start); 816 return EINVAL; 817 } 818 if (DMAADDR(p) % sc->dma_align != 0) { 819 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 820 "4kB align\n", (ulong)DMAADDR(p)); 821 return EINVAL; 822 } 823 824 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 825 sc->sc_rs = (char *)start; 826 sc->sc_re = (char *)end; 827 sc->sc_rdma = p; 828 sc->sc_rbuf = KERNADDR(p); 829 sc->sc_ri = 0; 830 sc->sc_rn = sc->sc_rs; 831 832 /* initiate capture dma */ 833 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 834 835 /* setup format information for internal converter */ 836 sc->sc_rparam = 0; 837 if (param->precision == 8) { 838 sc->sc_rparam += CF_8BIT; 839 sc->sc_rcount <<= 1; 840 } 841 if (param->channels == 1) { 842 sc->sc_rparam += CF_MONO; 843 sc->sc_rcount <<= 1; 844 } 845 846 /* set CIE */ 847 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 848 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 849 850 sc->sc_rrate = param->sample_rate; 851 cs4280_set_adc_rate(sc, param->sample_rate); 852 853 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 854 cctl |= sc->cctl; 855 BA1WRITE4(sc, CS4280_CCTL, cctl); 856 return 0; 857 } 858 859 /* Power Hook */ 860 void 861 cs4280_power(why, v) 862 int why; 863 void *v; 864 { 865 struct cs428x_softc *sc = (struct cs428x_softc *)v; 866 static u_int32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 867 static u_int32_t cctl = 0, cba = 0, cie = 0; 868 869 DPRINTF(("%s: cs4280_power why=%d\n", 870 sc->sc_dev.dv_xname, why)); 871 switch (why) { 872 case PWR_SUSPEND: 873 case PWR_STANDBY: 874 sc->sc_suspend = why; 875 876 /* save current playback status */ 877 if ( sc->sc_prun ) { 878 pctl = BA1READ4(sc, CS4280_PCTL); 879 pfie = BA1READ4(sc, CS4280_PFIE); 880 pba = BA1READ4(sc, CS4280_PBA); 881 pdtc = BA1READ4(sc, CS4280_PDTC); 882 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 883 pctl, pfie, pba, pdtc)); 884 } 885 886 /* save current capture status */ 887 if ( sc->sc_rrun ) { 888 cctl = BA1READ4(sc, CS4280_CCTL); 889 cie = BA1READ4(sc, CS4280_CIE); 890 cba = BA1READ4(sc, CS4280_CBA); 891 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 892 cctl, cie, cba)); 893 } 894 895 /* Stop DMA */ 896 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 897 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 898 break; 899 case PWR_RESUME: 900 if (sc->sc_suspend == PWR_RESUME) { 901 printf("cs4280_power: odd, resume without suspend.\n"); 902 sc->sc_suspend = why; 903 return; 904 } 905 sc->sc_suspend = why; 906 cs4280_init(sc, 0); 907 cs4280_reset_codec(sc); 908 909 /* restore ac97 registers */ 910 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 911 912 /* restore DMA related status */ 913 if(sc->sc_prun) { 914 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 915 pctl, pfie, pba, pdtc)); 916 cs4280_set_dac_rate(sc, sc->sc_prate); 917 BA1WRITE4(sc, CS4280_PDTC, pdtc); 918 BA1WRITE4(sc, CS4280_PBA, pba); 919 BA1WRITE4(sc, CS4280_PFIE, pfie); 920 BA1WRITE4(sc, CS4280_PCTL, pctl); 921 } 922 923 if (sc->sc_rrun) { 924 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 925 cctl, cie, cba)); 926 cs4280_set_adc_rate(sc, sc->sc_rrate); 927 BA1WRITE4(sc, CS4280_CBA, cba); 928 BA1WRITE4(sc, CS4280_CIE, cie); 929 BA1WRITE4(sc, CS4280_CCTL, cctl); 930 } 931 break; 932 case PWR_SOFTSUSPEND: 933 case PWR_SOFTSTANDBY: 934 case PWR_SOFTRESUME: 935 break; 936 } 937 } 938 939 /* control AC97 codec */ 940 void 941 cs4280_reset_codec(void *addr) 942 { 943 struct cs428x_softc *sc; 944 int n; 945 946 sc = addr; 947 948 /* Reset codec */ 949 BA0WRITE4(sc, CS428X_ACCTL, 0); 950 delay(100); /* delay 100us */ 951 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 952 953 /* 954 * It looks like we do the following procedure, too 955 */ 956 957 /* Enable AC-link sync generation */ 958 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 959 delay(50*1000); /* XXX delay 50ms */ 960 961 /* Assert valid frame signal */ 962 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 963 964 /* Wait for valid AC97 input slot */ 965 n = 0; 966 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 967 (ACISV_ISV3 | ACISV_ISV4)) { 968 delay(1000); 969 if (++n > 1000) { 970 printf("reset_codec: AC97 inputs slot ready timeout\n"); 971 return; 972 } 973 } 974 } 975 976 977 /* Internal functions */ 978 979 void 980 cs4280_set_adc_rate(sc, rate) 981 struct cs428x_softc *sc; 982 int rate; 983 { 984 /* calculate capture rate: 985 * 986 * capture_coefficient_increment = -round(rate*128*65536/48000; 987 * capture_phase_increment = floor(48000*65536*1024/rate); 988 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 989 * cy = floor(cx/200); 990 * capture_sample_rate_correction = cx - 200*cy; 991 * capture_delay = ceil(24*48000/rate); 992 * capture_num_triplets = floor(65536*rate/24000); 993 * capture_group_length = 24000/GCD(rate, 24000); 994 * where GCD means "Greatest Common Divisor". 995 * 996 * capture_coefficient_increment, capture_phase_increment and 997 * capture_num_triplets are 32-bit signed quantities. 998 * capture_sample_rate_correction and capture_group_length are 999 * 16-bit signed quantities. 1000 * capture_delay is a 14-bit unsigned quantity. 1001 */ 1002 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 1003 u_int16_t csrc, cgl, cdlay; 1004 1005 /* XXX 1006 * Even though, embedded_audio_spec says capture rate range 11025 to 1007 * 48000, dhwiface.cpp says, 1008 * 1009 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1010 * Return an error if an attempt is made to stray outside that limit." 1011 * 1012 * so assume range as 48000/9 to 48000 1013 */ 1014 1015 if (rate < 8000) 1016 rate = 8000; 1017 if (rate > 48000) 1018 rate = 48000; 1019 1020 cx = rate << 16; 1021 cci = cx / 48000; 1022 cx -= cci * 48000; 1023 cx <<= 7; 1024 cci <<= 7; 1025 cci += cx / 48000; 1026 cci = - cci; 1027 1028 cx = 48000 << 16; 1029 cpi = cx / rate; 1030 cx -= cpi * rate; 1031 cx <<= 10; 1032 cpi <<= 10; 1033 cy = cx / rate; 1034 cpi += cy; 1035 cx -= cy * rate; 1036 1037 cy = cx / 200; 1038 csrc = cx - 200*cy; 1039 1040 cdlay = ((48000 * 24) + rate - 1) / rate; 1041 #if 0 1042 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1043 #endif 1044 1045 cnt = rate << 16; 1046 cnt /= 24000; 1047 1048 cgl = 1; 1049 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1050 if (((rate / tmp1) * tmp1) != rate) 1051 cgl *= 2; 1052 } 1053 if (((rate / 3) * 3) != rate) 1054 cgl *= 3; 1055 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1056 if (((rate / tmp1) * tmp1) != rate) 1057 cgl *= 5; 1058 } 1059 #if 0 1060 /* XXX what manual says */ 1061 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1062 tmp1 |= csrc<<16; 1063 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1064 #else 1065 /* suggested by cs461x.c (ALSA driver) */ 1066 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1067 #endif 1068 1069 #if 0 1070 /* I am confused. The sample rate calculation section says 1071 * cci *is* 32-bit signed quantity but in the parameter description 1072 * section, CCI only assigned 16bit. 1073 * I believe size of the variable. 1074 */ 1075 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1076 tmp1 |= cci<<16; 1077 BA1WRITE4(sc, CS4280_CCI, tmp1); 1078 #else 1079 BA1WRITE4(sc, CS4280_CCI, cci); 1080 #endif 1081 1082 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1083 tmp1 |= cdlay <<18; 1084 BA1WRITE4(sc, CS4280_CD, tmp1); 1085 1086 BA1WRITE4(sc, CS4280_CPI, cpi); 1087 1088 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1089 tmp1 |= cgl; 1090 BA1WRITE4(sc, CS4280_CGL, tmp1); 1091 1092 BA1WRITE4(sc, CS4280_CNT, cnt); 1093 1094 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1095 tmp1 |= cgl; 1096 BA1WRITE4(sc, CS4280_CGC, tmp1); 1097 } 1098 1099 void 1100 cs4280_set_dac_rate(sc, rate) 1101 struct cs428x_softc *sc; 1102 int rate; 1103 { 1104 /* 1105 * playback rate may range from 8000Hz to 48000Hz 1106 * 1107 * play_phase_increment = floor(rate*65536*1024/48000) 1108 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1109 * py=floor(px/200) 1110 * play_sample_rate_correction = px - 200*py 1111 * 1112 * play_phase_increment is a 32bit signed quantity. 1113 * play_sample_rate_correction is a 16bit signed quantity. 1114 */ 1115 int32_t ppi; 1116 int16_t psrc; 1117 u_int32_t px, py; 1118 1119 if (rate < 8000) 1120 rate = 8000; 1121 if (rate > 48000) 1122 rate = 48000; 1123 px = rate << 16; 1124 ppi = px/48000; 1125 px -= ppi*48000; 1126 ppi <<= 10; 1127 px <<= 10; 1128 py = px / 48000; 1129 ppi += py; 1130 px -= py*48000; 1131 py = px/200; 1132 px -= py*200; 1133 psrc = px; 1134 #if 0 1135 /* what manual says */ 1136 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1137 BA1WRITE4(sc, CS4280_PSRC, 1138 ( ((psrc<<16) & PSRC_MASK) | px )); 1139 #else 1140 /* suggested by cs461x.c (ALSA driver) */ 1141 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1142 #endif 1143 BA1WRITE4(sc, CS4280_PPI, ppi); 1144 } 1145 1146 /* Download Proceessor Code and Data image */ 1147 int 1148 cs4280_download(sc, src, offset, len) 1149 struct cs428x_softc *sc; 1150 const u_int32_t *src; 1151 u_int32_t offset, len; 1152 { 1153 u_int32_t ctr; 1154 1155 #if CS4280_DEBUG > 10 1156 u_int32_t con, data; 1157 u_int8_t c0,c1,c2,c3; 1158 #endif 1159 if ((offset&3) || (len&3)) 1160 return -1; 1161 1162 len /= sizeof(u_int32_t); 1163 for (ctr = 0; ctr < len; ctr++) { 1164 /* XXX: 1165 * I cannot confirm this is the right thing or not 1166 * on BIG-ENDIAN machines. 1167 */ 1168 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1169 #if CS4280_DEBUG > 10 1170 data = htole32(*(src+ctr)); 1171 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1172 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1173 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1174 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1175 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 1176 if (data != con ) { 1177 printf("0x%06x: write=0x%08x read=0x%08x\n", 1178 offset+ctr*4, data, con); 1179 return -1; 1180 } 1181 #endif 1182 } 1183 return 0; 1184 } 1185 1186 int 1187 cs4280_download_image(sc) 1188 struct cs428x_softc *sc; 1189 { 1190 int idx, err; 1191 u_int32_t offset = 0; 1192 1193 err = 0; 1194 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1195 err = cs4280_download(sc, &BA1Struct.map[offset], 1196 BA1Struct.memory[idx].offset, 1197 BA1Struct.memory[idx].size); 1198 if (err != 0) { 1199 printf("%s: load_image failed at %d\n", 1200 sc->sc_dev.dv_xname, idx); 1201 return -1; 1202 } 1203 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1204 } 1205 return err; 1206 } 1207 1208 /* Processor Soft Reset */ 1209 void 1210 cs4280_reset(sc_) 1211 void *sc_; 1212 { 1213 struct cs428x_softc *sc = sc_; 1214 1215 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1216 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1217 delay(100); 1218 /* Clear RSTSP bit in SPCR */ 1219 BA1WRITE4(sc, CS4280_SPCR, 0); 1220 /* enable DMA reqest */ 1221 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1222 } 1223 1224 int 1225 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1226 struct cs428x_softc *sc; 1227 char *class, *device, *qualifier; 1228 { 1229 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1230 device, qualifier)); 1231 } 1232 1233 int 1234 cs4280_init(sc, init) 1235 struct cs428x_softc *sc; 1236 int init; 1237 { 1238 int n; 1239 u_int32_t mem; 1240 1241 /* Start PLL out in known state */ 1242 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1243 /* Start serial ports out in known state */ 1244 BA0WRITE4(sc, CS4280_SERMC1, 0); 1245 1246 /* Specify type of CODEC */ 1247 /* XXX should not be here */ 1248 #define SERACC_CODEC_TYPE_1_03 1249 #ifdef SERACC_CODEC_TYPE_1_03 1250 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1251 #else 1252 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1253 #endif 1254 1255 /* Reset codec */ 1256 BA0WRITE4(sc, CS428X_ACCTL, 0); 1257 delay(100); /* delay 100us */ 1258 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1259 1260 /* Enable AC-link sync generation */ 1261 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1262 delay(50*1000); /* delay 50ms */ 1263 1264 /* Set the serial port timing configuration */ 1265 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1266 1267 /* Setup clock control */ 1268 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1269 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1270 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1271 1272 /* Power up the PLL */ 1273 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1274 delay(50*1000); /* delay 50ms */ 1275 1276 /* Turn on clock */ 1277 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1278 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1279 1280 /* Set the serial port FIFO pointer to the 1281 * first sample in FIFO. (not documented) */ 1282 cs4280_clear_fifos(sc); 1283 1284 #if 0 1285 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1286 BA0WRITE4(sc, CS4280_SERBSP, 0); 1287 #endif 1288 1289 /* Configure the serial port */ 1290 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1291 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1292 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1293 1294 /* Wait for CODEC ready */ 1295 n = 0; 1296 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1297 delay(125); 1298 if (++n > 1000) { 1299 printf("%s: codec ready timeout\n", 1300 sc->sc_dev.dv_xname); 1301 return(1); 1302 } 1303 } 1304 1305 /* Assert valid frame signal */ 1306 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1307 1308 /* Wait for valid AC97 input slot */ 1309 n = 0; 1310 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1311 (ACISV_ISV3 | ACISV_ISV4)) { 1312 delay(1000); 1313 if (++n > 1000) { 1314 printf("AC97 inputs slot ready timeout\n"); 1315 return(1); 1316 } 1317 } 1318 1319 /* Set AC97 output slot valid signals */ 1320 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1321 1322 /* reset the processor */ 1323 cs4280_reset(sc); 1324 1325 /* Download the image to the processor */ 1326 if (cs4280_download_image(sc) != 0) { 1327 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1328 return(1); 1329 } 1330 1331 /* Save playback parameter and then write zero. 1332 * this ensures that DMA doesn't immediately occur upon 1333 * starting the processor core 1334 */ 1335 mem = BA1READ4(sc, CS4280_PCTL); 1336 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1337 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1338 if (init != 0) 1339 sc->sc_prun = 0; 1340 1341 /* Save capture parameter and then write zero. 1342 * this ensures that DMA doesn't immediately occur upon 1343 * starting the processor core 1344 */ 1345 mem = BA1READ4(sc, CS4280_CCTL); 1346 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1347 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1348 if (init != 0) 1349 sc->sc_rrun = 0; 1350 1351 /* Processor Startup Procedure */ 1352 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1353 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1354 1355 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1356 n = 0; 1357 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1358 delay(10); 1359 if (++n > 1000) { 1360 printf("SPCR 1->0 transition timeout\n"); 1361 return(1); 1362 } 1363 } 1364 1365 n = 0; 1366 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1367 delay(10); 1368 if (++n > 1000) { 1369 printf("SPCS 0->1 transition timeout\n"); 1370 return(1); 1371 } 1372 } 1373 /* Processor is now running !!! */ 1374 1375 /* Setup volume */ 1376 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1377 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1378 1379 /* Interrupt enable */ 1380 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1381 1382 /* playback interrupt enable */ 1383 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1384 mem |= PFIE_PI_ENABLE; 1385 BA1WRITE4(sc, CS4280_PFIE, mem); 1386 /* capture interrupt enable */ 1387 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1388 mem |= CIE_CI_ENABLE; 1389 BA1WRITE4(sc, CS4280_CIE, mem); 1390 1391 #if NMIDI > 0 1392 /* Reset midi port */ 1393 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1394 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1395 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1396 /* midi interrupt enable */ 1397 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1398 BA0WRITE4(sc, CS4280_MIDCR, mem); 1399 #endif 1400 return(0); 1401 } 1402 1403 void 1404 cs4280_clear_fifos(sc) 1405 struct cs428x_softc *sc; 1406 { 1407 int pd = 0, cnt, n; 1408 u_int32_t mem; 1409 1410 /* 1411 * If device power down, power up the device and keep power down 1412 * state. 1413 */ 1414 mem = BA0READ4(sc, CS4280_CLKCR1); 1415 if (!(mem & CLKCR1_SWCE)) { 1416 printf("cs4280_clear_fifo: power down found.\n"); 1417 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1418 pd = 1; 1419 } 1420 BA0WRITE4(sc, CS4280_SERBWP, 0); 1421 for (cnt = 0; cnt < 256; cnt++) { 1422 n = 0; 1423 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1424 delay(1000); 1425 if (++n > 1000) { 1426 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1427 break; 1428 } 1429 } 1430 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1431 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1432 } 1433 if (pd) 1434 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1435 } 1436 1437 #if NMIDI > 0 1438 int 1439 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1440 void *addr; 1441 int flags; 1442 void (*iintr)__P((void *, int)); 1443 void (*ointr)__P((void *)); 1444 void *arg; 1445 { 1446 struct cs428x_softc *sc = addr; 1447 u_int32_t mem; 1448 1449 DPRINTF(("midi_open\n")); 1450 sc->sc_iintr = iintr; 1451 sc->sc_ointr = ointr; 1452 sc->sc_arg = arg; 1453 1454 /* midi interrupt enable */ 1455 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1456 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1457 BA0WRITE4(sc, CS4280_MIDCR, mem); 1458 #ifdef CS4280_DEBUG 1459 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1460 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1461 return(EINVAL); 1462 } 1463 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1464 #endif 1465 return 0; 1466 } 1467 1468 void 1469 cs4280_midi_close(addr) 1470 void *addr; 1471 { 1472 struct cs428x_softc *sc = addr; 1473 u_int32_t mem; 1474 1475 DPRINTF(("midi_close\n")); 1476 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1477 mem = BA0READ4(sc, CS4280_MIDCR); 1478 mem &= ~MIDCR_MASK; 1479 BA0WRITE4(sc, CS4280_MIDCR, mem); 1480 1481 sc->sc_iintr = 0; 1482 sc->sc_ointr = 0; 1483 } 1484 1485 int 1486 cs4280_midi_output(addr, d) 1487 void *addr; 1488 int d; 1489 { 1490 struct cs428x_softc *sc = addr; 1491 u_int32_t mem; 1492 int x; 1493 1494 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1495 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1496 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1497 mem |= d & MIDWP_MASK; 1498 DPRINTFN(5,("midi_output d=0x%08x",d)); 1499 BA0WRITE4(sc, CS4280_MIDWP, mem); 1500 #ifdef DIAGNOSTIC 1501 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1502 DPRINTF(("Bad write data: %d %d", 1503 mem, BA0READ4(sc, CS4280_MIDWP))); 1504 return(EIO); 1505 } 1506 #endif 1507 return 0; 1508 } 1509 delay(MIDI_BUSY_DELAY); 1510 } 1511 return (EIO); 1512 } 1513 1514 void 1515 cs4280_midi_getinfo(addr, mi) 1516 void *addr; 1517 struct midi_info *mi; 1518 { 1519 mi->name = "CS4280 MIDI UART"; 1520 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1521 } 1522 1523 #endif 1524 1525 /* DEBUG functions */ 1526 #if CS4280_DEBUG > 10 1527 int 1528 cs4280_checkimage(sc, src, offset, len) 1529 struct cs428x_softc *sc; 1530 u_int32_t *src; 1531 u_int32_t offset, len; 1532 { 1533 u_int32_t ctr, data; 1534 int err = 0; 1535 1536 if ((offset&3) || (len&3)) 1537 return -1; 1538 1539 len /= sizeof(u_int32_t); 1540 for (ctr = 0; ctr < len; ctr++) { 1541 /* I cannot confirm this is the right thing 1542 * on BIG-ENDIAN machines 1543 */ 1544 data = BA1READ4(sc, offset+ctr*4); 1545 if (data != htole32(*(src+ctr))) { 1546 printf("0x%06x: 0x%08x(0x%08x)\n", 1547 offset+ctr*4, data, *(src+ctr)); 1548 *(src+ctr) = data; 1549 ++err; 1550 } 1551 } 1552 return err; 1553 } 1554 1555 int 1556 cs4280_check_images(sc) 1557 struct cs428x_softc *sc; 1558 { 1559 int idx, err; 1560 u_int32_t offset = 0; 1561 1562 err = 0; 1563 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 1564 for (idx = 0; idx < 1; ++idx) { 1565 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1566 BA1Struct.memory[idx].offset, 1567 BA1Struct.memory[idx].size); 1568 if (err != 0) { 1569 printf("%s: check_image failed at %d\n", 1570 sc->sc_dev.dv_xname, idx); 1571 } 1572 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1573 } 1574 return err; 1575 } 1576 1577 #endif 1578
Indexes created Thu Oct 02 14:10:14 GMT 2025