cs4280.c revision 1.23
1 /* $NetBSD: cs4280.c,v 1.23 2002/10/02 16:51:07 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.23 2002/10/02 16:51:07 thorpej Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <machine/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 int cs4280_match(struct device *, struct cfdata *, void *); 93 void cs4280_attach(struct device *, struct device *, void *); 94 int cs4280_intr(void *); 95 int cs4280_query_encoding(void *, struct audio_encoding *); 96 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 97 int cs4280_halt_output(void *); 98 int cs4280_halt_input(void *); 99 int cs4280_getdev(void *, struct audio_device *); 100 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 101 void *, struct audio_params *); 102 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 103 void *, struct audio_params *); 104 105 void cs4280_reset_codec(void *); 106 107 /* For PowerHook */ 108 void cs4280_power(int, void *); 109 110 /* Internal functions */ 111 void cs4280_set_adc_rate(struct cs428x_softc *, int ); 112 void cs4280_set_dac_rate(struct cs428x_softc *, int ); 113 int cs4280_download(struct cs428x_softc *, const u_int32_t *, u_int32_t, u_int32_t); 114 int cs4280_download_image(struct cs428x_softc *); 115 void cs4280_reset(void *); 116 int cs4280_get_portnum_by_name(struct cs428x_softc *, char *, char *, char *); 117 int cs4280_init(struct cs428x_softc *, int); 118 void cs4280_clear_fifos(struct cs428x_softc *); 119 120 #if CS4280_DEBUG > 10 121 /* Thease two function is only for checking image loading is succeeded or not. */ 122 int cs4280_check_images(struct cs428x_softc *); 123 int cs4280_checkimage(struct cs428x_softc *, u_int32_t *, u_int32_t, u_int32_t); 124 #endif 125 126 struct audio_hw_if cs4280_hw_if = { 127 cs428x_open, 128 cs428x_close, 129 NULL, 130 cs4280_query_encoding, 131 cs4280_set_params, 132 cs428x_round_blocksize, 133 NULL, 134 NULL, 135 NULL, 136 NULL, 137 NULL, 138 cs4280_halt_output, 139 cs4280_halt_input, 140 NULL, 141 cs4280_getdev, 142 NULL, 143 cs428x_mixer_set_port, 144 cs428x_mixer_get_port, 145 cs428x_query_devinfo, 146 cs428x_malloc, 147 cs428x_free, 148 cs428x_round_buffersize, 149 cs428x_mappage, 150 cs428x_get_props, 151 cs4280_trigger_output, 152 cs4280_trigger_input, 153 NULL, 154 }; 155 156 #if NMIDI > 0 157 /* Midi Interface */ 158 int cs4280_midi_open(void *, int, void (*)(void *, int), 159 void (*)(void *), void *); 160 void cs4280_midi_close(void*); 161 int cs4280_midi_output(void *, int); 162 void cs4280_midi_getinfo(void *, struct midi_info *); 163 164 struct midi_hw_if cs4280_midi_hw_if = { 165 cs4280_midi_open, 166 cs4280_midi_close, 167 cs4280_midi_output, 168 cs4280_midi_getinfo, 169 0, 170 }; 171 #endif 172 173 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 174 cs4280_match, cs4280_attach, NULL, NULL); 175 176 struct audio_device cs4280_device = { 177 "CS4280", 178 "", 179 "cs4280" 180 }; 181 182 183 int 184 cs4280_match(parent, match, aux) 185 struct device *parent; 186 struct cfdata *match; 187 void *aux; 188 { 189 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 190 191 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 192 return 0; 193 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 194 #if 0 /* I can't confirm */ 195 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 196 #endif 197 ) 198 return 1; 199 return 0; 200 } 201 202 void 203 cs4280_attach(parent, self, aux) 204 struct device *parent; 205 struct device *self; 206 void *aux; 207 { 208 struct cs428x_softc *sc = (struct cs428x_softc *)self; 209 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 210 pci_chipset_tag_t pc = pa->pa_pc; 211 char const *intrstr; 212 pci_intr_handle_t ih; 213 pcireg_t reg; 214 char devinfo[256]; 215 mixer_ctrl_t ctl; 216 u_int32_t mem; 217 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 218 219 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 220 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 221 222 /* Map I/O register */ 223 if (pci_mapreg_map(pa, PCI_BA0, 224 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 225 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 226 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 227 return; 228 } 229 if (pci_mapreg_map(pa, PCI_BA1, 230 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 231 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 232 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 233 return; 234 } 235 236 sc->sc_dmatag = pa->pa_dmat; 237 238 /* Check and set Power State */ 239 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 240 &pci_pwrmgmt_cap_reg, 0)) { 241 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 242 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 243 pci_pwrmgmt_csr_reg); 244 DPRINTF(("%s: Power State is %d\n", 245 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 246 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 247 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 248 (reg & ~PCI_PMCSR_STATE_MASK) | 249 PCI_PMCSR_STATE_D0); 250 } 251 } 252 253 /* Enable the device (set bus master flag) */ 254 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 255 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 256 reg | PCI_COMMAND_MASTER_ENABLE); 257 258 /* LATENCY_TIMER setting */ 259 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 260 if ( PCI_LATTIMER(mem) < 32 ) { 261 mem &= 0xffff00ff; 262 mem |= 0x00002000; 263 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 264 } 265 266 /* Map and establish the interrupt. */ 267 if (pci_intr_map(pa, &ih)) { 268 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 269 return; 270 } 271 intrstr = pci_intr_string(pc, ih); 272 273 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 274 if (sc->sc_ih == NULL) { 275 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 276 if (intrstr != NULL) 277 printf(" at %s", intrstr); 278 printf("\n"); 279 return; 280 } 281 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 282 283 /* Initialization */ 284 if(cs4280_init(sc, 1) != 0) 285 return; 286 287 sc->type = TYPE_CS4280; 288 sc->halt_input = cs4280_halt_input; 289 sc->halt_output = cs4280_halt_output; 290 291 /* setup buffer related parameters */ 292 sc->dma_size = CS4280_DCHUNK; 293 sc->dma_align = CS4280_DALIGN; 294 sc->hw_blocksize = CS4280_ICHUNK; 295 296 /* AC 97 attachment */ 297 sc->host_if.arg = sc; 298 sc->host_if.attach = cs428x_attach_codec; 299 sc->host_if.read = cs428x_read_codec; 300 sc->host_if.write = cs428x_write_codec; 301 sc->host_if.reset = cs4280_reset_codec; 302 if (ac97_attach(&sc->host_if) != 0) { 303 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 304 return; 305 } 306 307 /* Turn mute off of DAC, CD and master volumes by default */ 308 ctl.type = AUDIO_MIXER_ENUM; 309 ctl.un.ord = 0; /* off */ 310 311 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 312 AudioNmaster, AudioNmute); 313 cs428x_mixer_set_port(sc, &ctl); 314 315 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 316 AudioNdac, AudioNmute); 317 cs428x_mixer_set_port(sc, &ctl); 318 319 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 320 AudioNcd, AudioNmute); 321 cs428x_mixer_set_port(sc, &ctl); 322 323 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 324 325 #if NMIDI > 0 326 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 327 #endif 328 329 sc->sc_suspend = PWR_RESUME; 330 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 331 } 332 333 /* Interrupt handling function */ 334 int 335 cs4280_intr(p) 336 void *p; 337 { 338 /* 339 * XXX 340 * 341 * Since CS4280 has only 4kB dma buffer and 342 * interrupt occurs every 2kB block, I create dummy buffer 343 * which returns to audio driver and actual dma buffer 344 * using in DMA transfer. 345 * 346 * 347 * ring buffer in audio.c is pointed by BUFADDR 348 * <------ ring buffer size == 64kB ------> 349 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 350 * |= = = =|= = = =|= = = =|= = = =|= = = =| 351 * | | | | | | <- call audio_intp every 352 * sc->sc_[pr]_count time. 353 * 354 * actual dma buffer is pointed by KERNADDR 355 * <-> dma buffer size = 4kB 356 * |= =| 357 * 358 * 359 */ 360 struct cs428x_softc *sc = p; 361 u_int32_t intr, mem; 362 char * empty_dma; 363 int handled = 0; 364 365 /* grab interrupt register then clear it */ 366 intr = BA0READ4(sc, CS4280_HISR); 367 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 368 369 /* Playback Interrupt */ 370 if (intr & HISR_PINT) { 371 handled = 1; 372 mem = BA1READ4(sc, CS4280_PFIE); 373 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 374 if (sc->sc_pintr) { 375 if ((sc->sc_pi%sc->sc_pcount) == 0) 376 sc->sc_pintr(sc->sc_parg); 377 } else { 378 printf("unexpected play intr\n"); 379 } 380 /* copy buffer */ 381 ++sc->sc_pi; 382 empty_dma = sc->sc_pdma->addr; 383 if (sc->sc_pi&1) 384 empty_dma += sc->hw_blocksize; 385 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 386 sc->sc_pn += sc->hw_blocksize; 387 if (sc->sc_pn >= sc->sc_pe) 388 sc->sc_pn = sc->sc_ps; 389 BA1WRITE4(sc, CS4280_PFIE, mem); 390 } 391 /* Capture Interrupt */ 392 if (intr & HISR_CINT) { 393 int i; 394 int16_t rdata; 395 396 handled = 1; 397 mem = BA1READ4(sc, CS4280_CIE); 398 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 399 ++sc->sc_ri; 400 empty_dma = sc->sc_rdma->addr; 401 if ((sc->sc_ri&1) == 0) 402 empty_dma += sc->hw_blocksize; 403 404 /* 405 * XXX 406 * I think this audio data conversion should be 407 * happend in upper layer, but I put this here 408 * since there is no conversion function available. 409 */ 410 switch(sc->sc_rparam) { 411 case CF_16BIT_STEREO: 412 /* just copy it */ 413 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 414 sc->sc_rn += sc->hw_blocksize; 415 break; 416 case CF_16BIT_MONO: 417 for (i = 0; i < 512; i++) { 418 rdata = *((int16_t *)empty_dma)++>>1; 419 rdata += *((int16_t *)empty_dma)++>>1; 420 *((int16_t *)sc->sc_rn)++ = rdata; 421 } 422 break; 423 case CF_8BIT_STEREO: 424 for (i = 0; i < 512; i++) { 425 rdata = *((int16_t*)empty_dma)++; 426 *sc->sc_rn++ = rdata >> 8; 427 rdata = *((int16_t*)empty_dma)++; 428 *sc->sc_rn++ = rdata >> 8; 429 } 430 break; 431 case CF_8BIT_MONO: 432 for (i = 0; i < 512; i++) { 433 rdata = *((int16_t*)empty_dma)++ >>1; 434 rdata += *((int16_t*)empty_dma)++ >>1; 435 *sc->sc_rn++ = rdata >>8; 436 } 437 break; 438 default: 439 /* Should not reach here */ 440 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 441 } 442 if (sc->sc_rn >= sc->sc_re) 443 sc->sc_rn = sc->sc_rs; 444 BA1WRITE4(sc, CS4280_CIE, mem); 445 if (sc->sc_rintr) { 446 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 447 sc->sc_rintr(sc->sc_rarg); 448 } else { 449 printf("unexpected record intr\n"); 450 } 451 } 452 453 #if NMIDI > 0 454 /* Midi port Interrupt */ 455 if (intr & HISR_MIDI) { 456 int data; 457 458 handled = 1; 459 DPRINTF(("i: %d: ", 460 BA0READ4(sc, CS4280_MIDSR))); 461 /* Read the received data */ 462 while ((sc->sc_iintr != NULL) && 463 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 464 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 465 DPRINTF(("r:%x\n",data)); 466 sc->sc_iintr(sc->sc_arg, data); 467 } 468 469 /* Write the data */ 470 #if 1 471 /* XXX: 472 * It seems "Transmit Buffer Full" never activate until EOI 473 * is deliverd. Shall I throw EOI top of this routine ? 474 */ 475 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 476 DPRINTF(("w: ")); 477 if (sc->sc_ointr != NULL) 478 sc->sc_ointr(sc->sc_arg); 479 } 480 #else 481 while ((sc->sc_ointr != NULL) && 482 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 483 DPRINTF(("w: ")); 484 sc->sc_ointr(sc->sc_arg); 485 } 486 #endif 487 DPRINTF(("\n")); 488 } 489 #endif 490 491 return handled; 492 } 493 494 int 495 cs4280_query_encoding(addr, fp) 496 void *addr; 497 struct audio_encoding *fp; 498 { 499 switch (fp->index) { 500 case 0: 501 strcpy(fp->name, AudioEulinear); 502 fp->encoding = AUDIO_ENCODING_ULINEAR; 503 fp->precision = 8; 504 fp->flags = 0; 505 break; 506 case 1: 507 strcpy(fp->name, AudioEmulaw); 508 fp->encoding = AUDIO_ENCODING_ULAW; 509 fp->precision = 8; 510 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 511 break; 512 case 2: 513 strcpy(fp->name, AudioEalaw); 514 fp->encoding = AUDIO_ENCODING_ALAW; 515 fp->precision = 8; 516 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 517 break; 518 case 3: 519 strcpy(fp->name, AudioEslinear); 520 fp->encoding = AUDIO_ENCODING_SLINEAR; 521 fp->precision = 8; 522 fp->flags = 0; 523 break; 524 case 4: 525 strcpy(fp->name, AudioEslinear_le); 526 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 527 fp->precision = 16; 528 fp->flags = 0; 529 break; 530 case 5: 531 strcpy(fp->name, AudioEulinear_le); 532 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 533 fp->precision = 16; 534 fp->flags = 0; 535 break; 536 case 6: 537 strcpy(fp->name, AudioEslinear_be); 538 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 539 fp->precision = 16; 540 fp->flags = 0; 541 break; 542 case 7: 543 strcpy(fp->name, AudioEulinear_be); 544 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 545 fp->precision = 16; 546 fp->flags = 0; 547 break; 548 default: 549 return EINVAL; 550 } 551 return 0; 552 } 553 554 int 555 cs4280_set_params(addr, setmode, usemode, play, rec) 556 void *addr; 557 int setmode, usemode; 558 struct audio_params *play, *rec; 559 { 560 struct cs428x_softc *sc = addr; 561 struct audio_params *p; 562 int mode; 563 564 for (mode = AUMODE_RECORD; mode != -1; 565 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 566 if ((setmode & mode) == 0) 567 continue; 568 569 p = mode == AUMODE_PLAY ? play : rec; 570 571 if (p == play) { 572 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 573 p->sample_rate, p->precision, p->channels)); 574 /* play back data format may be 8- or 16-bit and 575 * either stereo or mono. 576 * playback rate may range from 8000Hz to 48000Hz 577 */ 578 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 579 (p->precision != 8 && p->precision != 16) || 580 (p->channels != 1 && p->channels != 2) ) { 581 return EINVAL; 582 } 583 } else { 584 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 585 p->sample_rate, p->precision, p->channels)); 586 /* capture data format must be 16bit stereo 587 * and sample rate range from 11025Hz to 48000Hz. 588 * 589 * XXX: it looks like to work with 8000Hz, 590 * although data sheets say lower limit is 591 * 11025 Hz. 592 */ 593 594 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 595 (p->precision != 8 && p->precision != 16) || 596 (p->channels != 1 && p->channels != 2) ) { 597 return EINVAL; 598 } 599 } 600 p->factor = 1; 601 p->sw_code = 0; 602 603 /* capturing data is slinear */ 604 switch (p->encoding) { 605 case AUDIO_ENCODING_SLINEAR_BE: 606 if (mode == AUMODE_RECORD) { 607 if (p->precision == 16) 608 p->sw_code = swap_bytes; 609 } 610 break; 611 case AUDIO_ENCODING_SLINEAR_LE: 612 break; 613 case AUDIO_ENCODING_ULINEAR_BE: 614 if (mode == AUMODE_RECORD) { 615 if (p->precision == 16) 616 p->sw_code = change_sign16_swap_bytes_le; 617 else 618 p->sw_code = change_sign8; 619 } 620 break; 621 case AUDIO_ENCODING_ULINEAR_LE: 622 if (mode == AUMODE_RECORD) { 623 if (p->precision == 16) 624 p->sw_code = change_sign16_le; 625 else 626 p->sw_code = change_sign8; 627 } 628 break; 629 case AUDIO_ENCODING_ULAW: 630 if (mode == AUMODE_PLAY) { 631 p->factor = 2; 632 p->sw_code = mulaw_to_slinear16_le; 633 } else { 634 p->sw_code = slinear8_to_mulaw; 635 } 636 break; 637 case AUDIO_ENCODING_ALAW: 638 if (mode == AUMODE_PLAY) { 639 p->factor = 2; 640 p->sw_code = alaw_to_slinear16_le; 641 } else { 642 p->sw_code = slinear8_to_alaw; 643 } 644 break; 645 default: 646 return EINVAL; 647 } 648 } 649 650 /* set sample rate */ 651 cs4280_set_dac_rate(sc, play->sample_rate); 652 cs4280_set_adc_rate(sc, rec->sample_rate); 653 return 0; 654 } 655 656 int 657 cs4280_halt_output(addr) 658 void *addr; 659 { 660 struct cs428x_softc *sc = addr; 661 u_int32_t mem; 662 663 mem = BA1READ4(sc, CS4280_PCTL); 664 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 665 sc->sc_prun = 0; 666 return 0; 667 } 668 669 int 670 cs4280_halt_input(addr) 671 void *addr; 672 { 673 struct cs428x_softc *sc = addr; 674 u_int32_t mem; 675 676 mem = BA1READ4(sc, CS4280_CCTL); 677 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 678 sc->sc_rrun = 0; 679 return 0; 680 } 681 682 int 683 cs4280_getdev(addr, retp) 684 void *addr; 685 struct audio_device *retp; 686 { 687 *retp = cs4280_device; 688 return 0; 689 } 690 691 int 692 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 693 void *addr; 694 void *start, *end; 695 int blksize; 696 void (*intr) __P((void *)); 697 void *arg; 698 struct audio_params *param; 699 { 700 struct cs428x_softc *sc = addr; 701 u_int32_t pfie, pctl, pdtc; 702 struct cs428x_dma *p; 703 704 #ifdef DIAGNOSTIC 705 if (sc->sc_prun) 706 printf("cs4280_trigger_output: already running\n"); 707 #endif 708 sc->sc_prun = 1; 709 710 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 711 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 712 sc->sc_pintr = intr; 713 sc->sc_parg = arg; 714 715 /* stop playback DMA */ 716 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 717 718 /* setup PDTC */ 719 pdtc = BA1READ4(sc, CS4280_PDTC); 720 pdtc &= ~PDTC_MASK; 721 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 722 BA1WRITE4(sc, CS4280_PDTC, pdtc); 723 724 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 725 param->precision, param->factor, param->channels, 726 param->encoding)); 727 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 728 ; 729 if (p == NULL) { 730 printf("cs4280_trigger_output: bad addr %p\n", start); 731 return EINVAL; 732 } 733 if (DMAADDR(p) % sc->dma_align != 0 ) { 734 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 735 "4kB align\n", (ulong)DMAADDR(p)); 736 return EINVAL; 737 } 738 739 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 740 sc->sc_ps = (char *)start; 741 sc->sc_pe = (char *)end; 742 sc->sc_pdma = p; 743 sc->sc_pbuf = KERNADDR(p); 744 sc->sc_pi = 0; 745 sc->sc_pn = sc->sc_ps; 746 if (blksize >= sc->dma_size) { 747 sc->sc_pn = sc->sc_ps + sc->dma_size; 748 memcpy(sc->sc_pbuf, start, sc->dma_size); 749 ++sc->sc_pi; 750 } else { 751 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 752 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 753 } 754 755 /* initiate playback dma */ 756 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 757 758 /* set PFIE */ 759 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 760 761 if (param->precision * param->factor == 8) 762 pfie |= PFIE_8BIT; 763 if (param->channels == 1) 764 pfie |= PFIE_MONO; 765 766 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 767 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 768 pfie |= PFIE_SWAPPED; 769 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 770 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 771 pfie |= PFIE_UNSIGNED; 772 773 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 774 775 sc->sc_prate = param->sample_rate; 776 cs4280_set_dac_rate(sc, param->sample_rate); 777 778 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 779 pctl |= sc->pctl; 780 BA1WRITE4(sc, CS4280_PCTL, pctl); 781 return 0; 782 } 783 784 int 785 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 786 void *addr; 787 void *start, *end; 788 int blksize; 789 void (*intr) __P((void *)); 790 void *arg; 791 struct audio_params *param; 792 { 793 struct cs428x_softc *sc = addr; 794 u_int32_t cctl, cie; 795 struct cs428x_dma *p; 796 797 #ifdef DIAGNOSTIC 798 if (sc->sc_rrun) 799 printf("cs4280_trigger_input: already running\n"); 800 #endif 801 sc->sc_rrun = 1; 802 803 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 804 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 805 sc->sc_rintr = intr; 806 sc->sc_rarg = arg; 807 808 /* stop capture DMA */ 809 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 810 811 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 812 ; 813 if (p == NULL) { 814 printf("cs4280_trigger_input: bad addr %p\n", start); 815 return EINVAL; 816 } 817 if (DMAADDR(p) % sc->dma_align != 0) { 818 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 819 "4kB align\n", (ulong)DMAADDR(p)); 820 return EINVAL; 821 } 822 823 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 824 sc->sc_rs = (char *)start; 825 sc->sc_re = (char *)end; 826 sc->sc_rdma = p; 827 sc->sc_rbuf = KERNADDR(p); 828 sc->sc_ri = 0; 829 sc->sc_rn = sc->sc_rs; 830 831 /* initiate capture dma */ 832 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 833 834 /* setup format information for internal converter */ 835 sc->sc_rparam = 0; 836 if (param->precision == 8) { 837 sc->sc_rparam += CF_8BIT; 838 sc->sc_rcount <<= 1; 839 } 840 if (param->channels == 1) { 841 sc->sc_rparam += CF_MONO; 842 sc->sc_rcount <<= 1; 843 } 844 845 /* set CIE */ 846 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 847 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 848 849 sc->sc_rrate = param->sample_rate; 850 cs4280_set_adc_rate(sc, param->sample_rate); 851 852 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 853 cctl |= sc->cctl; 854 BA1WRITE4(sc, CS4280_CCTL, cctl); 855 return 0; 856 } 857 858 /* Power Hook */ 859 void 860 cs4280_power(why, v) 861 int why; 862 void *v; 863 { 864 struct cs428x_softc *sc = (struct cs428x_softc *)v; 865 static u_int32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 866 static u_int32_t cctl = 0, cba = 0, cie = 0; 867 868 DPRINTF(("%s: cs4280_power why=%d\n", 869 sc->sc_dev.dv_xname, why)); 870 switch (why) { 871 case PWR_SUSPEND: 872 case PWR_STANDBY: 873 sc->sc_suspend = why; 874 875 /* save current playback status */ 876 if ( sc->sc_prun ) { 877 pctl = BA1READ4(sc, CS4280_PCTL); 878 pfie = BA1READ4(sc, CS4280_PFIE); 879 pba = BA1READ4(sc, CS4280_PBA); 880 pdtc = BA1READ4(sc, CS4280_PDTC); 881 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 882 pctl, pfie, pba, pdtc)); 883 } 884 885 /* save current capture status */ 886 if ( sc->sc_rrun ) { 887 cctl = BA1READ4(sc, CS4280_CCTL); 888 cie = BA1READ4(sc, CS4280_CIE); 889 cba = BA1READ4(sc, CS4280_CBA); 890 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 891 cctl, cie, cba)); 892 } 893 894 /* Stop DMA */ 895 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 896 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 897 break; 898 case PWR_RESUME: 899 if (sc->sc_suspend == PWR_RESUME) { 900 printf("cs4280_power: odd, resume without suspend.\n"); 901 sc->sc_suspend = why; 902 return; 903 } 904 sc->sc_suspend = why; 905 cs4280_init(sc, 0); 906 cs4280_reset_codec(sc); 907 908 /* restore ac97 registers */ 909 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 910 911 /* restore DMA related status */ 912 if(sc->sc_prun) { 913 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 914 pctl, pfie, pba, pdtc)); 915 cs4280_set_dac_rate(sc, sc->sc_prate); 916 BA1WRITE4(sc, CS4280_PDTC, pdtc); 917 BA1WRITE4(sc, CS4280_PBA, pba); 918 BA1WRITE4(sc, CS4280_PFIE, pfie); 919 BA1WRITE4(sc, CS4280_PCTL, pctl); 920 } 921 922 if (sc->sc_rrun) { 923 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 924 cctl, cie, cba)); 925 cs4280_set_adc_rate(sc, sc->sc_rrate); 926 BA1WRITE4(sc, CS4280_CBA, cba); 927 BA1WRITE4(sc, CS4280_CIE, cie); 928 BA1WRITE4(sc, CS4280_CCTL, cctl); 929 } 930 break; 931 case PWR_SOFTSUSPEND: 932 case PWR_SOFTSTANDBY: 933 case PWR_SOFTRESUME: 934 break; 935 } 936 } 937 938 /* control AC97 codec */ 939 void 940 cs4280_reset_codec(void *addr) 941 { 942 struct cs428x_softc *sc; 943 int n; 944 945 sc = addr; 946 947 /* Reset codec */ 948 BA0WRITE4(sc, CS428X_ACCTL, 0); 949 delay(100); /* delay 100us */ 950 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 951 952 /* 953 * It looks like we do the following procedure, too 954 */ 955 956 /* Enable AC-link sync generation */ 957 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 958 delay(50*1000); /* XXX delay 50ms */ 959 960 /* Assert valid frame signal */ 961 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 962 963 /* Wait for valid AC97 input slot */ 964 n = 0; 965 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 966 (ACISV_ISV3 | ACISV_ISV4)) { 967 delay(1000); 968 if (++n > 1000) { 969 printf("reset_codec: AC97 inputs slot ready timeout\n"); 970 return; 971 } 972 } 973 } 974 975 976 /* Internal functions */ 977 978 void 979 cs4280_set_adc_rate(sc, rate) 980 struct cs428x_softc *sc; 981 int rate; 982 { 983 /* calculate capture rate: 984 * 985 * capture_coefficient_increment = -round(rate*128*65536/48000; 986 * capture_phase_increment = floor(48000*65536*1024/rate); 987 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 988 * cy = floor(cx/200); 989 * capture_sample_rate_correction = cx - 200*cy; 990 * capture_delay = ceil(24*48000/rate); 991 * capture_num_triplets = floor(65536*rate/24000); 992 * capture_group_length = 24000/GCD(rate, 24000); 993 * where GCD means "Greatest Common Divisor". 994 * 995 * capture_coefficient_increment, capture_phase_increment and 996 * capture_num_triplets are 32-bit signed quantities. 997 * capture_sample_rate_correction and capture_group_length are 998 * 16-bit signed quantities. 999 * capture_delay is a 14-bit unsigned quantity. 1000 */ 1001 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 1002 u_int16_t csrc, cgl, cdlay; 1003 1004 /* XXX 1005 * Even though, embedded_audio_spec says capture rate range 11025 to 1006 * 48000, dhwiface.cpp says, 1007 * 1008 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1009 * Return an error if an attempt is made to stray outside that limit." 1010 * 1011 * so assume range as 48000/9 to 48000 1012 */ 1013 1014 if (rate < 8000) 1015 rate = 8000; 1016 if (rate > 48000) 1017 rate = 48000; 1018 1019 cx = rate << 16; 1020 cci = cx / 48000; 1021 cx -= cci * 48000; 1022 cx <<= 7; 1023 cci <<= 7; 1024 cci += cx / 48000; 1025 cci = - cci; 1026 1027 cx = 48000 << 16; 1028 cpi = cx / rate; 1029 cx -= cpi * rate; 1030 cx <<= 10; 1031 cpi <<= 10; 1032 cy = cx / rate; 1033 cpi += cy; 1034 cx -= cy * rate; 1035 1036 cy = cx / 200; 1037 csrc = cx - 200*cy; 1038 1039 cdlay = ((48000 * 24) + rate - 1) / rate; 1040 #if 0 1041 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1042 #endif 1043 1044 cnt = rate << 16; 1045 cnt /= 24000; 1046 1047 cgl = 1; 1048 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1049 if (((rate / tmp1) * tmp1) != rate) 1050 cgl *= 2; 1051 } 1052 if (((rate / 3) * 3) != rate) 1053 cgl *= 3; 1054 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1055 if (((rate / tmp1) * tmp1) != rate) 1056 cgl *= 5; 1057 } 1058 #if 0 1059 /* XXX what manual says */ 1060 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1061 tmp1 |= csrc<<16; 1062 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1063 #else 1064 /* suggested by cs461x.c (ALSA driver) */ 1065 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1066 #endif 1067 1068 #if 0 1069 /* I am confused. The sample rate calculation section says 1070 * cci *is* 32-bit signed quantity but in the parameter description 1071 * section, CCI only assigned 16bit. 1072 * I believe size of the variable. 1073 */ 1074 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1075 tmp1 |= cci<<16; 1076 BA1WRITE4(sc, CS4280_CCI, tmp1); 1077 #else 1078 BA1WRITE4(sc, CS4280_CCI, cci); 1079 #endif 1080 1081 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1082 tmp1 |= cdlay <<18; 1083 BA1WRITE4(sc, CS4280_CD, tmp1); 1084 1085 BA1WRITE4(sc, CS4280_CPI, cpi); 1086 1087 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1088 tmp1 |= cgl; 1089 BA1WRITE4(sc, CS4280_CGL, tmp1); 1090 1091 BA1WRITE4(sc, CS4280_CNT, cnt); 1092 1093 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1094 tmp1 |= cgl; 1095 BA1WRITE4(sc, CS4280_CGC, tmp1); 1096 } 1097 1098 void 1099 cs4280_set_dac_rate(sc, rate) 1100 struct cs428x_softc *sc; 1101 int rate; 1102 { 1103 /* 1104 * playback rate may range from 8000Hz to 48000Hz 1105 * 1106 * play_phase_increment = floor(rate*65536*1024/48000) 1107 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1108 * py=floor(px/200) 1109 * play_sample_rate_correction = px - 200*py 1110 * 1111 * play_phase_increment is a 32bit signed quantity. 1112 * play_sample_rate_correction is a 16bit signed quantity. 1113 */ 1114 int32_t ppi; 1115 int16_t psrc; 1116 u_int32_t px, py; 1117 1118 if (rate < 8000) 1119 rate = 8000; 1120 if (rate > 48000) 1121 rate = 48000; 1122 px = rate << 16; 1123 ppi = px/48000; 1124 px -= ppi*48000; 1125 ppi <<= 10; 1126 px <<= 10; 1127 py = px / 48000; 1128 ppi += py; 1129 px -= py*48000; 1130 py = px/200; 1131 px -= py*200; 1132 psrc = px; 1133 #if 0 1134 /* what manual says */ 1135 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1136 BA1WRITE4(sc, CS4280_PSRC, 1137 ( ((psrc<<16) & PSRC_MASK) | px )); 1138 #else 1139 /* suggested by cs461x.c (ALSA driver) */ 1140 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1141 #endif 1142 BA1WRITE4(sc, CS4280_PPI, ppi); 1143 } 1144 1145 /* Download Proceessor Code and Data image */ 1146 int 1147 cs4280_download(sc, src, offset, len) 1148 struct cs428x_softc *sc; 1149 const u_int32_t *src; 1150 u_int32_t offset, len; 1151 { 1152 u_int32_t ctr; 1153 1154 #if CS4280_DEBUG > 10 1155 u_int32_t con, data; 1156 u_int8_t c0,c1,c2,c3; 1157 #endif 1158 if ((offset&3) || (len&3)) 1159 return -1; 1160 1161 len /= sizeof(u_int32_t); 1162 for (ctr = 0; ctr < len; ctr++) { 1163 /* XXX: 1164 * I cannot confirm this is the right thing or not 1165 * on BIG-ENDIAN machines. 1166 */ 1167 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1168 #if CS4280_DEBUG > 10 1169 data = htole32(*(src+ctr)); 1170 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1171 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1172 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1173 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1174 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 1175 if (data != con ) { 1176 printf("0x%06x: write=0x%08x read=0x%08x\n", 1177 offset+ctr*4, data, con); 1178 return -1; 1179 } 1180 #endif 1181 } 1182 return 0; 1183 } 1184 1185 int 1186 cs4280_download_image(sc) 1187 struct cs428x_softc *sc; 1188 { 1189 int idx, err; 1190 u_int32_t offset = 0; 1191 1192 err = 0; 1193 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1194 err = cs4280_download(sc, &BA1Struct.map[offset], 1195 BA1Struct.memory[idx].offset, 1196 BA1Struct.memory[idx].size); 1197 if (err != 0) { 1198 printf("%s: load_image failed at %d\n", 1199 sc->sc_dev.dv_xname, idx); 1200 return -1; 1201 } 1202 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1203 } 1204 return err; 1205 } 1206 1207 /* Processor Soft Reset */ 1208 void 1209 cs4280_reset(sc_) 1210 void *sc_; 1211 { 1212 struct cs428x_softc *sc = sc_; 1213 1214 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1215 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1216 delay(100); 1217 /* Clear RSTSP bit in SPCR */ 1218 BA1WRITE4(sc, CS4280_SPCR, 0); 1219 /* enable DMA reqest */ 1220 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1221 } 1222 1223 int 1224 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1225 struct cs428x_softc *sc; 1226 char *class, *device, *qualifier; 1227 { 1228 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1229 device, qualifier)); 1230 } 1231 1232 int 1233 cs4280_init(sc, init) 1234 struct cs428x_softc *sc; 1235 int init; 1236 { 1237 int n; 1238 u_int32_t mem; 1239 1240 /* Start PLL out in known state */ 1241 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1242 /* Start serial ports out in known state */ 1243 BA0WRITE4(sc, CS4280_SERMC1, 0); 1244 1245 /* Specify type of CODEC */ 1246 /* XXX should not be here */ 1247 #define SERACC_CODEC_TYPE_1_03 1248 #ifdef SERACC_CODEC_TYPE_1_03 1249 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1250 #else 1251 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1252 #endif 1253 1254 /* Reset codec */ 1255 BA0WRITE4(sc, CS428X_ACCTL, 0); 1256 delay(100); /* delay 100us */ 1257 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1258 1259 /* Enable AC-link sync generation */ 1260 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1261 delay(50*1000); /* delay 50ms */ 1262 1263 /* Set the serial port timing configuration */ 1264 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1265 1266 /* Setup clock control */ 1267 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1268 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1269 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1270 1271 /* Power up the PLL */ 1272 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1273 delay(50*1000); /* delay 50ms */ 1274 1275 /* Turn on clock */ 1276 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1277 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1278 1279 /* Set the serial port FIFO pointer to the 1280 * first sample in FIFO. (not documented) */ 1281 cs4280_clear_fifos(sc); 1282 1283 #if 0 1284 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1285 BA0WRITE4(sc, CS4280_SERBSP, 0); 1286 #endif 1287 1288 /* Configure the serial port */ 1289 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1290 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1291 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1292 1293 /* Wait for CODEC ready */ 1294 n = 0; 1295 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1296 delay(125); 1297 if (++n > 1000) { 1298 printf("%s: codec ready timeout\n", 1299 sc->sc_dev.dv_xname); 1300 return(1); 1301 } 1302 } 1303 1304 /* Assert valid frame signal */ 1305 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1306 1307 /* Wait for valid AC97 input slot */ 1308 n = 0; 1309 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1310 (ACISV_ISV3 | ACISV_ISV4)) { 1311 delay(1000); 1312 if (++n > 1000) { 1313 printf("AC97 inputs slot ready timeout\n"); 1314 return(1); 1315 } 1316 } 1317 1318 /* Set AC97 output slot valid signals */ 1319 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1320 1321 /* reset the processor */ 1322 cs4280_reset(sc); 1323 1324 /* Download the image to the processor */ 1325 if (cs4280_download_image(sc) != 0) { 1326 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1327 return(1); 1328 } 1329 1330 /* Save playback parameter and then write zero. 1331 * this ensures that DMA doesn't immediately occur upon 1332 * starting the processor core 1333 */ 1334 mem = BA1READ4(sc, CS4280_PCTL); 1335 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1336 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1337 if (init != 0) 1338 sc->sc_prun = 0; 1339 1340 /* Save capture parameter and then write zero. 1341 * this ensures that DMA doesn't immediately occur upon 1342 * starting the processor core 1343 */ 1344 mem = BA1READ4(sc, CS4280_CCTL); 1345 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1346 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1347 if (init != 0) 1348 sc->sc_rrun = 0; 1349 1350 /* Processor Startup Procedure */ 1351 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1352 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1353 1354 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1355 n = 0; 1356 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1357 delay(10); 1358 if (++n > 1000) { 1359 printf("SPCR 1->0 transition timeout\n"); 1360 return(1); 1361 } 1362 } 1363 1364 n = 0; 1365 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1366 delay(10); 1367 if (++n > 1000) { 1368 printf("SPCS 0->1 transition timeout\n"); 1369 return(1); 1370 } 1371 } 1372 /* Processor is now running !!! */ 1373 1374 /* Setup volume */ 1375 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1376 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1377 1378 /* Interrupt enable */ 1379 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1380 1381 /* playback interrupt enable */ 1382 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1383 mem |= PFIE_PI_ENABLE; 1384 BA1WRITE4(sc, CS4280_PFIE, mem); 1385 /* capture interrupt enable */ 1386 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1387 mem |= CIE_CI_ENABLE; 1388 BA1WRITE4(sc, CS4280_CIE, mem); 1389 1390 #if NMIDI > 0 1391 /* Reset midi port */ 1392 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1393 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1394 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1395 /* midi interrupt enable */ 1396 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1397 BA0WRITE4(sc, CS4280_MIDCR, mem); 1398 #endif 1399 return(0); 1400 } 1401 1402 void 1403 cs4280_clear_fifos(sc) 1404 struct cs428x_softc *sc; 1405 { 1406 int pd = 0, cnt, n; 1407 u_int32_t mem; 1408 1409 /* 1410 * If device power down, power up the device and keep power down 1411 * state. 1412 */ 1413 mem = BA0READ4(sc, CS4280_CLKCR1); 1414 if (!(mem & CLKCR1_SWCE)) { 1415 printf("cs4280_clear_fifo: power down found.\n"); 1416 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1417 pd = 1; 1418 } 1419 BA0WRITE4(sc, CS4280_SERBWP, 0); 1420 for (cnt = 0; cnt < 256; cnt++) { 1421 n = 0; 1422 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1423 delay(1000); 1424 if (++n > 1000) { 1425 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1426 break; 1427 } 1428 } 1429 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1430 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1431 } 1432 if (pd) 1433 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1434 } 1435 1436 #if NMIDI > 0 1437 int 1438 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1439 void *addr; 1440 int flags; 1441 void (*iintr)__P((void *, int)); 1442 void (*ointr)__P((void *)); 1443 void *arg; 1444 { 1445 struct cs428x_softc *sc = addr; 1446 u_int32_t mem; 1447 1448 DPRINTF(("midi_open\n")); 1449 sc->sc_iintr = iintr; 1450 sc->sc_ointr = ointr; 1451 sc->sc_arg = arg; 1452 1453 /* midi interrupt enable */ 1454 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1455 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1456 BA0WRITE4(sc, CS4280_MIDCR, mem); 1457 #ifdef CS4280_DEBUG 1458 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1459 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1460 return(EINVAL); 1461 } 1462 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1463 #endif 1464 return 0; 1465 } 1466 1467 void 1468 cs4280_midi_close(addr) 1469 void *addr; 1470 { 1471 struct cs428x_softc *sc = addr; 1472 u_int32_t mem; 1473 1474 DPRINTF(("midi_close\n")); 1475 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1476 mem = BA0READ4(sc, CS4280_MIDCR); 1477 mem &= ~MIDCR_MASK; 1478 BA0WRITE4(sc, CS4280_MIDCR, mem); 1479 1480 sc->sc_iintr = 0; 1481 sc->sc_ointr = 0; 1482 } 1483 1484 int 1485 cs4280_midi_output(addr, d) 1486 void *addr; 1487 int d; 1488 { 1489 struct cs428x_softc *sc = addr; 1490 u_int32_t mem; 1491 int x; 1492 1493 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1494 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1495 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1496 mem |= d & MIDWP_MASK; 1497 DPRINTFN(5,("midi_output d=0x%08x",d)); 1498 BA0WRITE4(sc, CS4280_MIDWP, mem); 1499 #ifdef DIAGNOSTIC 1500 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1501 DPRINTF(("Bad write data: %d %d", 1502 mem, BA0READ4(sc, CS4280_MIDWP))); 1503 return(EIO); 1504 } 1505 #endif 1506 return 0; 1507 } 1508 delay(MIDI_BUSY_DELAY); 1509 } 1510 return (EIO); 1511 } 1512 1513 void 1514 cs4280_midi_getinfo(addr, mi) 1515 void *addr; 1516 struct midi_info *mi; 1517 { 1518 mi->name = "CS4280 MIDI UART"; 1519 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1520 } 1521 1522 #endif 1523 1524 /* DEBUG functions */ 1525 #if CS4280_DEBUG > 10 1526 int 1527 cs4280_checkimage(sc, src, offset, len) 1528 struct cs428x_softc *sc; 1529 u_int32_t *src; 1530 u_int32_t offset, len; 1531 { 1532 u_int32_t ctr, data; 1533 int err = 0; 1534 1535 if ((offset&3) || (len&3)) 1536 return -1; 1537 1538 len /= sizeof(u_int32_t); 1539 for (ctr = 0; ctr < len; ctr++) { 1540 /* I cannot confirm this is the right thing 1541 * on BIG-ENDIAN machines 1542 */ 1543 data = BA1READ4(sc, offset+ctr*4); 1544 if (data != htole32(*(src+ctr))) { 1545 printf("0x%06x: 0x%08x(0x%08x)\n", 1546 offset+ctr*4, data, *(src+ctr)); 1547 *(src+ctr) = data; 1548 ++err; 1549 } 1550 } 1551 return err; 1552 } 1553 1554 int 1555 cs4280_check_images(sc) 1556 struct cs428x_softc *sc; 1557 { 1558 int idx, err; 1559 u_int32_t offset = 0; 1560 1561 err = 0; 1562 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 1563 for (idx = 0; idx < 1; ++idx) { 1564 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1565 BA1Struct.memory[idx].offset, 1566 BA1Struct.memory[idx].size); 1567 if (err != 0) { 1568 printf("%s: check_image failed at %d\n", 1569 sc->sc_dev.dv_xname, idx); 1570 } 1571 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1572 } 1573 return err; 1574 } 1575 1576 #endif 1577
Indexes created Thu Oct 02 14:10:14 GMT 2025