cs4280.c revision 1.26.2.1
1 /* $NetBSD: cs4280.c,v 1.26.2.1 2004/08/03 10:49:06 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.26.2.1 2004/08/03 10:49:06 skrll Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <machine/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 int cs4280_match(struct device *, struct cfdata *, void *); 93 void cs4280_attach(struct device *, struct device *, void *); 94 int cs4280_intr(void *); 95 int cs4280_query_encoding(void *, struct audio_encoding *); 96 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 97 int cs4280_halt_output(void *); 98 int cs4280_halt_input(void *); 99 int cs4280_getdev(void *, struct audio_device *); 100 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 101 void *, struct audio_params *); 102 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 103 void *, struct audio_params *); 104 105 void cs4280_reset_codec(void *); 106 107 /* For PowerHook */ 108 void cs4280_power(int, void *); 109 110 /* Internal functions */ 111 void cs4280_set_adc_rate(struct cs428x_softc *, int ); 112 void cs4280_set_dac_rate(struct cs428x_softc *, int ); 113 int cs4280_download(struct cs428x_softc *, const u_int32_t *, u_int32_t, u_int32_t); 114 int cs4280_download_image(struct cs428x_softc *); 115 void cs4280_reset(void *); 116 int cs4280_get_portnum_by_name(struct cs428x_softc *, char *, char *, char *); 117 int cs4280_init(struct cs428x_softc *, int); 118 void cs4280_clear_fifos(struct cs428x_softc *); 119 120 #if CS4280_DEBUG > 10 121 /* Thease two function is only for checking image loading is succeeded or not. */ 122 int cs4280_check_images(struct cs428x_softc *); 123 int cs4280_checkimage(struct cs428x_softc *, u_int32_t *, u_int32_t, u_int32_t); 124 #endif 125 126 struct audio_hw_if cs4280_hw_if = { 127 cs428x_open, 128 cs428x_close, 129 NULL, 130 cs4280_query_encoding, 131 cs4280_set_params, 132 cs428x_round_blocksize, 133 NULL, 134 NULL, 135 NULL, 136 NULL, 137 NULL, 138 cs4280_halt_output, 139 cs4280_halt_input, 140 NULL, 141 cs4280_getdev, 142 NULL, 143 cs428x_mixer_set_port, 144 cs428x_mixer_get_port, 145 cs428x_query_devinfo, 146 cs428x_malloc, 147 cs428x_free, 148 cs428x_round_buffersize, 149 cs428x_mappage, 150 cs428x_get_props, 151 cs4280_trigger_output, 152 cs4280_trigger_input, 153 NULL, 154 }; 155 156 #if NMIDI > 0 157 /* Midi Interface */ 158 int cs4280_midi_open(void *, int, void (*)(void *, int), 159 void (*)(void *), void *); 160 void cs4280_midi_close(void*); 161 int cs4280_midi_output(void *, int); 162 void cs4280_midi_getinfo(void *, struct midi_info *); 163 164 struct midi_hw_if cs4280_midi_hw_if = { 165 cs4280_midi_open, 166 cs4280_midi_close, 167 cs4280_midi_output, 168 cs4280_midi_getinfo, 169 0, 170 }; 171 #endif 172 173 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 174 cs4280_match, cs4280_attach, NULL, NULL); 175 176 struct audio_device cs4280_device = { 177 "CS4280", 178 "", 179 "cs4280" 180 }; 181 182 183 int 184 cs4280_match(parent, match, aux) 185 struct device *parent; 186 struct cfdata *match; 187 void *aux; 188 { 189 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 190 191 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 192 return 0; 193 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 194 #if 0 /* I can't confirm */ 195 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 196 #endif 197 ) 198 return 1; 199 return 0; 200 } 201 202 void 203 cs4280_attach(parent, self, aux) 204 struct device *parent; 205 struct device *self; 206 void *aux; 207 { 208 struct cs428x_softc *sc = (struct cs428x_softc *)self; 209 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 210 pci_chipset_tag_t pc = pa->pa_pc; 211 char const *intrstr; 212 pci_intr_handle_t ih; 213 pcireg_t reg; 214 char devinfo[256]; 215 mixer_ctrl_t ctl; 216 u_int32_t mem; 217 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 218 219 aprint_naive(": Audio controller\n"); 220 221 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 222 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 223 PCI_REVISION(pa->pa_class)); 224 225 /* Map I/O register */ 226 if (pci_mapreg_map(pa, PCI_BA0, 227 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 228 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 229 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 230 return; 231 } 232 if (pci_mapreg_map(pa, PCI_BA1, 233 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 234 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 235 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 236 return; 237 } 238 239 sc->sc_dmatag = pa->pa_dmat; 240 241 /* Check and set Power State */ 242 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 243 &pci_pwrmgmt_cap_reg, 0)) { 244 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 245 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 246 pci_pwrmgmt_csr_reg); 247 DPRINTF(("%s: Power State is %d\n", 248 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 249 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 250 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 251 (reg & ~PCI_PMCSR_STATE_MASK) | 252 PCI_PMCSR_STATE_D0); 253 } 254 } 255 256 /* Enable the device (set bus master flag) */ 257 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 258 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 259 reg | PCI_COMMAND_MASTER_ENABLE); 260 261 /* LATENCY_TIMER setting */ 262 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 263 if ( PCI_LATTIMER(mem) < 32 ) { 264 mem &= 0xffff00ff; 265 mem |= 0x00002000; 266 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 267 } 268 269 /* Map and establish the interrupt. */ 270 if (pci_intr_map(pa, &ih)) { 271 aprint_error("%s: couldn't map interrupt\n", 272 sc->sc_dev.dv_xname); 273 return; 274 } 275 intrstr = pci_intr_string(pc, ih); 276 277 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 278 if (sc->sc_ih == NULL) { 279 aprint_error("%s: couldn't establish interrupt", 280 sc->sc_dev.dv_xname); 281 if (intrstr != NULL) 282 aprint_normal(" at %s", intrstr); 283 aprint_normal("\n"); 284 return; 285 } 286 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 287 288 /* Initialization */ 289 if(cs4280_init(sc, 1) != 0) 290 return; 291 292 sc->type = TYPE_CS4280; 293 sc->halt_input = cs4280_halt_input; 294 sc->halt_output = cs4280_halt_output; 295 296 /* setup buffer related parameters */ 297 sc->dma_size = CS4280_DCHUNK; 298 sc->dma_align = CS4280_DALIGN; 299 sc->hw_blocksize = CS4280_ICHUNK; 300 301 /* AC 97 attachment */ 302 sc->host_if.arg = sc; 303 sc->host_if.attach = cs428x_attach_codec; 304 sc->host_if.read = cs428x_read_codec; 305 sc->host_if.write = cs428x_write_codec; 306 sc->host_if.reset = cs4280_reset_codec; 307 if (ac97_attach(&sc->host_if) != 0) { 308 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 309 return; 310 } 311 312 /* Turn mute off of DAC, CD and master volumes by default */ 313 ctl.type = AUDIO_MIXER_ENUM; 314 ctl.un.ord = 0; /* off */ 315 316 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 317 AudioNmaster, AudioNmute); 318 cs428x_mixer_set_port(sc, &ctl); 319 320 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 321 AudioNdac, AudioNmute); 322 cs428x_mixer_set_port(sc, &ctl); 323 324 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 325 AudioNcd, AudioNmute); 326 cs428x_mixer_set_port(sc, &ctl); 327 328 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 329 330 #if NMIDI > 0 331 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 332 #endif 333 334 sc->sc_suspend = PWR_RESUME; 335 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 336 } 337 338 /* Interrupt handling function */ 339 int 340 cs4280_intr(p) 341 void *p; 342 { 343 /* 344 * XXX 345 * 346 * Since CS4280 has only 4kB DMA buffer and 347 * interrupt occurs every 2kB block, I create dummy buffer 348 * which returns to audio driver and actual DMA buffer 349 * using in DMA transfer. 350 * 351 * 352 * ring buffer in audio.c is pointed by BUFADDR 353 * <------ ring buffer size == 64kB ------> 354 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 355 * |= = = =|= = = =|= = = =|= = = =|= = = =| 356 * | | | | | | <- call audio_intp every 357 * sc->sc_[pr]_count time. 358 * 359 * actual DMA buffer is pointed by KERNADDR 360 * <-> DMA buffer size = 4kB 361 * |= =| 362 * 363 * 364 */ 365 struct cs428x_softc *sc = p; 366 u_int32_t intr, mem; 367 char * empty_dma; 368 int handled = 0; 369 370 /* grab interrupt register then clear it */ 371 intr = BA0READ4(sc, CS4280_HISR); 372 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 373 374 /* Playback Interrupt */ 375 if (intr & HISR_PINT) { 376 handled = 1; 377 mem = BA1READ4(sc, CS4280_PFIE); 378 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 379 if (sc->sc_prun) { 380 if ((sc->sc_pi%sc->sc_pcount) == 0) 381 sc->sc_pintr(sc->sc_parg); 382 } else { 383 printf("unexpected play intr\n"); 384 } 385 /* copy buffer */ 386 ++sc->sc_pi; 387 empty_dma = sc->sc_pdma->addr; 388 if (sc->sc_pi&1) 389 empty_dma += sc->hw_blocksize; 390 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 391 sc->sc_pn += sc->hw_blocksize; 392 if (sc->sc_pn >= sc->sc_pe) 393 sc->sc_pn = sc->sc_ps; 394 BA1WRITE4(sc, CS4280_PFIE, mem); 395 } 396 /* Capture Interrupt */ 397 if (intr & HISR_CINT) { 398 int i; 399 int16_t rdata; 400 401 handled = 1; 402 mem = BA1READ4(sc, CS4280_CIE); 403 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 404 ++sc->sc_ri; 405 empty_dma = sc->sc_rdma->addr; 406 if ((sc->sc_ri&1) == 0) 407 empty_dma += sc->hw_blocksize; 408 409 /* 410 * XXX 411 * I think this audio data conversion should be 412 * happend in upper layer, but I put this here 413 * since there is no conversion function available. 414 */ 415 switch(sc->sc_rparam) { 416 case CF_16BIT_STEREO: 417 /* just copy it */ 418 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 419 sc->sc_rn += sc->hw_blocksize; 420 break; 421 case CF_16BIT_MONO: 422 for (i = 0; i < 512; i++) { 423 rdata = *((int16_t *)empty_dma)++>>1; 424 rdata += *((int16_t *)empty_dma)++>>1; 425 *((int16_t *)sc->sc_rn)++ = rdata; 426 } 427 break; 428 case CF_8BIT_STEREO: 429 for (i = 0; i < 512; i++) { 430 rdata = *((int16_t*)empty_dma)++; 431 *sc->sc_rn++ = rdata >> 8; 432 rdata = *((int16_t*)empty_dma)++; 433 *sc->sc_rn++ = rdata >> 8; 434 } 435 break; 436 case CF_8BIT_MONO: 437 for (i = 0; i < 512; i++) { 438 rdata = *((int16_t*)empty_dma)++ >>1; 439 rdata += *((int16_t*)empty_dma)++ >>1; 440 *sc->sc_rn++ = rdata >>8; 441 } 442 break; 443 default: 444 /* Should not reach here */ 445 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 446 } 447 if (sc->sc_rn >= sc->sc_re) 448 sc->sc_rn = sc->sc_rs; 449 BA1WRITE4(sc, CS4280_CIE, mem); 450 if (sc->sc_rrun) { 451 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 452 sc->sc_rintr(sc->sc_rarg); 453 } else { 454 printf("unexpected record intr\n"); 455 } 456 } 457 458 #if NMIDI > 0 459 /* Midi port Interrupt */ 460 if (intr & HISR_MIDI) { 461 int data; 462 463 handled = 1; 464 DPRINTF(("i: %d: ", 465 BA0READ4(sc, CS4280_MIDSR))); 466 /* Read the received data */ 467 while ((sc->sc_iintr != NULL) && 468 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 469 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 470 DPRINTF(("r:%x\n",data)); 471 sc->sc_iintr(sc->sc_arg, data); 472 } 473 474 /* Write the data */ 475 #if 1 476 /* XXX: 477 * It seems "Transmit Buffer Full" never activate until EOI 478 * is deliverd. Shall I throw EOI top of this routine ? 479 */ 480 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 481 DPRINTF(("w: ")); 482 if (sc->sc_ointr != NULL) 483 sc->sc_ointr(sc->sc_arg); 484 } 485 #else 486 while ((sc->sc_ointr != NULL) && 487 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 488 DPRINTF(("w: ")); 489 sc->sc_ointr(sc->sc_arg); 490 } 491 #endif 492 DPRINTF(("\n")); 493 } 494 #endif 495 496 return handled; 497 } 498 499 int 500 cs4280_query_encoding(addr, fp) 501 void *addr; 502 struct audio_encoding *fp; 503 { 504 switch (fp->index) { 505 case 0: 506 strcpy(fp->name, AudioEulinear); 507 fp->encoding = AUDIO_ENCODING_ULINEAR; 508 fp->precision = 8; 509 fp->flags = 0; 510 break; 511 case 1: 512 strcpy(fp->name, AudioEmulaw); 513 fp->encoding = AUDIO_ENCODING_ULAW; 514 fp->precision = 8; 515 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 516 break; 517 case 2: 518 strcpy(fp->name, AudioEalaw); 519 fp->encoding = AUDIO_ENCODING_ALAW; 520 fp->precision = 8; 521 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 522 break; 523 case 3: 524 strcpy(fp->name, AudioEslinear); 525 fp->encoding = AUDIO_ENCODING_SLINEAR; 526 fp->precision = 8; 527 fp->flags = 0; 528 break; 529 case 4: 530 strcpy(fp->name, AudioEslinear_le); 531 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 532 fp->precision = 16; 533 fp->flags = 0; 534 break; 535 case 5: 536 strcpy(fp->name, AudioEulinear_le); 537 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 538 fp->precision = 16; 539 fp->flags = 0; 540 break; 541 case 6: 542 strcpy(fp->name, AudioEslinear_be); 543 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 544 fp->precision = 16; 545 fp->flags = 0; 546 break; 547 case 7: 548 strcpy(fp->name, AudioEulinear_be); 549 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 550 fp->precision = 16; 551 fp->flags = 0; 552 break; 553 default: 554 return EINVAL; 555 } 556 return 0; 557 } 558 559 int 560 cs4280_set_params(addr, setmode, usemode, play, rec) 561 void *addr; 562 int setmode, usemode; 563 struct audio_params *play, *rec; 564 { 565 struct cs428x_softc *sc = addr; 566 struct audio_params *p; 567 int mode; 568 569 for (mode = AUMODE_RECORD; mode != -1; 570 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 571 if ((setmode & mode) == 0) 572 continue; 573 574 p = mode == AUMODE_PLAY ? play : rec; 575 576 if (p == play) { 577 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 578 p->sample_rate, p->precision, p->channels)); 579 /* play back data format may be 8- or 16-bit and 580 * either stereo or mono. 581 * playback rate may range from 8000Hz to 48000Hz 582 */ 583 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 584 (p->precision != 8 && p->precision != 16) || 585 (p->channels != 1 && p->channels != 2) ) { 586 return EINVAL; 587 } 588 } else { 589 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 590 p->sample_rate, p->precision, p->channels)); 591 /* capture data format must be 16bit stereo 592 * and sample rate range from 11025Hz to 48000Hz. 593 * 594 * XXX: it looks like to work with 8000Hz, 595 * although data sheets say lower limit is 596 * 11025 Hz. 597 */ 598 599 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 600 (p->precision != 8 && p->precision != 16) || 601 (p->channels != 1 && p->channels != 2) ) { 602 return EINVAL; 603 } 604 } 605 p->factor = 1; 606 p->sw_code = 0; 607 608 /* capturing data is slinear */ 609 switch (p->encoding) { 610 case AUDIO_ENCODING_SLINEAR_BE: 611 if (mode == AUMODE_RECORD) { 612 if (p->precision == 16) 613 p->sw_code = swap_bytes; 614 } 615 break; 616 case AUDIO_ENCODING_SLINEAR_LE: 617 break; 618 case AUDIO_ENCODING_ULINEAR_BE: 619 if (mode == AUMODE_RECORD) { 620 if (p->precision == 16) 621 p->sw_code = change_sign16_swap_bytes_le; 622 else 623 p->sw_code = change_sign8; 624 } 625 break; 626 case AUDIO_ENCODING_ULINEAR_LE: 627 if (mode == AUMODE_RECORD) { 628 if (p->precision == 16) 629 p->sw_code = change_sign16_le; 630 else 631 p->sw_code = change_sign8; 632 } 633 break; 634 case AUDIO_ENCODING_ULAW: 635 if (mode == AUMODE_PLAY) { 636 p->factor = 2; 637 p->sw_code = mulaw_to_slinear16_le; 638 } else { 639 p->sw_code = slinear8_to_mulaw; 640 } 641 break; 642 case AUDIO_ENCODING_ALAW: 643 if (mode == AUMODE_PLAY) { 644 p->factor = 2; 645 p->sw_code = alaw_to_slinear16_le; 646 } else { 647 p->sw_code = slinear8_to_alaw; 648 } 649 break; 650 default: 651 return EINVAL; 652 } 653 } 654 655 /* set sample rate */ 656 cs4280_set_dac_rate(sc, play->sample_rate); 657 cs4280_set_adc_rate(sc, rec->sample_rate); 658 return 0; 659 } 660 661 int 662 cs4280_halt_output(addr) 663 void *addr; 664 { 665 struct cs428x_softc *sc = addr; 666 u_int32_t mem; 667 668 mem = BA1READ4(sc, CS4280_PCTL); 669 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 670 sc->sc_prun = 0; 671 return 0; 672 } 673 674 int 675 cs4280_halt_input(addr) 676 void *addr; 677 { 678 struct cs428x_softc *sc = addr; 679 u_int32_t mem; 680 681 mem = BA1READ4(sc, CS4280_CCTL); 682 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 683 sc->sc_rrun = 0; 684 return 0; 685 } 686 687 int 688 cs4280_getdev(addr, retp) 689 void *addr; 690 struct audio_device *retp; 691 { 692 *retp = cs4280_device; 693 return 0; 694 } 695 696 int 697 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 698 void *addr; 699 void *start, *end; 700 int blksize; 701 void (*intr) __P((void *)); 702 void *arg; 703 struct audio_params *param; 704 { 705 struct cs428x_softc *sc = addr; 706 u_int32_t pfie, pctl, pdtc; 707 struct cs428x_dma *p; 708 709 #ifdef DIAGNOSTIC 710 if (sc->sc_prun) 711 printf("cs4280_trigger_output: already running\n"); 712 #endif 713 sc->sc_prun = 1; 714 715 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 716 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 717 sc->sc_pintr = intr; 718 sc->sc_parg = arg; 719 720 /* stop playback DMA */ 721 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 722 723 /* setup PDTC */ 724 pdtc = BA1READ4(sc, CS4280_PDTC); 725 pdtc &= ~PDTC_MASK; 726 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 727 BA1WRITE4(sc, CS4280_PDTC, pdtc); 728 729 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 730 param->precision, param->factor, param->channels, 731 param->encoding)); 732 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 733 ; 734 if (p == NULL) { 735 printf("cs4280_trigger_output: bad addr %p\n", start); 736 return EINVAL; 737 } 738 if (DMAADDR(p) % sc->dma_align != 0 ) { 739 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 740 "4kB align\n", (ulong)DMAADDR(p)); 741 return EINVAL; 742 } 743 744 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 745 sc->sc_ps = (char *)start; 746 sc->sc_pe = (char *)end; 747 sc->sc_pdma = p; 748 sc->sc_pbuf = KERNADDR(p); 749 sc->sc_pi = 0; 750 sc->sc_pn = sc->sc_ps; 751 if (blksize >= sc->dma_size) { 752 sc->sc_pn = sc->sc_ps + sc->dma_size; 753 memcpy(sc->sc_pbuf, start, sc->dma_size); 754 ++sc->sc_pi; 755 } else { 756 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 757 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 758 } 759 760 /* initiate playback DMA */ 761 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 762 763 /* set PFIE */ 764 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 765 766 if (param->precision * param->factor == 8) 767 pfie |= PFIE_8BIT; 768 if (param->channels == 1) 769 pfie |= PFIE_MONO; 770 771 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 772 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 773 pfie |= PFIE_SWAPPED; 774 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 775 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 776 pfie |= PFIE_UNSIGNED; 777 778 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 779 780 sc->sc_prate = param->sample_rate; 781 cs4280_set_dac_rate(sc, param->sample_rate); 782 783 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 784 pctl |= sc->pctl; 785 BA1WRITE4(sc, CS4280_PCTL, pctl); 786 return 0; 787 } 788 789 int 790 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 791 void *addr; 792 void *start, *end; 793 int blksize; 794 void (*intr) __P((void *)); 795 void *arg; 796 struct audio_params *param; 797 { 798 struct cs428x_softc *sc = addr; 799 u_int32_t cctl, cie; 800 struct cs428x_dma *p; 801 802 #ifdef DIAGNOSTIC 803 if (sc->sc_rrun) 804 printf("cs4280_trigger_input: already running\n"); 805 #endif 806 sc->sc_rrun = 1; 807 808 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 809 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 810 sc->sc_rintr = intr; 811 sc->sc_rarg = arg; 812 813 /* stop capture DMA */ 814 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 815 816 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 817 ; 818 if (p == NULL) { 819 printf("cs4280_trigger_input: bad addr %p\n", start); 820 return EINVAL; 821 } 822 if (DMAADDR(p) % sc->dma_align != 0) { 823 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 824 "4kB align\n", (ulong)DMAADDR(p)); 825 return EINVAL; 826 } 827 828 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 829 sc->sc_rs = (char *)start; 830 sc->sc_re = (char *)end; 831 sc->sc_rdma = p; 832 sc->sc_rbuf = KERNADDR(p); 833 sc->sc_ri = 0; 834 sc->sc_rn = sc->sc_rs; 835 836 /* initiate capture DMA */ 837 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 838 839 /* setup format information for internal converter */ 840 sc->sc_rparam = 0; 841 if (param->precision == 8) { 842 sc->sc_rparam += CF_8BIT; 843 sc->sc_rcount <<= 1; 844 } 845 if (param->channels == 1) { 846 sc->sc_rparam += CF_MONO; 847 sc->sc_rcount <<= 1; 848 } 849 850 /* set CIE */ 851 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 852 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 853 854 sc->sc_rrate = param->sample_rate; 855 cs4280_set_adc_rate(sc, param->sample_rate); 856 857 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 858 cctl |= sc->cctl; 859 BA1WRITE4(sc, CS4280_CCTL, cctl); 860 return 0; 861 } 862 863 /* Power Hook */ 864 void 865 cs4280_power(why, v) 866 int why; 867 void *v; 868 { 869 struct cs428x_softc *sc = (struct cs428x_softc *)v; 870 static u_int32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 871 static u_int32_t cctl = 0, cba = 0, cie = 0; 872 873 DPRINTF(("%s: cs4280_power why=%d\n", 874 sc->sc_dev.dv_xname, why)); 875 switch (why) { 876 case PWR_SUSPEND: 877 case PWR_STANDBY: 878 sc->sc_suspend = why; 879 880 /* save current playback status */ 881 if ( sc->sc_prun ) { 882 pctl = BA1READ4(sc, CS4280_PCTL); 883 pfie = BA1READ4(sc, CS4280_PFIE); 884 pba = BA1READ4(sc, CS4280_PBA); 885 pdtc = BA1READ4(sc, CS4280_PDTC); 886 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 887 pctl, pfie, pba, pdtc)); 888 } 889 890 /* save current capture status */ 891 if ( sc->sc_rrun ) { 892 cctl = BA1READ4(sc, CS4280_CCTL); 893 cie = BA1READ4(sc, CS4280_CIE); 894 cba = BA1READ4(sc, CS4280_CBA); 895 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 896 cctl, cie, cba)); 897 } 898 899 /* Stop DMA */ 900 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 901 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 902 break; 903 case PWR_RESUME: 904 if (sc->sc_suspend == PWR_RESUME) { 905 printf("cs4280_power: odd, resume without suspend.\n"); 906 sc->sc_suspend = why; 907 return; 908 } 909 sc->sc_suspend = why; 910 cs4280_init(sc, 0); 911 cs4280_reset_codec(sc); 912 913 /* restore ac97 registers */ 914 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 915 916 /* restore DMA related status */ 917 if(sc->sc_prun) { 918 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 919 pctl, pfie, pba, pdtc)); 920 cs4280_set_dac_rate(sc, sc->sc_prate); 921 BA1WRITE4(sc, CS4280_PDTC, pdtc); 922 BA1WRITE4(sc, CS4280_PBA, pba); 923 BA1WRITE4(sc, CS4280_PFIE, pfie); 924 BA1WRITE4(sc, CS4280_PCTL, pctl); 925 } 926 927 if (sc->sc_rrun) { 928 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 929 cctl, cie, cba)); 930 cs4280_set_adc_rate(sc, sc->sc_rrate); 931 BA1WRITE4(sc, CS4280_CBA, cba); 932 BA1WRITE4(sc, CS4280_CIE, cie); 933 BA1WRITE4(sc, CS4280_CCTL, cctl); 934 } 935 break; 936 case PWR_SOFTSUSPEND: 937 case PWR_SOFTSTANDBY: 938 case PWR_SOFTRESUME: 939 break; 940 } 941 } 942 943 /* control AC97 codec */ 944 void 945 cs4280_reset_codec(void *addr) 946 { 947 struct cs428x_softc *sc; 948 int n; 949 950 sc = addr; 951 952 /* Reset codec */ 953 BA0WRITE4(sc, CS428X_ACCTL, 0); 954 delay(100); /* delay 100us */ 955 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 956 957 /* 958 * It looks like we do the following procedure, too 959 */ 960 961 /* Enable AC-link sync generation */ 962 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 963 delay(50*1000); /* XXX delay 50ms */ 964 965 /* Assert valid frame signal */ 966 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 967 968 /* Wait for valid AC97 input slot */ 969 n = 0; 970 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 971 (ACISV_ISV3 | ACISV_ISV4)) { 972 delay(1000); 973 if (++n > 1000) { 974 printf("reset_codec: AC97 inputs slot ready timeout\n"); 975 return; 976 } 977 } 978 } 979 980 981 /* Internal functions */ 982 983 void 984 cs4280_set_adc_rate(sc, rate) 985 struct cs428x_softc *sc; 986 int rate; 987 { 988 /* calculate capture rate: 989 * 990 * capture_coefficient_increment = -round(rate*128*65536/48000; 991 * capture_phase_increment = floor(48000*65536*1024/rate); 992 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 993 * cy = floor(cx/200); 994 * capture_sample_rate_correction = cx - 200*cy; 995 * capture_delay = ceil(24*48000/rate); 996 * capture_num_triplets = floor(65536*rate/24000); 997 * capture_group_length = 24000/GCD(rate, 24000); 998 * where GCD means "Greatest Common Divisor". 999 * 1000 * capture_coefficient_increment, capture_phase_increment and 1001 * capture_num_triplets are 32-bit signed quantities. 1002 * capture_sample_rate_correction and capture_group_length are 1003 * 16-bit signed quantities. 1004 * capture_delay is a 14-bit unsigned quantity. 1005 */ 1006 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 1007 u_int16_t csrc, cgl, cdlay; 1008 1009 /* XXX 1010 * Even though, embedded_audio_spec says capture rate range 11025 to 1011 * 48000, dhwiface.cpp says, 1012 * 1013 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1014 * Return an error if an attempt is made to stray outside that limit." 1015 * 1016 * so assume range as 48000/9 to 48000 1017 */ 1018 1019 if (rate < 8000) 1020 rate = 8000; 1021 if (rate > 48000) 1022 rate = 48000; 1023 1024 cx = rate << 16; 1025 cci = cx / 48000; 1026 cx -= cci * 48000; 1027 cx <<= 7; 1028 cci <<= 7; 1029 cci += cx / 48000; 1030 cci = - cci; 1031 1032 cx = 48000 << 16; 1033 cpi = cx / rate; 1034 cx -= cpi * rate; 1035 cx <<= 10; 1036 cpi <<= 10; 1037 cy = cx / rate; 1038 cpi += cy; 1039 cx -= cy * rate; 1040 1041 cy = cx / 200; 1042 csrc = cx - 200*cy; 1043 1044 cdlay = ((48000 * 24) + rate - 1) / rate; 1045 #if 0 1046 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1047 #endif 1048 1049 cnt = rate << 16; 1050 cnt /= 24000; 1051 1052 cgl = 1; 1053 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1054 if (((rate / tmp1) * tmp1) != rate) 1055 cgl *= 2; 1056 } 1057 if (((rate / 3) * 3) != rate) 1058 cgl *= 3; 1059 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1060 if (((rate / tmp1) * tmp1) != rate) 1061 cgl *= 5; 1062 } 1063 #if 0 1064 /* XXX what manual says */ 1065 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1066 tmp1 |= csrc<<16; 1067 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1068 #else 1069 /* suggested by cs461x.c (ALSA driver) */ 1070 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1071 #endif 1072 1073 #if 0 1074 /* I am confused. The sample rate calculation section says 1075 * cci *is* 32-bit signed quantity but in the parameter description 1076 * section, CCI only assigned 16bit. 1077 * I believe size of the variable. 1078 */ 1079 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1080 tmp1 |= cci<<16; 1081 BA1WRITE4(sc, CS4280_CCI, tmp1); 1082 #else 1083 BA1WRITE4(sc, CS4280_CCI, cci); 1084 #endif 1085 1086 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1087 tmp1 |= cdlay <<18; 1088 BA1WRITE4(sc, CS4280_CD, tmp1); 1089 1090 BA1WRITE4(sc, CS4280_CPI, cpi); 1091 1092 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1093 tmp1 |= cgl; 1094 BA1WRITE4(sc, CS4280_CGL, tmp1); 1095 1096 BA1WRITE4(sc, CS4280_CNT, cnt); 1097 1098 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1099 tmp1 |= cgl; 1100 BA1WRITE4(sc, CS4280_CGC, tmp1); 1101 } 1102 1103 void 1104 cs4280_set_dac_rate(sc, rate) 1105 struct cs428x_softc *sc; 1106 int rate; 1107 { 1108 /* 1109 * playback rate may range from 8000Hz to 48000Hz 1110 * 1111 * play_phase_increment = floor(rate*65536*1024/48000) 1112 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1113 * py=floor(px/200) 1114 * play_sample_rate_correction = px - 200*py 1115 * 1116 * play_phase_increment is a 32bit signed quantity. 1117 * play_sample_rate_correction is a 16bit signed quantity. 1118 */ 1119 int32_t ppi; 1120 int16_t psrc; 1121 u_int32_t px, py; 1122 1123 if (rate < 8000) 1124 rate = 8000; 1125 if (rate > 48000) 1126 rate = 48000; 1127 px = rate << 16; 1128 ppi = px/48000; 1129 px -= ppi*48000; 1130 ppi <<= 10; 1131 px <<= 10; 1132 py = px / 48000; 1133 ppi += py; 1134 px -= py*48000; 1135 py = px/200; 1136 px -= py*200; 1137 psrc = px; 1138 #if 0 1139 /* what manual says */ 1140 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1141 BA1WRITE4(sc, CS4280_PSRC, 1142 ( ((psrc<<16) & PSRC_MASK) | px )); 1143 #else 1144 /* suggested by cs461x.c (ALSA driver) */ 1145 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1146 #endif 1147 BA1WRITE4(sc, CS4280_PPI, ppi); 1148 } 1149 1150 /* Download Proceessor Code and Data image */ 1151 int 1152 cs4280_download(sc, src, offset, len) 1153 struct cs428x_softc *sc; 1154 const u_int32_t *src; 1155 u_int32_t offset, len; 1156 { 1157 u_int32_t ctr; 1158 1159 #if CS4280_DEBUG > 10 1160 u_int32_t con, data; 1161 u_int8_t c0,c1,c2,c3; 1162 #endif 1163 if ((offset&3) || (len&3)) 1164 return -1; 1165 1166 len /= sizeof(u_int32_t); 1167 for (ctr = 0; ctr < len; ctr++) { 1168 /* XXX: 1169 * I cannot confirm this is the right thing or not 1170 * on BIG-ENDIAN machines. 1171 */ 1172 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1173 #if CS4280_DEBUG > 10 1174 data = htole32(*(src+ctr)); 1175 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1176 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1177 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1178 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1179 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 1180 if (data != con ) { 1181 printf("0x%06x: write=0x%08x read=0x%08x\n", 1182 offset+ctr*4, data, con); 1183 return -1; 1184 } 1185 #endif 1186 } 1187 return 0; 1188 } 1189 1190 int 1191 cs4280_download_image(sc) 1192 struct cs428x_softc *sc; 1193 { 1194 int idx, err; 1195 u_int32_t offset = 0; 1196 1197 err = 0; 1198 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1199 err = cs4280_download(sc, &BA1Struct.map[offset], 1200 BA1Struct.memory[idx].offset, 1201 BA1Struct.memory[idx].size); 1202 if (err != 0) { 1203 printf("%s: load_image failed at %d\n", 1204 sc->sc_dev.dv_xname, idx); 1205 return -1; 1206 } 1207 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1208 } 1209 return err; 1210 } 1211 1212 /* Processor Soft Reset */ 1213 void 1214 cs4280_reset(sc_) 1215 void *sc_; 1216 { 1217 struct cs428x_softc *sc = sc_; 1218 1219 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1220 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1221 delay(100); 1222 /* Clear RSTSP bit in SPCR */ 1223 BA1WRITE4(sc, CS4280_SPCR, 0); 1224 /* enable DMA reqest */ 1225 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1226 } 1227 1228 int 1229 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1230 struct cs428x_softc *sc; 1231 char *class, *device, *qualifier; 1232 { 1233 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1234 device, qualifier)); 1235 } 1236 1237 int 1238 cs4280_init(sc, init) 1239 struct cs428x_softc *sc; 1240 int init; 1241 { 1242 int n; 1243 u_int32_t mem; 1244 1245 /* Start PLL out in known state */ 1246 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1247 /* Start serial ports out in known state */ 1248 BA0WRITE4(sc, CS4280_SERMC1, 0); 1249 1250 /* Specify type of CODEC */ 1251 /* XXX should not be here */ 1252 #define SERACC_CODEC_TYPE_1_03 1253 #ifdef SERACC_CODEC_TYPE_1_03 1254 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1255 #else 1256 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1257 #endif 1258 1259 /* Reset codec */ 1260 BA0WRITE4(sc, CS428X_ACCTL, 0); 1261 delay(100); /* delay 100us */ 1262 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1263 1264 /* Enable AC-link sync generation */ 1265 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1266 delay(50*1000); /* delay 50ms */ 1267 1268 /* Set the serial port timing configuration */ 1269 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1270 1271 /* Setup clock control */ 1272 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1273 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1274 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1275 1276 /* Power up the PLL */ 1277 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1278 delay(50*1000); /* delay 50ms */ 1279 1280 /* Turn on clock */ 1281 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1282 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1283 1284 /* Set the serial port FIFO pointer to the 1285 * first sample in FIFO. (not documented) */ 1286 cs4280_clear_fifos(sc); 1287 1288 #if 0 1289 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1290 BA0WRITE4(sc, CS4280_SERBSP, 0); 1291 #endif 1292 1293 /* Configure the serial port */ 1294 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1295 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1296 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1297 1298 /* Wait for CODEC ready */ 1299 n = 0; 1300 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1301 delay(125); 1302 if (++n > 1000) { 1303 printf("%s: codec ready timeout\n", 1304 sc->sc_dev.dv_xname); 1305 return(1); 1306 } 1307 } 1308 1309 /* Assert valid frame signal */ 1310 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1311 1312 /* Wait for valid AC97 input slot */ 1313 n = 0; 1314 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1315 (ACISV_ISV3 | ACISV_ISV4)) { 1316 delay(1000); 1317 if (++n > 1000) { 1318 printf("AC97 inputs slot ready timeout\n"); 1319 return(1); 1320 } 1321 } 1322 1323 /* Set AC97 output slot valid signals */ 1324 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1325 1326 /* reset the processor */ 1327 cs4280_reset(sc); 1328 1329 /* Download the image to the processor */ 1330 if (cs4280_download_image(sc) != 0) { 1331 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1332 return(1); 1333 } 1334 1335 /* Save playback parameter and then write zero. 1336 * this ensures that DMA doesn't immediately occur upon 1337 * starting the processor core 1338 */ 1339 mem = BA1READ4(sc, CS4280_PCTL); 1340 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1341 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1342 if (init != 0) 1343 sc->sc_prun = 0; 1344 1345 /* Save capture parameter and then write zero. 1346 * this ensures that DMA doesn't immediately occur upon 1347 * starting the processor core 1348 */ 1349 mem = BA1READ4(sc, CS4280_CCTL); 1350 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1351 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1352 if (init != 0) 1353 sc->sc_rrun = 0; 1354 1355 /* Processor Startup Procedure */ 1356 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1357 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1358 1359 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1360 n = 0; 1361 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1362 delay(10); 1363 if (++n > 1000) { 1364 printf("SPCR 1->0 transition timeout\n"); 1365 return(1); 1366 } 1367 } 1368 1369 n = 0; 1370 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1371 delay(10); 1372 if (++n > 1000) { 1373 printf("SPCS 0->1 transition timeout\n"); 1374 return(1); 1375 } 1376 } 1377 /* Processor is now running !!! */ 1378 1379 /* Setup volume */ 1380 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1381 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1382 1383 /* Interrupt enable */ 1384 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1385 1386 /* playback interrupt enable */ 1387 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1388 mem |= PFIE_PI_ENABLE; 1389 BA1WRITE4(sc, CS4280_PFIE, mem); 1390 /* capture interrupt enable */ 1391 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1392 mem |= CIE_CI_ENABLE; 1393 BA1WRITE4(sc, CS4280_CIE, mem); 1394 1395 #if NMIDI > 0 1396 /* Reset midi port */ 1397 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1398 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1399 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1400 /* midi interrupt enable */ 1401 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1402 BA0WRITE4(sc, CS4280_MIDCR, mem); 1403 #endif 1404 return(0); 1405 } 1406 1407 void 1408 cs4280_clear_fifos(sc) 1409 struct cs428x_softc *sc; 1410 { 1411 int pd = 0, cnt, n; 1412 u_int32_t mem; 1413 1414 /* 1415 * If device power down, power up the device and keep power down 1416 * state. 1417 */ 1418 mem = BA0READ4(sc, CS4280_CLKCR1); 1419 if (!(mem & CLKCR1_SWCE)) { 1420 printf("cs4280_clear_fifo: power down found.\n"); 1421 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1422 pd = 1; 1423 } 1424 BA0WRITE4(sc, CS4280_SERBWP, 0); 1425 for (cnt = 0; cnt < 256; cnt++) { 1426 n = 0; 1427 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1428 delay(1000); 1429 if (++n > 1000) { 1430 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1431 break; 1432 } 1433 } 1434 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1435 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1436 } 1437 if (pd) 1438 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1439 } 1440 1441 #if NMIDI > 0 1442 int 1443 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1444 void *addr; 1445 int flags; 1446 void (*iintr)__P((void *, int)); 1447 void (*ointr)__P((void *)); 1448 void *arg; 1449 { 1450 struct cs428x_softc *sc = addr; 1451 u_int32_t mem; 1452 1453 DPRINTF(("midi_open\n")); 1454 sc->sc_iintr = iintr; 1455 sc->sc_ointr = ointr; 1456 sc->sc_arg = arg; 1457 1458 /* midi interrupt enable */ 1459 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1460 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1461 BA0WRITE4(sc, CS4280_MIDCR, mem); 1462 #ifdef CS4280_DEBUG 1463 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1464 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1465 return(EINVAL); 1466 } 1467 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1468 #endif 1469 return 0; 1470 } 1471 1472 void 1473 cs4280_midi_close(addr) 1474 void *addr; 1475 { 1476 struct cs428x_softc *sc = addr; 1477 u_int32_t mem; 1478 1479 DPRINTF(("midi_close\n")); 1480 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1481 mem = BA0READ4(sc, CS4280_MIDCR); 1482 mem &= ~MIDCR_MASK; 1483 BA0WRITE4(sc, CS4280_MIDCR, mem); 1484 1485 sc->sc_iintr = 0; 1486 sc->sc_ointr = 0; 1487 } 1488 1489 int 1490 cs4280_midi_output(addr, d) 1491 void *addr; 1492 int d; 1493 { 1494 struct cs428x_softc *sc = addr; 1495 u_int32_t mem; 1496 int x; 1497 1498 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1499 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1500 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1501 mem |= d & MIDWP_MASK; 1502 DPRINTFN(5,("midi_output d=0x%08x",d)); 1503 BA0WRITE4(sc, CS4280_MIDWP, mem); 1504 #ifdef DIAGNOSTIC 1505 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1506 DPRINTF(("Bad write data: %d %d", 1507 mem, BA0READ4(sc, CS4280_MIDWP))); 1508 return(EIO); 1509 } 1510 #endif 1511 return 0; 1512 } 1513 delay(MIDI_BUSY_DELAY); 1514 } 1515 return (EIO); 1516 } 1517 1518 void 1519 cs4280_midi_getinfo(addr, mi) 1520 void *addr; 1521 struct midi_info *mi; 1522 { 1523 mi->name = "CS4280 MIDI UART"; 1524 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1525 } 1526 1527 #endif 1528 1529 /* DEBUG functions */ 1530 #if CS4280_DEBUG > 10 1531 int 1532 cs4280_checkimage(sc, src, offset, len) 1533 struct cs428x_softc *sc; 1534 u_int32_t *src; 1535 u_int32_t offset, len; 1536 { 1537 u_int32_t ctr, data; 1538 int err = 0; 1539 1540 if ((offset&3) || (len&3)) 1541 return -1; 1542 1543 len /= sizeof(u_int32_t); 1544 for (ctr = 0; ctr < len; ctr++) { 1545 /* I cannot confirm this is the right thing 1546 * on BIG-ENDIAN machines 1547 */ 1548 data = BA1READ4(sc, offset+ctr*4); 1549 if (data != htole32(*(src+ctr))) { 1550 printf("0x%06x: 0x%08x(0x%08x)\n", 1551 offset+ctr*4, data, *(src+ctr)); 1552 *(src+ctr) = data; 1553 ++err; 1554 } 1555 } 1556 return err; 1557 } 1558 1559 int 1560 cs4280_check_images(sc) 1561 struct cs428x_softc *sc; 1562 { 1563 int idx, err; 1564 u_int32_t offset = 0; 1565 1566 err = 0; 1567 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 1568 for (idx = 0; idx < 1; ++idx) { 1569 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1570 BA1Struct.memory[idx].offset, 1571 BA1Struct.memory[idx].size); 1572 if (err != 0) { 1573 printf("%s: check_image failed at %d\n", 1574 sc->sc_dev.dv_xname, idx); 1575 } 1576 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1577 } 1578 return err; 1579 } 1580 1581 #endif 1582
Indexes created Thu Oct 02 14:10:14 GMT 2025