cs4280.c revision 1.26.2.2
1 /* $NetBSD: cs4280.c,v 1.26.2.2 2004/08/12 11:41:44 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.26.2.2 2004/08/12 11:41:44 skrll Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <machine/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 int cs4280_match(struct device *, struct cfdata *, void *); 93 void cs4280_attach(struct device *, struct device *, void *); 94 int cs4280_intr(void *); 95 int cs4280_query_encoding(void *, struct audio_encoding *); 96 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 97 int cs4280_halt_output(void *); 98 int cs4280_halt_input(void *); 99 int cs4280_getdev(void *, struct audio_device *); 100 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 101 void *, struct audio_params *); 102 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 103 void *, struct audio_params *); 104 105 void cs4280_reset_codec(void *); 106 107 /* For PowerHook */ 108 void cs4280_power(int, void *); 109 110 /* Internal functions */ 111 void cs4280_set_adc_rate(struct cs428x_softc *, int ); 112 void cs4280_set_dac_rate(struct cs428x_softc *, int ); 113 int cs4280_download(struct cs428x_softc *, const u_int32_t *, u_int32_t, u_int32_t); 114 int cs4280_download_image(struct cs428x_softc *); 115 void cs4280_reset(void *); 116 int cs4280_get_portnum_by_name(struct cs428x_softc *, char *, char *, char *); 117 int cs4280_init(struct cs428x_softc *, int); 118 void cs4280_clear_fifos(struct cs428x_softc *); 119 120 #if CS4280_DEBUG > 10 121 /* Thease two function is only for checking image loading is succeeded or not. */ 122 int cs4280_check_images(struct cs428x_softc *); 123 int cs4280_checkimage(struct cs428x_softc *, u_int32_t *, u_int32_t, u_int32_t); 124 #endif 125 126 struct audio_hw_if cs4280_hw_if = { 127 cs428x_open, 128 cs428x_close, 129 NULL, 130 cs4280_query_encoding, 131 cs4280_set_params, 132 cs428x_round_blocksize, 133 NULL, 134 NULL, 135 NULL, 136 NULL, 137 NULL, 138 cs4280_halt_output, 139 cs4280_halt_input, 140 NULL, 141 cs4280_getdev, 142 NULL, 143 cs428x_mixer_set_port, 144 cs428x_mixer_get_port, 145 cs428x_query_devinfo, 146 cs428x_malloc, 147 cs428x_free, 148 cs428x_round_buffersize, 149 cs428x_mappage, 150 cs428x_get_props, 151 cs4280_trigger_output, 152 cs4280_trigger_input, 153 NULL, 154 }; 155 156 #if NMIDI > 0 157 /* Midi Interface */ 158 int cs4280_midi_open(void *, int, void (*)(void *, int), 159 void (*)(void *), void *); 160 void cs4280_midi_close(void*); 161 int cs4280_midi_output(void *, int); 162 void cs4280_midi_getinfo(void *, struct midi_info *); 163 164 struct midi_hw_if cs4280_midi_hw_if = { 165 cs4280_midi_open, 166 cs4280_midi_close, 167 cs4280_midi_output, 168 cs4280_midi_getinfo, 169 0, 170 }; 171 #endif 172 173 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 174 cs4280_match, cs4280_attach, NULL, NULL); 175 176 struct audio_device cs4280_device = { 177 "CS4280", 178 "", 179 "cs4280" 180 }; 181 182 183 int 184 cs4280_match(parent, match, aux) 185 struct device *parent; 186 struct cfdata *match; 187 void *aux; 188 { 189 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 190 191 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 192 return 0; 193 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 194 #if 0 /* I can't confirm */ 195 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 196 #endif 197 ) 198 return 1; 199 return 0; 200 } 201 202 void 203 cs4280_attach(parent, self, aux) 204 struct device *parent; 205 struct device *self; 206 void *aux; 207 { 208 struct cs428x_softc *sc = (struct cs428x_softc *)self; 209 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 210 pci_chipset_tag_t pc = pa->pa_pc; 211 char const *intrstr; 212 pci_intr_handle_t ih; 213 pcireg_t reg; 214 char devinfo[256]; 215 mixer_ctrl_t ctl; 216 u_int32_t mem; 217 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 218 219 aprint_naive(": Audio controller\n"); 220 221 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 222 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 223 PCI_REVISION(pa->pa_class)); 224 225 /* Map I/O register */ 226 if (pci_mapreg_map(pa, PCI_BA0, 227 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 228 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 229 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 230 return; 231 } 232 if (pci_mapreg_map(pa, PCI_BA1, 233 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 234 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 235 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 236 return; 237 } 238 239 sc->sc_dmatag = pa->pa_dmat; 240 241 /* Check and set Power State */ 242 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 243 &pci_pwrmgmt_cap_reg, 0)) { 244 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 245 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 246 pci_pwrmgmt_csr_reg); 247 DPRINTF(("%s: Power State is %d\n", 248 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 249 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 250 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 251 (reg & ~PCI_PMCSR_STATE_MASK) | 252 PCI_PMCSR_STATE_D0); 253 } 254 } 255 256 /* Enable the device (set bus master flag) */ 257 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 258 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 259 reg | PCI_COMMAND_MASTER_ENABLE); 260 261 /* LATENCY_TIMER setting */ 262 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 263 if ( PCI_LATTIMER(mem) < 32 ) { 264 mem &= 0xffff00ff; 265 mem |= 0x00002000; 266 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 267 } 268 269 /* Map and establish the interrupt. */ 270 if (pci_intr_map(pa, &ih)) { 271 aprint_error("%s: couldn't map interrupt\n", 272 sc->sc_dev.dv_xname); 273 return; 274 } 275 intrstr = pci_intr_string(pc, ih); 276 277 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 278 if (sc->sc_ih == NULL) { 279 aprint_error("%s: couldn't establish interrupt", 280 sc->sc_dev.dv_xname); 281 if (intrstr != NULL) 282 aprint_normal(" at %s", intrstr); 283 aprint_normal("\n"); 284 return; 285 } 286 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 287 288 /* Initialization */ 289 if(cs4280_init(sc, 1) != 0) 290 return; 291 292 sc->type = TYPE_CS4280; 293 sc->halt_input = cs4280_halt_input; 294 sc->halt_output = cs4280_halt_output; 295 296 /* setup buffer related parameters */ 297 sc->dma_size = CS4280_DCHUNK; 298 sc->dma_align = CS4280_DALIGN; 299 sc->hw_blocksize = CS4280_ICHUNK; 300 301 /* AC 97 attachment */ 302 sc->host_if.arg = sc; 303 sc->host_if.attach = cs428x_attach_codec; 304 sc->host_if.read = cs428x_read_codec; 305 sc->host_if.write = cs428x_write_codec; 306 sc->host_if.reset = cs4280_reset_codec; 307 if (ac97_attach(&sc->host_if) != 0) { 308 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 309 return; 310 } 311 312 /* Turn mute off of DAC, CD and master volumes by default */ 313 ctl.type = AUDIO_MIXER_ENUM; 314 ctl.un.ord = 0; /* off */ 315 316 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 317 AudioNmaster, AudioNmute); 318 cs428x_mixer_set_port(sc, &ctl); 319 320 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 321 AudioNdac, AudioNmute); 322 cs428x_mixer_set_port(sc, &ctl); 323 324 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 325 AudioNcd, AudioNmute); 326 cs428x_mixer_set_port(sc, &ctl); 327 328 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 329 330 #if NMIDI > 0 331 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 332 #endif 333 334 sc->sc_suspend = PWR_RESUME; 335 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 336 } 337 338 /* Interrupt handling function */ 339 int 340 cs4280_intr(p) 341 void *p; 342 { 343 /* 344 * XXX 345 * 346 * Since CS4280 has only 4kB DMA buffer and 347 * interrupt occurs every 2kB block, I create dummy buffer 348 * which returns to audio driver and actual DMA buffer 349 * using in DMA transfer. 350 * 351 * 352 * ring buffer in audio.c is pointed by BUFADDR 353 * <------ ring buffer size == 64kB ------> 354 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 355 * |= = = =|= = = =|= = = =|= = = =|= = = =| 356 * | | | | | | <- call audio_intp every 357 * sc->sc_[pr]_count time. 358 * 359 * actual DMA buffer is pointed by KERNADDR 360 * <-> DMA buffer size = 4kB 361 * |= =| 362 * 363 * 364 */ 365 struct cs428x_softc *sc = p; 366 u_int32_t intr, mem; 367 char * empty_dma; 368 int handled = 0; 369 370 /* grab interrupt register then clear it */ 371 intr = BA0READ4(sc, CS4280_HISR); 372 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 373 374 /* Playback Interrupt */ 375 if (intr & HISR_PINT) { 376 handled = 1; 377 mem = BA1READ4(sc, CS4280_PFIE); 378 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 379 if (sc->sc_prun) { 380 if ((sc->sc_pi%sc->sc_pcount) == 0) 381 sc->sc_pintr(sc->sc_parg); 382 } else { 383 printf("unexpected play intr\n"); 384 } 385 /* copy buffer */ 386 ++sc->sc_pi; 387 empty_dma = sc->sc_pdma->addr; 388 if (sc->sc_pi&1) 389 empty_dma += sc->hw_blocksize; 390 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 391 sc->sc_pn += sc->hw_blocksize; 392 if (sc->sc_pn >= sc->sc_pe) 393 sc->sc_pn = sc->sc_ps; 394 BA1WRITE4(sc, CS4280_PFIE, mem); 395 } 396 /* Capture Interrupt */ 397 if (intr & HISR_CINT) { 398 int i; 399 int16_t rdata; 400 401 handled = 1; 402 mem = BA1READ4(sc, CS4280_CIE); 403 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 404 ++sc->sc_ri; 405 empty_dma = sc->sc_rdma->addr; 406 if ((sc->sc_ri&1) == 0) 407 empty_dma += sc->hw_blocksize; 408 409 /* 410 * XXX 411 * I think this audio data conversion should be 412 * happend in upper layer, but I put this here 413 * since there is no conversion function available. 414 */ 415 switch(sc->sc_rparam) { 416 case CF_16BIT_STEREO: 417 /* just copy it */ 418 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 419 sc->sc_rn += sc->hw_blocksize; 420 break; 421 case CF_16BIT_MONO: 422 for (i = 0; i < 512; i++) { 423 rdata = *((int16_t *)empty_dma)>>1; 424 empty_dma += 2; 425 rdata += *((int16_t *)empty_dma)>>1; 426 empty_dma += 2; 427 *((int16_t *)sc->sc_rn) = rdata; 428 sc->sc_rn += 2; 429 } 430 break; 431 case CF_8BIT_STEREO: 432 for (i = 0; i < 512; i++) { 433 rdata = *((int16_t*)empty_dma); 434 empty_dma += 2; 435 *sc->sc_rn++ = rdata >> 8; 436 rdata = *((int16_t*)empty_dma); 437 empty_dma += 2; 438 *sc->sc_rn++ = rdata >> 8; 439 } 440 break; 441 case CF_8BIT_MONO: 442 for (i = 0; i < 512; i++) { 443 rdata = *((int16_t*)empty_dma) >>1; 444 empty_dma += 2; 445 rdata += *((int16_t*)empty_dma) >>1; 446 empty_dma += 2; 447 *sc->sc_rn++ = rdata >>8; 448 } 449 break; 450 default: 451 /* Should not reach here */ 452 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 453 } 454 if (sc->sc_rn >= sc->sc_re) 455 sc->sc_rn = sc->sc_rs; 456 BA1WRITE4(sc, CS4280_CIE, mem); 457 if (sc->sc_rrun) { 458 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 459 sc->sc_rintr(sc->sc_rarg); 460 } else { 461 printf("unexpected record intr\n"); 462 } 463 } 464 465 #if NMIDI > 0 466 /* Midi port Interrupt */ 467 if (intr & HISR_MIDI) { 468 int data; 469 470 handled = 1; 471 DPRINTF(("i: %d: ", 472 BA0READ4(sc, CS4280_MIDSR))); 473 /* Read the received data */ 474 while ((sc->sc_iintr != NULL) && 475 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 476 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 477 DPRINTF(("r:%x\n",data)); 478 sc->sc_iintr(sc->sc_arg, data); 479 } 480 481 /* Write the data */ 482 #if 1 483 /* XXX: 484 * It seems "Transmit Buffer Full" never activate until EOI 485 * is deliverd. Shall I throw EOI top of this routine ? 486 */ 487 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 488 DPRINTF(("w: ")); 489 if (sc->sc_ointr != NULL) 490 sc->sc_ointr(sc->sc_arg); 491 } 492 #else 493 while ((sc->sc_ointr != NULL) && 494 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 495 DPRINTF(("w: ")); 496 sc->sc_ointr(sc->sc_arg); 497 } 498 #endif 499 DPRINTF(("\n")); 500 } 501 #endif 502 503 return handled; 504 } 505 506 int 507 cs4280_query_encoding(addr, fp) 508 void *addr; 509 struct audio_encoding *fp; 510 { 511 switch (fp->index) { 512 case 0: 513 strcpy(fp->name, AudioEulinear); 514 fp->encoding = AUDIO_ENCODING_ULINEAR; 515 fp->precision = 8; 516 fp->flags = 0; 517 break; 518 case 1: 519 strcpy(fp->name, AudioEmulaw); 520 fp->encoding = AUDIO_ENCODING_ULAW; 521 fp->precision = 8; 522 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 523 break; 524 case 2: 525 strcpy(fp->name, AudioEalaw); 526 fp->encoding = AUDIO_ENCODING_ALAW; 527 fp->precision = 8; 528 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 529 break; 530 case 3: 531 strcpy(fp->name, AudioEslinear); 532 fp->encoding = AUDIO_ENCODING_SLINEAR; 533 fp->precision = 8; 534 fp->flags = 0; 535 break; 536 case 4: 537 strcpy(fp->name, AudioEslinear_le); 538 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 539 fp->precision = 16; 540 fp->flags = 0; 541 break; 542 case 5: 543 strcpy(fp->name, AudioEulinear_le); 544 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 545 fp->precision = 16; 546 fp->flags = 0; 547 break; 548 case 6: 549 strcpy(fp->name, AudioEslinear_be); 550 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 551 fp->precision = 16; 552 fp->flags = 0; 553 break; 554 case 7: 555 strcpy(fp->name, AudioEulinear_be); 556 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 557 fp->precision = 16; 558 fp->flags = 0; 559 break; 560 default: 561 return EINVAL; 562 } 563 return 0; 564 } 565 566 int 567 cs4280_set_params(addr, setmode, usemode, play, rec) 568 void *addr; 569 int setmode, usemode; 570 struct audio_params *play, *rec; 571 { 572 struct cs428x_softc *sc = addr; 573 struct audio_params *p; 574 int mode; 575 576 for (mode = AUMODE_RECORD; mode != -1; 577 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 578 if ((setmode & mode) == 0) 579 continue; 580 581 p = mode == AUMODE_PLAY ? play : rec; 582 583 if (p == play) { 584 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 585 p->sample_rate, p->precision, p->channels)); 586 /* play back data format may be 8- or 16-bit and 587 * either stereo or mono. 588 * playback rate may range from 8000Hz to 48000Hz 589 */ 590 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 591 (p->precision != 8 && p->precision != 16) || 592 (p->channels != 1 && p->channels != 2) ) { 593 return EINVAL; 594 } 595 } else { 596 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 597 p->sample_rate, p->precision, p->channels)); 598 /* capture data format must be 16bit stereo 599 * and sample rate range from 11025Hz to 48000Hz. 600 * 601 * XXX: it looks like to work with 8000Hz, 602 * although data sheets say lower limit is 603 * 11025 Hz. 604 */ 605 606 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 607 (p->precision != 8 && p->precision != 16) || 608 (p->channels != 1 && p->channels != 2) ) { 609 return EINVAL; 610 } 611 } 612 p->factor = 1; 613 p->sw_code = 0; 614 615 /* capturing data is slinear */ 616 switch (p->encoding) { 617 case AUDIO_ENCODING_SLINEAR_BE: 618 if (mode == AUMODE_RECORD) { 619 if (p->precision == 16) 620 p->sw_code = swap_bytes; 621 } 622 break; 623 case AUDIO_ENCODING_SLINEAR_LE: 624 break; 625 case AUDIO_ENCODING_ULINEAR_BE: 626 if (mode == AUMODE_RECORD) { 627 if (p->precision == 16) 628 p->sw_code = change_sign16_swap_bytes_le; 629 else 630 p->sw_code = change_sign8; 631 } 632 break; 633 case AUDIO_ENCODING_ULINEAR_LE: 634 if (mode == AUMODE_RECORD) { 635 if (p->precision == 16) 636 p->sw_code = change_sign16_le; 637 else 638 p->sw_code = change_sign8; 639 } 640 break; 641 case AUDIO_ENCODING_ULAW: 642 if (mode == AUMODE_PLAY) { 643 p->factor = 2; 644 p->sw_code = mulaw_to_slinear16_le; 645 } else { 646 p->sw_code = slinear8_to_mulaw; 647 } 648 break; 649 case AUDIO_ENCODING_ALAW: 650 if (mode == AUMODE_PLAY) { 651 p->factor = 2; 652 p->sw_code = alaw_to_slinear16_le; 653 } else { 654 p->sw_code = slinear8_to_alaw; 655 } 656 break; 657 default: 658 return EINVAL; 659 } 660 } 661 662 /* set sample rate */ 663 cs4280_set_dac_rate(sc, play->sample_rate); 664 cs4280_set_adc_rate(sc, rec->sample_rate); 665 return 0; 666 } 667 668 int 669 cs4280_halt_output(addr) 670 void *addr; 671 { 672 struct cs428x_softc *sc = addr; 673 u_int32_t mem; 674 675 mem = BA1READ4(sc, CS4280_PCTL); 676 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 677 sc->sc_prun = 0; 678 return 0; 679 } 680 681 int 682 cs4280_halt_input(addr) 683 void *addr; 684 { 685 struct cs428x_softc *sc = addr; 686 u_int32_t mem; 687 688 mem = BA1READ4(sc, CS4280_CCTL); 689 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 690 sc->sc_rrun = 0; 691 return 0; 692 } 693 694 int 695 cs4280_getdev(addr, retp) 696 void *addr; 697 struct audio_device *retp; 698 { 699 *retp = cs4280_device; 700 return 0; 701 } 702 703 int 704 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 705 void *addr; 706 void *start, *end; 707 int blksize; 708 void (*intr) __P((void *)); 709 void *arg; 710 struct audio_params *param; 711 { 712 struct cs428x_softc *sc = addr; 713 u_int32_t pfie, pctl, pdtc; 714 struct cs428x_dma *p; 715 716 #ifdef DIAGNOSTIC 717 if (sc->sc_prun) 718 printf("cs4280_trigger_output: already running\n"); 719 #endif 720 sc->sc_prun = 1; 721 722 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 723 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 724 sc->sc_pintr = intr; 725 sc->sc_parg = arg; 726 727 /* stop playback DMA */ 728 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 729 730 /* setup PDTC */ 731 pdtc = BA1READ4(sc, CS4280_PDTC); 732 pdtc &= ~PDTC_MASK; 733 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 734 BA1WRITE4(sc, CS4280_PDTC, pdtc); 735 736 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 737 param->precision, param->factor, param->channels, 738 param->encoding)); 739 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 740 ; 741 if (p == NULL) { 742 printf("cs4280_trigger_output: bad addr %p\n", start); 743 return EINVAL; 744 } 745 if (DMAADDR(p) % sc->dma_align != 0 ) { 746 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 747 "4kB align\n", (ulong)DMAADDR(p)); 748 return EINVAL; 749 } 750 751 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 752 sc->sc_ps = (char *)start; 753 sc->sc_pe = (char *)end; 754 sc->sc_pdma = p; 755 sc->sc_pbuf = KERNADDR(p); 756 sc->sc_pi = 0; 757 sc->sc_pn = sc->sc_ps; 758 if (blksize >= sc->dma_size) { 759 sc->sc_pn = sc->sc_ps + sc->dma_size; 760 memcpy(sc->sc_pbuf, start, sc->dma_size); 761 ++sc->sc_pi; 762 } else { 763 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 764 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 765 } 766 767 /* initiate playback DMA */ 768 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 769 770 /* set PFIE */ 771 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 772 773 if (param->precision * param->factor == 8) 774 pfie |= PFIE_8BIT; 775 if (param->channels == 1) 776 pfie |= PFIE_MONO; 777 778 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 779 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 780 pfie |= PFIE_SWAPPED; 781 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 782 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 783 pfie |= PFIE_UNSIGNED; 784 785 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 786 787 sc->sc_prate = param->sample_rate; 788 cs4280_set_dac_rate(sc, param->sample_rate); 789 790 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 791 pctl |= sc->pctl; 792 BA1WRITE4(sc, CS4280_PCTL, pctl); 793 return 0; 794 } 795 796 int 797 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 798 void *addr; 799 void *start, *end; 800 int blksize; 801 void (*intr) __P((void *)); 802 void *arg; 803 struct audio_params *param; 804 { 805 struct cs428x_softc *sc = addr; 806 u_int32_t cctl, cie; 807 struct cs428x_dma *p; 808 809 #ifdef DIAGNOSTIC 810 if (sc->sc_rrun) 811 printf("cs4280_trigger_input: already running\n"); 812 #endif 813 sc->sc_rrun = 1; 814 815 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 816 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 817 sc->sc_rintr = intr; 818 sc->sc_rarg = arg; 819 820 /* stop capture DMA */ 821 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 822 823 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 824 ; 825 if (p == NULL) { 826 printf("cs4280_trigger_input: bad addr %p\n", start); 827 return EINVAL; 828 } 829 if (DMAADDR(p) % sc->dma_align != 0) { 830 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 831 "4kB align\n", (ulong)DMAADDR(p)); 832 return EINVAL; 833 } 834 835 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 836 sc->sc_rs = (char *)start; 837 sc->sc_re = (char *)end; 838 sc->sc_rdma = p; 839 sc->sc_rbuf = KERNADDR(p); 840 sc->sc_ri = 0; 841 sc->sc_rn = sc->sc_rs; 842 843 /* initiate capture DMA */ 844 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 845 846 /* setup format information for internal converter */ 847 sc->sc_rparam = 0; 848 if (param->precision == 8) { 849 sc->sc_rparam += CF_8BIT; 850 sc->sc_rcount <<= 1; 851 } 852 if (param->channels == 1) { 853 sc->sc_rparam += CF_MONO; 854 sc->sc_rcount <<= 1; 855 } 856 857 /* set CIE */ 858 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 859 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 860 861 sc->sc_rrate = param->sample_rate; 862 cs4280_set_adc_rate(sc, param->sample_rate); 863 864 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 865 cctl |= sc->cctl; 866 BA1WRITE4(sc, CS4280_CCTL, cctl); 867 return 0; 868 } 869 870 /* Power Hook */ 871 void 872 cs4280_power(why, v) 873 int why; 874 void *v; 875 { 876 struct cs428x_softc *sc = (struct cs428x_softc *)v; 877 static u_int32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 878 static u_int32_t cctl = 0, cba = 0, cie = 0; 879 880 DPRINTF(("%s: cs4280_power why=%d\n", 881 sc->sc_dev.dv_xname, why)); 882 switch (why) { 883 case PWR_SUSPEND: 884 case PWR_STANDBY: 885 sc->sc_suspend = why; 886 887 /* save current playback status */ 888 if ( sc->sc_prun ) { 889 pctl = BA1READ4(sc, CS4280_PCTL); 890 pfie = BA1READ4(sc, CS4280_PFIE); 891 pba = BA1READ4(sc, CS4280_PBA); 892 pdtc = BA1READ4(sc, CS4280_PDTC); 893 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 894 pctl, pfie, pba, pdtc)); 895 } 896 897 /* save current capture status */ 898 if ( sc->sc_rrun ) { 899 cctl = BA1READ4(sc, CS4280_CCTL); 900 cie = BA1READ4(sc, CS4280_CIE); 901 cba = BA1READ4(sc, CS4280_CBA); 902 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 903 cctl, cie, cba)); 904 } 905 906 /* Stop DMA */ 907 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 908 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 909 break; 910 case PWR_RESUME: 911 if (sc->sc_suspend == PWR_RESUME) { 912 printf("cs4280_power: odd, resume without suspend.\n"); 913 sc->sc_suspend = why; 914 return; 915 } 916 sc->sc_suspend = why; 917 cs4280_init(sc, 0); 918 cs4280_reset_codec(sc); 919 920 /* restore ac97 registers */ 921 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 922 923 /* restore DMA related status */ 924 if(sc->sc_prun) { 925 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 926 pctl, pfie, pba, pdtc)); 927 cs4280_set_dac_rate(sc, sc->sc_prate); 928 BA1WRITE4(sc, CS4280_PDTC, pdtc); 929 BA1WRITE4(sc, CS4280_PBA, pba); 930 BA1WRITE4(sc, CS4280_PFIE, pfie); 931 BA1WRITE4(sc, CS4280_PCTL, pctl); 932 } 933 934 if (sc->sc_rrun) { 935 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 936 cctl, cie, cba)); 937 cs4280_set_adc_rate(sc, sc->sc_rrate); 938 BA1WRITE4(sc, CS4280_CBA, cba); 939 BA1WRITE4(sc, CS4280_CIE, cie); 940 BA1WRITE4(sc, CS4280_CCTL, cctl); 941 } 942 break; 943 case PWR_SOFTSUSPEND: 944 case PWR_SOFTSTANDBY: 945 case PWR_SOFTRESUME: 946 break; 947 } 948 } 949 950 /* control AC97 codec */ 951 void 952 cs4280_reset_codec(void *addr) 953 { 954 struct cs428x_softc *sc; 955 int n; 956 957 sc = addr; 958 959 /* Reset codec */ 960 BA0WRITE4(sc, CS428X_ACCTL, 0); 961 delay(100); /* delay 100us */ 962 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 963 964 /* 965 * It looks like we do the following procedure, too 966 */ 967 968 /* Enable AC-link sync generation */ 969 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 970 delay(50*1000); /* XXX delay 50ms */ 971 972 /* Assert valid frame signal */ 973 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 974 975 /* Wait for valid AC97 input slot */ 976 n = 0; 977 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 978 (ACISV_ISV3 | ACISV_ISV4)) { 979 delay(1000); 980 if (++n > 1000) { 981 printf("reset_codec: AC97 inputs slot ready timeout\n"); 982 return; 983 } 984 } 985 } 986 987 988 /* Internal functions */ 989 990 void 991 cs4280_set_adc_rate(sc, rate) 992 struct cs428x_softc *sc; 993 int rate; 994 { 995 /* calculate capture rate: 996 * 997 * capture_coefficient_increment = -round(rate*128*65536/48000; 998 * capture_phase_increment = floor(48000*65536*1024/rate); 999 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1000 * cy = floor(cx/200); 1001 * capture_sample_rate_correction = cx - 200*cy; 1002 * capture_delay = ceil(24*48000/rate); 1003 * capture_num_triplets = floor(65536*rate/24000); 1004 * capture_group_length = 24000/GCD(rate, 24000); 1005 * where GCD means "Greatest Common Divisor". 1006 * 1007 * capture_coefficient_increment, capture_phase_increment and 1008 * capture_num_triplets are 32-bit signed quantities. 1009 * capture_sample_rate_correction and capture_group_length are 1010 * 16-bit signed quantities. 1011 * capture_delay is a 14-bit unsigned quantity. 1012 */ 1013 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 1014 u_int16_t csrc, cgl, cdlay; 1015 1016 /* XXX 1017 * Even though, embedded_audio_spec says capture rate range 11025 to 1018 * 48000, dhwiface.cpp says, 1019 * 1020 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1021 * Return an error if an attempt is made to stray outside that limit." 1022 * 1023 * so assume range as 48000/9 to 48000 1024 */ 1025 1026 if (rate < 8000) 1027 rate = 8000; 1028 if (rate > 48000) 1029 rate = 48000; 1030 1031 cx = rate << 16; 1032 cci = cx / 48000; 1033 cx -= cci * 48000; 1034 cx <<= 7; 1035 cci <<= 7; 1036 cci += cx / 48000; 1037 cci = - cci; 1038 1039 cx = 48000 << 16; 1040 cpi = cx / rate; 1041 cx -= cpi * rate; 1042 cx <<= 10; 1043 cpi <<= 10; 1044 cy = cx / rate; 1045 cpi += cy; 1046 cx -= cy * rate; 1047 1048 cy = cx / 200; 1049 csrc = cx - 200*cy; 1050 1051 cdlay = ((48000 * 24) + rate - 1) / rate; 1052 #if 0 1053 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1054 #endif 1055 1056 cnt = rate << 16; 1057 cnt /= 24000; 1058 1059 cgl = 1; 1060 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1061 if (((rate / tmp1) * tmp1) != rate) 1062 cgl *= 2; 1063 } 1064 if (((rate / 3) * 3) != rate) 1065 cgl *= 3; 1066 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1067 if (((rate / tmp1) * tmp1) != rate) 1068 cgl *= 5; 1069 } 1070 #if 0 1071 /* XXX what manual says */ 1072 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1073 tmp1 |= csrc<<16; 1074 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1075 #else 1076 /* suggested by cs461x.c (ALSA driver) */ 1077 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1078 #endif 1079 1080 #if 0 1081 /* I am confused. The sample rate calculation section says 1082 * cci *is* 32-bit signed quantity but in the parameter description 1083 * section, CCI only assigned 16bit. 1084 * I believe size of the variable. 1085 */ 1086 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1087 tmp1 |= cci<<16; 1088 BA1WRITE4(sc, CS4280_CCI, tmp1); 1089 #else 1090 BA1WRITE4(sc, CS4280_CCI, cci); 1091 #endif 1092 1093 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1094 tmp1 |= cdlay <<18; 1095 BA1WRITE4(sc, CS4280_CD, tmp1); 1096 1097 BA1WRITE4(sc, CS4280_CPI, cpi); 1098 1099 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1100 tmp1 |= cgl; 1101 BA1WRITE4(sc, CS4280_CGL, tmp1); 1102 1103 BA1WRITE4(sc, CS4280_CNT, cnt); 1104 1105 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1106 tmp1 |= cgl; 1107 BA1WRITE4(sc, CS4280_CGC, tmp1); 1108 } 1109 1110 void 1111 cs4280_set_dac_rate(sc, rate) 1112 struct cs428x_softc *sc; 1113 int rate; 1114 { 1115 /* 1116 * playback rate may range from 8000Hz to 48000Hz 1117 * 1118 * play_phase_increment = floor(rate*65536*1024/48000) 1119 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1120 * py=floor(px/200) 1121 * play_sample_rate_correction = px - 200*py 1122 * 1123 * play_phase_increment is a 32bit signed quantity. 1124 * play_sample_rate_correction is a 16bit signed quantity. 1125 */ 1126 int32_t ppi; 1127 int16_t psrc; 1128 u_int32_t px, py; 1129 1130 if (rate < 8000) 1131 rate = 8000; 1132 if (rate > 48000) 1133 rate = 48000; 1134 px = rate << 16; 1135 ppi = px/48000; 1136 px -= ppi*48000; 1137 ppi <<= 10; 1138 px <<= 10; 1139 py = px / 48000; 1140 ppi += py; 1141 px -= py*48000; 1142 py = px/200; 1143 px -= py*200; 1144 psrc = px; 1145 #if 0 1146 /* what manual says */ 1147 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1148 BA1WRITE4(sc, CS4280_PSRC, 1149 ( ((psrc<<16) & PSRC_MASK) | px )); 1150 #else 1151 /* suggested by cs461x.c (ALSA driver) */ 1152 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1153 #endif 1154 BA1WRITE4(sc, CS4280_PPI, ppi); 1155 } 1156 1157 /* Download Proceessor Code and Data image */ 1158 int 1159 cs4280_download(sc, src, offset, len) 1160 struct cs428x_softc *sc; 1161 const u_int32_t *src; 1162 u_int32_t offset, len; 1163 { 1164 u_int32_t ctr; 1165 1166 #if CS4280_DEBUG > 10 1167 u_int32_t con, data; 1168 u_int8_t c0,c1,c2,c3; 1169 #endif 1170 if ((offset&3) || (len&3)) 1171 return -1; 1172 1173 len /= sizeof(u_int32_t); 1174 for (ctr = 0; ctr < len; ctr++) { 1175 /* XXX: 1176 * I cannot confirm this is the right thing or not 1177 * on BIG-ENDIAN machines. 1178 */ 1179 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1180 #if CS4280_DEBUG > 10 1181 data = htole32(*(src+ctr)); 1182 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1183 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1184 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1185 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1186 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 1187 if (data != con ) { 1188 printf("0x%06x: write=0x%08x read=0x%08x\n", 1189 offset+ctr*4, data, con); 1190 return -1; 1191 } 1192 #endif 1193 } 1194 return 0; 1195 } 1196 1197 int 1198 cs4280_download_image(sc) 1199 struct cs428x_softc *sc; 1200 { 1201 int idx, err; 1202 u_int32_t offset = 0; 1203 1204 err = 0; 1205 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1206 err = cs4280_download(sc, &BA1Struct.map[offset], 1207 BA1Struct.memory[idx].offset, 1208 BA1Struct.memory[idx].size); 1209 if (err != 0) { 1210 printf("%s: load_image failed at %d\n", 1211 sc->sc_dev.dv_xname, idx); 1212 return -1; 1213 } 1214 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1215 } 1216 return err; 1217 } 1218 1219 /* Processor Soft Reset */ 1220 void 1221 cs4280_reset(sc_) 1222 void *sc_; 1223 { 1224 struct cs428x_softc *sc = sc_; 1225 1226 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1227 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1228 delay(100); 1229 /* Clear RSTSP bit in SPCR */ 1230 BA1WRITE4(sc, CS4280_SPCR, 0); 1231 /* enable DMA reqest */ 1232 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1233 } 1234 1235 int 1236 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1237 struct cs428x_softc *sc; 1238 char *class, *device, *qualifier; 1239 { 1240 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1241 device, qualifier)); 1242 } 1243 1244 int 1245 cs4280_init(sc, init) 1246 struct cs428x_softc *sc; 1247 int init; 1248 { 1249 int n; 1250 u_int32_t mem; 1251 1252 /* Start PLL out in known state */ 1253 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1254 /* Start serial ports out in known state */ 1255 BA0WRITE4(sc, CS4280_SERMC1, 0); 1256 1257 /* Specify type of CODEC */ 1258 /* XXX should not be here */ 1259 #define SERACC_CODEC_TYPE_1_03 1260 #ifdef SERACC_CODEC_TYPE_1_03 1261 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1262 #else 1263 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1264 #endif 1265 1266 /* Reset codec */ 1267 BA0WRITE4(sc, CS428X_ACCTL, 0); 1268 delay(100); /* delay 100us */ 1269 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1270 1271 /* Enable AC-link sync generation */ 1272 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1273 delay(50*1000); /* delay 50ms */ 1274 1275 /* Set the serial port timing configuration */ 1276 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1277 1278 /* Setup clock control */ 1279 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1280 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1281 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1282 1283 /* Power up the PLL */ 1284 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1285 delay(50*1000); /* delay 50ms */ 1286 1287 /* Turn on clock */ 1288 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1289 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1290 1291 /* Set the serial port FIFO pointer to the 1292 * first sample in FIFO. (not documented) */ 1293 cs4280_clear_fifos(sc); 1294 1295 #if 0 1296 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1297 BA0WRITE4(sc, CS4280_SERBSP, 0); 1298 #endif 1299 1300 /* Configure the serial port */ 1301 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1302 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1303 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1304 1305 /* Wait for CODEC ready */ 1306 n = 0; 1307 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1308 delay(125); 1309 if (++n > 1000) { 1310 printf("%s: codec ready timeout\n", 1311 sc->sc_dev.dv_xname); 1312 return(1); 1313 } 1314 } 1315 1316 /* Assert valid frame signal */ 1317 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1318 1319 /* Wait for valid AC97 input slot */ 1320 n = 0; 1321 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1322 (ACISV_ISV3 | ACISV_ISV4)) { 1323 delay(1000); 1324 if (++n > 1000) { 1325 printf("AC97 inputs slot ready timeout\n"); 1326 return(1); 1327 } 1328 } 1329 1330 /* Set AC97 output slot valid signals */ 1331 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1332 1333 /* reset the processor */ 1334 cs4280_reset(sc); 1335 1336 /* Download the image to the processor */ 1337 if (cs4280_download_image(sc) != 0) { 1338 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1339 return(1); 1340 } 1341 1342 /* Save playback parameter and then write zero. 1343 * this ensures that DMA doesn't immediately occur upon 1344 * starting the processor core 1345 */ 1346 mem = BA1READ4(sc, CS4280_PCTL); 1347 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1348 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1349 if (init != 0) 1350 sc->sc_prun = 0; 1351 1352 /* Save capture parameter and then write zero. 1353 * this ensures that DMA doesn't immediately occur upon 1354 * starting the processor core 1355 */ 1356 mem = BA1READ4(sc, CS4280_CCTL); 1357 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1358 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1359 if (init != 0) 1360 sc->sc_rrun = 0; 1361 1362 /* Processor Startup Procedure */ 1363 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1364 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1365 1366 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1367 n = 0; 1368 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1369 delay(10); 1370 if (++n > 1000) { 1371 printf("SPCR 1->0 transition timeout\n"); 1372 return(1); 1373 } 1374 } 1375 1376 n = 0; 1377 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1378 delay(10); 1379 if (++n > 1000) { 1380 printf("SPCS 0->1 transition timeout\n"); 1381 return(1); 1382 } 1383 } 1384 /* Processor is now running !!! */ 1385 1386 /* Setup volume */ 1387 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1388 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1389 1390 /* Interrupt enable */ 1391 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1392 1393 /* playback interrupt enable */ 1394 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1395 mem |= PFIE_PI_ENABLE; 1396 BA1WRITE4(sc, CS4280_PFIE, mem); 1397 /* capture interrupt enable */ 1398 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1399 mem |= CIE_CI_ENABLE; 1400 BA1WRITE4(sc, CS4280_CIE, mem); 1401 1402 #if NMIDI > 0 1403 /* Reset midi port */ 1404 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1405 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1406 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1407 /* midi interrupt enable */ 1408 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1409 BA0WRITE4(sc, CS4280_MIDCR, mem); 1410 #endif 1411 return(0); 1412 } 1413 1414 void 1415 cs4280_clear_fifos(sc) 1416 struct cs428x_softc *sc; 1417 { 1418 int pd = 0, cnt, n; 1419 u_int32_t mem; 1420 1421 /* 1422 * If device power down, power up the device and keep power down 1423 * state. 1424 */ 1425 mem = BA0READ4(sc, CS4280_CLKCR1); 1426 if (!(mem & CLKCR1_SWCE)) { 1427 printf("cs4280_clear_fifo: power down found.\n"); 1428 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1429 pd = 1; 1430 } 1431 BA0WRITE4(sc, CS4280_SERBWP, 0); 1432 for (cnt = 0; cnt < 256; cnt++) { 1433 n = 0; 1434 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1435 delay(1000); 1436 if (++n > 1000) { 1437 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1438 break; 1439 } 1440 } 1441 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1442 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1443 } 1444 if (pd) 1445 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1446 } 1447 1448 #if NMIDI > 0 1449 int 1450 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1451 void *addr; 1452 int flags; 1453 void (*iintr)__P((void *, int)); 1454 void (*ointr)__P((void *)); 1455 void *arg; 1456 { 1457 struct cs428x_softc *sc = addr; 1458 u_int32_t mem; 1459 1460 DPRINTF(("midi_open\n")); 1461 sc->sc_iintr = iintr; 1462 sc->sc_ointr = ointr; 1463 sc->sc_arg = arg; 1464 1465 /* midi interrupt enable */ 1466 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1467 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1468 BA0WRITE4(sc, CS4280_MIDCR, mem); 1469 #ifdef CS4280_DEBUG 1470 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1471 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1472 return(EINVAL); 1473 } 1474 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1475 #endif 1476 return 0; 1477 } 1478 1479 void 1480 cs4280_midi_close(addr) 1481 void *addr; 1482 { 1483 struct cs428x_softc *sc = addr; 1484 u_int32_t mem; 1485 1486 DPRINTF(("midi_close\n")); 1487 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1488 mem = BA0READ4(sc, CS4280_MIDCR); 1489 mem &= ~MIDCR_MASK; 1490 BA0WRITE4(sc, CS4280_MIDCR, mem); 1491 1492 sc->sc_iintr = 0; 1493 sc->sc_ointr = 0; 1494 } 1495 1496 int 1497 cs4280_midi_output(addr, d) 1498 void *addr; 1499 int d; 1500 { 1501 struct cs428x_softc *sc = addr; 1502 u_int32_t mem; 1503 int x; 1504 1505 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1506 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1507 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1508 mem |= d & MIDWP_MASK; 1509 DPRINTFN(5,("midi_output d=0x%08x",d)); 1510 BA0WRITE4(sc, CS4280_MIDWP, mem); 1511 #ifdef DIAGNOSTIC 1512 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1513 DPRINTF(("Bad write data: %d %d", 1514 mem, BA0READ4(sc, CS4280_MIDWP))); 1515 return(EIO); 1516 } 1517 #endif 1518 return 0; 1519 } 1520 delay(MIDI_BUSY_DELAY); 1521 } 1522 return (EIO); 1523 } 1524 1525 void 1526 cs4280_midi_getinfo(addr, mi) 1527 void *addr; 1528 struct midi_info *mi; 1529 { 1530 mi->name = "CS4280 MIDI UART"; 1531 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1532 } 1533 1534 #endif 1535 1536 /* DEBUG functions */ 1537 #if CS4280_DEBUG > 10 1538 int 1539 cs4280_checkimage(sc, src, offset, len) 1540 struct cs428x_softc *sc; 1541 u_int32_t *src; 1542 u_int32_t offset, len; 1543 { 1544 u_int32_t ctr, data; 1545 int err = 0; 1546 1547 if ((offset&3) || (len&3)) 1548 return -1; 1549 1550 len /= sizeof(u_int32_t); 1551 for (ctr = 0; ctr < len; ctr++) { 1552 /* I cannot confirm this is the right thing 1553 * on BIG-ENDIAN machines 1554 */ 1555 data = BA1READ4(sc, offset+ctr*4); 1556 if (data != htole32(*(src+ctr))) { 1557 printf("0x%06x: 0x%08x(0x%08x)\n", 1558 offset+ctr*4, data, *(src+ctr)); 1559 *(src+ctr) = data; 1560 ++err; 1561 } 1562 } 1563 return err; 1564 } 1565 1566 int 1567 cs4280_check_images(sc) 1568 struct cs428x_softc *sc; 1569 { 1570 int idx, err; 1571 u_int32_t offset = 0; 1572 1573 err = 0; 1574 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 1575 for (idx = 0; idx < 1; ++idx) { 1576 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1577 BA1Struct.memory[idx].offset, 1578 BA1Struct.memory[idx].size); 1579 if (err != 0) { 1580 printf("%s: check_image failed at %d\n", 1581 sc->sc_dev.dv_xname, idx); 1582 } 1583 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1584 } 1585 return err; 1586 } 1587 1588 #endif 1589
Indexes created Thu Oct 02 14:10:14 GMT 2025