cs4280.c revision 1.26.2.9
1 /* $NetBSD: cs4280.c,v 1.26.2.9 2005/11/10 14:06:01 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.26.2.9 2005/11/10 14:06:01 skrll Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <machine/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(struct device *, struct cfdata *, void *); 93 static void cs4280_attach(struct device *, struct device *, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 107 static int cs4280_reset_codec(void *); 108 109 /* For PowerHook */ 110 static void cs4280_power(int, void *); 111 112 /* Internal functions */ 113 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 114 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 115 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 116 uint32_t); 117 static int cs4280_download_image(struct cs428x_softc *); 118 static void cs4280_reset(void *); 119 static int cs4280_init(struct cs428x_softc *, int); 120 static void cs4280_clear_fifos(struct cs428x_softc *); 121 122 #if CS4280_DEBUG > 10 123 /* Thease two function is only for checking image loading is succeeded or not. */ 124 static int cs4280_check_images(struct cs428x_softc *); 125 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 126 uint32_t); 127 #endif 128 129 static const struct audio_hw_if cs4280_hw_if = { 130 NULL, /* open */ 131 NULL, /* close */ 132 NULL, 133 cs4280_query_encoding, 134 cs4280_set_params, 135 cs428x_round_blocksize, 136 NULL, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 cs4280_halt_output, 142 cs4280_halt_input, 143 NULL, 144 cs4280_getdev, 145 NULL, 146 cs428x_mixer_set_port, 147 cs428x_mixer_get_port, 148 cs428x_query_devinfo, 149 cs428x_malloc, 150 cs428x_free, 151 cs428x_round_buffersize, 152 cs428x_mappage, 153 cs428x_get_props, 154 cs4280_trigger_output, 155 cs4280_trigger_input, 156 NULL, 157 }; 158 159 #if NMIDI > 0 160 /* Midi Interface */ 161 static int cs4280_midi_open(void *, int, void (*)(void *, int), 162 void (*)(void *), void *); 163 static void cs4280_midi_close(void*); 164 static int cs4280_midi_output(void *, int); 165 static void cs4280_midi_getinfo(void *, struct midi_info *); 166 167 static const struct midi_hw_if cs4280_midi_hw_if = { 168 cs4280_midi_open, 169 cs4280_midi_close, 170 cs4280_midi_output, 171 cs4280_midi_getinfo, 172 0, 173 }; 174 #endif 175 176 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 177 cs4280_match, cs4280_attach, NULL, NULL); 178 179 static struct audio_device cs4280_device = { 180 "CS4280", 181 "", 182 "cs4280" 183 }; 184 185 186 static int 187 cs4280_match(struct device *parent, struct cfdata *match, void *aux) 188 { 189 struct pci_attach_args *pa; 190 191 pa = (struct pci_attach_args *)aux; 192 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 193 return 0; 194 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 195 #if 0 /* I can't confirm */ 196 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 197 #endif 198 ) 199 return 1; 200 return 0; 201 } 202 203 static void 204 cs4280_attach(struct device *parent, struct device *self, void *aux) 205 { 206 struct cs428x_softc *sc; 207 struct pci_attach_args *pa; 208 pci_chipset_tag_t pc; 209 char const *intrstr; 210 pci_intr_handle_t ih; 211 pcireg_t reg; 212 char devinfo[256]; 213 uint32_t mem; 214 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 215 216 sc = (struct cs428x_softc *)self; 217 pa = (struct pci_attach_args *)aux; 218 pc = pa->pa_pc; 219 aprint_naive(": Audio controller\n"); 220 221 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 222 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 223 PCI_REVISION(pa->pa_class)); 224 225 /* Map I/O register */ 226 if (pci_mapreg_map(pa, PCI_BA0, 227 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 228 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 229 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 230 return; 231 } 232 if (pci_mapreg_map(pa, PCI_BA1, 233 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 234 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 235 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 236 return; 237 } 238 239 sc->sc_dmatag = pa->pa_dmat; 240 241 /* Check and set Power State */ 242 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 243 &pci_pwrmgmt_cap_reg, 0)) { 244 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 245 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 246 pci_pwrmgmt_csr_reg); 247 DPRINTF(("%s: Power State is %d\n", 248 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 249 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 250 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 251 (reg & ~PCI_PMCSR_STATE_MASK) | 252 PCI_PMCSR_STATE_D0); 253 } 254 } 255 256 /* Enable the device (set bus master flag) */ 257 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 258 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 259 reg | PCI_COMMAND_MASTER_ENABLE); 260 261 /* LATENCY_TIMER setting */ 262 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 263 if ( PCI_LATTIMER(mem) < 32 ) { 264 mem &= 0xffff00ff; 265 mem |= 0x00002000; 266 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 267 } 268 269 /* Map and establish the interrupt. */ 270 if (pci_intr_map(pa, &ih)) { 271 aprint_error("%s: couldn't map interrupt\n", 272 sc->sc_dev.dv_xname); 273 return; 274 } 275 intrstr = pci_intr_string(pc, ih); 276 277 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 278 if (sc->sc_ih == NULL) { 279 aprint_error("%s: couldn't establish interrupt", 280 sc->sc_dev.dv_xname); 281 if (intrstr != NULL) 282 aprint_normal(" at %s", intrstr); 283 aprint_normal("\n"); 284 return; 285 } 286 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 287 288 /* Initialization */ 289 if(cs4280_init(sc, 1) != 0) 290 return; 291 292 sc->type = TYPE_CS4280; 293 sc->halt_input = cs4280_halt_input; 294 sc->halt_output = cs4280_halt_output; 295 296 /* setup buffer related parameters */ 297 sc->dma_size = CS4280_DCHUNK; 298 sc->dma_align = CS4280_DALIGN; 299 sc->hw_blocksize = CS4280_ICHUNK; 300 301 /* AC 97 attachment */ 302 sc->host_if.arg = sc; 303 sc->host_if.attach = cs428x_attach_codec; 304 sc->host_if.read = cs428x_read_codec; 305 sc->host_if.write = cs428x_write_codec; 306 sc->host_if.reset = cs4280_reset_codec; 307 if (ac97_attach(&sc->host_if, self) != 0) { 308 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 309 return; 310 } 311 312 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 313 314 #if NMIDI > 0 315 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 316 #endif 317 318 sc->sc_suspend = PWR_RESUME; 319 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 320 } 321 322 /* Interrupt handling function */ 323 static int 324 cs4280_intr(void *p) 325 { 326 /* 327 * XXX 328 * 329 * Since CS4280 has only 4kB DMA buffer and 330 * interrupt occurs every 2kB block, I create dummy buffer 331 * which returns to audio driver and actual DMA buffer 332 * using in DMA transfer. 333 * 334 * 335 * ring buffer in audio.c is pointed by BUFADDR 336 * <------ ring buffer size == 64kB ------> 337 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 338 * |= = = =|= = = =|= = = =|= = = =|= = = =| 339 * | | | | | | <- call audio_intp every 340 * sc->sc_[pr]_count time. 341 * 342 * actual DMA buffer is pointed by KERNADDR 343 * <-> DMA buffer size = 4kB 344 * |= =| 345 * 346 * 347 */ 348 struct cs428x_softc *sc; 349 uint32_t intr, mem; 350 char * empty_dma; 351 int handled; 352 353 sc = p; 354 handled = 0; 355 /* grab interrupt register then clear it */ 356 intr = BA0READ4(sc, CS4280_HISR); 357 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 358 359 /* Playback Interrupt */ 360 if (intr & HISR_PINT) { 361 handled = 1; 362 mem = BA1READ4(sc, CS4280_PFIE); 363 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 364 if (sc->sc_prun) { 365 if ((sc->sc_pi%sc->sc_pcount) == 0) 366 sc->sc_pintr(sc->sc_parg); 367 } else { 368 printf("unexpected play intr\n"); 369 } 370 /* copy buffer */ 371 ++sc->sc_pi; 372 empty_dma = sc->sc_pdma->addr; 373 if (sc->sc_pi&1) 374 empty_dma += sc->hw_blocksize; 375 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 376 sc->sc_pn += sc->hw_blocksize; 377 if (sc->sc_pn >= sc->sc_pe) 378 sc->sc_pn = sc->sc_ps; 379 BA1WRITE4(sc, CS4280_PFIE, mem); 380 } 381 /* Capture Interrupt */ 382 if (intr & HISR_CINT) { 383 int i; 384 int16_t rdata; 385 386 handled = 1; 387 mem = BA1READ4(sc, CS4280_CIE); 388 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 389 ++sc->sc_ri; 390 empty_dma = sc->sc_rdma->addr; 391 if ((sc->sc_ri&1) == 0) 392 empty_dma += sc->hw_blocksize; 393 394 /* 395 * XXX 396 * I think this audio data conversion should be 397 * happend in upper layer, but I put this here 398 * since there is no conversion function available. 399 */ 400 switch(sc->sc_rparam) { 401 case CF_16BIT_STEREO: 402 /* just copy it */ 403 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 404 sc->sc_rn += sc->hw_blocksize; 405 break; 406 case CF_16BIT_MONO: 407 for (i = 0; i < 512; i++) { 408 rdata = *((int16_t *)empty_dma)>>1; 409 empty_dma += 2; 410 rdata += *((int16_t *)empty_dma)>>1; 411 empty_dma += 2; 412 *((int16_t *)sc->sc_rn) = rdata; 413 sc->sc_rn += 2; 414 } 415 break; 416 case CF_8BIT_STEREO: 417 for (i = 0; i < 512; i++) { 418 rdata = *((int16_t*)empty_dma); 419 empty_dma += 2; 420 *sc->sc_rn++ = rdata >> 8; 421 rdata = *((int16_t*)empty_dma); 422 empty_dma += 2; 423 *sc->sc_rn++ = rdata >> 8; 424 } 425 break; 426 case CF_8BIT_MONO: 427 for (i = 0; i < 512; i++) { 428 rdata = *((int16_t*)empty_dma) >>1; 429 empty_dma += 2; 430 rdata += *((int16_t*)empty_dma) >>1; 431 empty_dma += 2; 432 *sc->sc_rn++ = rdata >>8; 433 } 434 break; 435 default: 436 /* Should not reach here */ 437 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 438 } 439 if (sc->sc_rn >= sc->sc_re) 440 sc->sc_rn = sc->sc_rs; 441 BA1WRITE4(sc, CS4280_CIE, mem); 442 if (sc->sc_rrun) { 443 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 444 sc->sc_rintr(sc->sc_rarg); 445 } else { 446 printf("unexpected record intr\n"); 447 } 448 } 449 450 #if NMIDI > 0 451 /* Midi port Interrupt */ 452 if (intr & HISR_MIDI) { 453 int data; 454 455 handled = 1; 456 DPRINTF(("i: %d: ", 457 BA0READ4(sc, CS4280_MIDSR))); 458 /* Read the received data */ 459 while ((sc->sc_iintr != NULL) && 460 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 461 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 462 DPRINTF(("r:%x\n",data)); 463 sc->sc_iintr(sc->sc_arg, data); 464 } 465 466 /* Write the data */ 467 #if 1 468 /* XXX: 469 * It seems "Transmit Buffer Full" never activate until EOI 470 * is deliverd. Shall I throw EOI top of this routine ? 471 */ 472 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 473 DPRINTF(("w: ")); 474 if (sc->sc_ointr != NULL) 475 sc->sc_ointr(sc->sc_arg); 476 } 477 #else 478 while ((sc->sc_ointr != NULL) && 479 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 480 DPRINTF(("w: ")); 481 sc->sc_ointr(sc->sc_arg); 482 } 483 #endif 484 DPRINTF(("\n")); 485 } 486 #endif 487 488 return handled; 489 } 490 491 static int 492 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 493 { 494 switch (fp->index) { 495 case 0: 496 strcpy(fp->name, AudioEulinear); 497 fp->encoding = AUDIO_ENCODING_ULINEAR; 498 fp->precision = 8; 499 fp->flags = 0; 500 break; 501 case 1: 502 strcpy(fp->name, AudioEmulaw); 503 fp->encoding = AUDIO_ENCODING_ULAW; 504 fp->precision = 8; 505 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 506 break; 507 case 2: 508 strcpy(fp->name, AudioEalaw); 509 fp->encoding = AUDIO_ENCODING_ALAW; 510 fp->precision = 8; 511 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 512 break; 513 case 3: 514 strcpy(fp->name, AudioEslinear); 515 fp->encoding = AUDIO_ENCODING_SLINEAR; 516 fp->precision = 8; 517 fp->flags = 0; 518 break; 519 case 4: 520 strcpy(fp->name, AudioEslinear_le); 521 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 522 fp->precision = 16; 523 fp->flags = 0; 524 break; 525 case 5: 526 strcpy(fp->name, AudioEulinear_le); 527 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 528 fp->precision = 16; 529 fp->flags = 0; 530 break; 531 case 6: 532 strcpy(fp->name, AudioEslinear_be); 533 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 534 fp->precision = 16; 535 fp->flags = 0; 536 break; 537 case 7: 538 strcpy(fp->name, AudioEulinear_be); 539 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 540 fp->precision = 16; 541 fp->flags = 0; 542 break; 543 default: 544 return EINVAL; 545 } 546 return 0; 547 } 548 549 static int 550 cs4280_set_params(void *addr, int setmode, int usemode, 551 audio_params_t *play, audio_params_t *rec, 552 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 553 { 554 audio_params_t hw; 555 struct cs428x_softc *sc; 556 struct audio_params *p; 557 stream_filter_list_t *fil; 558 int mode; 559 560 sc = addr; 561 for (mode = AUMODE_RECORD; mode != -1; 562 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 563 if ((setmode & mode) == 0) 564 continue; 565 566 p = mode == AUMODE_PLAY ? play : rec; 567 568 if (p == play) { 569 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 570 p->sample_rate, p->precision, p->channels)); 571 /* play back data format may be 8- or 16-bit and 572 * either stereo or mono. 573 * playback rate may range from 8000Hz to 48000Hz 574 */ 575 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 576 (p->precision != 8 && p->precision != 16) || 577 (p->channels != 1 && p->channels != 2) ) { 578 return EINVAL; 579 } 580 } else { 581 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 582 p->sample_rate, p->precision, p->channels)); 583 /* capture data format must be 16bit stereo 584 * and sample rate range from 11025Hz to 48000Hz. 585 * 586 * XXX: it looks like to work with 8000Hz, 587 * although data sheets say lower limit is 588 * 11025 Hz. 589 */ 590 591 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 592 (p->precision != 8 && p->precision != 16) || 593 (p->channels != 1 && p->channels != 2) ) { 594 return EINVAL; 595 } 596 } 597 fil = mode == AUMODE_PLAY ? pfil : rfil; 598 hw = *p; 599 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 600 601 /* capturing data is slinear */ 602 switch (p->encoding) { 603 case AUDIO_ENCODING_SLINEAR_BE: 604 if (mode == AUMODE_RECORD && p->precision == 16) { 605 fil->append(fil, swap_bytes, &hw); 606 } 607 break; 608 case AUDIO_ENCODING_SLINEAR_LE: 609 break; 610 case AUDIO_ENCODING_ULINEAR_BE: 611 if (mode == AUMODE_RECORD) { 612 fil->append(fil, p->precision == 16 613 ? swap_bytes_change_sign16 614 : change_sign8, &hw); 615 } 616 break; 617 case AUDIO_ENCODING_ULINEAR_LE: 618 if (mode == AUMODE_RECORD) { 619 fil->append(fil, p->precision == 16 620 ? change_sign16 : change_sign8, 621 &hw); 622 } 623 break; 624 case AUDIO_ENCODING_ULAW: 625 if (mode == AUMODE_PLAY) { 626 hw.precision = 16; 627 hw.validbits = 16; 628 fil->append(fil, mulaw_to_linear16, &hw); 629 } else { 630 fil->append(fil, linear8_to_mulaw, &hw); 631 } 632 break; 633 case AUDIO_ENCODING_ALAW: 634 if (mode == AUMODE_PLAY) { 635 hw.precision = 16; 636 hw.validbits = 16; 637 fil->append(fil, alaw_to_linear16, &hw); 638 } else { 639 fil->append(fil, linear8_to_alaw, &hw); 640 } 641 break; 642 default: 643 return EINVAL; 644 } 645 } 646 647 /* set sample rate */ 648 cs4280_set_dac_rate(sc, play->sample_rate); 649 cs4280_set_adc_rate(sc, rec->sample_rate); 650 return 0; 651 } 652 653 static int 654 cs4280_halt_output(void *addr) 655 { 656 struct cs428x_softc *sc; 657 uint32_t mem; 658 659 sc = addr; 660 mem = BA1READ4(sc, CS4280_PCTL); 661 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 662 sc->sc_prun = 0; 663 return 0; 664 } 665 666 static int 667 cs4280_halt_input(void *addr) 668 { 669 struct cs428x_softc *sc; 670 uint32_t mem; 671 672 sc = addr; 673 mem = BA1READ4(sc, CS4280_CCTL); 674 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 675 sc->sc_rrun = 0; 676 return 0; 677 } 678 679 static int 680 cs4280_getdev(void *addr, struct audio_device *retp) 681 { 682 683 *retp = cs4280_device; 684 return 0; 685 } 686 687 static int 688 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 689 void (*intr)(void *), void *arg, 690 const audio_params_t *param) 691 { 692 struct cs428x_softc *sc; 693 uint32_t pfie, pctl, pdtc; 694 struct cs428x_dma *p; 695 696 sc = addr; 697 #ifdef DIAGNOSTIC 698 if (sc->sc_prun) 699 printf("cs4280_trigger_output: already running\n"); 700 #endif 701 sc->sc_prun = 1; 702 703 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 704 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 705 sc->sc_pintr = intr; 706 sc->sc_parg = arg; 707 708 /* stop playback DMA */ 709 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 710 711 /* setup PDTC */ 712 pdtc = BA1READ4(sc, CS4280_PDTC); 713 pdtc &= ~PDTC_MASK; 714 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 715 BA1WRITE4(sc, CS4280_PDTC, pdtc); 716 717 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 718 param->precision, param->channels, param->encoding)); 719 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 720 continue; 721 if (p == NULL) { 722 printf("cs4280_trigger_output: bad addr %p\n", start); 723 return EINVAL; 724 } 725 if (DMAADDR(p) % sc->dma_align != 0 ) { 726 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 727 "4kB align\n", (ulong)DMAADDR(p)); 728 return EINVAL; 729 } 730 731 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 732 sc->sc_ps = (char *)start; 733 sc->sc_pe = (char *)end; 734 sc->sc_pdma = p; 735 sc->sc_pbuf = KERNADDR(p); 736 sc->sc_pi = 0; 737 sc->sc_pn = sc->sc_ps; 738 if (blksize >= sc->dma_size) { 739 sc->sc_pn = sc->sc_ps + sc->dma_size; 740 memcpy(sc->sc_pbuf, start, sc->dma_size); 741 ++sc->sc_pi; 742 } else { 743 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 744 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 745 } 746 747 /* initiate playback DMA */ 748 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 749 750 /* set PFIE */ 751 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 752 753 if (param->precision == 8) 754 pfie |= PFIE_8BIT; 755 if (param->channels == 1) 756 pfie |= PFIE_MONO; 757 758 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 759 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 760 pfie |= PFIE_SWAPPED; 761 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 762 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 763 pfie |= PFIE_UNSIGNED; 764 765 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 766 767 sc->sc_prate = param->sample_rate; 768 cs4280_set_dac_rate(sc, param->sample_rate); 769 770 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 771 pctl |= sc->pctl; 772 BA1WRITE4(sc, CS4280_PCTL, pctl); 773 return 0; 774 } 775 776 static int 777 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 778 void (*intr)(void *), void *arg, 779 const audio_params_t *param) 780 { 781 struct cs428x_softc *sc; 782 uint32_t cctl, cie; 783 struct cs428x_dma *p; 784 785 sc = addr; 786 #ifdef DIAGNOSTIC 787 if (sc->sc_rrun) 788 printf("cs4280_trigger_input: already running\n"); 789 #endif 790 sc->sc_rrun = 1; 791 792 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 793 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 794 sc->sc_rintr = intr; 795 sc->sc_rarg = arg; 796 797 /* stop capture DMA */ 798 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 799 800 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 801 continue; 802 if (p == NULL) { 803 printf("cs4280_trigger_input: bad addr %p\n", start); 804 return EINVAL; 805 } 806 if (DMAADDR(p) % sc->dma_align != 0) { 807 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 808 "4kB align\n", (ulong)DMAADDR(p)); 809 return EINVAL; 810 } 811 812 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 813 sc->sc_rs = (char *)start; 814 sc->sc_re = (char *)end; 815 sc->sc_rdma = p; 816 sc->sc_rbuf = KERNADDR(p); 817 sc->sc_ri = 0; 818 sc->sc_rn = sc->sc_rs; 819 820 /* initiate capture DMA */ 821 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 822 823 /* setup format information for internal converter */ 824 sc->sc_rparam = 0; 825 if (param->precision == 8) { 826 sc->sc_rparam += CF_8BIT; 827 sc->sc_rcount <<= 1; 828 } 829 if (param->channels == 1) { 830 sc->sc_rparam += CF_MONO; 831 sc->sc_rcount <<= 1; 832 } 833 834 /* set CIE */ 835 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 836 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 837 838 sc->sc_rrate = param->sample_rate; 839 cs4280_set_adc_rate(sc, param->sample_rate); 840 841 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 842 cctl |= sc->cctl; 843 BA1WRITE4(sc, CS4280_CCTL, cctl); 844 return 0; 845 } 846 847 /* Power Hook */ 848 static void 849 cs4280_power(int why, void *v) 850 { 851 static uint32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 852 static uint32_t cctl = 0, cba = 0, cie = 0; 853 struct cs428x_softc *sc; 854 855 sc = (struct cs428x_softc *)v; 856 DPRINTF(("%s: cs4280_power why=%d\n", sc->sc_dev.dv_xname, why)); 857 switch (why) { 858 case PWR_SUSPEND: 859 case PWR_STANDBY: 860 sc->sc_suspend = why; 861 862 /* save current playback status */ 863 if (sc->sc_prun) { 864 pctl = BA1READ4(sc, CS4280_PCTL); 865 pfie = BA1READ4(sc, CS4280_PFIE); 866 pba = BA1READ4(sc, CS4280_PBA); 867 pdtc = BA1READ4(sc, CS4280_PDTC); 868 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 869 pctl, pfie, pba, pdtc)); 870 } 871 872 /* save current capture status */ 873 if (sc->sc_rrun) { 874 cctl = BA1READ4(sc, CS4280_CCTL); 875 cie = BA1READ4(sc, CS4280_CIE); 876 cba = BA1READ4(sc, CS4280_CBA); 877 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 878 cctl, cie, cba)); 879 } 880 881 /* Stop DMA */ 882 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 883 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 884 break; 885 case PWR_RESUME: 886 if (sc->sc_suspend == PWR_RESUME) { 887 printf("cs4280_power: odd, resume without suspend.\n"); 888 sc->sc_suspend = why; 889 return; 890 } 891 sc->sc_suspend = why; 892 cs4280_init(sc, 0); 893 cs4280_reset_codec(sc); 894 895 /* restore ac97 registers */ 896 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 897 898 /* restore DMA related status */ 899 if(sc->sc_prun) { 900 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 901 pctl, pfie, pba, pdtc)); 902 cs4280_set_dac_rate(sc, sc->sc_prate); 903 BA1WRITE4(sc, CS4280_PDTC, pdtc); 904 BA1WRITE4(sc, CS4280_PBA, pba); 905 BA1WRITE4(sc, CS4280_PFIE, pfie); 906 BA1WRITE4(sc, CS4280_PCTL, pctl); 907 } 908 909 if (sc->sc_rrun) { 910 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 911 cctl, cie, cba)); 912 cs4280_set_adc_rate(sc, sc->sc_rrate); 913 BA1WRITE4(sc, CS4280_CBA, cba); 914 BA1WRITE4(sc, CS4280_CIE, cie); 915 BA1WRITE4(sc, CS4280_CCTL, cctl); 916 } 917 break; 918 case PWR_SOFTSUSPEND: 919 case PWR_SOFTSTANDBY: 920 case PWR_SOFTRESUME: 921 break; 922 } 923 } 924 925 /* control AC97 codec */ 926 static int 927 cs4280_reset_codec(void *addr) 928 { 929 struct cs428x_softc *sc; 930 int n; 931 932 sc = addr; 933 934 /* Reset codec */ 935 BA0WRITE4(sc, CS428X_ACCTL, 0); 936 delay(100); /* delay 100us */ 937 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 938 939 /* 940 * It looks like we do the following procedure, too 941 */ 942 943 /* Enable AC-link sync generation */ 944 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 945 delay(50*1000); /* XXX delay 50ms */ 946 947 /* Assert valid frame signal */ 948 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 949 950 /* Wait for valid AC97 input slot */ 951 n = 0; 952 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 953 (ACISV_ISV3 | ACISV_ISV4)) { 954 delay(1000); 955 if (++n > 1000) { 956 printf("reset_codec: AC97 inputs slot ready timeout\n"); 957 return ETIMEDOUT; 958 } 959 } 960 return 0; 961 } 962 963 /* Internal functions */ 964 965 static void 966 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 967 { 968 /* calculate capture rate: 969 * 970 * capture_coefficient_increment = -round(rate*128*65536/48000; 971 * capture_phase_increment = floor(48000*65536*1024/rate); 972 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 973 * cy = floor(cx/200); 974 * capture_sample_rate_correction = cx - 200*cy; 975 * capture_delay = ceil(24*48000/rate); 976 * capture_num_triplets = floor(65536*rate/24000); 977 * capture_group_length = 24000/GCD(rate, 24000); 978 * where GCD means "Greatest Common Divisor". 979 * 980 * capture_coefficient_increment, capture_phase_increment and 981 * capture_num_triplets are 32-bit signed quantities. 982 * capture_sample_rate_correction and capture_group_length are 983 * 16-bit signed quantities. 984 * capture_delay is a 14-bit unsigned quantity. 985 */ 986 uint32_t cci, cpi, cnt, cx, cy, tmp1; 987 uint16_t csrc, cgl, cdlay; 988 989 /* XXX 990 * Even though, embedded_audio_spec says capture rate range 11025 to 991 * 48000, dhwiface.cpp says, 992 * 993 * "We can only decimate by up to a factor of 1/9th the hardware rate. 994 * Return an error if an attempt is made to stray outside that limit." 995 * 996 * so assume range as 48000/9 to 48000 997 */ 998 999 if (rate < 8000) 1000 rate = 8000; 1001 if (rate > 48000) 1002 rate = 48000; 1003 1004 cx = rate << 16; 1005 cci = cx / 48000; 1006 cx -= cci * 48000; 1007 cx <<= 7; 1008 cci <<= 7; 1009 cci += cx / 48000; 1010 cci = - cci; 1011 1012 cx = 48000 << 16; 1013 cpi = cx / rate; 1014 cx -= cpi * rate; 1015 cx <<= 10; 1016 cpi <<= 10; 1017 cy = cx / rate; 1018 cpi += cy; 1019 cx -= cy * rate; 1020 1021 cy = cx / 200; 1022 csrc = cx - 200*cy; 1023 1024 cdlay = ((48000 * 24) + rate - 1) / rate; 1025 #if 0 1026 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1027 #endif 1028 1029 cnt = rate << 16; 1030 cnt /= 24000; 1031 1032 cgl = 1; 1033 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1034 if (((rate / tmp1) * tmp1) != rate) 1035 cgl *= 2; 1036 } 1037 if (((rate / 3) * 3) != rate) 1038 cgl *= 3; 1039 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1040 if (((rate / tmp1) * tmp1) != rate) 1041 cgl *= 5; 1042 } 1043 #if 0 1044 /* XXX what manual says */ 1045 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1046 tmp1 |= csrc<<16; 1047 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1048 #else 1049 /* suggested by cs461x.c (ALSA driver) */ 1050 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1051 #endif 1052 1053 #if 0 1054 /* I am confused. The sample rate calculation section says 1055 * cci *is* 32-bit signed quantity but in the parameter description 1056 * section, CCI only assigned 16bit. 1057 * I believe size of the variable. 1058 */ 1059 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1060 tmp1 |= cci<<16; 1061 BA1WRITE4(sc, CS4280_CCI, tmp1); 1062 #else 1063 BA1WRITE4(sc, CS4280_CCI, cci); 1064 #endif 1065 1066 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1067 tmp1 |= cdlay <<18; 1068 BA1WRITE4(sc, CS4280_CD, tmp1); 1069 1070 BA1WRITE4(sc, CS4280_CPI, cpi); 1071 1072 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1073 tmp1 |= cgl; 1074 BA1WRITE4(sc, CS4280_CGL, tmp1); 1075 1076 BA1WRITE4(sc, CS4280_CNT, cnt); 1077 1078 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1079 tmp1 |= cgl; 1080 BA1WRITE4(sc, CS4280_CGC, tmp1); 1081 } 1082 1083 static void 1084 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1085 { 1086 /* 1087 * playback rate may range from 8000Hz to 48000Hz 1088 * 1089 * play_phase_increment = floor(rate*65536*1024/48000) 1090 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1091 * py=floor(px/200) 1092 * play_sample_rate_correction = px - 200*py 1093 * 1094 * play_phase_increment is a 32bit signed quantity. 1095 * play_sample_rate_correction is a 16bit signed quantity. 1096 */ 1097 int32_t ppi; 1098 int16_t psrc; 1099 uint32_t px, py; 1100 1101 if (rate < 8000) 1102 rate = 8000; 1103 if (rate > 48000) 1104 rate = 48000; 1105 px = rate << 16; 1106 ppi = px/48000; 1107 px -= ppi*48000; 1108 ppi <<= 10; 1109 px <<= 10; 1110 py = px / 48000; 1111 ppi += py; 1112 px -= py*48000; 1113 py = px/200; 1114 px -= py*200; 1115 psrc = px; 1116 #if 0 1117 /* what manual says */ 1118 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1119 BA1WRITE4(sc, CS4280_PSRC, 1120 ( ((psrc<<16) & PSRC_MASK) | px )); 1121 #else 1122 /* suggested by cs461x.c (ALSA driver) */ 1123 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1124 #endif 1125 BA1WRITE4(sc, CS4280_PPI, ppi); 1126 } 1127 1128 /* Download Proceessor Code and Data image */ 1129 static int 1130 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1131 uint32_t offset, uint32_t len) 1132 { 1133 uint32_t ctr; 1134 #if CS4280_DEBUG > 10 1135 uint32_t con, data; 1136 uint8_t c0, c1, c2, c3; 1137 #endif 1138 if ((offset & 3) || (len & 3)) 1139 return -1; 1140 1141 len /= sizeof(uint32_t); 1142 for (ctr = 0; ctr < len; ctr++) { 1143 /* XXX: 1144 * I cannot confirm this is the right thing or not 1145 * on BIG-ENDIAN machines. 1146 */ 1147 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1148 #if CS4280_DEBUG > 10 1149 data = htole32(*(src+ctr)); 1150 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1151 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1152 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1153 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1154 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1155 if (data != con ) { 1156 printf("0x%06x: write=0x%08x read=0x%08x\n", 1157 offset+ctr*4, data, con); 1158 return -1; 1159 } 1160 #endif 1161 } 1162 return 0; 1163 } 1164 1165 static int 1166 cs4280_download_image(struct cs428x_softc *sc) 1167 { 1168 int idx, err; 1169 uint32_t offset = 0; 1170 1171 err = 0; 1172 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1173 err = cs4280_download(sc, &BA1Struct.map[offset], 1174 BA1Struct.memory[idx].offset, 1175 BA1Struct.memory[idx].size); 1176 if (err != 0) { 1177 printf("%s: load_image failed at %d\n", 1178 sc->sc_dev.dv_xname, idx); 1179 return -1; 1180 } 1181 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1182 } 1183 return err; 1184 } 1185 1186 /* Processor Soft Reset */ 1187 static void 1188 cs4280_reset(void *sc_) 1189 { 1190 struct cs428x_softc *sc; 1191 1192 sc = sc_; 1193 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1194 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1195 delay(100); 1196 /* Clear RSTSP bit in SPCR */ 1197 BA1WRITE4(sc, CS4280_SPCR, 0); 1198 /* enable DMA reqest */ 1199 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1200 } 1201 1202 static int 1203 cs4280_init(struct cs428x_softc *sc, int init) 1204 { 1205 int n; 1206 uint32_t mem; 1207 1208 /* Start PLL out in known state */ 1209 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1210 /* Start serial ports out in known state */ 1211 BA0WRITE4(sc, CS4280_SERMC1, 0); 1212 1213 /* Specify type of CODEC */ 1214 /* XXX should not be here */ 1215 #define SERACC_CODEC_TYPE_1_03 1216 #ifdef SERACC_CODEC_TYPE_1_03 1217 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1218 #else 1219 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1220 #endif 1221 1222 /* Reset codec */ 1223 BA0WRITE4(sc, CS428X_ACCTL, 0); 1224 delay(100); /* delay 100us */ 1225 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1226 1227 /* Enable AC-link sync generation */ 1228 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1229 delay(50*1000); /* delay 50ms */ 1230 1231 /* Set the serial port timing configuration */ 1232 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1233 1234 /* Setup clock control */ 1235 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1236 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1237 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1238 1239 /* Power up the PLL */ 1240 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1241 delay(50*1000); /* delay 50ms */ 1242 1243 /* Turn on clock */ 1244 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1245 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1246 1247 /* Set the serial port FIFO pointer to the 1248 * first sample in FIFO. (not documented) */ 1249 cs4280_clear_fifos(sc); 1250 1251 #if 0 1252 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1253 BA0WRITE4(sc, CS4280_SERBSP, 0); 1254 #endif 1255 1256 /* Configure the serial port */ 1257 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1258 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1259 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1260 1261 /* Wait for CODEC ready */ 1262 n = 0; 1263 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1264 delay(125); 1265 if (++n > 1000) { 1266 printf("%s: codec ready timeout\n", 1267 sc->sc_dev.dv_xname); 1268 return 1; 1269 } 1270 } 1271 1272 /* Assert valid frame signal */ 1273 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1274 1275 /* Wait for valid AC97 input slot */ 1276 n = 0; 1277 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1278 (ACISV_ISV3 | ACISV_ISV4)) { 1279 delay(1000); 1280 if (++n > 1000) { 1281 printf("AC97 inputs slot ready timeout\n"); 1282 return 1; 1283 } 1284 } 1285 1286 /* Set AC97 output slot valid signals */ 1287 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1288 1289 /* reset the processor */ 1290 cs4280_reset(sc); 1291 1292 /* Download the image to the processor */ 1293 if (cs4280_download_image(sc) != 0) { 1294 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1295 return 1; 1296 } 1297 1298 /* Save playback parameter and then write zero. 1299 * this ensures that DMA doesn't immediately occur upon 1300 * starting the processor core 1301 */ 1302 mem = BA1READ4(sc, CS4280_PCTL); 1303 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1304 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1305 if (init != 0) 1306 sc->sc_prun = 0; 1307 1308 /* Save capture parameter and then write zero. 1309 * this ensures that DMA doesn't immediately occur upon 1310 * starting the processor core 1311 */ 1312 mem = BA1READ4(sc, CS4280_CCTL); 1313 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1314 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1315 if (init != 0) 1316 sc->sc_rrun = 0; 1317 1318 /* Processor Startup Procedure */ 1319 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1320 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1321 1322 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1323 n = 0; 1324 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1325 delay(10); 1326 if (++n > 1000) { 1327 printf("SPCR 1->0 transition timeout\n"); 1328 return 1; 1329 } 1330 } 1331 1332 n = 0; 1333 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1334 delay(10); 1335 if (++n > 1000) { 1336 printf("SPCS 0->1 transition timeout\n"); 1337 return 1; 1338 } 1339 } 1340 /* Processor is now running !!! */ 1341 1342 /* Setup volume */ 1343 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1344 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1345 1346 /* Interrupt enable */ 1347 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1348 1349 /* playback interrupt enable */ 1350 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1351 mem |= PFIE_PI_ENABLE; 1352 BA1WRITE4(sc, CS4280_PFIE, mem); 1353 /* capture interrupt enable */ 1354 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1355 mem |= CIE_CI_ENABLE; 1356 BA1WRITE4(sc, CS4280_CIE, mem); 1357 1358 #if NMIDI > 0 1359 /* Reset midi port */ 1360 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1361 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1362 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1363 /* midi interrupt enable */ 1364 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1365 BA0WRITE4(sc, CS4280_MIDCR, mem); 1366 #endif 1367 return 0; 1368 } 1369 1370 static void 1371 cs4280_clear_fifos(struct cs428x_softc *sc) 1372 { 1373 int pd, cnt, n; 1374 uint32_t mem; 1375 1376 pd = 0; 1377 /* 1378 * If device power down, power up the device and keep power down 1379 * state. 1380 */ 1381 mem = BA0READ4(sc, CS4280_CLKCR1); 1382 if (!(mem & CLKCR1_SWCE)) { 1383 printf("cs4280_clear_fifo: power down found.\n"); 1384 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1385 pd = 1; 1386 } 1387 BA0WRITE4(sc, CS4280_SERBWP, 0); 1388 for (cnt = 0; cnt < 256; cnt++) { 1389 n = 0; 1390 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1391 delay(1000); 1392 if (++n > 1000) { 1393 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1394 break; 1395 } 1396 } 1397 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1398 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1399 } 1400 if (pd) 1401 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1402 } 1403 1404 #if NMIDI > 0 1405 static int 1406 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1407 void (*ointr)(void *), void *arg) 1408 { 1409 struct cs428x_softc *sc; 1410 uint32_t mem; 1411 1412 DPRINTF(("midi_open\n")); 1413 sc = addr; 1414 sc->sc_iintr = iintr; 1415 sc->sc_ointr = ointr; 1416 sc->sc_arg = arg; 1417 1418 /* midi interrupt enable */ 1419 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1420 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1421 BA0WRITE4(sc, CS4280_MIDCR, mem); 1422 #ifdef CS4280_DEBUG 1423 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1424 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1425 return(EINVAL); 1426 } 1427 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1428 #endif 1429 return 0; 1430 } 1431 1432 static void 1433 cs4280_midi_close(void *addr) 1434 { 1435 struct cs428x_softc *sc; 1436 uint32_t mem; 1437 1438 DPRINTF(("midi_close\n")); 1439 sc = addr; 1440 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1441 mem = BA0READ4(sc, CS4280_MIDCR); 1442 mem &= ~MIDCR_MASK; 1443 BA0WRITE4(sc, CS4280_MIDCR, mem); 1444 1445 sc->sc_iintr = 0; 1446 sc->sc_ointr = 0; 1447 } 1448 1449 static int 1450 cs4280_midi_output(void *addr, int d) 1451 { 1452 struct cs428x_softc *sc; 1453 uint32_t mem; 1454 int x; 1455 1456 sc = addr; 1457 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1458 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1459 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1460 mem |= d & MIDWP_MASK; 1461 DPRINTFN(5,("midi_output d=0x%08x",d)); 1462 BA0WRITE4(sc, CS4280_MIDWP, mem); 1463 #ifdef DIAGNOSTIC 1464 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1465 DPRINTF(("Bad write data: %d %d", 1466 mem, BA0READ4(sc, CS4280_MIDWP))); 1467 return EIO; 1468 } 1469 #endif 1470 return 0; 1471 } 1472 delay(MIDI_BUSY_DELAY); 1473 } 1474 return EIO; 1475 } 1476 1477 static void 1478 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1479 { 1480 1481 mi->name = "CS4280 MIDI UART"; 1482 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1483 } 1484 1485 #endif /* NMIDI */ 1486 1487 /* DEBUG functions */ 1488 #if CS4280_DEBUG > 10 1489 static int 1490 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1491 uint32_t offset, uint32_t len) 1492 { 1493 uint32_t ctr, data; 1494 int err; 1495 1496 if ((offset & 3) || (len & 3)) 1497 return -1; 1498 1499 err = 0; 1500 len /= sizeof(uint32_t); 1501 for (ctr = 0; ctr < len; ctr++) { 1502 /* I cannot confirm this is the right thing 1503 * on BIG-ENDIAN machines 1504 */ 1505 data = BA1READ4(sc, offset+ctr*4); 1506 if (data != htole32(*(src+ctr))) { 1507 printf("0x%06x: 0x%08x(0x%08x)\n", 1508 offset+ctr*4, data, *(src+ctr)); 1509 *(src+ctr) = data; 1510 ++err; 1511 } 1512 } 1513 return err; 1514 } 1515 1516 static int 1517 cs4280_check_images(struct cs428x_softc *sc) 1518 { 1519 int idx, err; 1520 uint32_t offset; 1521 1522 offset = 0; 1523 err = 0; 1524 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1525 for (idx = 0; idx < 1; ++idx) { 1526 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1527 BA1Struct.memory[idx].offset, 1528 BA1Struct.memory[idx].size); 1529 if (err != 0) { 1530 printf("%s: check_image failed at %d\n", 1531 sc->sc_dev.dv_xname, idx); 1532 } 1533 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1534 } 1535 return err; 1536 } 1537 1538 #endif /* CS4280_DEBUG */ 1539
Indexes created Thu Oct 02 14:10:14 GMT 2025