cs4280.c revision 1.3
1 /* $NetBSD: cs4280.c,v 1.3 2000/05/15 01:27:46 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 */ 41 42 /* 43 * TODO 44 * Implement MIDI 45 * Joystick support 46 */ 47 48 #ifdef CS4280_DEBUG 49 #ifndef MIDI_READY 50 #define MIDI_READY 51 #endif /* ! MIDI_READY */ 52 #endif 53 54 #ifdef MIDI_READY 55 #include "midi.h" 56 #endif 57 58 #if defined(CS4280_DEBUG) 59 #define DPRINTF(x) if (cs4280debug) printf x 60 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 61 int cs4280debug = 0; 62 #else 63 #define DPRINTF(x) 64 #define DPRINTFN(n,x) 65 #endif 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/fcntl.h> 71 #include <sys/malloc.h> 72 #include <sys/device.h> 73 #include <sys/types.h> 74 #include <sys/systm.h> 75 76 #include <dev/pci/pcidevs.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/cs4280reg.h> 79 #include <dev/pci/cs4280_image.h> 80 81 #include <sys/audioio.h> 82 #include <dev/audio_if.h> 83 #include <dev/midi_if.h> 84 #include <dev/mulaw.h> 85 #include <dev/auconv.h> 86 #include <dev/ic/ac97var.h> 87 88 #include <machine/bus.h> 89 #include <machine/bswap.h> 90 91 #define CSCC_PCI_BA0 0x10 92 #define CSCC_PCI_BA1 0x14 93 94 struct cs4280_dma { 95 bus_dmamap_t map; 96 caddr_t addr; /* real dma buffer */ 97 caddr_t dum; /* dummy buffer for audio driver */ 98 bus_dma_segment_t segs[1]; 99 int nsegs; 100 size_t size; 101 struct cs4280_dma *next; 102 }; 103 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 104 #define BUFADDR(p) ((void *)((p)->dum)) 105 #define KERNADDR(p) ((void *)((p)->addr)) 106 107 /* 108 * Software state 109 */ 110 struct cs4280_softc { 111 struct device sc_dev; 112 113 pci_intr_handle_t * sc_ih; 114 115 /* I/O (BA0) */ 116 bus_space_tag_t ba0t; 117 bus_space_handle_t ba0h; 118 119 /* BA1 */ 120 bus_space_tag_t ba1t; 121 bus_space_handle_t ba1h; 122 123 /* DMA */ 124 bus_dma_tag_t sc_dmatag; 125 struct cs4280_dma *sc_dmas; 126 127 void (*sc_pintr)(void *); /* dma completion intr handler */ 128 void *sc_parg; /* arg for sc_intr() */ 129 char *sc_ps, *sc_pe, *sc_pn; 130 int sc_pcount; 131 int sc_pi; 132 struct cs4280_dma *sc_pdma; 133 char *sc_pbuf; 134 #ifdef DIAGNOSTIC 135 char sc_prun; 136 #endif 137 138 void (*sc_rintr)(void *); /* dma completion intr handler */ 139 void *sc_rarg; /* arg for sc_intr() */ 140 char *sc_rs, *sc_re, *sc_rn; 141 int sc_rcount; 142 int sc_ri; 143 struct cs4280_dma *sc_rdma; 144 char *sc_rbuf; 145 int sc_rparam; /* record format */ 146 #ifdef DIAGNOSTIC 147 char sc_rrun; 148 #endif 149 150 #if NMIDI > 0 151 void (*sc_iintr)(void *, int); /* midi input ready handler */ 152 void (*sc_ointr)(void *); /* midi output ready handler */ 153 void *sc_arg; 154 #endif 155 156 u_int32_t pctl; 157 u_int32_t cctl; 158 159 struct ac97_codec_if *codec_if; 160 struct ac97_host_if host_if; 161 162 char sc_suspend; 163 void *sc_powerhook; /* Power Hook */ 164 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 165 }; 166 167 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 168 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 169 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 170 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 171 172 int cs4280_match __P((struct device *, struct cfdata *, void *)); 173 void cs4280_attach __P((struct device *, struct device *, void *)); 174 int cs4280_intr __P((void *)); 175 void cs4280_reset __P((void *)); 176 int cs4280_download_image __P((struct cs4280_softc *)); 177 178 int cs4280_download(struct cs4280_softc *, u_int32_t *, u_int32_t, u_int32_t); 179 int cs4280_allocmem __P((struct cs4280_softc *, size_t, size_t, 180 struct cs4280_dma *)); 181 int cs4280_freemem __P((struct cs4280_softc *, struct cs4280_dma *)); 182 183 #ifdef CS4280_DEBUG 184 int cs4280_check_images __P((struct cs4280_softc *)); 185 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 186 u_int32_t); 187 #endif 188 189 struct cfattach clcs_ca = { 190 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 191 }; 192 193 int cs4280_init __P((struct cs4280_softc *, int)); 194 int cs4280_open __P((void *, int)); 195 void cs4280_close __P((void *)); 196 197 int cs4280_query_encoding __P((void *, struct audio_encoding *)); 198 int cs4280_set_params __P((void *, int, int, struct audio_params *, struct audio_params *)); 199 int cs4280_round_blocksize __P((void *, int)); 200 201 int cs4280_halt_output __P((void *)); 202 int cs4280_halt_input __P((void *)); 203 204 int cs4280_getdev __P((void *, struct audio_device *)); 205 206 int cs4280_mixer_set_port __P((void *, mixer_ctrl_t *)); 207 int cs4280_mixer_get_port __P((void *, mixer_ctrl_t *)); 208 int cs4280_query_devinfo __P((void *addr, mixer_devinfo_t *dip)); 209 void *cs4280_malloc __P((void *, int, size_t, int, int)); 210 void cs4280_free __P((void *, void *, int)); 211 size_t cs4280_round_buffersize __P((void *, int, size_t)); 212 int cs4280_mappage __P((void *, void *, int, int)); 213 int cs4280_get_props __P((void *)); 214 int cs4280_trigger_output __P((void *, void *, void *, int, void (*)(void *), 215 void *, struct audio_params *)); 216 int cs4280_trigger_input __P((void *, void *, void *, int, void (*)(void *), 217 void *, struct audio_params *)); 218 219 220 void cs4280_set_dac_rate __P((struct cs4280_softc *, int )); 221 void cs4280_set_adc_rate __P((struct cs4280_softc *, int )); 222 int cs4280_get_portnum_by_name __P((struct cs4280_softc *, char *, char *, 223 char *)); 224 int cs4280_src_wait __P((struct cs4280_softc *)); 225 int cs4280_attach_codec __P((void *sc, struct ac97_codec_if *)); 226 int cs4280_read_codec __P((void *sc, u_int8_t a, u_int16_t *d)); 227 int cs4280_write_codec __P((void *sc, u_int8_t a, u_int16_t d)); 228 void cs4280_reset_codec __P((void *sc)); 229 230 void cs4280_power __P((int, void *)); 231 232 void cs4280_clear_fifos __P((struct cs4280_softc *)); 233 234 #if NMIDI > 0 235 void cs4280_midi_close __P((void*)); 236 void cs4280_midi_getinfo __P((void *, struct midi_info *)); 237 int cs4280_midi_open __P((void *, int, void (*)(void *, int), 238 void (*)(void *), void *)); 239 int cs4280_midi_output __P((void *, int)); 240 #endif 241 242 struct audio_hw_if cs4280_hw_if = { 243 cs4280_open, 244 cs4280_close, 245 NULL, 246 cs4280_query_encoding, 247 cs4280_set_params, 248 cs4280_round_blocksize, 249 NULL, 250 NULL, 251 NULL, 252 NULL, 253 NULL, 254 cs4280_halt_output, 255 cs4280_halt_input, 256 NULL, 257 cs4280_getdev, 258 NULL, 259 cs4280_mixer_set_port, 260 cs4280_mixer_get_port, 261 cs4280_query_devinfo, 262 cs4280_malloc, 263 cs4280_free, 264 cs4280_round_buffersize, 265 cs4280_mappage, 266 cs4280_get_props, 267 cs4280_trigger_output, 268 cs4280_trigger_input, 269 }; 270 271 #if NMIDI > 0 272 struct midi_hw_if cs4280_midi_hw_if = { 273 cs4280_midi_open, 274 cs4280_midi_close, 275 cs4280_midi_output, 276 cs4280_midi_getinfo, 277 0, 278 }; 279 #endif 280 281 282 283 struct audio_device cs4280_device = { 284 "CS4280", 285 "", 286 "cs4280" 287 }; 288 289 290 int 291 cs4280_match(parent, match, aux) 292 struct device *parent; 293 struct cfdata *match; 294 void *aux; 295 { 296 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 297 298 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 299 return (0); 300 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 301 #if 0 /* I can't confirm */ 302 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 303 #endif 304 305 ) { 306 return (1); 307 } 308 return (0); 309 } 310 311 int 312 cs4280_read_codec(sc_, add, data) 313 void *sc_; 314 u_int8_t add; 315 u_int16_t *data; 316 { 317 struct cs4280_softc *sc = sc_; 318 int n; 319 320 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 321 /* 322 * Make sure that there is not data sitting around from a preivous 323 * uncompleted access. 324 */ 325 BA0READ4(sc, CS4280_ACSDA); 326 327 /* Set up AC97 control registers. */ 328 BA0WRITE4(sc, CS4280_ACCAD, add); 329 BA0WRITE4(sc, CS4280_ACCDA, 0); 330 BA0WRITE4(sc, CS4280_ACCTL, 331 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 332 333 if (cs4280_src_wait(sc) < 0) { 334 printf("%s: AC97 read prob. (DCV!=0) for add=0x%0x\n", 335 sc->sc_dev.dv_xname, add); 336 return (1); 337 } 338 339 /* wait for valid status bit is active */ 340 n = 0; 341 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 342 delay(1); 343 while (++n > 1000) { 344 printf("%s: AC97 read fail (VSTS==0) for add=0x%0x\n", 345 sc->sc_dev.dv_xname, add); 346 return (1); 347 } 348 } 349 *data = BA0READ4(sc, CS4280_ACSDA); 350 DPRINTFN(5,("data=0x%04x\n", *data)); 351 return (0); 352 } 353 354 int 355 cs4280_write_codec(sc_, add, data) 356 void *sc_; 357 u_int8_t add; 358 u_int16_t data; 359 { 360 struct cs4280_softc *sc = sc_; 361 362 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 363 BA0WRITE4(sc, CS4280_ACCAD, add); 364 BA0WRITE4(sc, CS4280_ACCDA, data); 365 BA0WRITE4(sc, CS4280_ACCTL, 366 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 367 368 if (cs4280_src_wait(sc) < 0) { 369 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 370 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 371 return (1); 372 } 373 return (0); 374 } 375 376 int 377 cs4280_src_wait(sc) 378 struct cs4280_softc *sc; 379 { 380 int n; 381 n = 0; 382 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 383 delay(1000); 384 while (++n > 1000) 385 return (-1); 386 } 387 return (0); 388 } 389 390 391 void 392 cs4280_set_adc_rate(sc, rate) 393 struct cs4280_softc *sc; 394 int rate; 395 { 396 /* calculate capture rate: 397 * 398 * capture_coefficient_increment = -round(rate*128*65536/48000; 399 * capture_phase_increment = floor(48000*65536*1024/rate); 400 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 401 * cy = floor(cx/200); 402 * capture_sample_rate_correction = cx - 200*cy; 403 * capture_delay = ceil(24*48000/rate); 404 * capture_num_triplets = floor(65536*rate/24000); 405 * capture_group_length = 24000/GCD(rate, 24000); 406 * where GCD means "Greatest Common Divisor". 407 * 408 * capture_coefficient_increment, capture_phase_increment and 409 * capture_num_triplets are 32-bit signed quantities. 410 * capture_sample_rate_correction and capture_group_length are 411 * 16-bit signed quantities. 412 * capture_delay is a 14-bit unsigned quantity. 413 */ 414 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 415 u_int16_t csrc, cgl, cdlay; 416 417 /* XXX 418 * Even though, embedded_audio_spec says capture rate range 11025 to 419 * 48000, dhwiface.cpp says, 420 * 421 * "We can only decimate by up to a factor of 1/9th the hardware rate. 422 * Return an error if an attempt is made to stray outside that limit." 423 * 424 * so assume range as 48000/9 to 48000 425 */ 426 427 if (rate < 8000) 428 rate = 8000; 429 if (rate > 48000) 430 rate = 48000; 431 432 cx = rate << 16; 433 cci = cx / 48000; 434 cx -= cci * 48000; 435 cx <<= 7; 436 cci <<= 7; 437 cci += cx / 48000; 438 cci = - cci; 439 440 cx = 48000 << 16; 441 cpi = cx / rate; 442 cx -= cpi * rate; 443 cx <<= 10; 444 cpi <<= 10; 445 cy = cx / rate; 446 cpi += cy; 447 cx -= cy * rate; 448 449 cy = cx / 200; 450 csrc = cx - 200*cy; 451 452 cdlay = ((48000 * 24) + rate - 1) / rate; 453 #if 0 454 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 455 #endif 456 457 cnt = rate << 16; 458 cnt /= 24000; 459 460 cgl = 1; 461 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 462 if (((rate / tmp1) * tmp1) != rate) 463 cgl *= 2; 464 } 465 if (((rate / 3) * 3) != rate) 466 cgl *= 3; 467 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 468 if (((rate / tmp1) * tmp1) != rate) 469 cgl *= 5; 470 } 471 #if 0 472 /* XXX what manual says */ 473 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 474 tmp1 |= csrc<<16; 475 BA1WRITE4(sc, CS4280_CSRC, tmp1); 476 #else 477 /* suggested by cs461x.c (ALSA driver) */ 478 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 479 #endif 480 481 #if 0 482 /* I am confused. The sample rate calculation section says 483 * cci *is* 32-bit signed quantity but in the parameter description 484 * section, CCI only assigned 16bit. 485 * I believe size of the variable. 486 */ 487 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 488 tmp1 |= cci<<16; 489 BA1WRITE4(sc, CS4280_CCI, tmp1); 490 #else 491 BA1WRITE4(sc, CS4280_CCI, cci); 492 #endif 493 494 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 495 tmp1 |= cdlay <<18; 496 BA1WRITE4(sc, CS4280_CD, tmp1); 497 498 BA1WRITE4(sc, CS4280_CPI, cpi); 499 500 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 501 tmp1 |= cgl; 502 BA1WRITE4(sc, CS4280_CGL, tmp1); 503 504 BA1WRITE4(sc, CS4280_CNT, cnt); 505 506 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 507 tmp1 |= cgl; 508 BA1WRITE4(sc, CS4280_CGC, tmp1); 509 } 510 511 void 512 cs4280_set_dac_rate(sc, rate) 513 struct cs4280_softc *sc; 514 int rate; 515 { 516 /* 517 * playback rate may range from 8000Hz to 48000Hz 518 * 519 * play_phase_increment = floor(rate*65536*1024/48000) 520 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 521 * py=floor(px/200) 522 * play_sample_rate_correction = px - 200*py 523 * 524 * play_phase_increment is a 32bit signed quantity. 525 * play_sample_rate_correction is a 16bit signed quantity. 526 */ 527 int32_t ppi; 528 int16_t psrc; 529 u_int32_t px, py; 530 531 if (rate < 8000) 532 rate = 8000; 533 if (rate > 48000) 534 rate = 48000; 535 px = rate << 16; 536 ppi = px/48000; 537 px -= ppi*48000; 538 ppi <<= 10; 539 px <<= 10; 540 py = px / 48000; 541 ppi += py; 542 px -= py*48000; 543 py = px/200; 544 px -= py*200; 545 psrc = px; 546 #if 0 547 /* what manual says */ 548 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 549 BA1WRITE4(sc, CS4280_PSRC, 550 ( ((psrc<<16) & PSRC_MASK) | px )); 551 #else 552 /* suggested by cs461x.c (ALSA driver) */ 553 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 554 #endif 555 BA1WRITE4(sc, CS4280_PPI, ppi); 556 } 557 558 void 559 cs4280_attach(parent, self, aux) 560 struct device *parent; 561 struct device *self; 562 void *aux; 563 { 564 struct cs4280_softc *sc = (struct cs4280_softc *)self; 565 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 566 pci_chipset_tag_t pc = pa->pa_pc; 567 char const *intrstr; 568 pci_intr_handle_t ih; 569 pcireg_t csr; 570 char devinfo[256]; 571 mixer_ctrl_t ctl; 572 u_int32_t mem; 573 574 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 575 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 576 577 /* Map I/O register */ 578 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 579 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 580 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 581 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 582 return; 583 } 584 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 585 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 586 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 587 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 588 return; 589 } 590 591 sc->sc_dmatag = pa->pa_dmat; 592 593 /* Enable the device (set bus master flag) */ 594 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 595 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 596 csr | PCI_COMMAND_MASTER_ENABLE); 597 598 /* LATENCY_TIMER setting */ 599 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 600 if ( PCI_LATTIMER(mem) < 32 ) { 601 mem &= 0xffff00ff; 602 mem |= 0x00002000; 603 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 604 } 605 606 /* Map and establish the interrupt. */ 607 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 608 pa->pa_intrline, &ih)) { 609 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 610 return; 611 } 612 intrstr = pci_intr_string(pc, ih); 613 614 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 615 if (sc->sc_ih == NULL) { 616 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 617 if (intrstr != NULL) 618 printf(" at %s", intrstr); 619 printf("\n"); 620 return; 621 } 622 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 623 624 /* Initialization */ 625 if(cs4280_init(sc, 1) != 0) 626 return; 627 628 /* AC 97 attachement */ 629 sc->host_if.arg = sc; 630 sc->host_if.attach = cs4280_attach_codec; 631 sc->host_if.read = cs4280_read_codec; 632 sc->host_if.write = cs4280_write_codec; 633 sc->host_if.reset = cs4280_reset_codec; 634 635 if (ac97_attach(&sc->host_if) != 0) { 636 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 637 return; 638 } 639 640 /* Turn mute off of DAC, CD and master volumes by default */ 641 ctl.type = AUDIO_MIXER_ENUM; 642 ctl.un.ord = 0; /* off */ 643 644 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 645 AudioNmaster, AudioNmute); 646 cs4280_mixer_set_port(sc, &ctl); 647 648 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 649 AudioNdac, AudioNmute); 650 cs4280_mixer_set_port(sc, &ctl); 651 652 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 653 AudioNcd, AudioNmute); 654 cs4280_mixer_set_port(sc, &ctl); 655 656 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 657 658 #if NMIDI > 0 659 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 660 #endif 661 sc->sc_suspend = PWR_RESUME; 662 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 663 } 664 665 int 666 cs4280_intr(p) 667 void *p; 668 { 669 /* 670 * XXX 671 * 672 * Since CS4280 has only 4kB dma buffer and 673 * interrupt occurs every 2kB block, I create dummy buffer 674 * which returns to audio driver and actual dma buffer 675 * using in DMA transfer. 676 * 677 * 678 * ring buffer in audio.c is pointed by BUFADDR 679 * <------ ring buffer size == 64kB ------> 680 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 681 * |= = = =|= = = =|= = = =|= = = =|= = = =| 682 * | | | | | | <- call audio_intp every 683 * sc->sc_[pr]_count time. 684 * 685 * actual dma buffer is pointed by KERNADDR 686 * <-> dma buffer size = 4kB 687 * |= =| 688 * 689 * 690 */ 691 struct cs4280_softc *sc = p; 692 u_int32_t intr, mem; 693 char * empty_dma; 694 695 intr = BA0READ4(sc, CS4280_HISR); 696 697 if ((intr & HISR_INTENA) == 0) { 698 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 699 return (0); 700 } 701 702 /* Playback Interrupt */ 703 if (intr & HISR_PINT) { 704 mem = BA1READ4(sc, CS4280_PFIE); 705 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 706 if (sc->sc_pintr) { 707 if ((sc->sc_pi%sc->sc_pcount) == 0) 708 sc->sc_pintr(sc->sc_parg); 709 } else { 710 printf("unexpected play intr\n"); 711 } 712 /* copy buffer */ 713 ++sc->sc_pi; 714 empty_dma = sc->sc_pdma->addr; 715 if (sc->sc_pi&1) 716 empty_dma += CS4280_ICHUNK; 717 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 718 sc->sc_pn += CS4280_ICHUNK; 719 if (sc->sc_pn >= sc->sc_pe) 720 sc->sc_pn = sc->sc_ps; 721 BA1WRITE4(sc, CS4280_PFIE, mem); 722 } 723 /* Capture Interrupt */ 724 if (intr & HISR_CINT) { 725 int i; 726 int16_t rdata; 727 728 mem = BA1READ4(sc, CS4280_CIE); 729 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 730 ++sc->sc_ri; 731 empty_dma = sc->sc_rdma->addr; 732 if ((sc->sc_ri&1) == 0) 733 empty_dma += CS4280_ICHUNK; 734 735 /* 736 * XXX 737 * I think this audio data conversion should be 738 * happend in upper layer, but I put this here 739 * since there is no conversion function available. 740 */ 741 switch(sc->sc_rparam) { 742 case CF_16BIT_STEREO: 743 /* just copy it */ 744 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 745 sc->sc_rn += CS4280_ICHUNK; 746 break; 747 case CF_16BIT_MONO: 748 for (i = 0; i < 512; i++) { 749 rdata = *((int16_t *)empty_dma)++>>1; 750 rdata += *((int16_t *)empty_dma)++>>1; 751 *((int16_t *)sc->sc_rn)++ = rdata; 752 } 753 break; 754 case CF_8BIT_STEREO: 755 for (i = 0; i < 512; i++) { 756 rdata = *((int16_t*)empty_dma)++; 757 *sc->sc_rn++ = rdata >> 8; 758 rdata = *((int16_t*)empty_dma)++; 759 *sc->sc_rn++ = rdata >> 8; 760 } 761 break; 762 case CF_8BIT_MONO: 763 for (i = 0; i < 512; i++) { 764 rdata = *((int16_t*)empty_dma)++ >>1; 765 rdata += *((int16_t*)empty_dma)++ >>1; 766 *sc->sc_rn++ = rdata >>8; 767 } 768 break; 769 default: 770 /* Should not reach here */ 771 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 772 } 773 if (sc->sc_rn >= sc->sc_re) 774 sc->sc_rn = sc->sc_rs; 775 BA1WRITE4(sc, CS4280_CIE, mem); 776 if (sc->sc_rintr) { 777 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 778 sc->sc_rintr(sc->sc_rarg); 779 } else { 780 printf("unexpected record intr\n"); 781 } 782 } 783 784 #if NMIDI > 0 785 /* Midi port Interrupt */ 786 if (intr & HISR_MIDI) { 787 int data; 788 789 DPRINTF(("i: %d: ", 790 BA0READ4(sc, CS4280_MIDSR))); 791 /* Read the received data */ 792 while ((sc->sc_iintr != NULL) && 793 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 794 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 795 DPRINTF(("r:%x\n",data)); 796 sc->sc_iintr(sc->sc_arg, data); 797 } 798 799 /* Write the data */ 800 #if 1 801 /* XXX: 802 * It seems "Transmit Buffer Full" never activate until EOI 803 * is deliverd. Shall I throw EOI top of this routine ? 804 */ 805 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 806 DPRINTF(("w: ")); 807 if (sc->sc_ointr != NULL) 808 sc->sc_ointr(sc->sc_arg); 809 } 810 #else 811 while ((sc->sc_ointr != NULL) && 812 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 813 DPRINTF(("w: ")); 814 sc->sc_ointr(sc->sc_arg); 815 } 816 #endif 817 DPRINTF(("\n")); 818 } 819 #endif 820 /* Throw EOI */ 821 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 822 return (0); 823 } 824 825 826 /* Download Proceessor Code and Data image */ 827 828 int 829 cs4280_download(sc, src, offset, len) 830 struct cs4280_softc *sc; 831 u_int32_t *src; 832 u_int32_t offset, len; 833 { 834 u_int32_t ctr; 835 836 #ifdef CS4280_DEBUG 837 u_int32_t con, data; 838 u_int8_t c0,c1,c2,c3; 839 #endif 840 if ((offset&3) || (len&3)) 841 return (-1); 842 843 len /= sizeof(u_int32_t); 844 for (ctr = 0; ctr < len; ctr++) { 845 /* XXX: 846 * I cannot confirm this is the right thing or not 847 * on BIG-ENDIAN machines. 848 */ 849 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 850 #ifdef CS4280_DEBUG 851 data = htole32(*(src+ctr)); 852 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 853 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 854 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 855 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 856 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 857 if (data != con ) { 858 printf("0x%06x: write=0x%08x read=0x%08x\n", 859 offset+ctr*4, data, con); 860 return (-1); 861 } 862 #endif 863 } 864 return (0); 865 } 866 867 int 868 cs4280_download_image(sc) 869 struct cs4280_softc *sc; 870 { 871 int idx, err; 872 u_int32_t offset = 0; 873 874 err = 0; 875 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 876 err = cs4280_download(sc, &BA1Struct.map[offset], 877 BA1Struct.memory[idx].offset, 878 BA1Struct.memory[idx].size); 879 if (err != 0) { 880 printf("%s: load_image failed at %d\n", 881 sc->sc_dev.dv_xname, idx); 882 return (-1); 883 } 884 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 885 } 886 return (err); 887 } 888 889 #ifdef CS4280_DEBUG 890 int 891 cs4280_checkimage(sc, src, offset, len) 892 struct cs4280_softc *sc; 893 u_int32_t *src; 894 u_int32_t offset, len; 895 { 896 u_int32_t ctr, data; 897 int err = 0; 898 899 if ((offset&3) || (len&3)) 900 return -1; 901 902 len /= sizeof(u_int32_t); 903 for (ctr = 0; ctr < len; ctr++) { 904 /* I cannot confirm this is the right thing 905 * on BIG-ENDIAN machines 906 */ 907 data = BA1READ4(sc, offset+ctr*4); 908 if (data != htole32(*(src+ctr))) { 909 printf("0x%06x: 0x%08x(0x%08x)\n", 910 offset+ctr*4, data, *(src+ctr)); 911 *(src+ctr) = data; 912 ++err; 913 } 914 } 915 return (err); 916 } 917 918 int 919 cs4280_check_images(sc) 920 struct cs4280_softc *sc; 921 { 922 int idx, err; 923 u_int32_t offset = 0; 924 925 err = 0; 926 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 927 for (idx = 0; idx < 1; ++idx) { 928 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 929 BA1Struct.memory[idx].offset, 930 BA1Struct.memory[idx].size); 931 if (err != 0) { 932 printf("%s: check_image failed at %d\n", 933 sc->sc_dev.dv_xname, idx); 934 } 935 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 936 } 937 return (err); 938 } 939 940 #endif 941 942 int 943 cs4280_attach_codec(sc_, codec_if) 944 void *sc_; 945 struct ac97_codec_if *codec_if; 946 { 947 struct cs4280_softc *sc = sc_; 948 949 sc->codec_if = codec_if; 950 return (0); 951 } 952 953 void 954 cs4280_reset_codec(sc_) 955 void *sc_; 956 { 957 struct cs4280_softc *sc = sc_; 958 int n; 959 960 /* Reset codec */ 961 BA0WRITE4(sc, CS4280_ACCTL, 0); 962 delay(100); /* delay 100us */ 963 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 964 965 /* 966 * It looks like we do the following procedure, too 967 */ 968 969 /* Enable AC-link sync generation */ 970 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 971 delay(50*1000); /* XXX delay 50ms */ 972 973 /* Assert valid frame signal */ 974 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 975 976 /* Wait for valid AC97 input slot */ 977 n = 0; 978 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 979 delay(1000); 980 if (++n > 1000) { 981 printf("reset_codec: AC97 inputs slot ready timeout\n"); 982 return; 983 } 984 } 985 } 986 987 988 /* Processor Soft Reset */ 989 void 990 cs4280_reset(sc_) 991 void *sc_; 992 { 993 struct cs4280_softc *sc = sc_; 994 995 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 996 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 997 delay(100); 998 /* Clear RSTSP bit in SPCR */ 999 BA1WRITE4(sc, CS4280_SPCR, 0); 1000 /* enable DMA reqest */ 1001 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1002 } 1003 1004 int 1005 cs4280_open(addr, flags) 1006 void *addr; 1007 int flags; 1008 { 1009 return (0); 1010 } 1011 1012 void 1013 cs4280_close(addr) 1014 void *addr; 1015 { 1016 struct cs4280_softc *sc = addr; 1017 1018 cs4280_halt_output(sc); 1019 cs4280_halt_input(sc); 1020 1021 sc->sc_pintr = 0; 1022 sc->sc_rintr = 0; 1023 } 1024 1025 int 1026 cs4280_query_encoding(addr, fp) 1027 void *addr; 1028 struct audio_encoding *fp; 1029 { 1030 switch (fp->index) { 1031 case 0: 1032 strcpy(fp->name, AudioEulinear); 1033 fp->encoding = AUDIO_ENCODING_ULINEAR; 1034 fp->precision = 8; 1035 fp->flags = 0; 1036 break; 1037 case 1: 1038 strcpy(fp->name, AudioEmulaw); 1039 fp->encoding = AUDIO_ENCODING_ULAW; 1040 fp->precision = 8; 1041 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1042 break; 1043 case 2: 1044 strcpy(fp->name, AudioEalaw); 1045 fp->encoding = AUDIO_ENCODING_ALAW; 1046 fp->precision = 8; 1047 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1048 break; 1049 case 3: 1050 strcpy(fp->name, AudioEslinear); 1051 fp->encoding = AUDIO_ENCODING_SLINEAR; 1052 fp->precision = 8; 1053 fp->flags = 0; 1054 break; 1055 case 4: 1056 strcpy(fp->name, AudioEslinear_le); 1057 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1058 fp->precision = 16; 1059 fp->flags = 0; 1060 break; 1061 case 5: 1062 strcpy(fp->name, AudioEulinear_le); 1063 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1064 fp->precision = 16; 1065 fp->flags = 0; 1066 break; 1067 case 6: 1068 strcpy(fp->name, AudioEslinear_be); 1069 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1070 fp->precision = 16; 1071 fp->flags = 0; 1072 break; 1073 case 7: 1074 strcpy(fp->name, AudioEulinear_be); 1075 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1076 fp->precision = 16; 1077 fp->flags = 0; 1078 break; 1079 default: 1080 return (EINVAL); 1081 } 1082 return (0); 1083 } 1084 1085 int 1086 cs4280_set_params(addr, setmode, usemode, play, rec) 1087 void *addr; 1088 int setmode, usemode; 1089 struct audio_params *play, *rec; 1090 { 1091 struct cs4280_softc *sc = addr; 1092 struct audio_params *p; 1093 int mode; 1094 1095 for (mode = AUMODE_RECORD; mode != -1; 1096 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1097 if ((setmode & mode) == 0) 1098 continue; 1099 1100 p = mode == AUMODE_PLAY ? play : rec; 1101 1102 if (p == play) { 1103 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1104 p->sample_rate, p->precision, p->channels)); 1105 /* play back data format may be 8- or 16-bit and 1106 * either stereo or mono. 1107 * playback rate may range from 8000Hz to 48000Hz 1108 */ 1109 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1110 (p->precision != 8 && p->precision != 16) || 1111 (p->channels != 1 && p->channels != 2) ) { 1112 return (EINVAL); 1113 } 1114 } else { 1115 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1116 p->sample_rate, p->precision, p->channels)); 1117 /* capture data format must be 16bit stereo 1118 * and sample rate range from 11025Hz to 48000Hz. 1119 * 1120 * XXX: it looks like to work with 8000Hz, 1121 * although data sheets say lower limit is 1122 * 11025 Hz. 1123 */ 1124 1125 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1126 (p->precision != 8 && p->precision != 16) || 1127 (p->channels != 1 && p->channels != 2) ) { 1128 return (EINVAL); 1129 } 1130 } 1131 p->factor = 1; 1132 p->sw_code = 0; 1133 1134 /* capturing data is slinear */ 1135 switch (p->encoding) { 1136 case AUDIO_ENCODING_SLINEAR_BE: 1137 if (mode == AUMODE_RECORD) { 1138 if (p->precision == 16) 1139 p->sw_code = swap_bytes; 1140 } 1141 break; 1142 case AUDIO_ENCODING_SLINEAR_LE: 1143 break; 1144 case AUDIO_ENCODING_ULINEAR_BE: 1145 if (mode == AUMODE_RECORD) { 1146 if (p->precision == 16) 1147 p->sw_code = change_sign16_swap_bytes_le; 1148 else 1149 p->sw_code = change_sign8; 1150 } 1151 break; 1152 case AUDIO_ENCODING_ULINEAR_LE: 1153 if (mode == AUMODE_RECORD) { 1154 if (p->precision == 16) 1155 p->sw_code = change_sign16_le; 1156 else 1157 p->sw_code = change_sign8; 1158 } 1159 break; 1160 case AUDIO_ENCODING_ULAW: 1161 if (mode == AUMODE_PLAY) { 1162 p->factor = 2; 1163 p->sw_code = mulaw_to_slinear16_le; 1164 } else { 1165 p->sw_code = slinear8_to_mulaw; 1166 } 1167 break; 1168 case AUDIO_ENCODING_ALAW: 1169 if (mode == AUMODE_PLAY) { 1170 p->factor = 2; 1171 p->sw_code = alaw_to_slinear16_le; 1172 } else { 1173 p->sw_code = slinear8_to_alaw; 1174 } 1175 break; 1176 default: 1177 return (EINVAL); 1178 } 1179 } 1180 1181 /* set sample rate */ 1182 cs4280_set_dac_rate(sc, play->sample_rate); 1183 cs4280_set_adc_rate(sc, rec->sample_rate); 1184 return (0); 1185 } 1186 1187 int 1188 cs4280_round_blocksize(hdl, blk) 1189 void *hdl; 1190 int blk; 1191 { 1192 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1193 } 1194 1195 size_t 1196 cs4280_round_buffersize(addr, direction, size) 1197 void *addr; 1198 int direction; 1199 size_t size; 1200 { 1201 /* although real dma buffer size is 4KB, 1202 * let the audio.c driver use a larger buffer. 1203 * ( suggested by Lennart Augustsson. ) 1204 */ 1205 return (size); 1206 } 1207 1208 int 1209 cs4280_get_props(hdl) 1210 void *hdl; 1211 { 1212 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1213 #ifdef notyet 1214 /* XXX 1215 * How can I mmap ? 1216 */ 1217 AUDIO_PROP_MMAP 1218 #endif 1219 1220 } 1221 1222 int 1223 cs4280_mixer_get_port(addr, cp) 1224 void *addr; 1225 mixer_ctrl_t *cp; 1226 { 1227 struct cs4280_softc *sc = addr; 1228 1229 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1230 } 1231 1232 int 1233 cs4280_mappage(addr, mem, off, prot) 1234 void *addr; 1235 void *mem; 1236 int off; 1237 int prot; 1238 { 1239 struct cs4280_softc *sc = addr; 1240 struct cs4280_dma *p; 1241 1242 if (off < 0) 1243 return (-1); 1244 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1245 ; 1246 if (!p) { 1247 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1248 return (-1); 1249 } 1250 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1251 off, prot, BUS_DMA_WAITOK)); 1252 } 1253 1254 1255 int 1256 cs4280_query_devinfo(addr, dip) 1257 void *addr; 1258 mixer_devinfo_t *dip; 1259 { 1260 struct cs4280_softc *sc = addr; 1261 1262 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1263 } 1264 1265 int 1266 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1267 struct cs4280_softc *sc; 1268 char *class, *device, *qualifier; 1269 { 1270 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1271 device, qualifier)); 1272 } 1273 1274 int 1275 cs4280_halt_output(addr) 1276 void *addr; 1277 { 1278 struct cs4280_softc *sc = addr; 1279 u_int32_t mem; 1280 1281 mem = BA1READ4(sc, CS4280_PCTL); 1282 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1283 #ifdef DIAGNOSTIC 1284 sc->sc_prun = 0; 1285 #endif 1286 return (0); 1287 } 1288 1289 int 1290 cs4280_halt_input(addr) 1291 void *addr; 1292 { 1293 struct cs4280_softc *sc = addr; 1294 u_int32_t mem; 1295 1296 mem = BA1READ4(sc, CS4280_CCTL); 1297 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1298 #ifdef DIAGNOSTIC 1299 sc->sc_rrun = 0; 1300 #endif 1301 return (0); 1302 } 1303 1304 int 1305 cs4280_getdev(addr, retp) 1306 void *addr; 1307 struct audio_device *retp; 1308 { 1309 *retp = cs4280_device; 1310 return (0); 1311 } 1312 1313 int 1314 cs4280_mixer_set_port(addr, cp) 1315 void *addr; 1316 mixer_ctrl_t *cp; 1317 { 1318 struct cs4280_softc *sc = addr; 1319 int val; 1320 1321 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1322 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1323 return (val); 1324 } 1325 1326 1327 int 1328 cs4280_freemem(sc, p) 1329 struct cs4280_softc *sc; 1330 struct cs4280_dma *p; 1331 { 1332 bus_dmamap_unload(sc->sc_dmatag, p->map); 1333 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1334 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1335 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1336 return (0); 1337 } 1338 1339 int 1340 cs4280_allocmem(sc, size, align, p) 1341 struct cs4280_softc *sc; 1342 size_t size; 1343 size_t align; 1344 struct cs4280_dma *p; 1345 { 1346 int error; 1347 1348 /* XXX */ 1349 p->size = size; 1350 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1351 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1352 &p->nsegs, BUS_DMA_NOWAIT); 1353 if (error) { 1354 printf("%s: unable to allocate dma, error=%d\n", 1355 sc->sc_dev.dv_xname, error); 1356 return (error); 1357 } 1358 1359 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1360 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1361 if (error) { 1362 printf("%s: unable to map dma, error=%d\n", 1363 sc->sc_dev.dv_xname, error); 1364 goto free; 1365 } 1366 1367 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1368 0, BUS_DMA_NOWAIT, &p->map); 1369 if (error) { 1370 printf("%s: unable to create dma map, error=%d\n", 1371 sc->sc_dev.dv_xname, error); 1372 goto unmap; 1373 } 1374 1375 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1376 BUS_DMA_NOWAIT); 1377 if (error) { 1378 printf("%s: unable to load dma map, error=%d\n", 1379 sc->sc_dev.dv_xname, error); 1380 goto destroy; 1381 } 1382 return (0); 1383 1384 destroy: 1385 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1386 unmap: 1387 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1388 free: 1389 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1390 return (error); 1391 } 1392 1393 1394 void * 1395 cs4280_malloc(addr, direction, size, pool, flags) 1396 void *addr; 1397 int direction; 1398 size_t size; 1399 int pool, flags; 1400 { 1401 struct cs4280_softc *sc = addr; 1402 struct cs4280_dma *p; 1403 caddr_t q; 1404 int error; 1405 1406 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1407 q = malloc(size, pool, flags); 1408 if (!q) 1409 return (0); 1410 p = malloc(sizeof(*p), pool, flags); 1411 if (!p) { 1412 free(q,pool); 1413 return (0); 1414 } 1415 /* 1416 * cs4280 has fixed 4kB buffer 1417 */ 1418 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1419 1420 if (error) { 1421 free(q, pool); 1422 free(p, pool); 1423 return (0); 1424 } 1425 1426 p->next = sc->sc_dmas; 1427 sc->sc_dmas = p; 1428 p->dum = q; /* return to audio driver */ 1429 1430 return (p->dum); 1431 } 1432 1433 void 1434 cs4280_free(addr, ptr, pool) 1435 void *addr; 1436 void *ptr; 1437 int pool; 1438 { 1439 struct cs4280_softc *sc = addr; 1440 struct cs4280_dma **pp, *p; 1441 1442 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1443 if (BUFADDR(p) == ptr) { 1444 cs4280_freemem(sc, p); 1445 *pp = p->next; 1446 free(p->dum, pool); 1447 free(p, pool); 1448 return; 1449 } 1450 } 1451 } 1452 1453 int 1454 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1455 void *addr; 1456 void *start, *end; 1457 int blksize; 1458 void (*intr) __P((void *)); 1459 void *arg; 1460 struct audio_params *param; 1461 { 1462 struct cs4280_softc *sc = addr; 1463 u_int32_t pfie, pctl, mem, pdtc; 1464 struct cs4280_dma *p; 1465 1466 #ifdef DIAGNOSTIC 1467 if (sc->sc_prun) 1468 printf("cs4280_trigger_output: already running\n"); 1469 sc->sc_prun = 1; 1470 #endif 1471 1472 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1473 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1474 sc->sc_pintr = intr; 1475 sc->sc_parg = arg; 1476 1477 /* stop playback DMA */ 1478 mem = BA1READ4(sc, CS4280_PCTL); 1479 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1480 1481 /* setup PDTC */ 1482 pdtc = BA1READ4(sc, CS4280_PDTC); 1483 pdtc &= ~PDTC_MASK; 1484 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1485 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1486 1487 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1488 param->precision, param->factor, param->channels, 1489 param->encoding)); 1490 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1491 ; 1492 if (p == NULL) { 1493 printf("cs4280_trigger_output: bad addr %p\n", start); 1494 return (EINVAL); 1495 } 1496 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1497 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1498 "4kB align\n", DMAADDR(p)); 1499 return (EINVAL); 1500 } 1501 1502 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1503 sc->sc_ps = (char *)start; 1504 sc->sc_pe = (char *)end; 1505 sc->sc_pdma = p; 1506 sc->sc_pbuf = KERNADDR(p); 1507 sc->sc_pi = 0; 1508 sc->sc_pn = sc->sc_ps; 1509 if (blksize >= CS4280_DCHUNK) { 1510 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1511 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1512 ++sc->sc_pi; 1513 } else { 1514 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1515 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1516 } 1517 1518 /* initiate playback dma */ 1519 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1520 1521 /* set PFIE */ 1522 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1523 1524 if (param->precision * param->factor == 8) 1525 pfie |= PFIE_8BIT; 1526 if (param->channels == 1) 1527 pfie |= PFIE_MONO; 1528 1529 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1530 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1531 pfie |= PFIE_SWAPPED; 1532 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1533 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1534 pfie |= PFIE_UNSIGNED; 1535 1536 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1537 1538 cs4280_set_dac_rate(sc, param->sample_rate); 1539 1540 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1541 pctl |= sc->pctl; 1542 BA1WRITE4(sc, CS4280_PCTL, pctl); 1543 return (0); 1544 } 1545 1546 int 1547 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1548 void *addr; 1549 void *start, *end; 1550 int blksize; 1551 void (*intr) __P((void *)); 1552 void *arg; 1553 struct audio_params *param; 1554 { 1555 struct cs4280_softc *sc = addr; 1556 u_int32_t cctl, cie; 1557 struct cs4280_dma *p; 1558 1559 #ifdef DIAGNOSTIC 1560 if (sc->sc_rrun) 1561 printf("cs4280_trigger_input: already running\n"); 1562 sc->sc_rrun = 1; 1563 #endif 1564 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1565 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1566 sc->sc_rintr = intr; 1567 sc->sc_rarg = arg; 1568 1569 sc->sc_ri = 0; 1570 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1571 sc->sc_rs = (char *)start; 1572 sc->sc_re = (char *)end; 1573 sc->sc_rn = sc->sc_rs; 1574 1575 /* setup format information for internal converter */ 1576 sc->sc_rparam = 0; 1577 if (param->precision == 8) { 1578 sc->sc_rparam += CF_8BIT; 1579 sc->sc_rcount <<= 1; 1580 } 1581 if (param->channels == 1) { 1582 sc->sc_rparam += CF_MONO; 1583 sc->sc_rcount <<= 1; 1584 } 1585 1586 /* stop capture DMA */ 1587 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1588 BA1WRITE4(sc, CS4280_CCTL, cctl); 1589 1590 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1591 ; 1592 if (!p) { 1593 printf("cs4280_trigger_input: bad addr %p\n", start); 1594 return (EINVAL); 1595 } 1596 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1597 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1598 "4kB align\n", DMAADDR(p)); 1599 return (EINVAL); 1600 } 1601 sc->sc_rdma = p; 1602 sc->sc_rbuf = KERNADDR(p); 1603 1604 /* initiate capture dma */ 1605 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1606 1607 /* set CIE */ 1608 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1609 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1610 1611 cs4280_set_adc_rate(sc, param->sample_rate); 1612 1613 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1614 cctl |= sc->cctl; 1615 BA1WRITE4(sc, CS4280_CCTL, cctl); 1616 return (0); 1617 } 1618 1619 int 1620 cs4280_init(sc, init) 1621 struct cs4280_softc *sc; 1622 int init; 1623 { 1624 int n; 1625 u_int32_t mem; 1626 1627 /* Start PLL out in known state */ 1628 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1629 /* Start serial ports out in known state */ 1630 BA0WRITE4(sc, CS4280_SERMC1, 0); 1631 1632 /* Specify type of CODEC */ 1633 /* XXX should no be here */ 1634 #define SERACC_CODEC_TYPE_1_03 1635 #ifdef SERACC_CODEC_TYPE_1_03 1636 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1637 #else 1638 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1639 #endif 1640 1641 /* Reset codec */ 1642 BA0WRITE4(sc, CS4280_ACCTL, 0); 1643 delay(100); /* delay 100us */ 1644 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1645 1646 /* Enable AC-link sync generation */ 1647 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1648 delay(50*1000); /* delay 50ms */ 1649 1650 /* Set the serial port timing configuration */ 1651 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1652 1653 /* Setup clock control */ 1654 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1655 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1656 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1657 1658 /* Power up the PLL */ 1659 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1660 delay(50*1000); /* delay 50ms */ 1661 1662 /* Turn on clock */ 1663 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE); 1664 1665 /* Set the serial port FIFO pointer to the 1666 * first sample in FIFO. (not documented) */ 1667 cs4280_clear_fifos(sc); 1668 1669 #if 0 1670 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1671 BA0WRITE4(sc, CS4280_SERBSP, 0); 1672 #endif 1673 1674 /* Configure the serial port */ 1675 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1676 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1677 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1678 1679 /* Wait for CODEC ready */ 1680 n = 0; 1681 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1682 delay(125); 1683 if (++n > 1000) { 1684 printf("%s: codec ready timeout\n", 1685 sc->sc_dev.dv_xname); 1686 return(1); 1687 } 1688 } 1689 1690 /* Assert valid frame signal */ 1691 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1692 1693 /* Wait for valid AC97 input slot */ 1694 n = 0; 1695 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 1696 delay(1000); 1697 if (++n > 1000) { 1698 printf("AC97 inputs slot ready timeout\n"); 1699 return(1); 1700 } 1701 } 1702 1703 /* Set AC97 output slot valid signals */ 1704 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1705 1706 /* reset the processor */ 1707 cs4280_reset(sc); 1708 1709 /* Download the image to the processor */ 1710 if (cs4280_download_image(sc) != 0) { 1711 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1712 return(1); 1713 } 1714 1715 /* Save playback parameter and then write zero. 1716 * this ensures that DMA doesn't immediately occur upon 1717 * starting the processor core 1718 */ 1719 mem = BA1READ4(sc, CS4280_PCTL); 1720 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1721 cs4280_halt_output(sc); 1722 1723 /* Save capture parameter and then write zero. 1724 * this ensures that DMA doesn't immediately occur upon 1725 * starting the processor core 1726 */ 1727 mem = BA1READ4(sc, CS4280_CCTL); 1728 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1729 cs4280_halt_input(sc); 1730 1731 /* Processor Startup Procedure */ 1732 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1733 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1734 1735 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1736 n = 0; 1737 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1738 delay(10); 1739 if (++n > 1000) { 1740 printf("SPCR 1->0 transition timeout\n"); 1741 return(1); 1742 } 1743 } 1744 1745 n = 0; 1746 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1747 delay(10); 1748 if (++n > 1000) { 1749 printf("SPCS 0->1 transition timeout\n"); 1750 return(1); 1751 } 1752 } 1753 /* Processor is now running !!! */ 1754 1755 /* Setup volume */ 1756 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1757 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1758 1759 /* Interrupt enable */ 1760 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1761 1762 /* playback interrupt enable */ 1763 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1764 mem |= PFIE_PI_ENABLE; 1765 BA1WRITE4(sc, CS4280_PFIE, mem); 1766 /* capture interrupt enable */ 1767 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1768 mem |= CIE_CI_ENABLE; 1769 BA1WRITE4(sc, CS4280_CIE, mem); 1770 1771 #if NMIDI > 0 1772 /* Reset midi port */ 1773 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1774 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1775 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1776 /* midi interrupt enable */ 1777 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1778 BA0WRITE4(sc, CS4280_MIDCR, mem); 1779 #endif 1780 return(0); 1781 } 1782 1783 void 1784 cs4280_power(why, v) 1785 int why; 1786 void *v; 1787 { 1788 struct cs4280_softc *sc = (struct cs4280_softc *)v; 1789 int i; 1790 1791 DPRINTF(("%s: cs4280_power why=%d\n", 1792 sc->sc_dev.dv_xname, why)); 1793 if (why != PWR_RESUME) { 1794 sc->sc_suspend = why; 1795 1796 cs4280_halt_output(sc); 1797 cs4280_halt_input(sc); 1798 /* Save AC97 registers */ 1799 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1800 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1801 continue; 1802 cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i>>1]); 1803 } 1804 /* should I powerdown here ? */ 1805 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1806 } else { 1807 if (sc->sc_suspend == PWR_RESUME) { 1808 printf("cs4280_power: odd, resume without suspend.\n"); 1809 sc->sc_suspend = why; 1810 return; 1811 } 1812 sc->sc_suspend = why; 1813 cs4280_init(sc, 0); 1814 cs4280_reset_codec(sc); 1815 1816 /* restore ac97 registers */ 1817 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1818 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1819 continue; 1820 cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]); 1821 } 1822 } 1823 } 1824 1825 void 1826 cs4280_clear_fifos(sc) 1827 struct cs4280_softc *sc; 1828 { 1829 int pd = 0, cnt, n; 1830 u_int32_t mem; 1831 1832 /* 1833 * If device power down, power up the device and keep power down 1834 * state. 1835 */ 1836 mem = BA0READ4(sc, CS4280_CLKCR1); 1837 if (!(mem & CLKCR1_SWCE)) { 1838 printf("cs4280_clear_fifo: power down found.\n"); 1839 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1840 pd = 1; 1841 } 1842 BA0WRITE4(sc, CS4280_SERBWP, 0); 1843 for (cnt = 0; cnt < 256; cnt++) { 1844 n = 0; 1845 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1846 delay(1000); 1847 if (++n > 1000) { 1848 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1849 break; 1850 } 1851 } 1852 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1853 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1854 } 1855 if (pd) 1856 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1857 } 1858 1859 #if NMIDI > 0 1860 int 1861 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1862 void *addr; 1863 int flags; 1864 void (*iintr)__P((void *, int)); 1865 void (*ointr)__P((void *)); 1866 void *arg; 1867 { 1868 struct cs4280_softc *sc = addr; 1869 u_int32_t mem; 1870 1871 DPRINTF(("midi_open\n")); 1872 sc->sc_iintr = iintr; 1873 sc->sc_ointr = ointr; 1874 sc->sc_arg = arg; 1875 1876 /* midi interrupt enable */ 1877 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1878 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1879 BA0WRITE4(sc, CS4280_MIDCR, mem); 1880 #ifdef CS4280_DEBUG 1881 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1882 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1883 return(EINVAL); 1884 } 1885 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1886 #endif 1887 return (0); 1888 } 1889 1890 void 1891 cs4280_midi_close(addr) 1892 void *addr; 1893 { 1894 struct cs4280_softc *sc = addr; 1895 u_int32_t mem; 1896 1897 DPRINTF(("midi_close\n")); 1898 mem = BA0READ4(sc, CS4280_MIDCR); 1899 mem &= ~MIDCR_MASK; 1900 BA0WRITE4(sc, CS4280_MIDCR, mem); 1901 1902 sc->sc_iintr = 0; 1903 sc->sc_ointr = 0; 1904 } 1905 1906 int 1907 cs4280_midi_output(addr, d) 1908 void *addr; 1909 int d; 1910 { 1911 struct cs4280_softc *sc = addr; 1912 u_int32_t mem; 1913 int x; 1914 1915 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1916 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1917 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1918 mem |= d & MIDWP_MASK; 1919 DPRINTFN(5,("midi_output d=0x%08x",d)); 1920 BA0WRITE4(sc, CS4280_MIDWP, mem); 1921 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1922 DPRINTF(("Bad write data: %d %d", 1923 mem, BA0READ4(sc, CS4280_MIDWP))); 1924 return(EIO); 1925 } 1926 return (0); 1927 } 1928 delay(MIDI_BUSY_DELAY); 1929 } 1930 return (EIO); 1931 } 1932 1933 void 1934 cs4280_midi_getinfo(addr, mi) 1935 void *addr; 1936 struct midi_info *mi; 1937 { 1938 mi->name = "CS4280 MIDI UART"; 1939 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1940 } 1941 1942 #endif 1943
Indexes created Thu Oct 02 14:10:14 GMT 2025