cs4280.c revision 1.32
1 /* $NetBSD: cs4280.c,v 1.32 2004/11/09 16:28:14 kent Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.32 2004/11/09 16:28:14 kent Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <machine/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 int cs4280_match(struct device *, struct cfdata *, void *); 93 void cs4280_attach(struct device *, struct device *, void *); 94 int cs4280_intr(void *); 95 int cs4280_query_encoding(void *, struct audio_encoding *); 96 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 97 int cs4280_halt_output(void *); 98 int cs4280_halt_input(void *); 99 int cs4280_getdev(void *, struct audio_device *); 100 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 101 void *, struct audio_params *); 102 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 103 void *, struct audio_params *); 104 105 int cs4280_reset_codec(void *); 106 107 /* For PowerHook */ 108 void cs4280_power(int, void *); 109 110 /* Internal functions */ 111 void cs4280_set_adc_rate(struct cs428x_softc *, int ); 112 void cs4280_set_dac_rate(struct cs428x_softc *, int ); 113 int cs4280_download(struct cs428x_softc *, const u_int32_t *, u_int32_t, u_int32_t); 114 int cs4280_download_image(struct cs428x_softc *); 115 void cs4280_reset(void *); 116 int cs4280_get_portnum_by_name(struct cs428x_softc *, char *, char *, char *); 117 int cs4280_init(struct cs428x_softc *, int); 118 void cs4280_clear_fifos(struct cs428x_softc *); 119 120 #if CS4280_DEBUG > 10 121 /* Thease two function is only for checking image loading is succeeded or not. */ 122 int cs4280_check_images(struct cs428x_softc *); 123 int cs4280_checkimage(struct cs428x_softc *, u_int32_t *, u_int32_t, u_int32_t); 124 #endif 125 126 const struct audio_hw_if cs4280_hw_if = { 127 cs428x_open, 128 cs428x_close, 129 NULL, 130 cs4280_query_encoding, 131 cs4280_set_params, 132 cs428x_round_blocksize, 133 NULL, 134 NULL, 135 NULL, 136 NULL, 137 NULL, 138 cs4280_halt_output, 139 cs4280_halt_input, 140 NULL, 141 cs4280_getdev, 142 NULL, 143 cs428x_mixer_set_port, 144 cs428x_mixer_get_port, 145 cs428x_query_devinfo, 146 cs428x_malloc, 147 cs428x_free, 148 cs428x_round_buffersize, 149 cs428x_mappage, 150 cs428x_get_props, 151 cs4280_trigger_output, 152 cs4280_trigger_input, 153 NULL, 154 }; 155 156 #if NMIDI > 0 157 /* Midi Interface */ 158 int cs4280_midi_open(void *, int, void (*)(void *, int), 159 void (*)(void *), void *); 160 void cs4280_midi_close(void*); 161 int cs4280_midi_output(void *, int); 162 void cs4280_midi_getinfo(void *, struct midi_info *); 163 164 const struct midi_hw_if cs4280_midi_hw_if = { 165 cs4280_midi_open, 166 cs4280_midi_close, 167 cs4280_midi_output, 168 cs4280_midi_getinfo, 169 0, 170 }; 171 #endif 172 173 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 174 cs4280_match, cs4280_attach, NULL, NULL); 175 176 struct audio_device cs4280_device = { 177 "CS4280", 178 "", 179 "cs4280" 180 }; 181 182 183 int 184 cs4280_match(parent, match, aux) 185 struct device *parent; 186 struct cfdata *match; 187 void *aux; 188 { 189 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 190 191 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 192 return 0; 193 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 194 #if 0 /* I can't confirm */ 195 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 196 #endif 197 ) 198 return 1; 199 return 0; 200 } 201 202 void 203 cs4280_attach(parent, self, aux) 204 struct device *parent; 205 struct device *self; 206 void *aux; 207 { 208 struct cs428x_softc *sc = (struct cs428x_softc *)self; 209 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 210 pci_chipset_tag_t pc = pa->pa_pc; 211 char const *intrstr; 212 pci_intr_handle_t ih; 213 pcireg_t reg; 214 char devinfo[256]; 215 u_int32_t mem; 216 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 217 218 aprint_naive(": Audio controller\n"); 219 220 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 221 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 222 PCI_REVISION(pa->pa_class)); 223 224 /* Map I/O register */ 225 if (pci_mapreg_map(pa, PCI_BA0, 226 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 227 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 228 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 229 return; 230 } 231 if (pci_mapreg_map(pa, PCI_BA1, 232 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 233 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 234 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 235 return; 236 } 237 238 sc->sc_dmatag = pa->pa_dmat; 239 240 /* Check and set Power State */ 241 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 242 &pci_pwrmgmt_cap_reg, 0)) { 243 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 244 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 245 pci_pwrmgmt_csr_reg); 246 DPRINTF(("%s: Power State is %d\n", 247 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 248 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 249 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 250 (reg & ~PCI_PMCSR_STATE_MASK) | 251 PCI_PMCSR_STATE_D0); 252 } 253 } 254 255 /* Enable the device (set bus master flag) */ 256 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 257 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 258 reg | PCI_COMMAND_MASTER_ENABLE); 259 260 /* LATENCY_TIMER setting */ 261 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 262 if ( PCI_LATTIMER(mem) < 32 ) { 263 mem &= 0xffff00ff; 264 mem |= 0x00002000; 265 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 266 } 267 268 /* Map and establish the interrupt. */ 269 if (pci_intr_map(pa, &ih)) { 270 aprint_error("%s: couldn't map interrupt\n", 271 sc->sc_dev.dv_xname); 272 return; 273 } 274 intrstr = pci_intr_string(pc, ih); 275 276 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 277 if (sc->sc_ih == NULL) { 278 aprint_error("%s: couldn't establish interrupt", 279 sc->sc_dev.dv_xname); 280 if (intrstr != NULL) 281 aprint_normal(" at %s", intrstr); 282 aprint_normal("\n"); 283 return; 284 } 285 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 286 287 /* Initialization */ 288 if(cs4280_init(sc, 1) != 0) 289 return; 290 291 sc->type = TYPE_CS4280; 292 sc->halt_input = cs4280_halt_input; 293 sc->halt_output = cs4280_halt_output; 294 295 /* setup buffer related parameters */ 296 sc->dma_size = CS4280_DCHUNK; 297 sc->dma_align = CS4280_DALIGN; 298 sc->hw_blocksize = CS4280_ICHUNK; 299 300 /* AC 97 attachment */ 301 sc->host_if.arg = sc; 302 sc->host_if.attach = cs428x_attach_codec; 303 sc->host_if.read = cs428x_read_codec; 304 sc->host_if.write = cs428x_write_codec; 305 sc->host_if.reset = cs4280_reset_codec; 306 if (ac97_attach(&sc->host_if) != 0) { 307 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 308 return; 309 } 310 311 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 312 313 #if NMIDI > 0 314 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 315 #endif 316 317 sc->sc_suspend = PWR_RESUME; 318 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 319 } 320 321 /* Interrupt handling function */ 322 int 323 cs4280_intr(p) 324 void *p; 325 { 326 /* 327 * XXX 328 * 329 * Since CS4280 has only 4kB DMA buffer and 330 * interrupt occurs every 2kB block, I create dummy buffer 331 * which returns to audio driver and actual DMA buffer 332 * using in DMA transfer. 333 * 334 * 335 * ring buffer in audio.c is pointed by BUFADDR 336 * <------ ring buffer size == 64kB ------> 337 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 338 * |= = = =|= = = =|= = = =|= = = =|= = = =| 339 * | | | | | | <- call audio_intp every 340 * sc->sc_[pr]_count time. 341 * 342 * actual DMA buffer is pointed by KERNADDR 343 * <-> DMA buffer size = 4kB 344 * |= =| 345 * 346 * 347 */ 348 struct cs428x_softc *sc = p; 349 u_int32_t intr, mem; 350 char * empty_dma; 351 int handled = 0; 352 353 /* grab interrupt register then clear it */ 354 intr = BA0READ4(sc, CS4280_HISR); 355 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 356 357 /* Playback Interrupt */ 358 if (intr & HISR_PINT) { 359 handled = 1; 360 mem = BA1READ4(sc, CS4280_PFIE); 361 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 362 if (sc->sc_prun) { 363 if ((sc->sc_pi%sc->sc_pcount) == 0) 364 sc->sc_pintr(sc->sc_parg); 365 } else { 366 printf("unexpected play intr\n"); 367 } 368 /* copy buffer */ 369 ++sc->sc_pi; 370 empty_dma = sc->sc_pdma->addr; 371 if (sc->sc_pi&1) 372 empty_dma += sc->hw_blocksize; 373 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 374 sc->sc_pn += sc->hw_blocksize; 375 if (sc->sc_pn >= sc->sc_pe) 376 sc->sc_pn = sc->sc_ps; 377 BA1WRITE4(sc, CS4280_PFIE, mem); 378 } 379 /* Capture Interrupt */ 380 if (intr & HISR_CINT) { 381 int i; 382 int16_t rdata; 383 384 handled = 1; 385 mem = BA1READ4(sc, CS4280_CIE); 386 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 387 ++sc->sc_ri; 388 empty_dma = sc->sc_rdma->addr; 389 if ((sc->sc_ri&1) == 0) 390 empty_dma += sc->hw_blocksize; 391 392 /* 393 * XXX 394 * I think this audio data conversion should be 395 * happend in upper layer, but I put this here 396 * since there is no conversion function available. 397 */ 398 switch(sc->sc_rparam) { 399 case CF_16BIT_STEREO: 400 /* just copy it */ 401 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 402 sc->sc_rn += sc->hw_blocksize; 403 break; 404 case CF_16BIT_MONO: 405 for (i = 0; i < 512; i++) { 406 rdata = *((int16_t *)empty_dma)>>1; 407 empty_dma += 2; 408 rdata += *((int16_t *)empty_dma)>>1; 409 empty_dma += 2; 410 *((int16_t *)sc->sc_rn) = rdata; 411 sc->sc_rn += 2; 412 } 413 break; 414 case CF_8BIT_STEREO: 415 for (i = 0; i < 512; i++) { 416 rdata = *((int16_t*)empty_dma); 417 empty_dma += 2; 418 *sc->sc_rn++ = rdata >> 8; 419 rdata = *((int16_t*)empty_dma); 420 empty_dma += 2; 421 *sc->sc_rn++ = rdata >> 8; 422 } 423 break; 424 case CF_8BIT_MONO: 425 for (i = 0; i < 512; i++) { 426 rdata = *((int16_t*)empty_dma) >>1; 427 empty_dma += 2; 428 rdata += *((int16_t*)empty_dma) >>1; 429 empty_dma += 2; 430 *sc->sc_rn++ = rdata >>8; 431 } 432 break; 433 default: 434 /* Should not reach here */ 435 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 436 } 437 if (sc->sc_rn >= sc->sc_re) 438 sc->sc_rn = sc->sc_rs; 439 BA1WRITE4(sc, CS4280_CIE, mem); 440 if (sc->sc_rrun) { 441 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 442 sc->sc_rintr(sc->sc_rarg); 443 } else { 444 printf("unexpected record intr\n"); 445 } 446 } 447 448 #if NMIDI > 0 449 /* Midi port Interrupt */ 450 if (intr & HISR_MIDI) { 451 int data; 452 453 handled = 1; 454 DPRINTF(("i: %d: ", 455 BA0READ4(sc, CS4280_MIDSR))); 456 /* Read the received data */ 457 while ((sc->sc_iintr != NULL) && 458 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 459 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 460 DPRINTF(("r:%x\n",data)); 461 sc->sc_iintr(sc->sc_arg, data); 462 } 463 464 /* Write the data */ 465 #if 1 466 /* XXX: 467 * It seems "Transmit Buffer Full" never activate until EOI 468 * is deliverd. Shall I throw EOI top of this routine ? 469 */ 470 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 471 DPRINTF(("w: ")); 472 if (sc->sc_ointr != NULL) 473 sc->sc_ointr(sc->sc_arg); 474 } 475 #else 476 while ((sc->sc_ointr != NULL) && 477 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 478 DPRINTF(("w: ")); 479 sc->sc_ointr(sc->sc_arg); 480 } 481 #endif 482 DPRINTF(("\n")); 483 } 484 #endif 485 486 return handled; 487 } 488 489 int 490 cs4280_query_encoding(addr, fp) 491 void *addr; 492 struct audio_encoding *fp; 493 { 494 switch (fp->index) { 495 case 0: 496 strcpy(fp->name, AudioEulinear); 497 fp->encoding = AUDIO_ENCODING_ULINEAR; 498 fp->precision = 8; 499 fp->flags = 0; 500 break; 501 case 1: 502 strcpy(fp->name, AudioEmulaw); 503 fp->encoding = AUDIO_ENCODING_ULAW; 504 fp->precision = 8; 505 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 506 break; 507 case 2: 508 strcpy(fp->name, AudioEalaw); 509 fp->encoding = AUDIO_ENCODING_ALAW; 510 fp->precision = 8; 511 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 512 break; 513 case 3: 514 strcpy(fp->name, AudioEslinear); 515 fp->encoding = AUDIO_ENCODING_SLINEAR; 516 fp->precision = 8; 517 fp->flags = 0; 518 break; 519 case 4: 520 strcpy(fp->name, AudioEslinear_le); 521 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 522 fp->precision = 16; 523 fp->flags = 0; 524 break; 525 case 5: 526 strcpy(fp->name, AudioEulinear_le); 527 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 528 fp->precision = 16; 529 fp->flags = 0; 530 break; 531 case 6: 532 strcpy(fp->name, AudioEslinear_be); 533 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 534 fp->precision = 16; 535 fp->flags = 0; 536 break; 537 case 7: 538 strcpy(fp->name, AudioEulinear_be); 539 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 540 fp->precision = 16; 541 fp->flags = 0; 542 break; 543 default: 544 return EINVAL; 545 } 546 return 0; 547 } 548 549 int 550 cs4280_set_params(addr, setmode, usemode, play, rec) 551 void *addr; 552 int setmode, usemode; 553 struct audio_params *play, *rec; 554 { 555 struct cs428x_softc *sc = addr; 556 struct audio_params *p; 557 int mode; 558 559 for (mode = AUMODE_RECORD; mode != -1; 560 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 561 if ((setmode & mode) == 0) 562 continue; 563 564 p = mode == AUMODE_PLAY ? play : rec; 565 566 if (p == play) { 567 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 568 p->sample_rate, p->precision, p->channels)); 569 /* play back data format may be 8- or 16-bit and 570 * either stereo or mono. 571 * playback rate may range from 8000Hz to 48000Hz 572 */ 573 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 574 (p->precision != 8 && p->precision != 16) || 575 (p->channels != 1 && p->channels != 2) ) { 576 return EINVAL; 577 } 578 } else { 579 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 580 p->sample_rate, p->precision, p->channels)); 581 /* capture data format must be 16bit stereo 582 * and sample rate range from 11025Hz to 48000Hz. 583 * 584 * XXX: it looks like to work with 8000Hz, 585 * although data sheets say lower limit is 586 * 11025 Hz. 587 */ 588 589 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 590 (p->precision != 8 && p->precision != 16) || 591 (p->channels != 1 && p->channels != 2) ) { 592 return EINVAL; 593 } 594 } 595 p->factor = 1; 596 p->sw_code = 0; 597 598 /* capturing data is slinear */ 599 switch (p->encoding) { 600 case AUDIO_ENCODING_SLINEAR_BE: 601 if (mode == AUMODE_RECORD) { 602 if (p->precision == 16) 603 p->sw_code = swap_bytes; 604 } 605 break; 606 case AUDIO_ENCODING_SLINEAR_LE: 607 break; 608 case AUDIO_ENCODING_ULINEAR_BE: 609 if (mode == AUMODE_RECORD) { 610 if (p->precision == 16) 611 p->sw_code = change_sign16_swap_bytes_le; 612 else 613 p->sw_code = change_sign8; 614 } 615 break; 616 case AUDIO_ENCODING_ULINEAR_LE: 617 if (mode == AUMODE_RECORD) { 618 if (p->precision == 16) 619 p->sw_code = change_sign16_le; 620 else 621 p->sw_code = change_sign8; 622 } 623 break; 624 case AUDIO_ENCODING_ULAW: 625 if (mode == AUMODE_PLAY) { 626 p->factor = 2; 627 p->sw_code = mulaw_to_slinear16_le; 628 } else { 629 p->sw_code = slinear8_to_mulaw; 630 } 631 break; 632 case AUDIO_ENCODING_ALAW: 633 if (mode == AUMODE_PLAY) { 634 p->factor = 2; 635 p->sw_code = alaw_to_slinear16_le; 636 } else { 637 p->sw_code = slinear8_to_alaw; 638 } 639 break; 640 default: 641 return EINVAL; 642 } 643 } 644 645 /* set sample rate */ 646 cs4280_set_dac_rate(sc, play->sample_rate); 647 cs4280_set_adc_rate(sc, rec->sample_rate); 648 return 0; 649 } 650 651 int 652 cs4280_halt_output(addr) 653 void *addr; 654 { 655 struct cs428x_softc *sc = addr; 656 u_int32_t mem; 657 658 mem = BA1READ4(sc, CS4280_PCTL); 659 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 660 sc->sc_prun = 0; 661 return 0; 662 } 663 664 int 665 cs4280_halt_input(addr) 666 void *addr; 667 { 668 struct cs428x_softc *sc = addr; 669 u_int32_t mem; 670 671 mem = BA1READ4(sc, CS4280_CCTL); 672 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 673 sc->sc_rrun = 0; 674 return 0; 675 } 676 677 int 678 cs4280_getdev(addr, retp) 679 void *addr; 680 struct audio_device *retp; 681 { 682 *retp = cs4280_device; 683 return 0; 684 } 685 686 int 687 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 688 void *addr; 689 void *start, *end; 690 int blksize; 691 void (*intr) __P((void *)); 692 void *arg; 693 struct audio_params *param; 694 { 695 struct cs428x_softc *sc = addr; 696 u_int32_t pfie, pctl, pdtc; 697 struct cs428x_dma *p; 698 699 #ifdef DIAGNOSTIC 700 if (sc->sc_prun) 701 printf("cs4280_trigger_output: already running\n"); 702 #endif 703 sc->sc_prun = 1; 704 705 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 706 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 707 sc->sc_pintr = intr; 708 sc->sc_parg = arg; 709 710 /* stop playback DMA */ 711 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 712 713 /* setup PDTC */ 714 pdtc = BA1READ4(sc, CS4280_PDTC); 715 pdtc &= ~PDTC_MASK; 716 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 717 BA1WRITE4(sc, CS4280_PDTC, pdtc); 718 719 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 720 param->precision, param->factor, param->channels, 721 param->encoding)); 722 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 723 ; 724 if (p == NULL) { 725 printf("cs4280_trigger_output: bad addr %p\n", start); 726 return EINVAL; 727 } 728 if (DMAADDR(p) % sc->dma_align != 0 ) { 729 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 730 "4kB align\n", (ulong)DMAADDR(p)); 731 return EINVAL; 732 } 733 734 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 735 sc->sc_ps = (char *)start; 736 sc->sc_pe = (char *)end; 737 sc->sc_pdma = p; 738 sc->sc_pbuf = KERNADDR(p); 739 sc->sc_pi = 0; 740 sc->sc_pn = sc->sc_ps; 741 if (blksize >= sc->dma_size) { 742 sc->sc_pn = sc->sc_ps + sc->dma_size; 743 memcpy(sc->sc_pbuf, start, sc->dma_size); 744 ++sc->sc_pi; 745 } else { 746 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 747 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 748 } 749 750 /* initiate playback DMA */ 751 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 752 753 /* set PFIE */ 754 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 755 756 if (param->precision * param->factor == 8) 757 pfie |= PFIE_8BIT; 758 if (param->channels == 1) 759 pfie |= PFIE_MONO; 760 761 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 762 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 763 pfie |= PFIE_SWAPPED; 764 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 765 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 766 pfie |= PFIE_UNSIGNED; 767 768 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 769 770 sc->sc_prate = param->sample_rate; 771 cs4280_set_dac_rate(sc, param->sample_rate); 772 773 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 774 pctl |= sc->pctl; 775 BA1WRITE4(sc, CS4280_PCTL, pctl); 776 return 0; 777 } 778 779 int 780 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 781 void *addr; 782 void *start, *end; 783 int blksize; 784 void (*intr) __P((void *)); 785 void *arg; 786 struct audio_params *param; 787 { 788 struct cs428x_softc *sc = addr; 789 u_int32_t cctl, cie; 790 struct cs428x_dma *p; 791 792 #ifdef DIAGNOSTIC 793 if (sc->sc_rrun) 794 printf("cs4280_trigger_input: already running\n"); 795 #endif 796 sc->sc_rrun = 1; 797 798 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 799 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 800 sc->sc_rintr = intr; 801 sc->sc_rarg = arg; 802 803 /* stop capture DMA */ 804 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 805 806 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 807 ; 808 if (p == NULL) { 809 printf("cs4280_trigger_input: bad addr %p\n", start); 810 return EINVAL; 811 } 812 if (DMAADDR(p) % sc->dma_align != 0) { 813 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 814 "4kB align\n", (ulong)DMAADDR(p)); 815 return EINVAL; 816 } 817 818 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 819 sc->sc_rs = (char *)start; 820 sc->sc_re = (char *)end; 821 sc->sc_rdma = p; 822 sc->sc_rbuf = KERNADDR(p); 823 sc->sc_ri = 0; 824 sc->sc_rn = sc->sc_rs; 825 826 /* initiate capture DMA */ 827 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 828 829 /* setup format information for internal converter */ 830 sc->sc_rparam = 0; 831 if (param->precision == 8) { 832 sc->sc_rparam += CF_8BIT; 833 sc->sc_rcount <<= 1; 834 } 835 if (param->channels == 1) { 836 sc->sc_rparam += CF_MONO; 837 sc->sc_rcount <<= 1; 838 } 839 840 /* set CIE */ 841 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 842 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 843 844 sc->sc_rrate = param->sample_rate; 845 cs4280_set_adc_rate(sc, param->sample_rate); 846 847 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 848 cctl |= sc->cctl; 849 BA1WRITE4(sc, CS4280_CCTL, cctl); 850 return 0; 851 } 852 853 /* Power Hook */ 854 void 855 cs4280_power(why, v) 856 int why; 857 void *v; 858 { 859 struct cs428x_softc *sc = (struct cs428x_softc *)v; 860 static u_int32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 861 static u_int32_t cctl = 0, cba = 0, cie = 0; 862 863 DPRINTF(("%s: cs4280_power why=%d\n", 864 sc->sc_dev.dv_xname, why)); 865 switch (why) { 866 case PWR_SUSPEND: 867 case PWR_STANDBY: 868 sc->sc_suspend = why; 869 870 /* save current playback status */ 871 if ( sc->sc_prun ) { 872 pctl = BA1READ4(sc, CS4280_PCTL); 873 pfie = BA1READ4(sc, CS4280_PFIE); 874 pba = BA1READ4(sc, CS4280_PBA); 875 pdtc = BA1READ4(sc, CS4280_PDTC); 876 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 877 pctl, pfie, pba, pdtc)); 878 } 879 880 /* save current capture status */ 881 if ( sc->sc_rrun ) { 882 cctl = BA1READ4(sc, CS4280_CCTL); 883 cie = BA1READ4(sc, CS4280_CIE); 884 cba = BA1READ4(sc, CS4280_CBA); 885 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 886 cctl, cie, cba)); 887 } 888 889 /* Stop DMA */ 890 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 891 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 892 break; 893 case PWR_RESUME: 894 if (sc->sc_suspend == PWR_RESUME) { 895 printf("cs4280_power: odd, resume without suspend.\n"); 896 sc->sc_suspend = why; 897 return; 898 } 899 sc->sc_suspend = why; 900 cs4280_init(sc, 0); 901 cs4280_reset_codec(sc); 902 903 /* restore ac97 registers */ 904 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 905 906 /* restore DMA related status */ 907 if(sc->sc_prun) { 908 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 909 pctl, pfie, pba, pdtc)); 910 cs4280_set_dac_rate(sc, sc->sc_prate); 911 BA1WRITE4(sc, CS4280_PDTC, pdtc); 912 BA1WRITE4(sc, CS4280_PBA, pba); 913 BA1WRITE4(sc, CS4280_PFIE, pfie); 914 BA1WRITE4(sc, CS4280_PCTL, pctl); 915 } 916 917 if (sc->sc_rrun) { 918 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 919 cctl, cie, cba)); 920 cs4280_set_adc_rate(sc, sc->sc_rrate); 921 BA1WRITE4(sc, CS4280_CBA, cba); 922 BA1WRITE4(sc, CS4280_CIE, cie); 923 BA1WRITE4(sc, CS4280_CCTL, cctl); 924 } 925 break; 926 case PWR_SOFTSUSPEND: 927 case PWR_SOFTSTANDBY: 928 case PWR_SOFTRESUME: 929 break; 930 } 931 } 932 933 /* control AC97 codec */ 934 int 935 cs4280_reset_codec(void *addr) 936 { 937 struct cs428x_softc *sc; 938 int n; 939 940 sc = addr; 941 942 /* Reset codec */ 943 BA0WRITE4(sc, CS428X_ACCTL, 0); 944 delay(100); /* delay 100us */ 945 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 946 947 /* 948 * It looks like we do the following procedure, too 949 */ 950 951 /* Enable AC-link sync generation */ 952 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 953 delay(50*1000); /* XXX delay 50ms */ 954 955 /* Assert valid frame signal */ 956 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 957 958 /* Wait for valid AC97 input slot */ 959 n = 0; 960 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 961 (ACISV_ISV3 | ACISV_ISV4)) { 962 delay(1000); 963 if (++n > 1000) { 964 printf("reset_codec: AC97 inputs slot ready timeout\n"); 965 return ETIMEDOUT; 966 } 967 } 968 return 0; 969 } 970 971 972 /* Internal functions */ 973 974 void 975 cs4280_set_adc_rate(sc, rate) 976 struct cs428x_softc *sc; 977 int rate; 978 { 979 /* calculate capture rate: 980 * 981 * capture_coefficient_increment = -round(rate*128*65536/48000; 982 * capture_phase_increment = floor(48000*65536*1024/rate); 983 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 984 * cy = floor(cx/200); 985 * capture_sample_rate_correction = cx - 200*cy; 986 * capture_delay = ceil(24*48000/rate); 987 * capture_num_triplets = floor(65536*rate/24000); 988 * capture_group_length = 24000/GCD(rate, 24000); 989 * where GCD means "Greatest Common Divisor". 990 * 991 * capture_coefficient_increment, capture_phase_increment and 992 * capture_num_triplets are 32-bit signed quantities. 993 * capture_sample_rate_correction and capture_group_length are 994 * 16-bit signed quantities. 995 * capture_delay is a 14-bit unsigned quantity. 996 */ 997 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 998 u_int16_t csrc, cgl, cdlay; 999 1000 /* XXX 1001 * Even though, embedded_audio_spec says capture rate range 11025 to 1002 * 48000, dhwiface.cpp says, 1003 * 1004 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1005 * Return an error if an attempt is made to stray outside that limit." 1006 * 1007 * so assume range as 48000/9 to 48000 1008 */ 1009 1010 if (rate < 8000) 1011 rate = 8000; 1012 if (rate > 48000) 1013 rate = 48000; 1014 1015 cx = rate << 16; 1016 cci = cx / 48000; 1017 cx -= cci * 48000; 1018 cx <<= 7; 1019 cci <<= 7; 1020 cci += cx / 48000; 1021 cci = - cci; 1022 1023 cx = 48000 << 16; 1024 cpi = cx / rate; 1025 cx -= cpi * rate; 1026 cx <<= 10; 1027 cpi <<= 10; 1028 cy = cx / rate; 1029 cpi += cy; 1030 cx -= cy * rate; 1031 1032 cy = cx / 200; 1033 csrc = cx - 200*cy; 1034 1035 cdlay = ((48000 * 24) + rate - 1) / rate; 1036 #if 0 1037 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1038 #endif 1039 1040 cnt = rate << 16; 1041 cnt /= 24000; 1042 1043 cgl = 1; 1044 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1045 if (((rate / tmp1) * tmp1) != rate) 1046 cgl *= 2; 1047 } 1048 if (((rate / 3) * 3) != rate) 1049 cgl *= 3; 1050 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1051 if (((rate / tmp1) * tmp1) != rate) 1052 cgl *= 5; 1053 } 1054 #if 0 1055 /* XXX what manual says */ 1056 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1057 tmp1 |= csrc<<16; 1058 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1059 #else 1060 /* suggested by cs461x.c (ALSA driver) */ 1061 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1062 #endif 1063 1064 #if 0 1065 /* I am confused. The sample rate calculation section says 1066 * cci *is* 32-bit signed quantity but in the parameter description 1067 * section, CCI only assigned 16bit. 1068 * I believe size of the variable. 1069 */ 1070 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1071 tmp1 |= cci<<16; 1072 BA1WRITE4(sc, CS4280_CCI, tmp1); 1073 #else 1074 BA1WRITE4(sc, CS4280_CCI, cci); 1075 #endif 1076 1077 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1078 tmp1 |= cdlay <<18; 1079 BA1WRITE4(sc, CS4280_CD, tmp1); 1080 1081 BA1WRITE4(sc, CS4280_CPI, cpi); 1082 1083 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1084 tmp1 |= cgl; 1085 BA1WRITE4(sc, CS4280_CGL, tmp1); 1086 1087 BA1WRITE4(sc, CS4280_CNT, cnt); 1088 1089 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1090 tmp1 |= cgl; 1091 BA1WRITE4(sc, CS4280_CGC, tmp1); 1092 } 1093 1094 void 1095 cs4280_set_dac_rate(sc, rate) 1096 struct cs428x_softc *sc; 1097 int rate; 1098 { 1099 /* 1100 * playback rate may range from 8000Hz to 48000Hz 1101 * 1102 * play_phase_increment = floor(rate*65536*1024/48000) 1103 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1104 * py=floor(px/200) 1105 * play_sample_rate_correction = px - 200*py 1106 * 1107 * play_phase_increment is a 32bit signed quantity. 1108 * play_sample_rate_correction is a 16bit signed quantity. 1109 */ 1110 int32_t ppi; 1111 int16_t psrc; 1112 u_int32_t px, py; 1113 1114 if (rate < 8000) 1115 rate = 8000; 1116 if (rate > 48000) 1117 rate = 48000; 1118 px = rate << 16; 1119 ppi = px/48000; 1120 px -= ppi*48000; 1121 ppi <<= 10; 1122 px <<= 10; 1123 py = px / 48000; 1124 ppi += py; 1125 px -= py*48000; 1126 py = px/200; 1127 px -= py*200; 1128 psrc = px; 1129 #if 0 1130 /* what manual says */ 1131 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1132 BA1WRITE4(sc, CS4280_PSRC, 1133 ( ((psrc<<16) & PSRC_MASK) | px )); 1134 #else 1135 /* suggested by cs461x.c (ALSA driver) */ 1136 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1137 #endif 1138 BA1WRITE4(sc, CS4280_PPI, ppi); 1139 } 1140 1141 /* Download Proceessor Code and Data image */ 1142 int 1143 cs4280_download(sc, src, offset, len) 1144 struct cs428x_softc *sc; 1145 const u_int32_t *src; 1146 u_int32_t offset, len; 1147 { 1148 u_int32_t ctr; 1149 1150 #if CS4280_DEBUG > 10 1151 u_int32_t con, data; 1152 u_int8_t c0,c1,c2,c3; 1153 #endif 1154 if ((offset&3) || (len&3)) 1155 return -1; 1156 1157 len /= sizeof(u_int32_t); 1158 for (ctr = 0; ctr < len; ctr++) { 1159 /* XXX: 1160 * I cannot confirm this is the right thing or not 1161 * on BIG-ENDIAN machines. 1162 */ 1163 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1164 #if CS4280_DEBUG > 10 1165 data = htole32(*(src+ctr)); 1166 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1167 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1168 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1169 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1170 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 1171 if (data != con ) { 1172 printf("0x%06x: write=0x%08x read=0x%08x\n", 1173 offset+ctr*4, data, con); 1174 return -1; 1175 } 1176 #endif 1177 } 1178 return 0; 1179 } 1180 1181 int 1182 cs4280_download_image(sc) 1183 struct cs428x_softc *sc; 1184 { 1185 int idx, err; 1186 u_int32_t offset = 0; 1187 1188 err = 0; 1189 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1190 err = cs4280_download(sc, &BA1Struct.map[offset], 1191 BA1Struct.memory[idx].offset, 1192 BA1Struct.memory[idx].size); 1193 if (err != 0) { 1194 printf("%s: load_image failed at %d\n", 1195 sc->sc_dev.dv_xname, idx); 1196 return -1; 1197 } 1198 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1199 } 1200 return err; 1201 } 1202 1203 /* Processor Soft Reset */ 1204 void 1205 cs4280_reset(sc_) 1206 void *sc_; 1207 { 1208 struct cs428x_softc *sc = sc_; 1209 1210 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1211 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1212 delay(100); 1213 /* Clear RSTSP bit in SPCR */ 1214 BA1WRITE4(sc, CS4280_SPCR, 0); 1215 /* enable DMA reqest */ 1216 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1217 } 1218 1219 int 1220 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1221 struct cs428x_softc *sc; 1222 char *class, *device, *qualifier; 1223 { 1224 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1225 device, qualifier)); 1226 } 1227 1228 int 1229 cs4280_init(sc, init) 1230 struct cs428x_softc *sc; 1231 int init; 1232 { 1233 int n; 1234 u_int32_t mem; 1235 1236 /* Start PLL out in known state */ 1237 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1238 /* Start serial ports out in known state */ 1239 BA0WRITE4(sc, CS4280_SERMC1, 0); 1240 1241 /* Specify type of CODEC */ 1242 /* XXX should not be here */ 1243 #define SERACC_CODEC_TYPE_1_03 1244 #ifdef SERACC_CODEC_TYPE_1_03 1245 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1246 #else 1247 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1248 #endif 1249 1250 /* Reset codec */ 1251 BA0WRITE4(sc, CS428X_ACCTL, 0); 1252 delay(100); /* delay 100us */ 1253 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1254 1255 /* Enable AC-link sync generation */ 1256 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1257 delay(50*1000); /* delay 50ms */ 1258 1259 /* Set the serial port timing configuration */ 1260 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1261 1262 /* Setup clock control */ 1263 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1264 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1265 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1266 1267 /* Power up the PLL */ 1268 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1269 delay(50*1000); /* delay 50ms */ 1270 1271 /* Turn on clock */ 1272 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1273 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1274 1275 /* Set the serial port FIFO pointer to the 1276 * first sample in FIFO. (not documented) */ 1277 cs4280_clear_fifos(sc); 1278 1279 #if 0 1280 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1281 BA0WRITE4(sc, CS4280_SERBSP, 0); 1282 #endif 1283 1284 /* Configure the serial port */ 1285 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1286 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1287 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1288 1289 /* Wait for CODEC ready */ 1290 n = 0; 1291 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1292 delay(125); 1293 if (++n > 1000) { 1294 printf("%s: codec ready timeout\n", 1295 sc->sc_dev.dv_xname); 1296 return(1); 1297 } 1298 } 1299 1300 /* Assert valid frame signal */ 1301 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1302 1303 /* Wait for valid AC97 input slot */ 1304 n = 0; 1305 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1306 (ACISV_ISV3 | ACISV_ISV4)) { 1307 delay(1000); 1308 if (++n > 1000) { 1309 printf("AC97 inputs slot ready timeout\n"); 1310 return(1); 1311 } 1312 } 1313 1314 /* Set AC97 output slot valid signals */ 1315 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1316 1317 /* reset the processor */ 1318 cs4280_reset(sc); 1319 1320 /* Download the image to the processor */ 1321 if (cs4280_download_image(sc) != 0) { 1322 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1323 return(1); 1324 } 1325 1326 /* Save playback parameter and then write zero. 1327 * this ensures that DMA doesn't immediately occur upon 1328 * starting the processor core 1329 */ 1330 mem = BA1READ4(sc, CS4280_PCTL); 1331 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1332 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1333 if (init != 0) 1334 sc->sc_prun = 0; 1335 1336 /* Save capture parameter and then write zero. 1337 * this ensures that DMA doesn't immediately occur upon 1338 * starting the processor core 1339 */ 1340 mem = BA1READ4(sc, CS4280_CCTL); 1341 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1342 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1343 if (init != 0) 1344 sc->sc_rrun = 0; 1345 1346 /* Processor Startup Procedure */ 1347 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1348 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1349 1350 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1351 n = 0; 1352 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1353 delay(10); 1354 if (++n > 1000) { 1355 printf("SPCR 1->0 transition timeout\n"); 1356 return(1); 1357 } 1358 } 1359 1360 n = 0; 1361 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1362 delay(10); 1363 if (++n > 1000) { 1364 printf("SPCS 0->1 transition timeout\n"); 1365 return(1); 1366 } 1367 } 1368 /* Processor is now running !!! */ 1369 1370 /* Setup volume */ 1371 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1372 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1373 1374 /* Interrupt enable */ 1375 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1376 1377 /* playback interrupt enable */ 1378 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1379 mem |= PFIE_PI_ENABLE; 1380 BA1WRITE4(sc, CS4280_PFIE, mem); 1381 /* capture interrupt enable */ 1382 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1383 mem |= CIE_CI_ENABLE; 1384 BA1WRITE4(sc, CS4280_CIE, mem); 1385 1386 #if NMIDI > 0 1387 /* Reset midi port */ 1388 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1389 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1390 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1391 /* midi interrupt enable */ 1392 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1393 BA0WRITE4(sc, CS4280_MIDCR, mem); 1394 #endif 1395 return(0); 1396 } 1397 1398 void 1399 cs4280_clear_fifos(sc) 1400 struct cs428x_softc *sc; 1401 { 1402 int pd = 0, cnt, n; 1403 u_int32_t mem; 1404 1405 /* 1406 * If device power down, power up the device and keep power down 1407 * state. 1408 */ 1409 mem = BA0READ4(sc, CS4280_CLKCR1); 1410 if (!(mem & CLKCR1_SWCE)) { 1411 printf("cs4280_clear_fifo: power down found.\n"); 1412 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1413 pd = 1; 1414 } 1415 BA0WRITE4(sc, CS4280_SERBWP, 0); 1416 for (cnt = 0; cnt < 256; cnt++) { 1417 n = 0; 1418 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1419 delay(1000); 1420 if (++n > 1000) { 1421 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1422 break; 1423 } 1424 } 1425 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1426 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1427 } 1428 if (pd) 1429 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1430 } 1431 1432 #if NMIDI > 0 1433 int 1434 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1435 void *addr; 1436 int flags; 1437 void (*iintr)__P((void *, int)); 1438 void (*ointr)__P((void *)); 1439 void *arg; 1440 { 1441 struct cs428x_softc *sc = addr; 1442 u_int32_t mem; 1443 1444 DPRINTF(("midi_open\n")); 1445 sc->sc_iintr = iintr; 1446 sc->sc_ointr = ointr; 1447 sc->sc_arg = arg; 1448 1449 /* midi interrupt enable */ 1450 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1451 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1452 BA0WRITE4(sc, CS4280_MIDCR, mem); 1453 #ifdef CS4280_DEBUG 1454 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1455 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1456 return(EINVAL); 1457 } 1458 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1459 #endif 1460 return 0; 1461 } 1462 1463 void 1464 cs4280_midi_close(addr) 1465 void *addr; 1466 { 1467 struct cs428x_softc *sc = addr; 1468 u_int32_t mem; 1469 1470 DPRINTF(("midi_close\n")); 1471 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1472 mem = BA0READ4(sc, CS4280_MIDCR); 1473 mem &= ~MIDCR_MASK; 1474 BA0WRITE4(sc, CS4280_MIDCR, mem); 1475 1476 sc->sc_iintr = 0; 1477 sc->sc_ointr = 0; 1478 } 1479 1480 int 1481 cs4280_midi_output(addr, d) 1482 void *addr; 1483 int d; 1484 { 1485 struct cs428x_softc *sc = addr; 1486 u_int32_t mem; 1487 int x; 1488 1489 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1490 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1491 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1492 mem |= d & MIDWP_MASK; 1493 DPRINTFN(5,("midi_output d=0x%08x",d)); 1494 BA0WRITE4(sc, CS4280_MIDWP, mem); 1495 #ifdef DIAGNOSTIC 1496 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1497 DPRINTF(("Bad write data: %d %d", 1498 mem, BA0READ4(sc, CS4280_MIDWP))); 1499 return(EIO); 1500 } 1501 #endif 1502 return 0; 1503 } 1504 delay(MIDI_BUSY_DELAY); 1505 } 1506 return (EIO); 1507 } 1508 1509 void 1510 cs4280_midi_getinfo(addr, mi) 1511 void *addr; 1512 struct midi_info *mi; 1513 { 1514 mi->name = "CS4280 MIDI UART"; 1515 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1516 } 1517 1518 #endif 1519 1520 /* DEBUG functions */ 1521 #if CS4280_DEBUG > 10 1522 int 1523 cs4280_checkimage(sc, src, offset, len) 1524 struct cs428x_softc *sc; 1525 u_int32_t *src; 1526 u_int32_t offset, len; 1527 { 1528 u_int32_t ctr, data; 1529 int err = 0; 1530 1531 if ((offset&3) || (len&3)) 1532 return -1; 1533 1534 len /= sizeof(u_int32_t); 1535 for (ctr = 0; ctr < len; ctr++) { 1536 /* I cannot confirm this is the right thing 1537 * on BIG-ENDIAN machines 1538 */ 1539 data = BA1READ4(sc, offset+ctr*4); 1540 if (data != htole32(*(src+ctr))) { 1541 printf("0x%06x: 0x%08x(0x%08x)\n", 1542 offset+ctr*4, data, *(src+ctr)); 1543 *(src+ctr) = data; 1544 ++err; 1545 } 1546 } 1547 return err; 1548 } 1549 1550 int 1551 cs4280_check_images(sc) 1552 struct cs428x_softc *sc; 1553 { 1554 int idx, err; 1555 u_int32_t offset = 0; 1556 1557 err = 0; 1558 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 1559 for (idx = 0; idx < 1; ++idx) { 1560 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1561 BA1Struct.memory[idx].offset, 1562 BA1Struct.memory[idx].size); 1563 if (err != 0) { 1564 printf("%s: check_image failed at %d\n", 1565 sc->sc_dev.dv_xname, idx); 1566 } 1567 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1568 } 1569 return err; 1570 } 1571 1572 #endif 1573
Indexes created Thu Oct 02 14:10:14 GMT 2025