cs4280.c revision 1.32.2.1
1 /* $NetBSD: cs4280.c,v 1.32.2.1 2005/01/02 20:03:11 kent Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.32.2.1 2005/01/02 20:03:11 kent Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <machine/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 int cs4280_match(struct device *, struct cfdata *, void *); 93 void cs4280_attach(struct device *, struct device *, void *); 94 int cs4280_intr(void *); 95 int cs4280_query_encoding(void *, struct audio_encoding *); 96 int cs4280_set_params(void *, int, int, audio_params_t *, audio_params_t *, 97 stream_filter_list_t *, stream_filter_list_t *); 98 int cs4280_halt_output(void *); 99 int cs4280_halt_input(void *); 100 int cs4280_getdev(void *, struct audio_device *); 101 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 102 void *, const audio_params_t *); 103 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 104 void *, const audio_params_t *); 105 106 int cs4280_reset_codec(void *); 107 108 /* For PowerHook */ 109 void cs4280_power(int, void *); 110 111 /* Internal functions */ 112 void cs4280_set_adc_rate(struct cs428x_softc *, int ); 113 void cs4280_set_dac_rate(struct cs428x_softc *, int ); 114 int cs4280_download(struct cs428x_softc *, const u_int32_t *, u_int32_t, u_int32_t); 115 int cs4280_download_image(struct cs428x_softc *); 116 void cs4280_reset(void *); 117 int cs4280_get_portnum_by_name(struct cs428x_softc *, char *, char *, char *); 118 int cs4280_init(struct cs428x_softc *, int); 119 void cs4280_clear_fifos(struct cs428x_softc *); 120 121 #if CS4280_DEBUG > 10 122 /* Thease two function is only for checking image loading is succeeded or not. */ 123 int cs4280_check_images(struct cs428x_softc *); 124 int cs4280_checkimage(struct cs428x_softc *, u_int32_t *, u_int32_t, u_int32_t); 125 #endif 126 127 const struct audio_hw_if cs4280_hw_if = { 128 cs428x_open, 129 cs428x_close, 130 NULL, 131 cs4280_query_encoding, 132 cs4280_set_params, 133 cs428x_round_blocksize, 134 NULL, 135 NULL, 136 NULL, 137 NULL, 138 NULL, 139 cs4280_halt_output, 140 cs4280_halt_input, 141 NULL, 142 cs4280_getdev, 143 NULL, 144 cs428x_mixer_set_port, 145 cs428x_mixer_get_port, 146 cs428x_query_devinfo, 147 cs428x_malloc, 148 cs428x_free, 149 cs428x_round_buffersize, 150 cs428x_mappage, 151 cs428x_get_props, 152 cs4280_trigger_output, 153 cs4280_trigger_input, 154 NULL, 155 }; 156 157 #if NMIDI > 0 158 /* Midi Interface */ 159 int cs4280_midi_open(void *, int, void (*)(void *, int), 160 void (*)(void *), void *); 161 void cs4280_midi_close(void*); 162 int cs4280_midi_output(void *, int); 163 void cs4280_midi_getinfo(void *, struct midi_info *); 164 165 const struct midi_hw_if cs4280_midi_hw_if = { 166 cs4280_midi_open, 167 cs4280_midi_close, 168 cs4280_midi_output, 169 cs4280_midi_getinfo, 170 0, 171 }; 172 #endif 173 174 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 175 cs4280_match, cs4280_attach, NULL, NULL); 176 177 struct audio_device cs4280_device = { 178 "CS4280", 179 "", 180 "cs4280" 181 }; 182 183 184 int 185 cs4280_match(parent, match, aux) 186 struct device *parent; 187 struct cfdata *match; 188 void *aux; 189 { 190 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 191 192 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 193 return 0; 194 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 195 #if 0 /* I can't confirm */ 196 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 197 #endif 198 ) 199 return 1; 200 return 0; 201 } 202 203 void 204 cs4280_attach(parent, self, aux) 205 struct device *parent; 206 struct device *self; 207 void *aux; 208 { 209 struct cs428x_softc *sc = (struct cs428x_softc *)self; 210 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 211 pci_chipset_tag_t pc = pa->pa_pc; 212 char const *intrstr; 213 pci_intr_handle_t ih; 214 pcireg_t reg; 215 char devinfo[256]; 216 u_int32_t mem; 217 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 218 219 aprint_naive(": Audio controller\n"); 220 221 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 222 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 223 PCI_REVISION(pa->pa_class)); 224 225 /* Map I/O register */ 226 if (pci_mapreg_map(pa, PCI_BA0, 227 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 228 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 229 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 230 return; 231 } 232 if (pci_mapreg_map(pa, PCI_BA1, 233 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 234 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 235 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 236 return; 237 } 238 239 sc->sc_dmatag = pa->pa_dmat; 240 241 /* Check and set Power State */ 242 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 243 &pci_pwrmgmt_cap_reg, 0)) { 244 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 245 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 246 pci_pwrmgmt_csr_reg); 247 DPRINTF(("%s: Power State is %d\n", 248 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 249 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 250 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 251 (reg & ~PCI_PMCSR_STATE_MASK) | 252 PCI_PMCSR_STATE_D0); 253 } 254 } 255 256 /* Enable the device (set bus master flag) */ 257 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 258 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 259 reg | PCI_COMMAND_MASTER_ENABLE); 260 261 /* LATENCY_TIMER setting */ 262 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 263 if ( PCI_LATTIMER(mem) < 32 ) { 264 mem &= 0xffff00ff; 265 mem |= 0x00002000; 266 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 267 } 268 269 /* Map and establish the interrupt. */ 270 if (pci_intr_map(pa, &ih)) { 271 aprint_error("%s: couldn't map interrupt\n", 272 sc->sc_dev.dv_xname); 273 return; 274 } 275 intrstr = pci_intr_string(pc, ih); 276 277 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 278 if (sc->sc_ih == NULL) { 279 aprint_error("%s: couldn't establish interrupt", 280 sc->sc_dev.dv_xname); 281 if (intrstr != NULL) 282 aprint_normal(" at %s", intrstr); 283 aprint_normal("\n"); 284 return; 285 } 286 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 287 288 /* Initialization */ 289 if(cs4280_init(sc, 1) != 0) 290 return; 291 292 sc->type = TYPE_CS4280; 293 sc->halt_input = cs4280_halt_input; 294 sc->halt_output = cs4280_halt_output; 295 296 /* setup buffer related parameters */ 297 sc->dma_size = CS4280_DCHUNK; 298 sc->dma_align = CS4280_DALIGN; 299 sc->hw_blocksize = CS4280_ICHUNK; 300 301 /* AC 97 attachment */ 302 sc->host_if.arg = sc; 303 sc->host_if.attach = cs428x_attach_codec; 304 sc->host_if.read = cs428x_read_codec; 305 sc->host_if.write = cs428x_write_codec; 306 sc->host_if.reset = cs4280_reset_codec; 307 if (ac97_attach(&sc->host_if, self) != 0) { 308 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 309 return; 310 } 311 312 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 313 314 #if NMIDI > 0 315 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 316 #endif 317 318 sc->sc_suspend = PWR_RESUME; 319 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 320 } 321 322 /* Interrupt handling function */ 323 int 324 cs4280_intr(p) 325 void *p; 326 { 327 /* 328 * XXX 329 * 330 * Since CS4280 has only 4kB DMA buffer and 331 * interrupt occurs every 2kB block, I create dummy buffer 332 * which returns to audio driver and actual DMA buffer 333 * using in DMA transfer. 334 * 335 * 336 * ring buffer in audio.c is pointed by BUFADDR 337 * <------ ring buffer size == 64kB ------> 338 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 339 * |= = = =|= = = =|= = = =|= = = =|= = = =| 340 * | | | | | | <- call audio_intp every 341 * sc->sc_[pr]_count time. 342 * 343 * actual DMA buffer is pointed by KERNADDR 344 * <-> DMA buffer size = 4kB 345 * |= =| 346 * 347 * 348 */ 349 struct cs428x_softc *sc = p; 350 u_int32_t intr, mem; 351 char * empty_dma; 352 int handled = 0; 353 354 /* grab interrupt register then clear it */ 355 intr = BA0READ4(sc, CS4280_HISR); 356 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 357 358 /* Playback Interrupt */ 359 if (intr & HISR_PINT) { 360 handled = 1; 361 mem = BA1READ4(sc, CS4280_PFIE); 362 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 363 if (sc->sc_prun) { 364 if ((sc->sc_pi%sc->sc_pcount) == 0) 365 sc->sc_pintr(sc->sc_parg); 366 } else { 367 printf("unexpected play intr\n"); 368 } 369 /* copy buffer */ 370 ++sc->sc_pi; 371 empty_dma = sc->sc_pdma->addr; 372 if (sc->sc_pi&1) 373 empty_dma += sc->hw_blocksize; 374 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 375 sc->sc_pn += sc->hw_blocksize; 376 if (sc->sc_pn >= sc->sc_pe) 377 sc->sc_pn = sc->sc_ps; 378 BA1WRITE4(sc, CS4280_PFIE, mem); 379 } 380 /* Capture Interrupt */ 381 if (intr & HISR_CINT) { 382 int i; 383 int16_t rdata; 384 385 handled = 1; 386 mem = BA1READ4(sc, CS4280_CIE); 387 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 388 ++sc->sc_ri; 389 empty_dma = sc->sc_rdma->addr; 390 if ((sc->sc_ri&1) == 0) 391 empty_dma += sc->hw_blocksize; 392 393 /* 394 * XXX 395 * I think this audio data conversion should be 396 * happend in upper layer, but I put this here 397 * since there is no conversion function available. 398 */ 399 switch(sc->sc_rparam) { 400 case CF_16BIT_STEREO: 401 /* just copy it */ 402 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 403 sc->sc_rn += sc->hw_blocksize; 404 break; 405 case CF_16BIT_MONO: 406 for (i = 0; i < 512; i++) { 407 rdata = *((int16_t *)empty_dma)>>1; 408 empty_dma += 2; 409 rdata += *((int16_t *)empty_dma)>>1; 410 empty_dma += 2; 411 *((int16_t *)sc->sc_rn) = rdata; 412 sc->sc_rn += 2; 413 } 414 break; 415 case CF_8BIT_STEREO: 416 for (i = 0; i < 512; i++) { 417 rdata = *((int16_t*)empty_dma); 418 empty_dma += 2; 419 *sc->sc_rn++ = rdata >> 8; 420 rdata = *((int16_t*)empty_dma); 421 empty_dma += 2; 422 *sc->sc_rn++ = rdata >> 8; 423 } 424 break; 425 case CF_8BIT_MONO: 426 for (i = 0; i < 512; i++) { 427 rdata = *((int16_t*)empty_dma) >>1; 428 empty_dma += 2; 429 rdata += *((int16_t*)empty_dma) >>1; 430 empty_dma += 2; 431 *sc->sc_rn++ = rdata >>8; 432 } 433 break; 434 default: 435 /* Should not reach here */ 436 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 437 } 438 if (sc->sc_rn >= sc->sc_re) 439 sc->sc_rn = sc->sc_rs; 440 BA1WRITE4(sc, CS4280_CIE, mem); 441 if (sc->sc_rrun) { 442 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 443 sc->sc_rintr(sc->sc_rarg); 444 } else { 445 printf("unexpected record intr\n"); 446 } 447 } 448 449 #if NMIDI > 0 450 /* Midi port Interrupt */ 451 if (intr & HISR_MIDI) { 452 int data; 453 454 handled = 1; 455 DPRINTF(("i: %d: ", 456 BA0READ4(sc, CS4280_MIDSR))); 457 /* Read the received data */ 458 while ((sc->sc_iintr != NULL) && 459 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 460 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 461 DPRINTF(("r:%x\n",data)); 462 sc->sc_iintr(sc->sc_arg, data); 463 } 464 465 /* Write the data */ 466 #if 1 467 /* XXX: 468 * It seems "Transmit Buffer Full" never activate until EOI 469 * is deliverd. Shall I throw EOI top of this routine ? 470 */ 471 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 472 DPRINTF(("w: ")); 473 if (sc->sc_ointr != NULL) 474 sc->sc_ointr(sc->sc_arg); 475 } 476 #else 477 while ((sc->sc_ointr != NULL) && 478 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 479 DPRINTF(("w: ")); 480 sc->sc_ointr(sc->sc_arg); 481 } 482 #endif 483 DPRINTF(("\n")); 484 } 485 #endif 486 487 return handled; 488 } 489 490 int 491 cs4280_query_encoding(addr, fp) 492 void *addr; 493 struct audio_encoding *fp; 494 { 495 switch (fp->index) { 496 case 0: 497 strcpy(fp->name, AudioEulinear); 498 fp->encoding = AUDIO_ENCODING_ULINEAR; 499 fp->precision = 8; 500 fp->flags = 0; 501 break; 502 case 1: 503 strcpy(fp->name, AudioEmulaw); 504 fp->encoding = AUDIO_ENCODING_ULAW; 505 fp->precision = 8; 506 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 507 break; 508 case 2: 509 strcpy(fp->name, AudioEalaw); 510 fp->encoding = AUDIO_ENCODING_ALAW; 511 fp->precision = 8; 512 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 513 break; 514 case 3: 515 strcpy(fp->name, AudioEslinear); 516 fp->encoding = AUDIO_ENCODING_SLINEAR; 517 fp->precision = 8; 518 fp->flags = 0; 519 break; 520 case 4: 521 strcpy(fp->name, AudioEslinear_le); 522 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 523 fp->precision = 16; 524 fp->flags = 0; 525 break; 526 case 5: 527 strcpy(fp->name, AudioEulinear_le); 528 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 529 fp->precision = 16; 530 fp->flags = 0; 531 break; 532 case 6: 533 strcpy(fp->name, AudioEslinear_be); 534 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 535 fp->precision = 16; 536 fp->flags = 0; 537 break; 538 case 7: 539 strcpy(fp->name, AudioEulinear_be); 540 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 541 fp->precision = 16; 542 fp->flags = 0; 543 break; 544 default: 545 return EINVAL; 546 } 547 return 0; 548 } 549 550 int 551 cs4280_set_params(void *addr, int setmode, int usemode, 552 audio_params_t *play, audio_params_t *rec, 553 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 554 { 555 audio_params_t hw; 556 struct cs428x_softc *sc = addr; 557 struct audio_params *p; 558 stream_filter_list_t *fil; 559 int mode; 560 561 for (mode = AUMODE_RECORD; mode != -1; 562 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 563 if ((setmode & mode) == 0) 564 continue; 565 566 p = mode == AUMODE_PLAY ? play : rec; 567 568 if (p == play) { 569 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 570 p->sample_rate, p->precision, p->channels)); 571 /* play back data format may be 8- or 16-bit and 572 * either stereo or mono. 573 * playback rate may range from 8000Hz to 48000Hz 574 */ 575 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 576 (p->precision != 8 && p->precision != 16) || 577 (p->channels != 1 && p->channels != 2) ) { 578 return EINVAL; 579 } 580 } else { 581 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 582 p->sample_rate, p->precision, p->channels)); 583 /* capture data format must be 16bit stereo 584 * and sample rate range from 11025Hz to 48000Hz. 585 * 586 * XXX: it looks like to work with 8000Hz, 587 * although data sheets say lower limit is 588 * 11025 Hz. 589 */ 590 591 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 592 (p->precision != 8 && p->precision != 16) || 593 (p->channels != 1 && p->channels != 2) ) { 594 return EINVAL; 595 } 596 } 597 fil = mode == AUMODE_PLAY ? pfil : rfil; 598 hw = *p; 599 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 600 601 /* capturing data is slinear */ 602 switch (p->encoding) { 603 case AUDIO_ENCODING_SLINEAR_BE: 604 if (mode == AUMODE_RECORD && p->precision == 16) { 605 stream_filter_list_append(fil, swap_bytes, &hw); 606 } 607 break; 608 case AUDIO_ENCODING_SLINEAR_LE: 609 break; 610 case AUDIO_ENCODING_ULINEAR_BE: 611 if (mode == AUMODE_RECORD) { 612 stream_filter_list_append 613 (fil, p->precision == 16 614 ? swap_bytes_change_sign16 615 : change_sign8, &hw); 616 } 617 break; 618 case AUDIO_ENCODING_ULINEAR_LE: 619 if (mode == AUMODE_RECORD) { 620 stream_filter_list_append 621 (fil, p->precision == 16 622 ? change_sign16 : change_sign8, 623 &hw); 624 } 625 break; 626 case AUDIO_ENCODING_ULAW: 627 if (mode == AUMODE_PLAY) { 628 hw.precision = 16; 629 hw.validbits = 16; 630 stream_filter_list_append 631 (fil, mulaw_to_linear16, &hw); 632 } else { 633 stream_filter_list_append 634 (fil, linear8_to_mulaw, &hw); 635 } 636 break; 637 case AUDIO_ENCODING_ALAW: 638 if (mode == AUMODE_PLAY) { 639 hw.precision = 16; 640 hw.validbits = 16; 641 stream_filter_list_append 642 (fil, alaw_to_linear16, &hw); 643 } else { 644 stream_filter_list_append 645 (fil, linear8_to_alaw, &hw); 646 } 647 break; 648 default: 649 return EINVAL; 650 } 651 } 652 653 /* set sample rate */ 654 cs4280_set_dac_rate(sc, play->sample_rate); 655 cs4280_set_adc_rate(sc, rec->sample_rate); 656 return 0; 657 } 658 659 int 660 cs4280_halt_output(addr) 661 void *addr; 662 { 663 struct cs428x_softc *sc = addr; 664 u_int32_t mem; 665 666 mem = BA1READ4(sc, CS4280_PCTL); 667 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 668 sc->sc_prun = 0; 669 return 0; 670 } 671 672 int 673 cs4280_halt_input(addr) 674 void *addr; 675 { 676 struct cs428x_softc *sc = addr; 677 u_int32_t mem; 678 679 mem = BA1READ4(sc, CS4280_CCTL); 680 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 681 sc->sc_rrun = 0; 682 return 0; 683 } 684 685 int 686 cs4280_getdev(addr, retp) 687 void *addr; 688 struct audio_device *retp; 689 { 690 *retp = cs4280_device; 691 return 0; 692 } 693 694 int 695 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 696 void *addr; 697 void *start, *end; 698 int blksize; 699 void (*intr) __P((void *)); 700 void *arg; 701 const audio_params_t *param; 702 { 703 struct cs428x_softc *sc = addr; 704 u_int32_t pfie, pctl, pdtc; 705 struct cs428x_dma *p; 706 707 #ifdef DIAGNOSTIC 708 if (sc->sc_prun) 709 printf("cs4280_trigger_output: already running\n"); 710 #endif 711 sc->sc_prun = 1; 712 713 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 714 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 715 sc->sc_pintr = intr; 716 sc->sc_parg = arg; 717 718 /* stop playback DMA */ 719 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 720 721 /* setup PDTC */ 722 pdtc = BA1READ4(sc, CS4280_PDTC); 723 pdtc &= ~PDTC_MASK; 724 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 725 BA1WRITE4(sc, CS4280_PDTC, pdtc); 726 727 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 728 param->precision, param->channels, param->encoding)); 729 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 730 ; 731 if (p == NULL) { 732 printf("cs4280_trigger_output: bad addr %p\n", start); 733 return EINVAL; 734 } 735 if (DMAADDR(p) % sc->dma_align != 0 ) { 736 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 737 "4kB align\n", (ulong)DMAADDR(p)); 738 return EINVAL; 739 } 740 741 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 742 sc->sc_ps = (char *)start; 743 sc->sc_pe = (char *)end; 744 sc->sc_pdma = p; 745 sc->sc_pbuf = KERNADDR(p); 746 sc->sc_pi = 0; 747 sc->sc_pn = sc->sc_ps; 748 if (blksize >= sc->dma_size) { 749 sc->sc_pn = sc->sc_ps + sc->dma_size; 750 memcpy(sc->sc_pbuf, start, sc->dma_size); 751 ++sc->sc_pi; 752 } else { 753 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 754 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 755 } 756 757 /* initiate playback DMA */ 758 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 759 760 /* set PFIE */ 761 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 762 763 if (param->precision == 8) 764 pfie |= PFIE_8BIT; 765 if (param->channels == 1) 766 pfie |= PFIE_MONO; 767 768 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 769 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 770 pfie |= PFIE_SWAPPED; 771 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 772 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 773 pfie |= PFIE_UNSIGNED; 774 775 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 776 777 sc->sc_prate = param->sample_rate; 778 cs4280_set_dac_rate(sc, param->sample_rate); 779 780 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 781 pctl |= sc->pctl; 782 BA1WRITE4(sc, CS4280_PCTL, pctl); 783 return 0; 784 } 785 786 int 787 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 788 void *addr; 789 void *start, *end; 790 int blksize; 791 void (*intr) __P((void *)); 792 void *arg; 793 const audio_params_t *param; 794 { 795 struct cs428x_softc *sc = addr; 796 u_int32_t cctl, cie; 797 struct cs428x_dma *p; 798 799 #ifdef DIAGNOSTIC 800 if (sc->sc_rrun) 801 printf("cs4280_trigger_input: already running\n"); 802 #endif 803 sc->sc_rrun = 1; 804 805 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 806 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 807 sc->sc_rintr = intr; 808 sc->sc_rarg = arg; 809 810 /* stop capture DMA */ 811 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 812 813 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 814 ; 815 if (p == NULL) { 816 printf("cs4280_trigger_input: bad addr %p\n", start); 817 return EINVAL; 818 } 819 if (DMAADDR(p) % sc->dma_align != 0) { 820 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 821 "4kB align\n", (ulong)DMAADDR(p)); 822 return EINVAL; 823 } 824 825 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 826 sc->sc_rs = (char *)start; 827 sc->sc_re = (char *)end; 828 sc->sc_rdma = p; 829 sc->sc_rbuf = KERNADDR(p); 830 sc->sc_ri = 0; 831 sc->sc_rn = sc->sc_rs; 832 833 /* initiate capture DMA */ 834 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 835 836 /* setup format information for internal converter */ 837 sc->sc_rparam = 0; 838 if (param->precision == 8) { 839 sc->sc_rparam += CF_8BIT; 840 sc->sc_rcount <<= 1; 841 } 842 if (param->channels == 1) { 843 sc->sc_rparam += CF_MONO; 844 sc->sc_rcount <<= 1; 845 } 846 847 /* set CIE */ 848 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 849 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 850 851 sc->sc_rrate = param->sample_rate; 852 cs4280_set_adc_rate(sc, param->sample_rate); 853 854 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 855 cctl |= sc->cctl; 856 BA1WRITE4(sc, CS4280_CCTL, cctl); 857 return 0; 858 } 859 860 /* Power Hook */ 861 void 862 cs4280_power(why, v) 863 int why; 864 void *v; 865 { 866 struct cs428x_softc *sc = (struct cs428x_softc *)v; 867 static u_int32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 868 static u_int32_t cctl = 0, cba = 0, cie = 0; 869 870 DPRINTF(("%s: cs4280_power why=%d\n", 871 sc->sc_dev.dv_xname, why)); 872 switch (why) { 873 case PWR_SUSPEND: 874 case PWR_STANDBY: 875 sc->sc_suspend = why; 876 877 /* save current playback status */ 878 if ( sc->sc_prun ) { 879 pctl = BA1READ4(sc, CS4280_PCTL); 880 pfie = BA1READ4(sc, CS4280_PFIE); 881 pba = BA1READ4(sc, CS4280_PBA); 882 pdtc = BA1READ4(sc, CS4280_PDTC); 883 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 884 pctl, pfie, pba, pdtc)); 885 } 886 887 /* save current capture status */ 888 if ( sc->sc_rrun ) { 889 cctl = BA1READ4(sc, CS4280_CCTL); 890 cie = BA1READ4(sc, CS4280_CIE); 891 cba = BA1READ4(sc, CS4280_CBA); 892 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 893 cctl, cie, cba)); 894 } 895 896 /* Stop DMA */ 897 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 898 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 899 break; 900 case PWR_RESUME: 901 if (sc->sc_suspend == PWR_RESUME) { 902 printf("cs4280_power: odd, resume without suspend.\n"); 903 sc->sc_suspend = why; 904 return; 905 } 906 sc->sc_suspend = why; 907 cs4280_init(sc, 0); 908 cs4280_reset_codec(sc); 909 910 /* restore ac97 registers */ 911 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 912 913 /* restore DMA related status */ 914 if(sc->sc_prun) { 915 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 916 pctl, pfie, pba, pdtc)); 917 cs4280_set_dac_rate(sc, sc->sc_prate); 918 BA1WRITE4(sc, CS4280_PDTC, pdtc); 919 BA1WRITE4(sc, CS4280_PBA, pba); 920 BA1WRITE4(sc, CS4280_PFIE, pfie); 921 BA1WRITE4(sc, CS4280_PCTL, pctl); 922 } 923 924 if (sc->sc_rrun) { 925 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 926 cctl, cie, cba)); 927 cs4280_set_adc_rate(sc, sc->sc_rrate); 928 BA1WRITE4(sc, CS4280_CBA, cba); 929 BA1WRITE4(sc, CS4280_CIE, cie); 930 BA1WRITE4(sc, CS4280_CCTL, cctl); 931 } 932 break; 933 case PWR_SOFTSUSPEND: 934 case PWR_SOFTSTANDBY: 935 case PWR_SOFTRESUME: 936 break; 937 } 938 } 939 940 /* control AC97 codec */ 941 int 942 cs4280_reset_codec(void *addr) 943 { 944 struct cs428x_softc *sc; 945 int n; 946 947 sc = addr; 948 949 /* Reset codec */ 950 BA0WRITE4(sc, CS428X_ACCTL, 0); 951 delay(100); /* delay 100us */ 952 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 953 954 /* 955 * It looks like we do the following procedure, too 956 */ 957 958 /* Enable AC-link sync generation */ 959 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 960 delay(50*1000); /* XXX delay 50ms */ 961 962 /* Assert valid frame signal */ 963 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 964 965 /* Wait for valid AC97 input slot */ 966 n = 0; 967 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 968 (ACISV_ISV3 | ACISV_ISV4)) { 969 delay(1000); 970 if (++n > 1000) { 971 printf("reset_codec: AC97 inputs slot ready timeout\n"); 972 return ETIMEDOUT; 973 } 974 } 975 return 0; 976 } 977 978 979 /* Internal functions */ 980 981 void 982 cs4280_set_adc_rate(sc, rate) 983 struct cs428x_softc *sc; 984 int rate; 985 { 986 /* calculate capture rate: 987 * 988 * capture_coefficient_increment = -round(rate*128*65536/48000; 989 * capture_phase_increment = floor(48000*65536*1024/rate); 990 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 991 * cy = floor(cx/200); 992 * capture_sample_rate_correction = cx - 200*cy; 993 * capture_delay = ceil(24*48000/rate); 994 * capture_num_triplets = floor(65536*rate/24000); 995 * capture_group_length = 24000/GCD(rate, 24000); 996 * where GCD means "Greatest Common Divisor". 997 * 998 * capture_coefficient_increment, capture_phase_increment and 999 * capture_num_triplets are 32-bit signed quantities. 1000 * capture_sample_rate_correction and capture_group_length are 1001 * 16-bit signed quantities. 1002 * capture_delay is a 14-bit unsigned quantity. 1003 */ 1004 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 1005 u_int16_t csrc, cgl, cdlay; 1006 1007 /* XXX 1008 * Even though, embedded_audio_spec says capture rate range 11025 to 1009 * 48000, dhwiface.cpp says, 1010 * 1011 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1012 * Return an error if an attempt is made to stray outside that limit." 1013 * 1014 * so assume range as 48000/9 to 48000 1015 */ 1016 1017 if (rate < 8000) 1018 rate = 8000; 1019 if (rate > 48000) 1020 rate = 48000; 1021 1022 cx = rate << 16; 1023 cci = cx / 48000; 1024 cx -= cci * 48000; 1025 cx <<= 7; 1026 cci <<= 7; 1027 cci += cx / 48000; 1028 cci = - cci; 1029 1030 cx = 48000 << 16; 1031 cpi = cx / rate; 1032 cx -= cpi * rate; 1033 cx <<= 10; 1034 cpi <<= 10; 1035 cy = cx / rate; 1036 cpi += cy; 1037 cx -= cy * rate; 1038 1039 cy = cx / 200; 1040 csrc = cx - 200*cy; 1041 1042 cdlay = ((48000 * 24) + rate - 1) / rate; 1043 #if 0 1044 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1045 #endif 1046 1047 cnt = rate << 16; 1048 cnt /= 24000; 1049 1050 cgl = 1; 1051 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1052 if (((rate / tmp1) * tmp1) != rate) 1053 cgl *= 2; 1054 } 1055 if (((rate / 3) * 3) != rate) 1056 cgl *= 3; 1057 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1058 if (((rate / tmp1) * tmp1) != rate) 1059 cgl *= 5; 1060 } 1061 #if 0 1062 /* XXX what manual says */ 1063 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1064 tmp1 |= csrc<<16; 1065 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1066 #else 1067 /* suggested by cs461x.c (ALSA driver) */ 1068 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1069 #endif 1070 1071 #if 0 1072 /* I am confused. The sample rate calculation section says 1073 * cci *is* 32-bit signed quantity but in the parameter description 1074 * section, CCI only assigned 16bit. 1075 * I believe size of the variable. 1076 */ 1077 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1078 tmp1 |= cci<<16; 1079 BA1WRITE4(sc, CS4280_CCI, tmp1); 1080 #else 1081 BA1WRITE4(sc, CS4280_CCI, cci); 1082 #endif 1083 1084 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1085 tmp1 |= cdlay <<18; 1086 BA1WRITE4(sc, CS4280_CD, tmp1); 1087 1088 BA1WRITE4(sc, CS4280_CPI, cpi); 1089 1090 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1091 tmp1 |= cgl; 1092 BA1WRITE4(sc, CS4280_CGL, tmp1); 1093 1094 BA1WRITE4(sc, CS4280_CNT, cnt); 1095 1096 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1097 tmp1 |= cgl; 1098 BA1WRITE4(sc, CS4280_CGC, tmp1); 1099 } 1100 1101 void 1102 cs4280_set_dac_rate(sc, rate) 1103 struct cs428x_softc *sc; 1104 int rate; 1105 { 1106 /* 1107 * playback rate may range from 8000Hz to 48000Hz 1108 * 1109 * play_phase_increment = floor(rate*65536*1024/48000) 1110 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1111 * py=floor(px/200) 1112 * play_sample_rate_correction = px - 200*py 1113 * 1114 * play_phase_increment is a 32bit signed quantity. 1115 * play_sample_rate_correction is a 16bit signed quantity. 1116 */ 1117 int32_t ppi; 1118 int16_t psrc; 1119 u_int32_t px, py; 1120 1121 if (rate < 8000) 1122 rate = 8000; 1123 if (rate > 48000) 1124 rate = 48000; 1125 px = rate << 16; 1126 ppi = px/48000; 1127 px -= ppi*48000; 1128 ppi <<= 10; 1129 px <<= 10; 1130 py = px / 48000; 1131 ppi += py; 1132 px -= py*48000; 1133 py = px/200; 1134 px -= py*200; 1135 psrc = px; 1136 #if 0 1137 /* what manual says */ 1138 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1139 BA1WRITE4(sc, CS4280_PSRC, 1140 ( ((psrc<<16) & PSRC_MASK) | px )); 1141 #else 1142 /* suggested by cs461x.c (ALSA driver) */ 1143 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1144 #endif 1145 BA1WRITE4(sc, CS4280_PPI, ppi); 1146 } 1147 1148 /* Download Proceessor Code and Data image */ 1149 int 1150 cs4280_download(sc, src, offset, len) 1151 struct cs428x_softc *sc; 1152 const u_int32_t *src; 1153 u_int32_t offset, len; 1154 { 1155 u_int32_t ctr; 1156 1157 #if CS4280_DEBUG > 10 1158 u_int32_t con, data; 1159 u_int8_t c0,c1,c2,c3; 1160 #endif 1161 if ((offset&3) || (len&3)) 1162 return -1; 1163 1164 len /= sizeof(u_int32_t); 1165 for (ctr = 0; ctr < len; ctr++) { 1166 /* XXX: 1167 * I cannot confirm this is the right thing or not 1168 * on BIG-ENDIAN machines. 1169 */ 1170 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1171 #if CS4280_DEBUG > 10 1172 data = htole32(*(src+ctr)); 1173 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1174 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1175 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1176 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1177 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 1178 if (data != con ) { 1179 printf("0x%06x: write=0x%08x read=0x%08x\n", 1180 offset+ctr*4, data, con); 1181 return -1; 1182 } 1183 #endif 1184 } 1185 return 0; 1186 } 1187 1188 int 1189 cs4280_download_image(sc) 1190 struct cs428x_softc *sc; 1191 { 1192 int idx, err; 1193 u_int32_t offset = 0; 1194 1195 err = 0; 1196 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1197 err = cs4280_download(sc, &BA1Struct.map[offset], 1198 BA1Struct.memory[idx].offset, 1199 BA1Struct.memory[idx].size); 1200 if (err != 0) { 1201 printf("%s: load_image failed at %d\n", 1202 sc->sc_dev.dv_xname, idx); 1203 return -1; 1204 } 1205 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1206 } 1207 return err; 1208 } 1209 1210 /* Processor Soft Reset */ 1211 void 1212 cs4280_reset(sc_) 1213 void *sc_; 1214 { 1215 struct cs428x_softc *sc = sc_; 1216 1217 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1218 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1219 delay(100); 1220 /* Clear RSTSP bit in SPCR */ 1221 BA1WRITE4(sc, CS4280_SPCR, 0); 1222 /* enable DMA reqest */ 1223 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1224 } 1225 1226 int 1227 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1228 struct cs428x_softc *sc; 1229 char *class, *device, *qualifier; 1230 { 1231 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1232 device, qualifier)); 1233 } 1234 1235 int 1236 cs4280_init(sc, init) 1237 struct cs428x_softc *sc; 1238 int init; 1239 { 1240 int n; 1241 u_int32_t mem; 1242 1243 /* Start PLL out in known state */ 1244 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1245 /* Start serial ports out in known state */ 1246 BA0WRITE4(sc, CS4280_SERMC1, 0); 1247 1248 /* Specify type of CODEC */ 1249 /* XXX should not be here */ 1250 #define SERACC_CODEC_TYPE_1_03 1251 #ifdef SERACC_CODEC_TYPE_1_03 1252 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1253 #else 1254 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1255 #endif 1256 1257 /* Reset codec */ 1258 BA0WRITE4(sc, CS428X_ACCTL, 0); 1259 delay(100); /* delay 100us */ 1260 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1261 1262 /* Enable AC-link sync generation */ 1263 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1264 delay(50*1000); /* delay 50ms */ 1265 1266 /* Set the serial port timing configuration */ 1267 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1268 1269 /* Setup clock control */ 1270 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1271 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1272 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1273 1274 /* Power up the PLL */ 1275 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1276 delay(50*1000); /* delay 50ms */ 1277 1278 /* Turn on clock */ 1279 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1280 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1281 1282 /* Set the serial port FIFO pointer to the 1283 * first sample in FIFO. (not documented) */ 1284 cs4280_clear_fifos(sc); 1285 1286 #if 0 1287 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1288 BA0WRITE4(sc, CS4280_SERBSP, 0); 1289 #endif 1290 1291 /* Configure the serial port */ 1292 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1293 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1294 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1295 1296 /* Wait for CODEC ready */ 1297 n = 0; 1298 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1299 delay(125); 1300 if (++n > 1000) { 1301 printf("%s: codec ready timeout\n", 1302 sc->sc_dev.dv_xname); 1303 return(1); 1304 } 1305 } 1306 1307 /* Assert valid frame signal */ 1308 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1309 1310 /* Wait for valid AC97 input slot */ 1311 n = 0; 1312 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1313 (ACISV_ISV3 | ACISV_ISV4)) { 1314 delay(1000); 1315 if (++n > 1000) { 1316 printf("AC97 inputs slot ready timeout\n"); 1317 return(1); 1318 } 1319 } 1320 1321 /* Set AC97 output slot valid signals */ 1322 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1323 1324 /* reset the processor */ 1325 cs4280_reset(sc); 1326 1327 /* Download the image to the processor */ 1328 if (cs4280_download_image(sc) != 0) { 1329 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1330 return(1); 1331 } 1332 1333 /* Save playback parameter and then write zero. 1334 * this ensures that DMA doesn't immediately occur upon 1335 * starting the processor core 1336 */ 1337 mem = BA1READ4(sc, CS4280_PCTL); 1338 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1339 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1340 if (init != 0) 1341 sc->sc_prun = 0; 1342 1343 /* Save capture parameter and then write zero. 1344 * this ensures that DMA doesn't immediately occur upon 1345 * starting the processor core 1346 */ 1347 mem = BA1READ4(sc, CS4280_CCTL); 1348 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1349 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1350 if (init != 0) 1351 sc->sc_rrun = 0; 1352 1353 /* Processor Startup Procedure */ 1354 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1355 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1356 1357 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1358 n = 0; 1359 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1360 delay(10); 1361 if (++n > 1000) { 1362 printf("SPCR 1->0 transition timeout\n"); 1363 return(1); 1364 } 1365 } 1366 1367 n = 0; 1368 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1369 delay(10); 1370 if (++n > 1000) { 1371 printf("SPCS 0->1 transition timeout\n"); 1372 return(1); 1373 } 1374 } 1375 /* Processor is now running !!! */ 1376 1377 /* Setup volume */ 1378 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1379 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1380 1381 /* Interrupt enable */ 1382 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1383 1384 /* playback interrupt enable */ 1385 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1386 mem |= PFIE_PI_ENABLE; 1387 BA1WRITE4(sc, CS4280_PFIE, mem); 1388 /* capture interrupt enable */ 1389 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1390 mem |= CIE_CI_ENABLE; 1391 BA1WRITE4(sc, CS4280_CIE, mem); 1392 1393 #if NMIDI > 0 1394 /* Reset midi port */ 1395 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1396 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1397 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1398 /* midi interrupt enable */ 1399 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1400 BA0WRITE4(sc, CS4280_MIDCR, mem); 1401 #endif 1402 return(0); 1403 } 1404 1405 void 1406 cs4280_clear_fifos(sc) 1407 struct cs428x_softc *sc; 1408 { 1409 int pd = 0, cnt, n; 1410 u_int32_t mem; 1411 1412 /* 1413 * If device power down, power up the device and keep power down 1414 * state. 1415 */ 1416 mem = BA0READ4(sc, CS4280_CLKCR1); 1417 if (!(mem & CLKCR1_SWCE)) { 1418 printf("cs4280_clear_fifo: power down found.\n"); 1419 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1420 pd = 1; 1421 } 1422 BA0WRITE4(sc, CS4280_SERBWP, 0); 1423 for (cnt = 0; cnt < 256; cnt++) { 1424 n = 0; 1425 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1426 delay(1000); 1427 if (++n > 1000) { 1428 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1429 break; 1430 } 1431 } 1432 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1433 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1434 } 1435 if (pd) 1436 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1437 } 1438 1439 #if NMIDI > 0 1440 int 1441 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1442 void *addr; 1443 int flags; 1444 void (*iintr)__P((void *, int)); 1445 void (*ointr)__P((void *)); 1446 void *arg; 1447 { 1448 struct cs428x_softc *sc = addr; 1449 u_int32_t mem; 1450 1451 DPRINTF(("midi_open\n")); 1452 sc->sc_iintr = iintr; 1453 sc->sc_ointr = ointr; 1454 sc->sc_arg = arg; 1455 1456 /* midi interrupt enable */ 1457 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1458 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1459 BA0WRITE4(sc, CS4280_MIDCR, mem); 1460 #ifdef CS4280_DEBUG 1461 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1462 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1463 return(EINVAL); 1464 } 1465 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1466 #endif 1467 return 0; 1468 } 1469 1470 void 1471 cs4280_midi_close(addr) 1472 void *addr; 1473 { 1474 struct cs428x_softc *sc = addr; 1475 u_int32_t mem; 1476 1477 DPRINTF(("midi_close\n")); 1478 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1479 mem = BA0READ4(sc, CS4280_MIDCR); 1480 mem &= ~MIDCR_MASK; 1481 BA0WRITE4(sc, CS4280_MIDCR, mem); 1482 1483 sc->sc_iintr = 0; 1484 sc->sc_ointr = 0; 1485 } 1486 1487 int 1488 cs4280_midi_output(addr, d) 1489 void *addr; 1490 int d; 1491 { 1492 struct cs428x_softc *sc = addr; 1493 u_int32_t mem; 1494 int x; 1495 1496 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1497 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1498 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1499 mem |= d & MIDWP_MASK; 1500 DPRINTFN(5,("midi_output d=0x%08x",d)); 1501 BA0WRITE4(sc, CS4280_MIDWP, mem); 1502 #ifdef DIAGNOSTIC 1503 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1504 DPRINTF(("Bad write data: %d %d", 1505 mem, BA0READ4(sc, CS4280_MIDWP))); 1506 return(EIO); 1507 } 1508 #endif 1509 return 0; 1510 } 1511 delay(MIDI_BUSY_DELAY); 1512 } 1513 return (EIO); 1514 } 1515 1516 void 1517 cs4280_midi_getinfo(addr, mi) 1518 void *addr; 1519 struct midi_info *mi; 1520 { 1521 mi->name = "CS4280 MIDI UART"; 1522 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1523 } 1524 1525 #endif 1526 1527 /* DEBUG functions */ 1528 #if CS4280_DEBUG > 10 1529 int 1530 cs4280_checkimage(sc, src, offset, len) 1531 struct cs428x_softc *sc; 1532 u_int32_t *src; 1533 u_int32_t offset, len; 1534 { 1535 u_int32_t ctr, data; 1536 int err = 0; 1537 1538 if ((offset&3) || (len&3)) 1539 return -1; 1540 1541 len /= sizeof(u_int32_t); 1542 for (ctr = 0; ctr < len; ctr++) { 1543 /* I cannot confirm this is the right thing 1544 * on BIG-ENDIAN machines 1545 */ 1546 data = BA1READ4(sc, offset+ctr*4); 1547 if (data != htole32(*(src+ctr))) { 1548 printf("0x%06x: 0x%08x(0x%08x)\n", 1549 offset+ctr*4, data, *(src+ctr)); 1550 *(src+ctr) = data; 1551 ++err; 1552 } 1553 } 1554 return err; 1555 } 1556 1557 int 1558 cs4280_check_images(sc) 1559 struct cs428x_softc *sc; 1560 { 1561 int idx, err; 1562 u_int32_t offset = 0; 1563 1564 err = 0; 1565 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 1566 for (idx = 0; idx < 1; ++idx) { 1567 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1568 BA1Struct.memory[idx].offset, 1569 BA1Struct.memory[idx].size); 1570 if (err != 0) { 1571 printf("%s: check_image failed at %d\n", 1572 sc->sc_dev.dv_xname, idx); 1573 } 1574 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1575 } 1576 return err; 1577 } 1578 1579 #endif 1580
Indexes created Thu Oct 02 14:10:14 GMT 2025