cs4280.c revision 1.33
1 /* $NetBSD: cs4280.c,v 1.33 2005/01/10 22:01:37 kent Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.33 2005/01/10 22:01:37 kent Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <machine/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 int cs4280_match(struct device *, struct cfdata *, void *); 93 void cs4280_attach(struct device *, struct device *, void *); 94 int cs4280_intr(void *); 95 int cs4280_query_encoding(void *, struct audio_encoding *); 96 int cs4280_set_params(void *, int, int, audio_params_t *, audio_params_t *, 97 stream_filter_list_t *, stream_filter_list_t *); 98 int cs4280_halt_output(void *); 99 int cs4280_halt_input(void *); 100 int cs4280_getdev(void *, struct audio_device *); 101 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 102 void *, const audio_params_t *); 103 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 104 void *, const audio_params_t *); 105 106 int cs4280_reset_codec(void *); 107 108 /* For PowerHook */ 109 void cs4280_power(int, void *); 110 111 /* Internal functions */ 112 void cs4280_set_adc_rate(struct cs428x_softc *, int ); 113 void cs4280_set_dac_rate(struct cs428x_softc *, int ); 114 int cs4280_download(struct cs428x_softc *, const u_int32_t *, u_int32_t, u_int32_t); 115 int cs4280_download_image(struct cs428x_softc *); 116 void cs4280_reset(void *); 117 int cs4280_get_portnum_by_name(struct cs428x_softc *, char *, char *, char *); 118 int cs4280_init(struct cs428x_softc *, int); 119 void cs4280_clear_fifos(struct cs428x_softc *); 120 121 #if CS4280_DEBUG > 10 122 /* Thease two function is only for checking image loading is succeeded or not. */ 123 int cs4280_check_images(struct cs428x_softc *); 124 int cs4280_checkimage(struct cs428x_softc *, u_int32_t *, u_int32_t, u_int32_t); 125 #endif 126 127 const struct audio_hw_if cs4280_hw_if = { 128 NULL, /* open */ 129 NULL, /* close */ 130 NULL, 131 cs4280_query_encoding, 132 cs4280_set_params, 133 cs428x_round_blocksize, 134 NULL, 135 NULL, 136 NULL, 137 NULL, 138 NULL, 139 cs4280_halt_output, 140 cs4280_halt_input, 141 NULL, 142 cs4280_getdev, 143 NULL, 144 cs428x_mixer_set_port, 145 cs428x_mixer_get_port, 146 cs428x_query_devinfo, 147 cs428x_malloc, 148 cs428x_free, 149 cs428x_round_buffersize, 150 cs428x_mappage, 151 cs428x_get_props, 152 cs4280_trigger_output, 153 cs4280_trigger_input, 154 NULL, 155 }; 156 157 #if NMIDI > 0 158 /* Midi Interface */ 159 int cs4280_midi_open(void *, int, void (*)(void *, int), 160 void (*)(void *), void *); 161 void cs4280_midi_close(void*); 162 int cs4280_midi_output(void *, int); 163 void cs4280_midi_getinfo(void *, struct midi_info *); 164 165 const struct midi_hw_if cs4280_midi_hw_if = { 166 cs4280_midi_open, 167 cs4280_midi_close, 168 cs4280_midi_output, 169 cs4280_midi_getinfo, 170 0, 171 }; 172 #endif 173 174 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 175 cs4280_match, cs4280_attach, NULL, NULL); 176 177 struct audio_device cs4280_device = { 178 "CS4280", 179 "", 180 "cs4280" 181 }; 182 183 184 int 185 cs4280_match(parent, match, aux) 186 struct device *parent; 187 struct cfdata *match; 188 void *aux; 189 { 190 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 191 192 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 193 return 0; 194 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 195 #if 0 /* I can't confirm */ 196 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 197 #endif 198 ) 199 return 1; 200 return 0; 201 } 202 203 void 204 cs4280_attach(parent, self, aux) 205 struct device *parent; 206 struct device *self; 207 void *aux; 208 { 209 struct cs428x_softc *sc = (struct cs428x_softc *)self; 210 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 211 pci_chipset_tag_t pc = pa->pa_pc; 212 char const *intrstr; 213 pci_intr_handle_t ih; 214 pcireg_t reg; 215 char devinfo[256]; 216 u_int32_t mem; 217 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 218 219 aprint_naive(": Audio controller\n"); 220 221 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 222 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 223 PCI_REVISION(pa->pa_class)); 224 225 /* Map I/O register */ 226 if (pci_mapreg_map(pa, PCI_BA0, 227 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 228 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 229 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 230 return; 231 } 232 if (pci_mapreg_map(pa, PCI_BA1, 233 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 234 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 235 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 236 return; 237 } 238 239 sc->sc_dmatag = pa->pa_dmat; 240 241 /* Check and set Power State */ 242 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 243 &pci_pwrmgmt_cap_reg, 0)) { 244 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 245 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 246 pci_pwrmgmt_csr_reg); 247 DPRINTF(("%s: Power State is %d\n", 248 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 249 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 250 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 251 (reg & ~PCI_PMCSR_STATE_MASK) | 252 PCI_PMCSR_STATE_D0); 253 } 254 } 255 256 /* Enable the device (set bus master flag) */ 257 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 258 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 259 reg | PCI_COMMAND_MASTER_ENABLE); 260 261 /* LATENCY_TIMER setting */ 262 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 263 if ( PCI_LATTIMER(mem) < 32 ) { 264 mem &= 0xffff00ff; 265 mem |= 0x00002000; 266 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 267 } 268 269 /* Map and establish the interrupt. */ 270 if (pci_intr_map(pa, &ih)) { 271 aprint_error("%s: couldn't map interrupt\n", 272 sc->sc_dev.dv_xname); 273 return; 274 } 275 intrstr = pci_intr_string(pc, ih); 276 277 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 278 if (sc->sc_ih == NULL) { 279 aprint_error("%s: couldn't establish interrupt", 280 sc->sc_dev.dv_xname); 281 if (intrstr != NULL) 282 aprint_normal(" at %s", intrstr); 283 aprint_normal("\n"); 284 return; 285 } 286 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 287 288 /* Initialization */ 289 if(cs4280_init(sc, 1) != 0) 290 return; 291 292 sc->type = TYPE_CS4280; 293 sc->halt_input = cs4280_halt_input; 294 sc->halt_output = cs4280_halt_output; 295 296 /* setup buffer related parameters */ 297 sc->dma_size = CS4280_DCHUNK; 298 sc->dma_align = CS4280_DALIGN; 299 sc->hw_blocksize = CS4280_ICHUNK; 300 301 /* AC 97 attachment */ 302 sc->host_if.arg = sc; 303 sc->host_if.attach = cs428x_attach_codec; 304 sc->host_if.read = cs428x_read_codec; 305 sc->host_if.write = cs428x_write_codec; 306 sc->host_if.reset = cs4280_reset_codec; 307 if (ac97_attach(&sc->host_if, self) != 0) { 308 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 309 return; 310 } 311 312 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 313 314 #if NMIDI > 0 315 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 316 #endif 317 318 sc->sc_suspend = PWR_RESUME; 319 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 320 } 321 322 /* Interrupt handling function */ 323 int 324 cs4280_intr(p) 325 void *p; 326 { 327 /* 328 * XXX 329 * 330 * Since CS4280 has only 4kB DMA buffer and 331 * interrupt occurs every 2kB block, I create dummy buffer 332 * which returns to audio driver and actual DMA buffer 333 * using in DMA transfer. 334 * 335 * 336 * ring buffer in audio.c is pointed by BUFADDR 337 * <------ ring buffer size == 64kB ------> 338 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 339 * |= = = =|= = = =|= = = =|= = = =|= = = =| 340 * | | | | | | <- call audio_intp every 341 * sc->sc_[pr]_count time. 342 * 343 * actual DMA buffer is pointed by KERNADDR 344 * <-> DMA buffer size = 4kB 345 * |= =| 346 * 347 * 348 */ 349 struct cs428x_softc *sc = p; 350 u_int32_t intr, mem; 351 char * empty_dma; 352 int handled = 0; 353 354 /* grab interrupt register then clear it */ 355 intr = BA0READ4(sc, CS4280_HISR); 356 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 357 358 /* Playback Interrupt */ 359 if (intr & HISR_PINT) { 360 handled = 1; 361 mem = BA1READ4(sc, CS4280_PFIE); 362 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 363 if (sc->sc_prun) { 364 if ((sc->sc_pi%sc->sc_pcount) == 0) 365 sc->sc_pintr(sc->sc_parg); 366 } else { 367 printf("unexpected play intr\n"); 368 } 369 /* copy buffer */ 370 ++sc->sc_pi; 371 empty_dma = sc->sc_pdma->addr; 372 if (sc->sc_pi&1) 373 empty_dma += sc->hw_blocksize; 374 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 375 sc->sc_pn += sc->hw_blocksize; 376 if (sc->sc_pn >= sc->sc_pe) 377 sc->sc_pn = sc->sc_ps; 378 BA1WRITE4(sc, CS4280_PFIE, mem); 379 } 380 /* Capture Interrupt */ 381 if (intr & HISR_CINT) { 382 int i; 383 int16_t rdata; 384 385 handled = 1; 386 mem = BA1READ4(sc, CS4280_CIE); 387 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 388 ++sc->sc_ri; 389 empty_dma = sc->sc_rdma->addr; 390 if ((sc->sc_ri&1) == 0) 391 empty_dma += sc->hw_blocksize; 392 393 /* 394 * XXX 395 * I think this audio data conversion should be 396 * happend in upper layer, but I put this here 397 * since there is no conversion function available. 398 */ 399 switch(sc->sc_rparam) { 400 case CF_16BIT_STEREO: 401 /* just copy it */ 402 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 403 sc->sc_rn += sc->hw_blocksize; 404 break; 405 case CF_16BIT_MONO: 406 for (i = 0; i < 512; i++) { 407 rdata = *((int16_t *)empty_dma)>>1; 408 empty_dma += 2; 409 rdata += *((int16_t *)empty_dma)>>1; 410 empty_dma += 2; 411 *((int16_t *)sc->sc_rn) = rdata; 412 sc->sc_rn += 2; 413 } 414 break; 415 case CF_8BIT_STEREO: 416 for (i = 0; i < 512; i++) { 417 rdata = *((int16_t*)empty_dma); 418 empty_dma += 2; 419 *sc->sc_rn++ = rdata >> 8; 420 rdata = *((int16_t*)empty_dma); 421 empty_dma += 2; 422 *sc->sc_rn++ = rdata >> 8; 423 } 424 break; 425 case CF_8BIT_MONO: 426 for (i = 0; i < 512; i++) { 427 rdata = *((int16_t*)empty_dma) >>1; 428 empty_dma += 2; 429 rdata += *((int16_t*)empty_dma) >>1; 430 empty_dma += 2; 431 *sc->sc_rn++ = rdata >>8; 432 } 433 break; 434 default: 435 /* Should not reach here */ 436 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 437 } 438 if (sc->sc_rn >= sc->sc_re) 439 sc->sc_rn = sc->sc_rs; 440 BA1WRITE4(sc, CS4280_CIE, mem); 441 if (sc->sc_rrun) { 442 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 443 sc->sc_rintr(sc->sc_rarg); 444 } else { 445 printf("unexpected record intr\n"); 446 } 447 } 448 449 #if NMIDI > 0 450 /* Midi port Interrupt */ 451 if (intr & HISR_MIDI) { 452 int data; 453 454 handled = 1; 455 DPRINTF(("i: %d: ", 456 BA0READ4(sc, CS4280_MIDSR))); 457 /* Read the received data */ 458 while ((sc->sc_iintr != NULL) && 459 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 460 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 461 DPRINTF(("r:%x\n",data)); 462 sc->sc_iintr(sc->sc_arg, data); 463 } 464 465 /* Write the data */ 466 #if 1 467 /* XXX: 468 * It seems "Transmit Buffer Full" never activate until EOI 469 * is deliverd. Shall I throw EOI top of this routine ? 470 */ 471 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 472 DPRINTF(("w: ")); 473 if (sc->sc_ointr != NULL) 474 sc->sc_ointr(sc->sc_arg); 475 } 476 #else 477 while ((sc->sc_ointr != NULL) && 478 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 479 DPRINTF(("w: ")); 480 sc->sc_ointr(sc->sc_arg); 481 } 482 #endif 483 DPRINTF(("\n")); 484 } 485 #endif 486 487 return handled; 488 } 489 490 int 491 cs4280_query_encoding(addr, fp) 492 void *addr; 493 struct audio_encoding *fp; 494 { 495 switch (fp->index) { 496 case 0: 497 strcpy(fp->name, AudioEulinear); 498 fp->encoding = AUDIO_ENCODING_ULINEAR; 499 fp->precision = 8; 500 fp->flags = 0; 501 break; 502 case 1: 503 strcpy(fp->name, AudioEmulaw); 504 fp->encoding = AUDIO_ENCODING_ULAW; 505 fp->precision = 8; 506 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 507 break; 508 case 2: 509 strcpy(fp->name, AudioEalaw); 510 fp->encoding = AUDIO_ENCODING_ALAW; 511 fp->precision = 8; 512 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 513 break; 514 case 3: 515 strcpy(fp->name, AudioEslinear); 516 fp->encoding = AUDIO_ENCODING_SLINEAR; 517 fp->precision = 8; 518 fp->flags = 0; 519 break; 520 case 4: 521 strcpy(fp->name, AudioEslinear_le); 522 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 523 fp->precision = 16; 524 fp->flags = 0; 525 break; 526 case 5: 527 strcpy(fp->name, AudioEulinear_le); 528 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 529 fp->precision = 16; 530 fp->flags = 0; 531 break; 532 case 6: 533 strcpy(fp->name, AudioEslinear_be); 534 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 535 fp->precision = 16; 536 fp->flags = 0; 537 break; 538 case 7: 539 strcpy(fp->name, AudioEulinear_be); 540 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 541 fp->precision = 16; 542 fp->flags = 0; 543 break; 544 default: 545 return EINVAL; 546 } 547 return 0; 548 } 549 550 int 551 cs4280_set_params(void *addr, int setmode, int usemode, 552 audio_params_t *play, audio_params_t *rec, 553 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 554 { 555 audio_params_t hw; 556 struct cs428x_softc *sc = addr; 557 struct audio_params *p; 558 stream_filter_list_t *fil; 559 int mode; 560 561 for (mode = AUMODE_RECORD; mode != -1; 562 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 563 if ((setmode & mode) == 0) 564 continue; 565 566 p = mode == AUMODE_PLAY ? play : rec; 567 568 if (p == play) { 569 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 570 p->sample_rate, p->precision, p->channels)); 571 /* play back data format may be 8- or 16-bit and 572 * either stereo or mono. 573 * playback rate may range from 8000Hz to 48000Hz 574 */ 575 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 576 (p->precision != 8 && p->precision != 16) || 577 (p->channels != 1 && p->channels != 2) ) { 578 return EINVAL; 579 } 580 } else { 581 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 582 p->sample_rate, p->precision, p->channels)); 583 /* capture data format must be 16bit stereo 584 * and sample rate range from 11025Hz to 48000Hz. 585 * 586 * XXX: it looks like to work with 8000Hz, 587 * although data sheets say lower limit is 588 * 11025 Hz. 589 */ 590 591 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 592 (p->precision != 8 && p->precision != 16) || 593 (p->channels != 1 && p->channels != 2) ) { 594 return EINVAL; 595 } 596 } 597 fil = mode == AUMODE_PLAY ? pfil : rfil; 598 hw = *p; 599 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 600 601 /* capturing data is slinear */ 602 switch (p->encoding) { 603 case AUDIO_ENCODING_SLINEAR_BE: 604 if (mode == AUMODE_RECORD && p->precision == 16) { 605 fil->append(fil, swap_bytes, &hw); 606 } 607 break; 608 case AUDIO_ENCODING_SLINEAR_LE: 609 break; 610 case AUDIO_ENCODING_ULINEAR_BE: 611 if (mode == AUMODE_RECORD) { 612 fil->append(fil, p->precision == 16 613 ? swap_bytes_change_sign16 614 : change_sign8, &hw); 615 } 616 break; 617 case AUDIO_ENCODING_ULINEAR_LE: 618 if (mode == AUMODE_RECORD) { 619 fil->append(fil, p->precision == 16 620 ? change_sign16 : change_sign8, 621 &hw); 622 } 623 break; 624 case AUDIO_ENCODING_ULAW: 625 if (mode == AUMODE_PLAY) { 626 hw.precision = 16; 627 hw.validbits = 16; 628 fil->append(fil, mulaw_to_linear16, &hw); 629 } else { 630 fil->append(fil, linear8_to_mulaw, &hw); 631 } 632 break; 633 case AUDIO_ENCODING_ALAW: 634 if (mode == AUMODE_PLAY) { 635 hw.precision = 16; 636 hw.validbits = 16; 637 fil->append(fil, alaw_to_linear16, &hw); 638 } else { 639 fil->append(fil, linear8_to_alaw, &hw); 640 } 641 break; 642 default: 643 return EINVAL; 644 } 645 } 646 647 /* set sample rate */ 648 cs4280_set_dac_rate(sc, play->sample_rate); 649 cs4280_set_adc_rate(sc, rec->sample_rate); 650 return 0; 651 } 652 653 int 654 cs4280_halt_output(addr) 655 void *addr; 656 { 657 struct cs428x_softc *sc = addr; 658 u_int32_t mem; 659 660 mem = BA1READ4(sc, CS4280_PCTL); 661 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 662 sc->sc_prun = 0; 663 return 0; 664 } 665 666 int 667 cs4280_halt_input(addr) 668 void *addr; 669 { 670 struct cs428x_softc *sc = addr; 671 u_int32_t mem; 672 673 mem = BA1READ4(sc, CS4280_CCTL); 674 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 675 sc->sc_rrun = 0; 676 return 0; 677 } 678 679 int 680 cs4280_getdev(addr, retp) 681 void *addr; 682 struct audio_device *retp; 683 { 684 *retp = cs4280_device; 685 return 0; 686 } 687 688 int 689 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 690 void *addr; 691 void *start, *end; 692 int blksize; 693 void (*intr) __P((void *)); 694 void *arg; 695 const audio_params_t *param; 696 { 697 struct cs428x_softc *sc = addr; 698 u_int32_t pfie, pctl, pdtc; 699 struct cs428x_dma *p; 700 701 #ifdef DIAGNOSTIC 702 if (sc->sc_prun) 703 printf("cs4280_trigger_output: already running\n"); 704 #endif 705 sc->sc_prun = 1; 706 707 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 708 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 709 sc->sc_pintr = intr; 710 sc->sc_parg = arg; 711 712 /* stop playback DMA */ 713 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 714 715 /* setup PDTC */ 716 pdtc = BA1READ4(sc, CS4280_PDTC); 717 pdtc &= ~PDTC_MASK; 718 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 719 BA1WRITE4(sc, CS4280_PDTC, pdtc); 720 721 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 722 param->precision, param->channels, param->encoding)); 723 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 724 ; 725 if (p == NULL) { 726 printf("cs4280_trigger_output: bad addr %p\n", start); 727 return EINVAL; 728 } 729 if (DMAADDR(p) % sc->dma_align != 0 ) { 730 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 731 "4kB align\n", (ulong)DMAADDR(p)); 732 return EINVAL; 733 } 734 735 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 736 sc->sc_ps = (char *)start; 737 sc->sc_pe = (char *)end; 738 sc->sc_pdma = p; 739 sc->sc_pbuf = KERNADDR(p); 740 sc->sc_pi = 0; 741 sc->sc_pn = sc->sc_ps; 742 if (blksize >= sc->dma_size) { 743 sc->sc_pn = sc->sc_ps + sc->dma_size; 744 memcpy(sc->sc_pbuf, start, sc->dma_size); 745 ++sc->sc_pi; 746 } else { 747 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 748 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 749 } 750 751 /* initiate playback DMA */ 752 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 753 754 /* set PFIE */ 755 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 756 757 if (param->precision == 8) 758 pfie |= PFIE_8BIT; 759 if (param->channels == 1) 760 pfie |= PFIE_MONO; 761 762 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 763 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 764 pfie |= PFIE_SWAPPED; 765 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 766 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 767 pfie |= PFIE_UNSIGNED; 768 769 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 770 771 sc->sc_prate = param->sample_rate; 772 cs4280_set_dac_rate(sc, param->sample_rate); 773 774 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 775 pctl |= sc->pctl; 776 BA1WRITE4(sc, CS4280_PCTL, pctl); 777 return 0; 778 } 779 780 int 781 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 782 void *addr; 783 void *start, *end; 784 int blksize; 785 void (*intr) __P((void *)); 786 void *arg; 787 const audio_params_t *param; 788 { 789 struct cs428x_softc *sc = addr; 790 u_int32_t cctl, cie; 791 struct cs428x_dma *p; 792 793 #ifdef DIAGNOSTIC 794 if (sc->sc_rrun) 795 printf("cs4280_trigger_input: already running\n"); 796 #endif 797 sc->sc_rrun = 1; 798 799 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 800 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 801 sc->sc_rintr = intr; 802 sc->sc_rarg = arg; 803 804 /* stop capture DMA */ 805 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 806 807 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 808 ; 809 if (p == NULL) { 810 printf("cs4280_trigger_input: bad addr %p\n", start); 811 return EINVAL; 812 } 813 if (DMAADDR(p) % sc->dma_align != 0) { 814 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 815 "4kB align\n", (ulong)DMAADDR(p)); 816 return EINVAL; 817 } 818 819 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 820 sc->sc_rs = (char *)start; 821 sc->sc_re = (char *)end; 822 sc->sc_rdma = p; 823 sc->sc_rbuf = KERNADDR(p); 824 sc->sc_ri = 0; 825 sc->sc_rn = sc->sc_rs; 826 827 /* initiate capture DMA */ 828 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 829 830 /* setup format information for internal converter */ 831 sc->sc_rparam = 0; 832 if (param->precision == 8) { 833 sc->sc_rparam += CF_8BIT; 834 sc->sc_rcount <<= 1; 835 } 836 if (param->channels == 1) { 837 sc->sc_rparam += CF_MONO; 838 sc->sc_rcount <<= 1; 839 } 840 841 /* set CIE */ 842 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 843 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 844 845 sc->sc_rrate = param->sample_rate; 846 cs4280_set_adc_rate(sc, param->sample_rate); 847 848 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 849 cctl |= sc->cctl; 850 BA1WRITE4(sc, CS4280_CCTL, cctl); 851 return 0; 852 } 853 854 /* Power Hook */ 855 void 856 cs4280_power(why, v) 857 int why; 858 void *v; 859 { 860 struct cs428x_softc *sc = (struct cs428x_softc *)v; 861 static u_int32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 862 static u_int32_t cctl = 0, cba = 0, cie = 0; 863 864 DPRINTF(("%s: cs4280_power why=%d\n", 865 sc->sc_dev.dv_xname, why)); 866 switch (why) { 867 case PWR_SUSPEND: 868 case PWR_STANDBY: 869 sc->sc_suspend = why; 870 871 /* save current playback status */ 872 if ( sc->sc_prun ) { 873 pctl = BA1READ4(sc, CS4280_PCTL); 874 pfie = BA1READ4(sc, CS4280_PFIE); 875 pba = BA1READ4(sc, CS4280_PBA); 876 pdtc = BA1READ4(sc, CS4280_PDTC); 877 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 878 pctl, pfie, pba, pdtc)); 879 } 880 881 /* save current capture status */ 882 if ( sc->sc_rrun ) { 883 cctl = BA1READ4(sc, CS4280_CCTL); 884 cie = BA1READ4(sc, CS4280_CIE); 885 cba = BA1READ4(sc, CS4280_CBA); 886 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 887 cctl, cie, cba)); 888 } 889 890 /* Stop DMA */ 891 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 892 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 893 break; 894 case PWR_RESUME: 895 if (sc->sc_suspend == PWR_RESUME) { 896 printf("cs4280_power: odd, resume without suspend.\n"); 897 sc->sc_suspend = why; 898 return; 899 } 900 sc->sc_suspend = why; 901 cs4280_init(sc, 0); 902 cs4280_reset_codec(sc); 903 904 /* restore ac97 registers */ 905 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 906 907 /* restore DMA related status */ 908 if(sc->sc_prun) { 909 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 910 pctl, pfie, pba, pdtc)); 911 cs4280_set_dac_rate(sc, sc->sc_prate); 912 BA1WRITE4(sc, CS4280_PDTC, pdtc); 913 BA1WRITE4(sc, CS4280_PBA, pba); 914 BA1WRITE4(sc, CS4280_PFIE, pfie); 915 BA1WRITE4(sc, CS4280_PCTL, pctl); 916 } 917 918 if (sc->sc_rrun) { 919 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 920 cctl, cie, cba)); 921 cs4280_set_adc_rate(sc, sc->sc_rrate); 922 BA1WRITE4(sc, CS4280_CBA, cba); 923 BA1WRITE4(sc, CS4280_CIE, cie); 924 BA1WRITE4(sc, CS4280_CCTL, cctl); 925 } 926 break; 927 case PWR_SOFTSUSPEND: 928 case PWR_SOFTSTANDBY: 929 case PWR_SOFTRESUME: 930 break; 931 } 932 } 933 934 /* control AC97 codec */ 935 int 936 cs4280_reset_codec(void *addr) 937 { 938 struct cs428x_softc *sc; 939 int n; 940 941 sc = addr; 942 943 /* Reset codec */ 944 BA0WRITE4(sc, CS428X_ACCTL, 0); 945 delay(100); /* delay 100us */ 946 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 947 948 /* 949 * It looks like we do the following procedure, too 950 */ 951 952 /* Enable AC-link sync generation */ 953 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 954 delay(50*1000); /* XXX delay 50ms */ 955 956 /* Assert valid frame signal */ 957 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 958 959 /* Wait for valid AC97 input slot */ 960 n = 0; 961 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 962 (ACISV_ISV3 | ACISV_ISV4)) { 963 delay(1000); 964 if (++n > 1000) { 965 printf("reset_codec: AC97 inputs slot ready timeout\n"); 966 return ETIMEDOUT; 967 } 968 } 969 return 0; 970 } 971 972 973 /* Internal functions */ 974 975 void 976 cs4280_set_adc_rate(sc, rate) 977 struct cs428x_softc *sc; 978 int rate; 979 { 980 /* calculate capture rate: 981 * 982 * capture_coefficient_increment = -round(rate*128*65536/48000; 983 * capture_phase_increment = floor(48000*65536*1024/rate); 984 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 985 * cy = floor(cx/200); 986 * capture_sample_rate_correction = cx - 200*cy; 987 * capture_delay = ceil(24*48000/rate); 988 * capture_num_triplets = floor(65536*rate/24000); 989 * capture_group_length = 24000/GCD(rate, 24000); 990 * where GCD means "Greatest Common Divisor". 991 * 992 * capture_coefficient_increment, capture_phase_increment and 993 * capture_num_triplets are 32-bit signed quantities. 994 * capture_sample_rate_correction and capture_group_length are 995 * 16-bit signed quantities. 996 * capture_delay is a 14-bit unsigned quantity. 997 */ 998 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 999 u_int16_t csrc, cgl, cdlay; 1000 1001 /* XXX 1002 * Even though, embedded_audio_spec says capture rate range 11025 to 1003 * 48000, dhwiface.cpp says, 1004 * 1005 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1006 * Return an error if an attempt is made to stray outside that limit." 1007 * 1008 * so assume range as 48000/9 to 48000 1009 */ 1010 1011 if (rate < 8000) 1012 rate = 8000; 1013 if (rate > 48000) 1014 rate = 48000; 1015 1016 cx = rate << 16; 1017 cci = cx / 48000; 1018 cx -= cci * 48000; 1019 cx <<= 7; 1020 cci <<= 7; 1021 cci += cx / 48000; 1022 cci = - cci; 1023 1024 cx = 48000 << 16; 1025 cpi = cx / rate; 1026 cx -= cpi * rate; 1027 cx <<= 10; 1028 cpi <<= 10; 1029 cy = cx / rate; 1030 cpi += cy; 1031 cx -= cy * rate; 1032 1033 cy = cx / 200; 1034 csrc = cx - 200*cy; 1035 1036 cdlay = ((48000 * 24) + rate - 1) / rate; 1037 #if 0 1038 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1039 #endif 1040 1041 cnt = rate << 16; 1042 cnt /= 24000; 1043 1044 cgl = 1; 1045 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1046 if (((rate / tmp1) * tmp1) != rate) 1047 cgl *= 2; 1048 } 1049 if (((rate / 3) * 3) != rate) 1050 cgl *= 3; 1051 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1052 if (((rate / tmp1) * tmp1) != rate) 1053 cgl *= 5; 1054 } 1055 #if 0 1056 /* XXX what manual says */ 1057 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1058 tmp1 |= csrc<<16; 1059 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1060 #else 1061 /* suggested by cs461x.c (ALSA driver) */ 1062 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1063 #endif 1064 1065 #if 0 1066 /* I am confused. The sample rate calculation section says 1067 * cci *is* 32-bit signed quantity but in the parameter description 1068 * section, CCI only assigned 16bit. 1069 * I believe size of the variable. 1070 */ 1071 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1072 tmp1 |= cci<<16; 1073 BA1WRITE4(sc, CS4280_CCI, tmp1); 1074 #else 1075 BA1WRITE4(sc, CS4280_CCI, cci); 1076 #endif 1077 1078 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1079 tmp1 |= cdlay <<18; 1080 BA1WRITE4(sc, CS4280_CD, tmp1); 1081 1082 BA1WRITE4(sc, CS4280_CPI, cpi); 1083 1084 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1085 tmp1 |= cgl; 1086 BA1WRITE4(sc, CS4280_CGL, tmp1); 1087 1088 BA1WRITE4(sc, CS4280_CNT, cnt); 1089 1090 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1091 tmp1 |= cgl; 1092 BA1WRITE4(sc, CS4280_CGC, tmp1); 1093 } 1094 1095 void 1096 cs4280_set_dac_rate(sc, rate) 1097 struct cs428x_softc *sc; 1098 int rate; 1099 { 1100 /* 1101 * playback rate may range from 8000Hz to 48000Hz 1102 * 1103 * play_phase_increment = floor(rate*65536*1024/48000) 1104 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1105 * py=floor(px/200) 1106 * play_sample_rate_correction = px - 200*py 1107 * 1108 * play_phase_increment is a 32bit signed quantity. 1109 * play_sample_rate_correction is a 16bit signed quantity. 1110 */ 1111 int32_t ppi; 1112 int16_t psrc; 1113 u_int32_t px, py; 1114 1115 if (rate < 8000) 1116 rate = 8000; 1117 if (rate > 48000) 1118 rate = 48000; 1119 px = rate << 16; 1120 ppi = px/48000; 1121 px -= ppi*48000; 1122 ppi <<= 10; 1123 px <<= 10; 1124 py = px / 48000; 1125 ppi += py; 1126 px -= py*48000; 1127 py = px/200; 1128 px -= py*200; 1129 psrc = px; 1130 #if 0 1131 /* what manual says */ 1132 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1133 BA1WRITE4(sc, CS4280_PSRC, 1134 ( ((psrc<<16) & PSRC_MASK) | px )); 1135 #else 1136 /* suggested by cs461x.c (ALSA driver) */ 1137 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1138 #endif 1139 BA1WRITE4(sc, CS4280_PPI, ppi); 1140 } 1141 1142 /* Download Proceessor Code and Data image */ 1143 int 1144 cs4280_download(sc, src, offset, len) 1145 struct cs428x_softc *sc; 1146 const u_int32_t *src; 1147 u_int32_t offset, len; 1148 { 1149 u_int32_t ctr; 1150 1151 #if CS4280_DEBUG > 10 1152 u_int32_t con, data; 1153 u_int8_t c0,c1,c2,c3; 1154 #endif 1155 if ((offset&3) || (len&3)) 1156 return -1; 1157 1158 len /= sizeof(u_int32_t); 1159 for (ctr = 0; ctr < len; ctr++) { 1160 /* XXX: 1161 * I cannot confirm this is the right thing or not 1162 * on BIG-ENDIAN machines. 1163 */ 1164 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1165 #if CS4280_DEBUG > 10 1166 data = htole32(*(src+ctr)); 1167 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1168 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1169 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1170 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1171 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 1172 if (data != con ) { 1173 printf("0x%06x: write=0x%08x read=0x%08x\n", 1174 offset+ctr*4, data, con); 1175 return -1; 1176 } 1177 #endif 1178 } 1179 return 0; 1180 } 1181 1182 int 1183 cs4280_download_image(sc) 1184 struct cs428x_softc *sc; 1185 { 1186 int idx, err; 1187 u_int32_t offset = 0; 1188 1189 err = 0; 1190 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1191 err = cs4280_download(sc, &BA1Struct.map[offset], 1192 BA1Struct.memory[idx].offset, 1193 BA1Struct.memory[idx].size); 1194 if (err != 0) { 1195 printf("%s: load_image failed at %d\n", 1196 sc->sc_dev.dv_xname, idx); 1197 return -1; 1198 } 1199 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1200 } 1201 return err; 1202 } 1203 1204 /* Processor Soft Reset */ 1205 void 1206 cs4280_reset(sc_) 1207 void *sc_; 1208 { 1209 struct cs428x_softc *sc = sc_; 1210 1211 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1212 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1213 delay(100); 1214 /* Clear RSTSP bit in SPCR */ 1215 BA1WRITE4(sc, CS4280_SPCR, 0); 1216 /* enable DMA reqest */ 1217 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1218 } 1219 1220 int 1221 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1222 struct cs428x_softc *sc; 1223 char *class, *device, *qualifier; 1224 { 1225 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1226 device, qualifier)); 1227 } 1228 1229 int 1230 cs4280_init(sc, init) 1231 struct cs428x_softc *sc; 1232 int init; 1233 { 1234 int n; 1235 u_int32_t mem; 1236 1237 /* Start PLL out in known state */ 1238 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1239 /* Start serial ports out in known state */ 1240 BA0WRITE4(sc, CS4280_SERMC1, 0); 1241 1242 /* Specify type of CODEC */ 1243 /* XXX should not be here */ 1244 #define SERACC_CODEC_TYPE_1_03 1245 #ifdef SERACC_CODEC_TYPE_1_03 1246 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1247 #else 1248 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1249 #endif 1250 1251 /* Reset codec */ 1252 BA0WRITE4(sc, CS428X_ACCTL, 0); 1253 delay(100); /* delay 100us */ 1254 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1255 1256 /* Enable AC-link sync generation */ 1257 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1258 delay(50*1000); /* delay 50ms */ 1259 1260 /* Set the serial port timing configuration */ 1261 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1262 1263 /* Setup clock control */ 1264 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1265 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1266 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1267 1268 /* Power up the PLL */ 1269 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1270 delay(50*1000); /* delay 50ms */ 1271 1272 /* Turn on clock */ 1273 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1274 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1275 1276 /* Set the serial port FIFO pointer to the 1277 * first sample in FIFO. (not documented) */ 1278 cs4280_clear_fifos(sc); 1279 1280 #if 0 1281 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1282 BA0WRITE4(sc, CS4280_SERBSP, 0); 1283 #endif 1284 1285 /* Configure the serial port */ 1286 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1287 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1288 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1289 1290 /* Wait for CODEC ready */ 1291 n = 0; 1292 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1293 delay(125); 1294 if (++n > 1000) { 1295 printf("%s: codec ready timeout\n", 1296 sc->sc_dev.dv_xname); 1297 return(1); 1298 } 1299 } 1300 1301 /* Assert valid frame signal */ 1302 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1303 1304 /* Wait for valid AC97 input slot */ 1305 n = 0; 1306 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1307 (ACISV_ISV3 | ACISV_ISV4)) { 1308 delay(1000); 1309 if (++n > 1000) { 1310 printf("AC97 inputs slot ready timeout\n"); 1311 return(1); 1312 } 1313 } 1314 1315 /* Set AC97 output slot valid signals */ 1316 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1317 1318 /* reset the processor */ 1319 cs4280_reset(sc); 1320 1321 /* Download the image to the processor */ 1322 if (cs4280_download_image(sc) != 0) { 1323 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1324 return(1); 1325 } 1326 1327 /* Save playback parameter and then write zero. 1328 * this ensures that DMA doesn't immediately occur upon 1329 * starting the processor core 1330 */ 1331 mem = BA1READ4(sc, CS4280_PCTL); 1332 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1333 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1334 if (init != 0) 1335 sc->sc_prun = 0; 1336 1337 /* Save capture parameter and then write zero. 1338 * this ensures that DMA doesn't immediately occur upon 1339 * starting the processor core 1340 */ 1341 mem = BA1READ4(sc, CS4280_CCTL); 1342 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1343 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1344 if (init != 0) 1345 sc->sc_rrun = 0; 1346 1347 /* Processor Startup Procedure */ 1348 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1349 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1350 1351 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1352 n = 0; 1353 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1354 delay(10); 1355 if (++n > 1000) { 1356 printf("SPCR 1->0 transition timeout\n"); 1357 return(1); 1358 } 1359 } 1360 1361 n = 0; 1362 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1363 delay(10); 1364 if (++n > 1000) { 1365 printf("SPCS 0->1 transition timeout\n"); 1366 return(1); 1367 } 1368 } 1369 /* Processor is now running !!! */ 1370 1371 /* Setup volume */ 1372 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1373 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1374 1375 /* Interrupt enable */ 1376 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1377 1378 /* playback interrupt enable */ 1379 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1380 mem |= PFIE_PI_ENABLE; 1381 BA1WRITE4(sc, CS4280_PFIE, mem); 1382 /* capture interrupt enable */ 1383 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1384 mem |= CIE_CI_ENABLE; 1385 BA1WRITE4(sc, CS4280_CIE, mem); 1386 1387 #if NMIDI > 0 1388 /* Reset midi port */ 1389 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1390 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1391 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1392 /* midi interrupt enable */ 1393 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1394 BA0WRITE4(sc, CS4280_MIDCR, mem); 1395 #endif 1396 return(0); 1397 } 1398 1399 void 1400 cs4280_clear_fifos(sc) 1401 struct cs428x_softc *sc; 1402 { 1403 int pd = 0, cnt, n; 1404 u_int32_t mem; 1405 1406 /* 1407 * If device power down, power up the device and keep power down 1408 * state. 1409 */ 1410 mem = BA0READ4(sc, CS4280_CLKCR1); 1411 if (!(mem & CLKCR1_SWCE)) { 1412 printf("cs4280_clear_fifo: power down found.\n"); 1413 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1414 pd = 1; 1415 } 1416 BA0WRITE4(sc, CS4280_SERBWP, 0); 1417 for (cnt = 0; cnt < 256; cnt++) { 1418 n = 0; 1419 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1420 delay(1000); 1421 if (++n > 1000) { 1422 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1423 break; 1424 } 1425 } 1426 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1427 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1428 } 1429 if (pd) 1430 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1431 } 1432 1433 #if NMIDI > 0 1434 int 1435 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1436 void *addr; 1437 int flags; 1438 void (*iintr)__P((void *, int)); 1439 void (*ointr)__P((void *)); 1440 void *arg; 1441 { 1442 struct cs428x_softc *sc = addr; 1443 u_int32_t mem; 1444 1445 DPRINTF(("midi_open\n")); 1446 sc->sc_iintr = iintr; 1447 sc->sc_ointr = ointr; 1448 sc->sc_arg = arg; 1449 1450 /* midi interrupt enable */ 1451 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1452 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1453 BA0WRITE4(sc, CS4280_MIDCR, mem); 1454 #ifdef CS4280_DEBUG 1455 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1456 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1457 return(EINVAL); 1458 } 1459 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1460 #endif 1461 return 0; 1462 } 1463 1464 void 1465 cs4280_midi_close(addr) 1466 void *addr; 1467 { 1468 struct cs428x_softc *sc = addr; 1469 u_int32_t mem; 1470 1471 DPRINTF(("midi_close\n")); 1472 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1473 mem = BA0READ4(sc, CS4280_MIDCR); 1474 mem &= ~MIDCR_MASK; 1475 BA0WRITE4(sc, CS4280_MIDCR, mem); 1476 1477 sc->sc_iintr = 0; 1478 sc->sc_ointr = 0; 1479 } 1480 1481 int 1482 cs4280_midi_output(addr, d) 1483 void *addr; 1484 int d; 1485 { 1486 struct cs428x_softc *sc = addr; 1487 u_int32_t mem; 1488 int x; 1489 1490 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1491 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1492 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1493 mem |= d & MIDWP_MASK; 1494 DPRINTFN(5,("midi_output d=0x%08x",d)); 1495 BA0WRITE4(sc, CS4280_MIDWP, mem); 1496 #ifdef DIAGNOSTIC 1497 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1498 DPRINTF(("Bad write data: %d %d", 1499 mem, BA0READ4(sc, CS4280_MIDWP))); 1500 return(EIO); 1501 } 1502 #endif 1503 return 0; 1504 } 1505 delay(MIDI_BUSY_DELAY); 1506 } 1507 return (EIO); 1508 } 1509 1510 void 1511 cs4280_midi_getinfo(addr, mi) 1512 void *addr; 1513 struct midi_info *mi; 1514 { 1515 mi->name = "CS4280 MIDI UART"; 1516 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1517 } 1518 1519 #endif 1520 1521 /* DEBUG functions */ 1522 #if CS4280_DEBUG > 10 1523 int 1524 cs4280_checkimage(sc, src, offset, len) 1525 struct cs428x_softc *sc; 1526 u_int32_t *src; 1527 u_int32_t offset, len; 1528 { 1529 u_int32_t ctr, data; 1530 int err = 0; 1531 1532 if ((offset&3) || (len&3)) 1533 return -1; 1534 1535 len /= sizeof(u_int32_t); 1536 for (ctr = 0; ctr < len; ctr++) { 1537 /* I cannot confirm this is the right thing 1538 * on BIG-ENDIAN machines 1539 */ 1540 data = BA1READ4(sc, offset+ctr*4); 1541 if (data != htole32(*(src+ctr))) { 1542 printf("0x%06x: 0x%08x(0x%08x)\n", 1543 offset+ctr*4, data, *(src+ctr)); 1544 *(src+ctr) = data; 1545 ++err; 1546 } 1547 } 1548 return err; 1549 } 1550 1551 int 1552 cs4280_check_images(sc) 1553 struct cs428x_softc *sc; 1554 { 1555 int idx, err; 1556 u_int32_t offset = 0; 1557 1558 err = 0; 1559 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 1560 for (idx = 0; idx < 1; ++idx) { 1561 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1562 BA1Struct.memory[idx].offset, 1563 BA1Struct.memory[idx].size); 1564 if (err != 0) { 1565 printf("%s: check_image failed at %d\n", 1566 sc->sc_dev.dv_xname, idx); 1567 } 1568 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 1569 } 1570 return err; 1571 } 1572 1573 #endif 1574
Indexes created Thu Oct 02 14:10:14 GMT 2025