cs4280.c revision 1.38
1 /* $NetBSD: cs4280.c,v 1.38 2006/04/15 21:20:47 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.38 2006/04/15 21:20:47 jmcneill Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <sys/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(struct device *, struct cfdata *, void *); 93 static void cs4280_attach(struct device *, struct device *, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 #if 0 107 static int cs4280_reset_codec(void *); 108 #endif 109 static enum ac97_host_flags cs4280_flags_codec(void *); 110 111 /* For PowerHook */ 112 static void cs4280_power(int, void *); 113 114 /* Internal functions */ 115 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *); 116 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 117 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 118 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 119 uint32_t); 120 static int cs4280_download_image(struct cs428x_softc *); 121 static void cs4280_reset(void *); 122 static int cs4280_init(struct cs428x_softc *, int); 123 static void cs4280_clear_fifos(struct cs428x_softc *); 124 125 #if CS4280_DEBUG > 10 126 /* Thease two function is only for checking image loading is succeeded or not. */ 127 static int cs4280_check_images(struct cs428x_softc *); 128 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 129 uint32_t); 130 #endif 131 132 /* Special cards */ 133 struct cs4280_card_t 134 { 135 pcireg_t id; 136 enum cs428x_flags flags; 137 }; 138 139 #define _card(vend, prod, flags) \ 140 {PCI_ID_CODE(vend, prod), flags} 141 142 static const struct cs4280_card_t cs4280_cards[] = { 143 #if 0 /* untested, from ALSA driver */ 144 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 145 CS428X_FLAG_INVAC97EAMP), 146 #endif 147 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 148 CS428X_FLAG_INVAC97EAMP) 149 }; 150 151 #undef _card 152 153 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 154 155 static const struct audio_hw_if cs4280_hw_if = { 156 NULL, /* open */ 157 NULL, /* close */ 158 NULL, 159 cs4280_query_encoding, 160 cs4280_set_params, 161 cs428x_round_blocksize, 162 NULL, 163 NULL, 164 NULL, 165 NULL, 166 NULL, 167 cs4280_halt_output, 168 cs4280_halt_input, 169 NULL, 170 cs4280_getdev, 171 NULL, 172 cs428x_mixer_set_port, 173 cs428x_mixer_get_port, 174 cs428x_query_devinfo, 175 cs428x_malloc, 176 cs428x_free, 177 cs428x_round_buffersize, 178 cs428x_mappage, 179 cs428x_get_props, 180 cs4280_trigger_output, 181 cs4280_trigger_input, 182 NULL, 183 }; 184 185 #if NMIDI > 0 186 /* Midi Interface */ 187 static int cs4280_midi_open(void *, int, void (*)(void *, int), 188 void (*)(void *), void *); 189 static void cs4280_midi_close(void*); 190 static int cs4280_midi_output(void *, int); 191 static void cs4280_midi_getinfo(void *, struct midi_info *); 192 193 static const struct midi_hw_if cs4280_midi_hw_if = { 194 cs4280_midi_open, 195 cs4280_midi_close, 196 cs4280_midi_output, 197 cs4280_midi_getinfo, 198 0, 199 }; 200 #endif 201 202 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 203 cs4280_match, cs4280_attach, NULL, NULL); 204 205 static struct audio_device cs4280_device = { 206 "CS4280", 207 "", 208 "cs4280" 209 }; 210 211 212 static int 213 cs4280_match(struct device *parent, struct cfdata *match, void *aux) 214 { 215 struct pci_attach_args *pa; 216 217 pa = (struct pci_attach_args *)aux; 218 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 219 return 0; 220 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 221 #if 0 /* I can't confirm */ 222 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 223 #endif 224 ) 225 return 1; 226 return 0; 227 } 228 229 static void 230 cs4280_attach(struct device *parent, struct device *self, void *aux) 231 { 232 struct cs428x_softc *sc; 233 struct pci_attach_args *pa; 234 pci_chipset_tag_t pc; 235 const struct cs4280_card_t *cs_card; 236 char const *intrstr; 237 pci_intr_handle_t ih; 238 pcireg_t reg; 239 char devinfo[256]; 240 uint32_t mem; 241 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 242 243 sc = (struct cs428x_softc *)self; 244 pa = (struct pci_attach_args *)aux; 245 pc = pa->pa_pc; 246 aprint_naive(": Audio controller\n"); 247 248 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 249 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 250 PCI_REVISION(pa->pa_class)); 251 252 cs_card = cs4280_identify_card(pa); 253 if (cs_card != NULL) { 254 aprint_normal("%s: %s %s\n",sc->sc_dev.dv_xname, 255 pci_findvendor(cs_card->id), 256 pci_findproduct(cs_card->id)); 257 sc->sc_flags = cs_card->flags; 258 } else { 259 sc->sc_flags = CS428X_FLAG_NONE; 260 } 261 262 /* Map I/O register */ 263 if (pci_mapreg_map(pa, PCI_BA0, 264 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 265 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 266 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 267 return; 268 } 269 if (pci_mapreg_map(pa, PCI_BA1, 270 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 271 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 272 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 273 return; 274 } 275 276 sc->sc_dmatag = pa->pa_dmat; 277 278 /* Check and set Power State */ 279 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 280 &pci_pwrmgmt_cap_reg, 0)) { 281 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 282 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 283 pci_pwrmgmt_csr_reg); 284 DPRINTF(("%s: Power State is %d\n", 285 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 286 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 287 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 288 (reg & ~PCI_PMCSR_STATE_MASK) | 289 PCI_PMCSR_STATE_D0); 290 } 291 } 292 293 /* Enable the device (set bus master flag) */ 294 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 295 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 296 reg | PCI_COMMAND_MASTER_ENABLE); 297 298 /* LATENCY_TIMER setting */ 299 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 300 if ( PCI_LATTIMER(mem) < 32 ) { 301 mem &= 0xffff00ff; 302 mem |= 0x00002000; 303 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 304 } 305 306 /* Map and establish the interrupt. */ 307 if (pci_intr_map(pa, &ih)) { 308 aprint_error("%s: couldn't map interrupt\n", 309 sc->sc_dev.dv_xname); 310 return; 311 } 312 intrstr = pci_intr_string(pc, ih); 313 314 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 315 if (sc->sc_ih == NULL) { 316 aprint_error("%s: couldn't establish interrupt", 317 sc->sc_dev.dv_xname); 318 if (intrstr != NULL) 319 aprint_normal(" at %s", intrstr); 320 aprint_normal("\n"); 321 return; 322 } 323 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 324 325 /* Initialization */ 326 if(cs4280_init(sc, 1) != 0) 327 return; 328 329 sc->type = TYPE_CS4280; 330 sc->halt_input = cs4280_halt_input; 331 sc->halt_output = cs4280_halt_output; 332 333 /* setup buffer related parameters */ 334 sc->dma_size = CS4280_DCHUNK; 335 sc->dma_align = CS4280_DALIGN; 336 sc->hw_blocksize = CS4280_ICHUNK; 337 338 /* AC 97 attachment */ 339 sc->host_if.arg = sc; 340 sc->host_if.attach = cs428x_attach_codec; 341 sc->host_if.read = cs428x_read_codec; 342 sc->host_if.write = cs428x_write_codec; 343 #if 0 344 sc->host_if.reset = cs4280_reset_codec; 345 #else 346 sc->host_if.reset = NULL; 347 #endif 348 sc->host_if.flags = cs4280_flags_codec; 349 if (ac97_attach(&sc->host_if, self) != 0) { 350 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 351 return; 352 } 353 354 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 355 356 #if NMIDI > 0 357 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 358 #endif 359 360 sc->sc_suspend = PWR_RESUME; 361 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 362 } 363 364 /* Interrupt handling function */ 365 static int 366 cs4280_intr(void *p) 367 { 368 /* 369 * XXX 370 * 371 * Since CS4280 has only 4kB DMA buffer and 372 * interrupt occurs every 2kB block, I create dummy buffer 373 * which returns to audio driver and actual DMA buffer 374 * using in DMA transfer. 375 * 376 * 377 * ring buffer in audio.c is pointed by BUFADDR 378 * <------ ring buffer size == 64kB ------> 379 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 380 * |= = = =|= = = =|= = = =|= = = =|= = = =| 381 * | | | | | | <- call audio_intp every 382 * sc->sc_[pr]_count time. 383 * 384 * actual DMA buffer is pointed by KERNADDR 385 * <-> DMA buffer size = 4kB 386 * |= =| 387 * 388 * 389 */ 390 struct cs428x_softc *sc; 391 uint32_t intr, mem; 392 char * empty_dma; 393 int handled; 394 395 sc = p; 396 handled = 0; 397 /* grab interrupt register then clear it */ 398 intr = BA0READ4(sc, CS4280_HISR); 399 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 400 401 /* not for us ? */ 402 if ((intr & HISR_INTENA) == 0) 403 return 0; 404 405 /* Playback Interrupt */ 406 if (intr & HISR_PINT) { 407 handled = 1; 408 mem = BA1READ4(sc, CS4280_PFIE); 409 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 410 if (sc->sc_prun) { 411 if ((sc->sc_pi%sc->sc_pcount) == 0) 412 sc->sc_pintr(sc->sc_parg); 413 /* copy buffer */ 414 ++sc->sc_pi; 415 empty_dma = sc->sc_pdma->addr; 416 if (sc->sc_pi&1) 417 empty_dma += sc->hw_blocksize; 418 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 419 sc->sc_pn += sc->hw_blocksize; 420 if (sc->sc_pn >= sc->sc_pe) 421 sc->sc_pn = sc->sc_ps; 422 } else { 423 printf("%s: unexpected play intr\n", 424 sc->sc_dev.dv_xname); 425 } 426 BA1WRITE4(sc, CS4280_PFIE, mem); 427 } 428 /* Capture Interrupt */ 429 if (intr & HISR_CINT) { 430 int i; 431 int16_t rdata; 432 433 handled = 1; 434 mem = BA1READ4(sc, CS4280_CIE); 435 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 436 437 if (sc->sc_rrun) { 438 ++sc->sc_ri; 439 empty_dma = sc->sc_rdma->addr; 440 if ((sc->sc_ri&1) == 0) 441 empty_dma += sc->hw_blocksize; 442 443 /* 444 * XXX 445 * I think this audio data conversion should be 446 * happend in upper layer, but I put this here 447 * since there is no conversion function available. 448 */ 449 switch(sc->sc_rparam) { 450 case CF_16BIT_STEREO: 451 /* just copy it */ 452 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 453 sc->sc_rn += sc->hw_blocksize; 454 break; 455 case CF_16BIT_MONO: 456 for (i = 0; i < 512; i++) { 457 rdata = *((int16_t *)empty_dma)>>1; 458 empty_dma += 2; 459 rdata += *((int16_t *)empty_dma)>>1; 460 empty_dma += 2; 461 *((int16_t *)sc->sc_rn) = rdata; 462 sc->sc_rn += 2; 463 } 464 break; 465 case CF_8BIT_STEREO: 466 for (i = 0; i < 512; i++) { 467 rdata = *((int16_t*)empty_dma); 468 empty_dma += 2; 469 *sc->sc_rn++ = rdata >> 8; 470 rdata = *((int16_t*)empty_dma); 471 empty_dma += 2; 472 *sc->sc_rn++ = rdata >> 8; 473 } 474 break; 475 case CF_8BIT_MONO: 476 for (i = 0; i < 512; i++) { 477 rdata = *((int16_t*)empty_dma) >>1; 478 empty_dma += 2; 479 rdata += *((int16_t*)empty_dma) >>1; 480 empty_dma += 2; 481 *sc->sc_rn++ = rdata >>8; 482 } 483 break; 484 default: 485 /* Should not reach here */ 486 printf("%s: unknown sc->sc_rparam: %d\n", 487 sc->sc_dev.dv_xname, sc->sc_rparam); 488 } 489 if (sc->sc_rn >= sc->sc_re) 490 sc->sc_rn = sc->sc_rs; 491 } 492 BA1WRITE4(sc, CS4280_CIE, mem); 493 494 if (sc->sc_rrun) { 495 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 496 sc->sc_rintr(sc->sc_rarg); 497 } else { 498 printf("%s: unexpected record intr\n", 499 sc->sc_dev.dv_xname); 500 } 501 } 502 503 #if NMIDI > 0 504 /* Midi port Interrupt */ 505 if (intr & HISR_MIDI) { 506 int data; 507 508 handled = 1; 509 DPRINTF(("i: %d: ", 510 BA0READ4(sc, CS4280_MIDSR))); 511 /* Read the received data */ 512 while ((sc->sc_iintr != NULL) && 513 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 514 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 515 DPRINTF(("r:%x\n",data)); 516 sc->sc_iintr(sc->sc_arg, data); 517 } 518 519 /* Write the data */ 520 #if 1 521 /* XXX: 522 * It seems "Transmit Buffer Full" never activate until EOI 523 * is deliverd. Shall I throw EOI top of this routine ? 524 */ 525 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 526 DPRINTF(("w: ")); 527 if (sc->sc_ointr != NULL) 528 sc->sc_ointr(sc->sc_arg); 529 } 530 #else 531 while ((sc->sc_ointr != NULL) && 532 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 533 DPRINTF(("w: ")); 534 sc->sc_ointr(sc->sc_arg); 535 } 536 #endif 537 DPRINTF(("\n")); 538 } 539 #endif 540 541 return handled; 542 } 543 544 static int 545 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 546 { 547 switch (fp->index) { 548 case 0: 549 strcpy(fp->name, AudioEulinear); 550 fp->encoding = AUDIO_ENCODING_ULINEAR; 551 fp->precision = 8; 552 fp->flags = 0; 553 break; 554 case 1: 555 strcpy(fp->name, AudioEmulaw); 556 fp->encoding = AUDIO_ENCODING_ULAW; 557 fp->precision = 8; 558 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 559 break; 560 case 2: 561 strcpy(fp->name, AudioEalaw); 562 fp->encoding = AUDIO_ENCODING_ALAW; 563 fp->precision = 8; 564 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 565 break; 566 case 3: 567 strcpy(fp->name, AudioEslinear); 568 fp->encoding = AUDIO_ENCODING_SLINEAR; 569 fp->precision = 8; 570 fp->flags = 0; 571 break; 572 case 4: 573 strcpy(fp->name, AudioEslinear_le); 574 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 575 fp->precision = 16; 576 fp->flags = 0; 577 break; 578 case 5: 579 strcpy(fp->name, AudioEulinear_le); 580 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 581 fp->precision = 16; 582 fp->flags = 0; 583 break; 584 case 6: 585 strcpy(fp->name, AudioEslinear_be); 586 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 587 fp->precision = 16; 588 fp->flags = 0; 589 break; 590 case 7: 591 strcpy(fp->name, AudioEulinear_be); 592 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 593 fp->precision = 16; 594 fp->flags = 0; 595 break; 596 default: 597 return EINVAL; 598 } 599 return 0; 600 } 601 602 static int 603 cs4280_set_params(void *addr, int setmode, int usemode, 604 audio_params_t *play, audio_params_t *rec, 605 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 606 { 607 audio_params_t hw; 608 struct cs428x_softc *sc; 609 struct audio_params *p; 610 stream_filter_list_t *fil; 611 int mode; 612 613 sc = addr; 614 for (mode = AUMODE_RECORD; mode != -1; 615 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 616 if ((setmode & mode) == 0) 617 continue; 618 619 p = mode == AUMODE_PLAY ? play : rec; 620 621 if (p == play) { 622 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 623 p->sample_rate, p->precision, p->channels)); 624 /* play back data format may be 8- or 16-bit and 625 * either stereo or mono. 626 * playback rate may range from 8000Hz to 48000Hz 627 */ 628 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 629 (p->precision != 8 && p->precision != 16) || 630 (p->channels != 1 && p->channels != 2) ) { 631 return EINVAL; 632 } 633 } else { 634 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 635 p->sample_rate, p->precision, p->channels)); 636 /* capture data format must be 16bit stereo 637 * and sample rate range from 11025Hz to 48000Hz. 638 * 639 * XXX: it looks like to work with 8000Hz, 640 * although data sheets say lower limit is 641 * 11025 Hz. 642 */ 643 644 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 645 (p->precision != 8 && p->precision != 16) || 646 (p->channels != 1 && p->channels != 2) ) { 647 return EINVAL; 648 } 649 } 650 fil = mode == AUMODE_PLAY ? pfil : rfil; 651 hw = *p; 652 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 653 654 /* capturing data is slinear */ 655 switch (p->encoding) { 656 case AUDIO_ENCODING_SLINEAR_BE: 657 if (mode == AUMODE_RECORD && p->precision == 16) { 658 fil->append(fil, swap_bytes, &hw); 659 } 660 break; 661 case AUDIO_ENCODING_SLINEAR_LE: 662 break; 663 case AUDIO_ENCODING_ULINEAR_BE: 664 if (mode == AUMODE_RECORD) { 665 fil->append(fil, p->precision == 16 666 ? swap_bytes_change_sign16 667 : change_sign8, &hw); 668 } 669 break; 670 case AUDIO_ENCODING_ULINEAR_LE: 671 if (mode == AUMODE_RECORD) { 672 fil->append(fil, p->precision == 16 673 ? change_sign16 : change_sign8, 674 &hw); 675 } 676 break; 677 case AUDIO_ENCODING_ULAW: 678 if (mode == AUMODE_PLAY) { 679 hw.precision = 16; 680 hw.validbits = 16; 681 fil->append(fil, mulaw_to_linear16, &hw); 682 } else { 683 fil->append(fil, linear8_to_mulaw, &hw); 684 } 685 break; 686 case AUDIO_ENCODING_ALAW: 687 if (mode == AUMODE_PLAY) { 688 hw.precision = 16; 689 hw.validbits = 16; 690 fil->append(fil, alaw_to_linear16, &hw); 691 } else { 692 fil->append(fil, linear8_to_alaw, &hw); 693 } 694 break; 695 default: 696 return EINVAL; 697 } 698 } 699 700 /* set sample rate */ 701 cs4280_set_dac_rate(sc, play->sample_rate); 702 cs4280_set_adc_rate(sc, rec->sample_rate); 703 return 0; 704 } 705 706 static int 707 cs4280_halt_output(void *addr) 708 { 709 struct cs428x_softc *sc; 710 uint32_t mem; 711 712 sc = addr; 713 mem = BA1READ4(sc, CS4280_PCTL); 714 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 715 sc->sc_prun = 0; 716 return 0; 717 } 718 719 static int 720 cs4280_halt_input(void *addr) 721 { 722 struct cs428x_softc *sc; 723 uint32_t mem; 724 725 sc = addr; 726 mem = BA1READ4(sc, CS4280_CCTL); 727 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 728 sc->sc_rrun = 0; 729 return 0; 730 } 731 732 static int 733 cs4280_getdev(void *addr, struct audio_device *retp) 734 { 735 736 *retp = cs4280_device; 737 return 0; 738 } 739 740 static int 741 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 742 void (*intr)(void *), void *arg, 743 const audio_params_t *param) 744 { 745 struct cs428x_softc *sc; 746 uint32_t pfie, pctl, pdtc; 747 struct cs428x_dma *p; 748 749 sc = addr; 750 #ifdef DIAGNOSTIC 751 if (sc->sc_prun) 752 printf("cs4280_trigger_output: already running\n"); 753 #endif 754 sc->sc_prun = 1; 755 756 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 757 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 758 sc->sc_pintr = intr; 759 sc->sc_parg = arg; 760 761 /* stop playback DMA */ 762 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 763 764 /* setup PDTC */ 765 pdtc = BA1READ4(sc, CS4280_PDTC); 766 pdtc &= ~PDTC_MASK; 767 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 768 BA1WRITE4(sc, CS4280_PDTC, pdtc); 769 770 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 771 param->precision, param->channels, param->encoding)); 772 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 773 continue; 774 if (p == NULL) { 775 printf("cs4280_trigger_output: bad addr %p\n", start); 776 return EINVAL; 777 } 778 if (DMAADDR(p) % sc->dma_align != 0 ) { 779 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 780 "4kB align\n", (ulong)DMAADDR(p)); 781 return EINVAL; 782 } 783 784 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 785 sc->sc_ps = (char *)start; 786 sc->sc_pe = (char *)end; 787 sc->sc_pdma = p; 788 sc->sc_pbuf = KERNADDR(p); 789 sc->sc_pi = 0; 790 sc->sc_pn = sc->sc_ps; 791 if (blksize >= sc->dma_size) { 792 sc->sc_pn = sc->sc_ps + sc->dma_size; 793 memcpy(sc->sc_pbuf, start, sc->dma_size); 794 ++sc->sc_pi; 795 } else { 796 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 797 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 798 } 799 800 /* initiate playback DMA */ 801 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 802 803 /* set PFIE */ 804 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 805 806 if (param->precision == 8) 807 pfie |= PFIE_8BIT; 808 if (param->channels == 1) 809 pfie |= PFIE_MONO; 810 811 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 812 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 813 pfie |= PFIE_SWAPPED; 814 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 815 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 816 pfie |= PFIE_UNSIGNED; 817 818 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 819 820 sc->sc_prate = param->sample_rate; 821 cs4280_set_dac_rate(sc, param->sample_rate); 822 823 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 824 pctl |= sc->pctl; 825 BA1WRITE4(sc, CS4280_PCTL, pctl); 826 return 0; 827 } 828 829 static int 830 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 831 void (*intr)(void *), void *arg, 832 const audio_params_t *param) 833 { 834 struct cs428x_softc *sc; 835 uint32_t cctl, cie; 836 struct cs428x_dma *p; 837 838 sc = addr; 839 #ifdef DIAGNOSTIC 840 if (sc->sc_rrun) 841 printf("cs4280_trigger_input: already running\n"); 842 #endif 843 sc->sc_rrun = 1; 844 845 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 846 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 847 sc->sc_rintr = intr; 848 sc->sc_rarg = arg; 849 850 /* stop capture DMA */ 851 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 852 853 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 854 continue; 855 if (p == NULL) { 856 printf("cs4280_trigger_input: bad addr %p\n", start); 857 return EINVAL; 858 } 859 if (DMAADDR(p) % sc->dma_align != 0) { 860 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 861 "4kB align\n", (ulong)DMAADDR(p)); 862 return EINVAL; 863 } 864 865 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 866 sc->sc_rs = (char *)start; 867 sc->sc_re = (char *)end; 868 sc->sc_rdma = p; 869 sc->sc_rbuf = KERNADDR(p); 870 sc->sc_ri = 0; 871 sc->sc_rn = sc->sc_rs; 872 873 /* initiate capture DMA */ 874 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 875 876 /* setup format information for internal converter */ 877 sc->sc_rparam = 0; 878 if (param->precision == 8) { 879 sc->sc_rparam += CF_8BIT; 880 sc->sc_rcount <<= 1; 881 } 882 if (param->channels == 1) { 883 sc->sc_rparam += CF_MONO; 884 sc->sc_rcount <<= 1; 885 } 886 887 /* set CIE */ 888 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 889 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 890 891 sc->sc_rrate = param->sample_rate; 892 cs4280_set_adc_rate(sc, param->sample_rate); 893 894 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 895 cctl |= sc->cctl; 896 BA1WRITE4(sc, CS4280_CCTL, cctl); 897 return 0; 898 } 899 900 /* Power Hook */ 901 static void 902 cs4280_power(int why, void *v) 903 { 904 static uint32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 905 static uint32_t cctl = 0, cba = 0, cie = 0; 906 struct cs428x_softc *sc; 907 908 sc = (struct cs428x_softc *)v; 909 DPRINTF(("%s: cs4280_power why=%d\n", sc->sc_dev.dv_xname, why)); 910 switch (why) { 911 case PWR_SUSPEND: 912 case PWR_STANDBY: 913 sc->sc_suspend = why; 914 915 /* save current playback status */ 916 if (sc->sc_prun) { 917 pctl = BA1READ4(sc, CS4280_PCTL); 918 pfie = BA1READ4(sc, CS4280_PFIE); 919 pba = BA1READ4(sc, CS4280_PBA); 920 pdtc = BA1READ4(sc, CS4280_PDTC); 921 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 922 pctl, pfie, pba, pdtc)); 923 } 924 925 /* save current capture status */ 926 if (sc->sc_rrun) { 927 cctl = BA1READ4(sc, CS4280_CCTL); 928 cie = BA1READ4(sc, CS4280_CIE); 929 cba = BA1READ4(sc, CS4280_CBA); 930 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 931 cctl, cie, cba)); 932 } 933 934 /* Stop DMA */ 935 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 936 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 937 break; 938 case PWR_RESUME: 939 if (sc->sc_suspend == PWR_RESUME) { 940 printf("cs4280_power: odd, resume without suspend.\n"); 941 sc->sc_suspend = why; 942 return; 943 } 944 sc->sc_suspend = why; 945 cs4280_init(sc, 0); 946 #if 0 947 cs4280_reset_codec(sc); 948 #endif 949 /* restore ac97 registers */ 950 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 951 952 /* restore DMA related status */ 953 if(sc->sc_prun) { 954 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 955 pctl, pfie, pba, pdtc)); 956 cs4280_set_dac_rate(sc, sc->sc_prate); 957 BA1WRITE4(sc, CS4280_PDTC, pdtc); 958 BA1WRITE4(sc, CS4280_PBA, pba); 959 BA1WRITE4(sc, CS4280_PFIE, pfie); 960 BA1WRITE4(sc, CS4280_PCTL, pctl); 961 } 962 963 if (sc->sc_rrun) { 964 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 965 cctl, cie, cba)); 966 cs4280_set_adc_rate(sc, sc->sc_rrate); 967 BA1WRITE4(sc, CS4280_CBA, cba); 968 BA1WRITE4(sc, CS4280_CIE, cie); 969 BA1WRITE4(sc, CS4280_CCTL, cctl); 970 } 971 break; 972 case PWR_SOFTSUSPEND: 973 case PWR_SOFTSTANDBY: 974 case PWR_SOFTRESUME: 975 break; 976 } 977 } 978 979 #if 0 /* XXX buggy and not required */ 980 /* control AC97 codec */ 981 static int 982 cs4280_reset_codec(void *addr) 983 { 984 struct cs428x_softc *sc; 985 int n; 986 987 sc = addr; 988 989 /* Reset codec */ 990 BA0WRITE4(sc, CS428X_ACCTL, 0); 991 delay(100); /* delay 100us */ 992 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 993 994 /* 995 * It looks like we do the following procedure, too 996 */ 997 998 /* Enable AC-link sync generation */ 999 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1000 delay(50*1000); /* XXX delay 50ms */ 1001 1002 /* Assert valid frame signal */ 1003 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1004 1005 /* Wait for valid AC97 input slot */ 1006 n = 0; 1007 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1008 (ACISV_ISV3 | ACISV_ISV4)) { 1009 delay(1000); 1010 if (++n > 1000) { 1011 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1012 return ETIMEDOUT; 1013 } 1014 } 1015 1016 return 0; 1017 } 1018 #endif 1019 1020 static enum ac97_host_flags cs4280_flags_codec(void *addr) 1021 { 1022 struct cs428x_softc *sc; 1023 1024 sc = addr; 1025 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1026 return AC97_HOST_INVERTED_EAMP; 1027 1028 return 0; 1029 } 1030 1031 /* Internal functions */ 1032 1033 static const struct cs4280_card_t * 1034 cs4280_identify_card(struct pci_attach_args *pa) 1035 { 1036 pcireg_t idreg; 1037 u_int16_t i; 1038 1039 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1040 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1041 if (idreg == cs4280_cards[i].id) 1042 return &cs4280_cards[i]; 1043 } 1044 1045 return NULL; 1046 } 1047 1048 static void 1049 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1050 { 1051 /* calculate capture rate: 1052 * 1053 * capture_coefficient_increment = -round(rate*128*65536/48000; 1054 * capture_phase_increment = floor(48000*65536*1024/rate); 1055 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1056 * cy = floor(cx/200); 1057 * capture_sample_rate_correction = cx - 200*cy; 1058 * capture_delay = ceil(24*48000/rate); 1059 * capture_num_triplets = floor(65536*rate/24000); 1060 * capture_group_length = 24000/GCD(rate, 24000); 1061 * where GCD means "Greatest Common Divisor". 1062 * 1063 * capture_coefficient_increment, capture_phase_increment and 1064 * capture_num_triplets are 32-bit signed quantities. 1065 * capture_sample_rate_correction and capture_group_length are 1066 * 16-bit signed quantities. 1067 * capture_delay is a 14-bit unsigned quantity. 1068 */ 1069 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1070 uint16_t csrc, cgl, cdlay; 1071 1072 /* XXX 1073 * Even though, embedded_audio_spec says capture rate range 11025 to 1074 * 48000, dhwiface.cpp says, 1075 * 1076 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1077 * Return an error if an attempt is made to stray outside that limit." 1078 * 1079 * so assume range as 48000/9 to 48000 1080 */ 1081 1082 if (rate < 8000) 1083 rate = 8000; 1084 if (rate > 48000) 1085 rate = 48000; 1086 1087 cx = rate << 16; 1088 cci = cx / 48000; 1089 cx -= cci * 48000; 1090 cx <<= 7; 1091 cci <<= 7; 1092 cci += cx / 48000; 1093 cci = - cci; 1094 1095 cx = 48000 << 16; 1096 cpi = cx / rate; 1097 cx -= cpi * rate; 1098 cx <<= 10; 1099 cpi <<= 10; 1100 cy = cx / rate; 1101 cpi += cy; 1102 cx -= cy * rate; 1103 1104 cy = cx / 200; 1105 csrc = cx - 200*cy; 1106 1107 cdlay = ((48000 * 24) + rate - 1) / rate; 1108 #if 0 1109 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1110 #endif 1111 1112 cnt = rate << 16; 1113 cnt /= 24000; 1114 1115 cgl = 1; 1116 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1117 if (((rate / tmp1) * tmp1) != rate) 1118 cgl *= 2; 1119 } 1120 if (((rate / 3) * 3) != rate) 1121 cgl *= 3; 1122 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1123 if (((rate / tmp1) * tmp1) != rate) 1124 cgl *= 5; 1125 } 1126 #if 0 1127 /* XXX what manual says */ 1128 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1129 tmp1 |= csrc<<16; 1130 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1131 #else 1132 /* suggested by cs461x.c (ALSA driver) */ 1133 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1134 #endif 1135 1136 #if 0 1137 /* I am confused. The sample rate calculation section says 1138 * cci *is* 32-bit signed quantity but in the parameter description 1139 * section, CCI only assigned 16bit. 1140 * I believe size of the variable. 1141 */ 1142 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1143 tmp1 |= cci<<16; 1144 BA1WRITE4(sc, CS4280_CCI, tmp1); 1145 #else 1146 BA1WRITE4(sc, CS4280_CCI, cci); 1147 #endif 1148 1149 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1150 tmp1 |= cdlay <<18; 1151 BA1WRITE4(sc, CS4280_CD, tmp1); 1152 1153 BA1WRITE4(sc, CS4280_CPI, cpi); 1154 1155 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1156 tmp1 |= cgl; 1157 BA1WRITE4(sc, CS4280_CGL, tmp1); 1158 1159 BA1WRITE4(sc, CS4280_CNT, cnt); 1160 1161 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1162 tmp1 |= cgl; 1163 BA1WRITE4(sc, CS4280_CGC, tmp1); 1164 } 1165 1166 static void 1167 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1168 { 1169 /* 1170 * playback rate may range from 8000Hz to 48000Hz 1171 * 1172 * play_phase_increment = floor(rate*65536*1024/48000) 1173 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1174 * py=floor(px/200) 1175 * play_sample_rate_correction = px - 200*py 1176 * 1177 * play_phase_increment is a 32bit signed quantity. 1178 * play_sample_rate_correction is a 16bit signed quantity. 1179 */ 1180 int32_t ppi; 1181 int16_t psrc; 1182 uint32_t px, py; 1183 1184 if (rate < 8000) 1185 rate = 8000; 1186 if (rate > 48000) 1187 rate = 48000; 1188 px = rate << 16; 1189 ppi = px/48000; 1190 px -= ppi*48000; 1191 ppi <<= 10; 1192 px <<= 10; 1193 py = px / 48000; 1194 ppi += py; 1195 px -= py*48000; 1196 py = px/200; 1197 px -= py*200; 1198 psrc = px; 1199 #if 0 1200 /* what manual says */ 1201 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1202 BA1WRITE4(sc, CS4280_PSRC, 1203 ( ((psrc<<16) & PSRC_MASK) | px )); 1204 #else 1205 /* suggested by cs461x.c (ALSA driver) */ 1206 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1207 #endif 1208 BA1WRITE4(sc, CS4280_PPI, ppi); 1209 } 1210 1211 /* Download Processor Code and Data image */ 1212 static int 1213 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1214 uint32_t offset, uint32_t len) 1215 { 1216 uint32_t ctr; 1217 #if CS4280_DEBUG > 10 1218 uint32_t con, data; 1219 uint8_t c0, c1, c2, c3; 1220 #endif 1221 if ((offset & 3) || (len & 3)) 1222 return -1; 1223 1224 len /= sizeof(uint32_t); 1225 for (ctr = 0; ctr < len; ctr++) { 1226 /* XXX: 1227 * I cannot confirm this is the right thing or not 1228 * on BIG-ENDIAN machines. 1229 */ 1230 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1231 #if CS4280_DEBUG > 10 1232 data = htole32(*(src+ctr)); 1233 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1234 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1235 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1236 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1237 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1238 if (data != con ) { 1239 printf("0x%06x: write=0x%08x read=0x%08x\n", 1240 offset+ctr*4, data, con); 1241 return -1; 1242 } 1243 #endif 1244 } 1245 return 0; 1246 } 1247 1248 static int 1249 cs4280_download_image(struct cs428x_softc *sc) 1250 { 1251 int idx, err; 1252 uint32_t offset = 0; 1253 1254 err = 0; 1255 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1256 err = cs4280_download(sc, &BA1Struct.map[offset], 1257 BA1Struct.memory[idx].offset, 1258 BA1Struct.memory[idx].size); 1259 if (err != 0) { 1260 printf("%s: load_image failed at %d\n", 1261 sc->sc_dev.dv_xname, idx); 1262 return -1; 1263 } 1264 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1265 } 1266 return err; 1267 } 1268 1269 /* Processor Soft Reset */ 1270 static void 1271 cs4280_reset(void *sc_) 1272 { 1273 struct cs428x_softc *sc; 1274 1275 sc = sc_; 1276 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1277 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1278 delay(100); 1279 /* Clear RSTSP bit in SPCR */ 1280 BA1WRITE4(sc, CS4280_SPCR, 0); 1281 /* enable DMA reqest */ 1282 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1283 } 1284 1285 static int 1286 cs4280_init(struct cs428x_softc *sc, int init) 1287 { 1288 int n; 1289 uint32_t mem; 1290 1291 /* Start PLL out in known state */ 1292 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1293 /* Start serial ports out in known state */ 1294 BA0WRITE4(sc, CS4280_SERMC1, 0); 1295 1296 /* Specify type of CODEC */ 1297 /* XXX should not be here */ 1298 #define SERACC_CODEC_TYPE_1_03 1299 #ifdef SERACC_CODEC_TYPE_1_03 1300 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1301 #else 1302 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1303 #endif 1304 1305 /* Reset codec */ 1306 BA0WRITE4(sc, CS428X_ACCTL, 0); 1307 delay(100); /* delay 100us */ 1308 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1309 1310 /* Enable AC-link sync generation */ 1311 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1312 delay(50*1000); /* delay 50ms */ 1313 1314 /* Set the serial port timing configuration */ 1315 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1316 1317 /* Setup clock control */ 1318 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1319 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1320 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1321 1322 /* Power up the PLL */ 1323 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1324 delay(50*1000); /* delay 50ms */ 1325 1326 /* Turn on clock */ 1327 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1328 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1329 1330 /* Set the serial port FIFO pointer to the 1331 * first sample in FIFO. (not documented) */ 1332 cs4280_clear_fifos(sc); 1333 1334 #if 0 1335 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1336 BA0WRITE4(sc, CS4280_SERBSP, 0); 1337 #endif 1338 1339 /* Configure the serial port */ 1340 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1341 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1342 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1343 1344 /* Wait for CODEC ready */ 1345 n = 0; 1346 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1347 delay(125); 1348 if (++n > 1000) { 1349 printf("%s: codec ready timeout\n", 1350 sc->sc_dev.dv_xname); 1351 return 1; 1352 } 1353 } 1354 1355 /* Assert valid frame signal */ 1356 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1357 1358 /* Wait for valid AC97 input slot */ 1359 n = 0; 1360 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1361 (ACISV_ISV3 | ACISV_ISV4)) { 1362 delay(1000); 1363 if (++n > 1000) { 1364 printf("AC97 inputs slot ready timeout\n"); 1365 return 1; 1366 } 1367 } 1368 1369 /* Set AC97 output slot valid signals */ 1370 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1371 1372 /* reset the processor */ 1373 cs4280_reset(sc); 1374 1375 /* Download the image to the processor */ 1376 if (cs4280_download_image(sc) != 0) { 1377 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1378 return 1; 1379 } 1380 1381 /* Save playback parameter and then write zero. 1382 * this ensures that DMA doesn't immediately occur upon 1383 * starting the processor core 1384 */ 1385 mem = BA1READ4(sc, CS4280_PCTL); 1386 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1387 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1388 if (init != 0) 1389 sc->sc_prun = 0; 1390 1391 /* Save capture parameter and then write zero. 1392 * this ensures that DMA doesn't immediately occur upon 1393 * starting the processor core 1394 */ 1395 mem = BA1READ4(sc, CS4280_CCTL); 1396 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1397 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1398 if (init != 0) 1399 sc->sc_rrun = 0; 1400 1401 /* Processor Startup Procedure */ 1402 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1403 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1404 1405 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1406 n = 0; 1407 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1408 delay(10); 1409 if (++n > 1000) { 1410 printf("SPCR 1->0 transition timeout\n"); 1411 return 1; 1412 } 1413 } 1414 1415 n = 0; 1416 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1417 delay(10); 1418 if (++n > 1000) { 1419 printf("SPCS 0->1 transition timeout\n"); 1420 return 1; 1421 } 1422 } 1423 /* Processor is now running !!! */ 1424 1425 /* Setup volume */ 1426 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1427 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1428 1429 /* Interrupt enable */ 1430 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1431 1432 /* playback interrupt enable */ 1433 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1434 mem |= PFIE_PI_ENABLE; 1435 BA1WRITE4(sc, CS4280_PFIE, mem); 1436 /* capture interrupt enable */ 1437 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1438 mem |= CIE_CI_ENABLE; 1439 BA1WRITE4(sc, CS4280_CIE, mem); 1440 1441 #if NMIDI > 0 1442 /* Reset midi port */ 1443 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1444 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1445 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1446 /* midi interrupt enable */ 1447 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1448 BA0WRITE4(sc, CS4280_MIDCR, mem); 1449 #endif 1450 return 0; 1451 } 1452 1453 static void 1454 cs4280_clear_fifos(struct cs428x_softc *sc) 1455 { 1456 int pd, cnt, n; 1457 uint32_t mem; 1458 1459 pd = 0; 1460 /* 1461 * If device power down, power up the device and keep power down 1462 * state. 1463 */ 1464 mem = BA0READ4(sc, CS4280_CLKCR1); 1465 if (!(mem & CLKCR1_SWCE)) { 1466 printf("cs4280_clear_fifo: power down found.\n"); 1467 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1468 pd = 1; 1469 } 1470 BA0WRITE4(sc, CS4280_SERBWP, 0); 1471 for (cnt = 0; cnt < 256; cnt++) { 1472 n = 0; 1473 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1474 delay(1000); 1475 if (++n > 1000) { 1476 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1477 break; 1478 } 1479 } 1480 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1481 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1482 } 1483 if (pd) 1484 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1485 } 1486 1487 #if NMIDI > 0 1488 static int 1489 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1490 void (*ointr)(void *), void *arg) 1491 { 1492 struct cs428x_softc *sc; 1493 uint32_t mem; 1494 1495 DPRINTF(("midi_open\n")); 1496 sc = addr; 1497 sc->sc_iintr = iintr; 1498 sc->sc_ointr = ointr; 1499 sc->sc_arg = arg; 1500 1501 /* midi interrupt enable */ 1502 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1503 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1504 BA0WRITE4(sc, CS4280_MIDCR, mem); 1505 #ifdef CS4280_DEBUG 1506 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1507 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1508 return(EINVAL); 1509 } 1510 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1511 #endif 1512 return 0; 1513 } 1514 1515 static void 1516 cs4280_midi_close(void *addr) 1517 { 1518 struct cs428x_softc *sc; 1519 uint32_t mem; 1520 1521 DPRINTF(("midi_close\n")); 1522 sc = addr; 1523 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1524 mem = BA0READ4(sc, CS4280_MIDCR); 1525 mem &= ~MIDCR_MASK; 1526 BA0WRITE4(sc, CS4280_MIDCR, mem); 1527 1528 sc->sc_iintr = 0; 1529 sc->sc_ointr = 0; 1530 } 1531 1532 static int 1533 cs4280_midi_output(void *addr, int d) 1534 { 1535 struct cs428x_softc *sc; 1536 uint32_t mem; 1537 int x; 1538 1539 sc = addr; 1540 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1541 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1542 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1543 mem |= d & MIDWP_MASK; 1544 DPRINTFN(5,("midi_output d=0x%08x",d)); 1545 BA0WRITE4(sc, CS4280_MIDWP, mem); 1546 #ifdef DIAGNOSTIC 1547 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1548 DPRINTF(("Bad write data: %d %d", 1549 mem, BA0READ4(sc, CS4280_MIDWP))); 1550 return EIO; 1551 } 1552 #endif 1553 return 0; 1554 } 1555 delay(MIDI_BUSY_DELAY); 1556 } 1557 return EIO; 1558 } 1559 1560 static void 1561 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1562 { 1563 1564 mi->name = "CS4280 MIDI UART"; 1565 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1566 } 1567 1568 #endif /* NMIDI */ 1569 1570 /* DEBUG functions */ 1571 #if CS4280_DEBUG > 10 1572 static int 1573 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1574 uint32_t offset, uint32_t len) 1575 { 1576 uint32_t ctr, data; 1577 int err; 1578 1579 if ((offset & 3) || (len & 3)) 1580 return -1; 1581 1582 err = 0; 1583 len /= sizeof(uint32_t); 1584 for (ctr = 0; ctr < len; ctr++) { 1585 /* I cannot confirm this is the right thing 1586 * on BIG-ENDIAN machines 1587 */ 1588 data = BA1READ4(sc, offset+ctr*4); 1589 if (data != htole32(*(src+ctr))) { 1590 printf("0x%06x: 0x%08x(0x%08x)\n", 1591 offset+ctr*4, data, *(src+ctr)); 1592 *(src+ctr) = data; 1593 ++err; 1594 } 1595 } 1596 return err; 1597 } 1598 1599 static int 1600 cs4280_check_images(struct cs428x_softc *sc) 1601 { 1602 int idx, err; 1603 uint32_t offset; 1604 1605 offset = 0; 1606 err = 0; 1607 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1608 for (idx = 0; idx < 1; ++idx) { 1609 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1610 BA1Struct.memory[idx].offset, 1611 BA1Struct.memory[idx].size); 1612 if (err != 0) { 1613 printf("%s: check_image failed at %d\n", 1614 sc->sc_dev.dv_xname, idx); 1615 } 1616 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1617 } 1618 return err; 1619 } 1620 1621 #endif /* CS4280_DEBUG */ 1622
Indexes created Thu Oct 02 14:10:14 GMT 2025