cs4280.c revision 1.39
1 /* $NetBSD: cs4280.c,v 1.39 2006/06/17 23:34:26 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.39 2006/06/17 23:34:26 christos Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <sys/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(struct device *, struct cfdata *, void *); 93 static void cs4280_attach(struct device *, struct device *, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 #if 0 107 static int cs4280_reset_codec(void *); 108 #endif 109 static enum ac97_host_flags cs4280_flags_codec(void *); 110 111 /* For PowerHook */ 112 static void cs4280_power(int, void *); 113 114 /* Internal functions */ 115 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *); 116 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 117 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 118 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 119 uint32_t); 120 static int cs4280_download_image(struct cs428x_softc *); 121 static void cs4280_reset(void *); 122 static int cs4280_init(struct cs428x_softc *, int); 123 static void cs4280_clear_fifos(struct cs428x_softc *); 124 125 #if CS4280_DEBUG > 10 126 /* Thease two function is only for checking image loading is succeeded or not. */ 127 static int cs4280_check_images(struct cs428x_softc *); 128 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 129 uint32_t); 130 #endif 131 132 /* Special cards */ 133 struct cs4280_card_t 134 { 135 pcireg_t id; 136 enum cs428x_flags flags; 137 }; 138 139 #define _card(vend, prod, flags) \ 140 {PCI_ID_CODE(vend, prod), flags} 141 142 static const struct cs4280_card_t cs4280_cards[] = { 143 #if 0 /* untested, from ALSA driver */ 144 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 145 CS428X_FLAG_INVAC97EAMP), 146 #endif 147 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 148 CS428X_FLAG_INVAC97EAMP) 149 }; 150 151 #undef _card 152 153 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 154 155 static const struct audio_hw_if cs4280_hw_if = { 156 NULL, /* open */ 157 NULL, /* close */ 158 NULL, 159 cs4280_query_encoding, 160 cs4280_set_params, 161 cs428x_round_blocksize, 162 NULL, 163 NULL, 164 NULL, 165 NULL, 166 NULL, 167 cs4280_halt_output, 168 cs4280_halt_input, 169 NULL, 170 cs4280_getdev, 171 NULL, 172 cs428x_mixer_set_port, 173 cs428x_mixer_get_port, 174 cs428x_query_devinfo, 175 cs428x_malloc, 176 cs428x_free, 177 cs428x_round_buffersize, 178 cs428x_mappage, 179 cs428x_get_props, 180 cs4280_trigger_output, 181 cs4280_trigger_input, 182 NULL, 183 }; 184 185 #if NMIDI > 0 186 /* Midi Interface */ 187 static int cs4280_midi_open(void *, int, void (*)(void *, int), 188 void (*)(void *), void *); 189 static void cs4280_midi_close(void*); 190 static int cs4280_midi_output(void *, int); 191 static void cs4280_midi_getinfo(void *, struct midi_info *); 192 193 static const struct midi_hw_if cs4280_midi_hw_if = { 194 cs4280_midi_open, 195 cs4280_midi_close, 196 cs4280_midi_output, 197 cs4280_midi_getinfo, 198 0, 199 }; 200 #endif 201 202 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 203 cs4280_match, cs4280_attach, NULL, NULL); 204 205 static struct audio_device cs4280_device = { 206 "CS4280", 207 "", 208 "cs4280" 209 }; 210 211 212 static int 213 cs4280_match(struct device *parent, struct cfdata *match, void *aux) 214 { 215 struct pci_attach_args *pa; 216 217 pa = (struct pci_attach_args *)aux; 218 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 219 return 0; 220 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 221 #if 0 /* I can't confirm */ 222 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 223 #endif 224 ) 225 return 1; 226 return 0; 227 } 228 229 static void 230 cs4280_attach(struct device *parent, struct device *self, void *aux) 231 { 232 struct cs428x_softc *sc; 233 struct pci_attach_args *pa; 234 pci_chipset_tag_t pc; 235 const struct cs4280_card_t *cs_card; 236 char const *intrstr; 237 pci_intr_handle_t ih; 238 pcireg_t reg; 239 char devinfo[256]; 240 uint32_t mem; 241 int error; 242 243 sc = (struct cs428x_softc *)self; 244 pa = (struct pci_attach_args *)aux; 245 pc = pa->pa_pc; 246 aprint_naive(": Audio controller\n"); 247 248 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 249 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 250 PCI_REVISION(pa->pa_class)); 251 252 cs_card = cs4280_identify_card(pa); 253 if (cs_card != NULL) { 254 aprint_normal("%s: %s %s\n",sc->sc_dev.dv_xname, 255 pci_findvendor(cs_card->id), 256 pci_findproduct(cs_card->id)); 257 sc->sc_flags = cs_card->flags; 258 } else { 259 sc->sc_flags = CS428X_FLAG_NONE; 260 } 261 262 /* Map I/O register */ 263 if (pci_mapreg_map(pa, PCI_BA0, 264 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 265 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 266 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 267 return; 268 } 269 if (pci_mapreg_map(pa, PCI_BA1, 270 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 271 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 272 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 273 return; 274 } 275 276 sc->sc_dmatag = pa->pa_dmat; 277 278 /* power up chip */ 279 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 280 pci_activate_null)) && error != EOPNOTSUPP) { 281 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 282 error); 283 return; 284 } 285 286 /* Enable the device (set bus master flag) */ 287 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 288 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 289 reg | PCI_COMMAND_MASTER_ENABLE); 290 291 /* LATENCY_TIMER setting */ 292 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 293 if ( PCI_LATTIMER(mem) < 32 ) { 294 mem &= 0xffff00ff; 295 mem |= 0x00002000; 296 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 297 } 298 299 /* Map and establish the interrupt. */ 300 if (pci_intr_map(pa, &ih)) { 301 aprint_error("%s: couldn't map interrupt\n", 302 sc->sc_dev.dv_xname); 303 return; 304 } 305 intrstr = pci_intr_string(pc, ih); 306 307 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 308 if (sc->sc_ih == NULL) { 309 aprint_error("%s: couldn't establish interrupt", 310 sc->sc_dev.dv_xname); 311 if (intrstr != NULL) 312 aprint_normal(" at %s", intrstr); 313 aprint_normal("\n"); 314 return; 315 } 316 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 317 318 /* Initialization */ 319 if(cs4280_init(sc, 1) != 0) 320 return; 321 322 sc->type = TYPE_CS4280; 323 sc->halt_input = cs4280_halt_input; 324 sc->halt_output = cs4280_halt_output; 325 326 /* setup buffer related parameters */ 327 sc->dma_size = CS4280_DCHUNK; 328 sc->dma_align = CS4280_DALIGN; 329 sc->hw_blocksize = CS4280_ICHUNK; 330 331 /* AC 97 attachment */ 332 sc->host_if.arg = sc; 333 sc->host_if.attach = cs428x_attach_codec; 334 sc->host_if.read = cs428x_read_codec; 335 sc->host_if.write = cs428x_write_codec; 336 #if 0 337 sc->host_if.reset = cs4280_reset_codec; 338 #else 339 sc->host_if.reset = NULL; 340 #endif 341 sc->host_if.flags = cs4280_flags_codec; 342 if (ac97_attach(&sc->host_if, self) != 0) { 343 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 344 return; 345 } 346 347 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 348 349 #if NMIDI > 0 350 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 351 #endif 352 353 sc->sc_suspend = PWR_RESUME; 354 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 355 } 356 357 /* Interrupt handling function */ 358 static int 359 cs4280_intr(void *p) 360 { 361 /* 362 * XXX 363 * 364 * Since CS4280 has only 4kB DMA buffer and 365 * interrupt occurs every 2kB block, I create dummy buffer 366 * which returns to audio driver and actual DMA buffer 367 * using in DMA transfer. 368 * 369 * 370 * ring buffer in audio.c is pointed by BUFADDR 371 * <------ ring buffer size == 64kB ------> 372 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 373 * |= = = =|= = = =|= = = =|= = = =|= = = =| 374 * | | | | | | <- call audio_intp every 375 * sc->sc_[pr]_count time. 376 * 377 * actual DMA buffer is pointed by KERNADDR 378 * <-> DMA buffer size = 4kB 379 * |= =| 380 * 381 * 382 */ 383 struct cs428x_softc *sc; 384 uint32_t intr, mem; 385 char * empty_dma; 386 int handled; 387 388 sc = p; 389 handled = 0; 390 /* grab interrupt register then clear it */ 391 intr = BA0READ4(sc, CS4280_HISR); 392 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 393 394 /* not for us ? */ 395 if ((intr & HISR_INTENA) == 0) 396 return 0; 397 398 /* Playback Interrupt */ 399 if (intr & HISR_PINT) { 400 handled = 1; 401 mem = BA1READ4(sc, CS4280_PFIE); 402 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 403 if (sc->sc_prun) { 404 if ((sc->sc_pi%sc->sc_pcount) == 0) 405 sc->sc_pintr(sc->sc_parg); 406 /* copy buffer */ 407 ++sc->sc_pi; 408 empty_dma = sc->sc_pdma->addr; 409 if (sc->sc_pi&1) 410 empty_dma += sc->hw_blocksize; 411 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 412 sc->sc_pn += sc->hw_blocksize; 413 if (sc->sc_pn >= sc->sc_pe) 414 sc->sc_pn = sc->sc_ps; 415 } else { 416 printf("%s: unexpected play intr\n", 417 sc->sc_dev.dv_xname); 418 } 419 BA1WRITE4(sc, CS4280_PFIE, mem); 420 } 421 /* Capture Interrupt */ 422 if (intr & HISR_CINT) { 423 int i; 424 int16_t rdata; 425 426 handled = 1; 427 mem = BA1READ4(sc, CS4280_CIE); 428 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 429 430 if (sc->sc_rrun) { 431 ++sc->sc_ri; 432 empty_dma = sc->sc_rdma->addr; 433 if ((sc->sc_ri&1) == 0) 434 empty_dma += sc->hw_blocksize; 435 436 /* 437 * XXX 438 * I think this audio data conversion should be 439 * happend in upper layer, but I put this here 440 * since there is no conversion function available. 441 */ 442 switch(sc->sc_rparam) { 443 case CF_16BIT_STEREO: 444 /* just copy it */ 445 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 446 sc->sc_rn += sc->hw_blocksize; 447 break; 448 case CF_16BIT_MONO: 449 for (i = 0; i < 512; i++) { 450 rdata = *((int16_t *)empty_dma)>>1; 451 empty_dma += 2; 452 rdata += *((int16_t *)empty_dma)>>1; 453 empty_dma += 2; 454 *((int16_t *)sc->sc_rn) = rdata; 455 sc->sc_rn += 2; 456 } 457 break; 458 case CF_8BIT_STEREO: 459 for (i = 0; i < 512; i++) { 460 rdata = *((int16_t*)empty_dma); 461 empty_dma += 2; 462 *sc->sc_rn++ = rdata >> 8; 463 rdata = *((int16_t*)empty_dma); 464 empty_dma += 2; 465 *sc->sc_rn++ = rdata >> 8; 466 } 467 break; 468 case CF_8BIT_MONO: 469 for (i = 0; i < 512; i++) { 470 rdata = *((int16_t*)empty_dma) >>1; 471 empty_dma += 2; 472 rdata += *((int16_t*)empty_dma) >>1; 473 empty_dma += 2; 474 *sc->sc_rn++ = rdata >>8; 475 } 476 break; 477 default: 478 /* Should not reach here */ 479 printf("%s: unknown sc->sc_rparam: %d\n", 480 sc->sc_dev.dv_xname, sc->sc_rparam); 481 } 482 if (sc->sc_rn >= sc->sc_re) 483 sc->sc_rn = sc->sc_rs; 484 } 485 BA1WRITE4(sc, CS4280_CIE, mem); 486 487 if (sc->sc_rrun) { 488 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 489 sc->sc_rintr(sc->sc_rarg); 490 } else { 491 printf("%s: unexpected record intr\n", 492 sc->sc_dev.dv_xname); 493 } 494 } 495 496 #if NMIDI > 0 497 /* Midi port Interrupt */ 498 if (intr & HISR_MIDI) { 499 int data; 500 501 handled = 1; 502 DPRINTF(("i: %d: ", 503 BA0READ4(sc, CS4280_MIDSR))); 504 /* Read the received data */ 505 while ((sc->sc_iintr != NULL) && 506 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 507 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 508 DPRINTF(("r:%x\n",data)); 509 sc->sc_iintr(sc->sc_arg, data); 510 } 511 512 /* Write the data */ 513 #if 1 514 /* XXX: 515 * It seems "Transmit Buffer Full" never activate until EOI 516 * is deliverd. Shall I throw EOI top of this routine ? 517 */ 518 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 519 DPRINTF(("w: ")); 520 if (sc->sc_ointr != NULL) 521 sc->sc_ointr(sc->sc_arg); 522 } 523 #else 524 while ((sc->sc_ointr != NULL) && 525 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 526 DPRINTF(("w: ")); 527 sc->sc_ointr(sc->sc_arg); 528 } 529 #endif 530 DPRINTF(("\n")); 531 } 532 #endif 533 534 return handled; 535 } 536 537 static int 538 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 539 { 540 switch (fp->index) { 541 case 0: 542 strcpy(fp->name, AudioEulinear); 543 fp->encoding = AUDIO_ENCODING_ULINEAR; 544 fp->precision = 8; 545 fp->flags = 0; 546 break; 547 case 1: 548 strcpy(fp->name, AudioEmulaw); 549 fp->encoding = AUDIO_ENCODING_ULAW; 550 fp->precision = 8; 551 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 552 break; 553 case 2: 554 strcpy(fp->name, AudioEalaw); 555 fp->encoding = AUDIO_ENCODING_ALAW; 556 fp->precision = 8; 557 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 558 break; 559 case 3: 560 strcpy(fp->name, AudioEslinear); 561 fp->encoding = AUDIO_ENCODING_SLINEAR; 562 fp->precision = 8; 563 fp->flags = 0; 564 break; 565 case 4: 566 strcpy(fp->name, AudioEslinear_le); 567 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 568 fp->precision = 16; 569 fp->flags = 0; 570 break; 571 case 5: 572 strcpy(fp->name, AudioEulinear_le); 573 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 574 fp->precision = 16; 575 fp->flags = 0; 576 break; 577 case 6: 578 strcpy(fp->name, AudioEslinear_be); 579 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 580 fp->precision = 16; 581 fp->flags = 0; 582 break; 583 case 7: 584 strcpy(fp->name, AudioEulinear_be); 585 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 586 fp->precision = 16; 587 fp->flags = 0; 588 break; 589 default: 590 return EINVAL; 591 } 592 return 0; 593 } 594 595 static int 596 cs4280_set_params(void *addr, int setmode, int usemode, 597 audio_params_t *play, audio_params_t *rec, 598 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 599 { 600 audio_params_t hw; 601 struct cs428x_softc *sc; 602 struct audio_params *p; 603 stream_filter_list_t *fil; 604 int mode; 605 606 sc = addr; 607 for (mode = AUMODE_RECORD; mode != -1; 608 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 609 if ((setmode & mode) == 0) 610 continue; 611 612 p = mode == AUMODE_PLAY ? play : rec; 613 614 if (p == play) { 615 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 616 p->sample_rate, p->precision, p->channels)); 617 /* play back data format may be 8- or 16-bit and 618 * either stereo or mono. 619 * playback rate may range from 8000Hz to 48000Hz 620 */ 621 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 622 (p->precision != 8 && p->precision != 16) || 623 (p->channels != 1 && p->channels != 2) ) { 624 return EINVAL; 625 } 626 } else { 627 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 628 p->sample_rate, p->precision, p->channels)); 629 /* capture data format must be 16bit stereo 630 * and sample rate range from 11025Hz to 48000Hz. 631 * 632 * XXX: it looks like to work with 8000Hz, 633 * although data sheets say lower limit is 634 * 11025 Hz. 635 */ 636 637 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 638 (p->precision != 8 && p->precision != 16) || 639 (p->channels != 1 && p->channels != 2) ) { 640 return EINVAL; 641 } 642 } 643 fil = mode == AUMODE_PLAY ? pfil : rfil; 644 hw = *p; 645 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 646 647 /* capturing data is slinear */ 648 switch (p->encoding) { 649 case AUDIO_ENCODING_SLINEAR_BE: 650 if (mode == AUMODE_RECORD && p->precision == 16) { 651 fil->append(fil, swap_bytes, &hw); 652 } 653 break; 654 case AUDIO_ENCODING_SLINEAR_LE: 655 break; 656 case AUDIO_ENCODING_ULINEAR_BE: 657 if (mode == AUMODE_RECORD) { 658 fil->append(fil, p->precision == 16 659 ? swap_bytes_change_sign16 660 : change_sign8, &hw); 661 } 662 break; 663 case AUDIO_ENCODING_ULINEAR_LE: 664 if (mode == AUMODE_RECORD) { 665 fil->append(fil, p->precision == 16 666 ? change_sign16 : change_sign8, 667 &hw); 668 } 669 break; 670 case AUDIO_ENCODING_ULAW: 671 if (mode == AUMODE_PLAY) { 672 hw.precision = 16; 673 hw.validbits = 16; 674 fil->append(fil, mulaw_to_linear16, &hw); 675 } else { 676 fil->append(fil, linear8_to_mulaw, &hw); 677 } 678 break; 679 case AUDIO_ENCODING_ALAW: 680 if (mode == AUMODE_PLAY) { 681 hw.precision = 16; 682 hw.validbits = 16; 683 fil->append(fil, alaw_to_linear16, &hw); 684 } else { 685 fil->append(fil, linear8_to_alaw, &hw); 686 } 687 break; 688 default: 689 return EINVAL; 690 } 691 } 692 693 /* set sample rate */ 694 cs4280_set_dac_rate(sc, play->sample_rate); 695 cs4280_set_adc_rate(sc, rec->sample_rate); 696 return 0; 697 } 698 699 static int 700 cs4280_halt_output(void *addr) 701 { 702 struct cs428x_softc *sc; 703 uint32_t mem; 704 705 sc = addr; 706 mem = BA1READ4(sc, CS4280_PCTL); 707 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 708 sc->sc_prun = 0; 709 return 0; 710 } 711 712 static int 713 cs4280_halt_input(void *addr) 714 { 715 struct cs428x_softc *sc; 716 uint32_t mem; 717 718 sc = addr; 719 mem = BA1READ4(sc, CS4280_CCTL); 720 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 721 sc->sc_rrun = 0; 722 return 0; 723 } 724 725 static int 726 cs4280_getdev(void *addr, struct audio_device *retp) 727 { 728 729 *retp = cs4280_device; 730 return 0; 731 } 732 733 static int 734 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 735 void (*intr)(void *), void *arg, 736 const audio_params_t *param) 737 { 738 struct cs428x_softc *sc; 739 uint32_t pfie, pctl, pdtc; 740 struct cs428x_dma *p; 741 742 sc = addr; 743 #ifdef DIAGNOSTIC 744 if (sc->sc_prun) 745 printf("cs4280_trigger_output: already running\n"); 746 #endif 747 sc->sc_prun = 1; 748 749 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 750 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 751 sc->sc_pintr = intr; 752 sc->sc_parg = arg; 753 754 /* stop playback DMA */ 755 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 756 757 /* setup PDTC */ 758 pdtc = BA1READ4(sc, CS4280_PDTC); 759 pdtc &= ~PDTC_MASK; 760 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 761 BA1WRITE4(sc, CS4280_PDTC, pdtc); 762 763 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 764 param->precision, param->channels, param->encoding)); 765 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 766 continue; 767 if (p == NULL) { 768 printf("cs4280_trigger_output: bad addr %p\n", start); 769 return EINVAL; 770 } 771 if (DMAADDR(p) % sc->dma_align != 0 ) { 772 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 773 "4kB align\n", (ulong)DMAADDR(p)); 774 return EINVAL; 775 } 776 777 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 778 sc->sc_ps = (char *)start; 779 sc->sc_pe = (char *)end; 780 sc->sc_pdma = p; 781 sc->sc_pbuf = KERNADDR(p); 782 sc->sc_pi = 0; 783 sc->sc_pn = sc->sc_ps; 784 if (blksize >= sc->dma_size) { 785 sc->sc_pn = sc->sc_ps + sc->dma_size; 786 memcpy(sc->sc_pbuf, start, sc->dma_size); 787 ++sc->sc_pi; 788 } else { 789 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 790 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 791 } 792 793 /* initiate playback DMA */ 794 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 795 796 /* set PFIE */ 797 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 798 799 if (param->precision == 8) 800 pfie |= PFIE_8BIT; 801 if (param->channels == 1) 802 pfie |= PFIE_MONO; 803 804 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 805 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 806 pfie |= PFIE_SWAPPED; 807 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 808 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 809 pfie |= PFIE_UNSIGNED; 810 811 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 812 813 sc->sc_prate = param->sample_rate; 814 cs4280_set_dac_rate(sc, param->sample_rate); 815 816 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 817 pctl |= sc->pctl; 818 BA1WRITE4(sc, CS4280_PCTL, pctl); 819 return 0; 820 } 821 822 static int 823 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 824 void (*intr)(void *), void *arg, 825 const audio_params_t *param) 826 { 827 struct cs428x_softc *sc; 828 uint32_t cctl, cie; 829 struct cs428x_dma *p; 830 831 sc = addr; 832 #ifdef DIAGNOSTIC 833 if (sc->sc_rrun) 834 printf("cs4280_trigger_input: already running\n"); 835 #endif 836 sc->sc_rrun = 1; 837 838 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 839 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 840 sc->sc_rintr = intr; 841 sc->sc_rarg = arg; 842 843 /* stop capture DMA */ 844 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 845 846 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 847 continue; 848 if (p == NULL) { 849 printf("cs4280_trigger_input: bad addr %p\n", start); 850 return EINVAL; 851 } 852 if (DMAADDR(p) % sc->dma_align != 0) { 853 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 854 "4kB align\n", (ulong)DMAADDR(p)); 855 return EINVAL; 856 } 857 858 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 859 sc->sc_rs = (char *)start; 860 sc->sc_re = (char *)end; 861 sc->sc_rdma = p; 862 sc->sc_rbuf = KERNADDR(p); 863 sc->sc_ri = 0; 864 sc->sc_rn = sc->sc_rs; 865 866 /* initiate capture DMA */ 867 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 868 869 /* setup format information for internal converter */ 870 sc->sc_rparam = 0; 871 if (param->precision == 8) { 872 sc->sc_rparam += CF_8BIT; 873 sc->sc_rcount <<= 1; 874 } 875 if (param->channels == 1) { 876 sc->sc_rparam += CF_MONO; 877 sc->sc_rcount <<= 1; 878 } 879 880 /* set CIE */ 881 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 882 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 883 884 sc->sc_rrate = param->sample_rate; 885 cs4280_set_adc_rate(sc, param->sample_rate); 886 887 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 888 cctl |= sc->cctl; 889 BA1WRITE4(sc, CS4280_CCTL, cctl); 890 return 0; 891 } 892 893 /* Power Hook */ 894 static void 895 cs4280_power(int why, void *v) 896 { 897 static uint32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 898 static uint32_t cctl = 0, cba = 0, cie = 0; 899 struct cs428x_softc *sc; 900 901 sc = (struct cs428x_softc *)v; 902 DPRINTF(("%s: cs4280_power why=%d\n", sc->sc_dev.dv_xname, why)); 903 switch (why) { 904 case PWR_SUSPEND: 905 case PWR_STANDBY: 906 sc->sc_suspend = why; 907 908 /* save current playback status */ 909 if (sc->sc_prun) { 910 pctl = BA1READ4(sc, CS4280_PCTL); 911 pfie = BA1READ4(sc, CS4280_PFIE); 912 pba = BA1READ4(sc, CS4280_PBA); 913 pdtc = BA1READ4(sc, CS4280_PDTC); 914 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 915 pctl, pfie, pba, pdtc)); 916 } 917 918 /* save current capture status */ 919 if (sc->sc_rrun) { 920 cctl = BA1READ4(sc, CS4280_CCTL); 921 cie = BA1READ4(sc, CS4280_CIE); 922 cba = BA1READ4(sc, CS4280_CBA); 923 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 924 cctl, cie, cba)); 925 } 926 927 /* Stop DMA */ 928 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 929 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 930 break; 931 case PWR_RESUME: 932 if (sc->sc_suspend == PWR_RESUME) { 933 printf("cs4280_power: odd, resume without suspend.\n"); 934 sc->sc_suspend = why; 935 return; 936 } 937 sc->sc_suspend = why; 938 cs4280_init(sc, 0); 939 #if 0 940 cs4280_reset_codec(sc); 941 #endif 942 /* restore ac97 registers */ 943 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 944 945 /* restore DMA related status */ 946 if(sc->sc_prun) { 947 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 948 pctl, pfie, pba, pdtc)); 949 cs4280_set_dac_rate(sc, sc->sc_prate); 950 BA1WRITE4(sc, CS4280_PDTC, pdtc); 951 BA1WRITE4(sc, CS4280_PBA, pba); 952 BA1WRITE4(sc, CS4280_PFIE, pfie); 953 BA1WRITE4(sc, CS4280_PCTL, pctl); 954 } 955 956 if (sc->sc_rrun) { 957 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 958 cctl, cie, cba)); 959 cs4280_set_adc_rate(sc, sc->sc_rrate); 960 BA1WRITE4(sc, CS4280_CBA, cba); 961 BA1WRITE4(sc, CS4280_CIE, cie); 962 BA1WRITE4(sc, CS4280_CCTL, cctl); 963 } 964 break; 965 case PWR_SOFTSUSPEND: 966 case PWR_SOFTSTANDBY: 967 case PWR_SOFTRESUME: 968 break; 969 } 970 } 971 972 #if 0 /* XXX buggy and not required */ 973 /* control AC97 codec */ 974 static int 975 cs4280_reset_codec(void *addr) 976 { 977 struct cs428x_softc *sc; 978 int n; 979 980 sc = addr; 981 982 /* Reset codec */ 983 BA0WRITE4(sc, CS428X_ACCTL, 0); 984 delay(100); /* delay 100us */ 985 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 986 987 /* 988 * It looks like we do the following procedure, too 989 */ 990 991 /* Enable AC-link sync generation */ 992 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 993 delay(50*1000); /* XXX delay 50ms */ 994 995 /* Assert valid frame signal */ 996 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 997 998 /* Wait for valid AC97 input slot */ 999 n = 0; 1000 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1001 (ACISV_ISV3 | ACISV_ISV4)) { 1002 delay(1000); 1003 if (++n > 1000) { 1004 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1005 return ETIMEDOUT; 1006 } 1007 } 1008 1009 return 0; 1010 } 1011 #endif 1012 1013 static enum ac97_host_flags cs4280_flags_codec(void *addr) 1014 { 1015 struct cs428x_softc *sc; 1016 1017 sc = addr; 1018 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1019 return AC97_HOST_INVERTED_EAMP; 1020 1021 return 0; 1022 } 1023 1024 /* Internal functions */ 1025 1026 static const struct cs4280_card_t * 1027 cs4280_identify_card(struct pci_attach_args *pa) 1028 { 1029 pcireg_t idreg; 1030 u_int16_t i; 1031 1032 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1033 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1034 if (idreg == cs4280_cards[i].id) 1035 return &cs4280_cards[i]; 1036 } 1037 1038 return NULL; 1039 } 1040 1041 static void 1042 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1043 { 1044 /* calculate capture rate: 1045 * 1046 * capture_coefficient_increment = -round(rate*128*65536/48000; 1047 * capture_phase_increment = floor(48000*65536*1024/rate); 1048 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1049 * cy = floor(cx/200); 1050 * capture_sample_rate_correction = cx - 200*cy; 1051 * capture_delay = ceil(24*48000/rate); 1052 * capture_num_triplets = floor(65536*rate/24000); 1053 * capture_group_length = 24000/GCD(rate, 24000); 1054 * where GCD means "Greatest Common Divisor". 1055 * 1056 * capture_coefficient_increment, capture_phase_increment and 1057 * capture_num_triplets are 32-bit signed quantities. 1058 * capture_sample_rate_correction and capture_group_length are 1059 * 16-bit signed quantities. 1060 * capture_delay is a 14-bit unsigned quantity. 1061 */ 1062 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1063 uint16_t csrc, cgl, cdlay; 1064 1065 /* XXX 1066 * Even though, embedded_audio_spec says capture rate range 11025 to 1067 * 48000, dhwiface.cpp says, 1068 * 1069 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1070 * Return an error if an attempt is made to stray outside that limit." 1071 * 1072 * so assume range as 48000/9 to 48000 1073 */ 1074 1075 if (rate < 8000) 1076 rate = 8000; 1077 if (rate > 48000) 1078 rate = 48000; 1079 1080 cx = rate << 16; 1081 cci = cx / 48000; 1082 cx -= cci * 48000; 1083 cx <<= 7; 1084 cci <<= 7; 1085 cci += cx / 48000; 1086 cci = - cci; 1087 1088 cx = 48000 << 16; 1089 cpi = cx / rate; 1090 cx -= cpi * rate; 1091 cx <<= 10; 1092 cpi <<= 10; 1093 cy = cx / rate; 1094 cpi += cy; 1095 cx -= cy * rate; 1096 1097 cy = cx / 200; 1098 csrc = cx - 200*cy; 1099 1100 cdlay = ((48000 * 24) + rate - 1) / rate; 1101 #if 0 1102 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1103 #endif 1104 1105 cnt = rate << 16; 1106 cnt /= 24000; 1107 1108 cgl = 1; 1109 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1110 if (((rate / tmp1) * tmp1) != rate) 1111 cgl *= 2; 1112 } 1113 if (((rate / 3) * 3) != rate) 1114 cgl *= 3; 1115 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1116 if (((rate / tmp1) * tmp1) != rate) 1117 cgl *= 5; 1118 } 1119 #if 0 1120 /* XXX what manual says */ 1121 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1122 tmp1 |= csrc<<16; 1123 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1124 #else 1125 /* suggested by cs461x.c (ALSA driver) */ 1126 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1127 #endif 1128 1129 #if 0 1130 /* I am confused. The sample rate calculation section says 1131 * cci *is* 32-bit signed quantity but in the parameter description 1132 * section, CCI only assigned 16bit. 1133 * I believe size of the variable. 1134 */ 1135 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1136 tmp1 |= cci<<16; 1137 BA1WRITE4(sc, CS4280_CCI, tmp1); 1138 #else 1139 BA1WRITE4(sc, CS4280_CCI, cci); 1140 #endif 1141 1142 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1143 tmp1 |= cdlay <<18; 1144 BA1WRITE4(sc, CS4280_CD, tmp1); 1145 1146 BA1WRITE4(sc, CS4280_CPI, cpi); 1147 1148 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1149 tmp1 |= cgl; 1150 BA1WRITE4(sc, CS4280_CGL, tmp1); 1151 1152 BA1WRITE4(sc, CS4280_CNT, cnt); 1153 1154 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1155 tmp1 |= cgl; 1156 BA1WRITE4(sc, CS4280_CGC, tmp1); 1157 } 1158 1159 static void 1160 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1161 { 1162 /* 1163 * playback rate may range from 8000Hz to 48000Hz 1164 * 1165 * play_phase_increment = floor(rate*65536*1024/48000) 1166 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1167 * py=floor(px/200) 1168 * play_sample_rate_correction = px - 200*py 1169 * 1170 * play_phase_increment is a 32bit signed quantity. 1171 * play_sample_rate_correction is a 16bit signed quantity. 1172 */ 1173 int32_t ppi; 1174 int16_t psrc; 1175 uint32_t px, py; 1176 1177 if (rate < 8000) 1178 rate = 8000; 1179 if (rate > 48000) 1180 rate = 48000; 1181 px = rate << 16; 1182 ppi = px/48000; 1183 px -= ppi*48000; 1184 ppi <<= 10; 1185 px <<= 10; 1186 py = px / 48000; 1187 ppi += py; 1188 px -= py*48000; 1189 py = px/200; 1190 px -= py*200; 1191 psrc = px; 1192 #if 0 1193 /* what manual says */ 1194 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1195 BA1WRITE4(sc, CS4280_PSRC, 1196 ( ((psrc<<16) & PSRC_MASK) | px )); 1197 #else 1198 /* suggested by cs461x.c (ALSA driver) */ 1199 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1200 #endif 1201 BA1WRITE4(sc, CS4280_PPI, ppi); 1202 } 1203 1204 /* Download Processor Code and Data image */ 1205 static int 1206 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1207 uint32_t offset, uint32_t len) 1208 { 1209 uint32_t ctr; 1210 #if CS4280_DEBUG > 10 1211 uint32_t con, data; 1212 uint8_t c0, c1, c2, c3; 1213 #endif 1214 if ((offset & 3) || (len & 3)) 1215 return -1; 1216 1217 len /= sizeof(uint32_t); 1218 for (ctr = 0; ctr < len; ctr++) { 1219 /* XXX: 1220 * I cannot confirm this is the right thing or not 1221 * on BIG-ENDIAN machines. 1222 */ 1223 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1224 #if CS4280_DEBUG > 10 1225 data = htole32(*(src+ctr)); 1226 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1227 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1228 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1229 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1230 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1231 if (data != con ) { 1232 printf("0x%06x: write=0x%08x read=0x%08x\n", 1233 offset+ctr*4, data, con); 1234 return -1; 1235 } 1236 #endif 1237 } 1238 return 0; 1239 } 1240 1241 static int 1242 cs4280_download_image(struct cs428x_softc *sc) 1243 { 1244 int idx, err; 1245 uint32_t offset = 0; 1246 1247 err = 0; 1248 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1249 err = cs4280_download(sc, &BA1Struct.map[offset], 1250 BA1Struct.memory[idx].offset, 1251 BA1Struct.memory[idx].size); 1252 if (err != 0) { 1253 printf("%s: load_image failed at %d\n", 1254 sc->sc_dev.dv_xname, idx); 1255 return -1; 1256 } 1257 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1258 } 1259 return err; 1260 } 1261 1262 /* Processor Soft Reset */ 1263 static void 1264 cs4280_reset(void *sc_) 1265 { 1266 struct cs428x_softc *sc; 1267 1268 sc = sc_; 1269 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1270 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1271 delay(100); 1272 /* Clear RSTSP bit in SPCR */ 1273 BA1WRITE4(sc, CS4280_SPCR, 0); 1274 /* enable DMA reqest */ 1275 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1276 } 1277 1278 static int 1279 cs4280_init(struct cs428x_softc *sc, int init) 1280 { 1281 int n; 1282 uint32_t mem; 1283 1284 /* Start PLL out in known state */ 1285 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1286 /* Start serial ports out in known state */ 1287 BA0WRITE4(sc, CS4280_SERMC1, 0); 1288 1289 /* Specify type of CODEC */ 1290 /* XXX should not be here */ 1291 #define SERACC_CODEC_TYPE_1_03 1292 #ifdef SERACC_CODEC_TYPE_1_03 1293 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1294 #else 1295 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1296 #endif 1297 1298 /* Reset codec */ 1299 BA0WRITE4(sc, CS428X_ACCTL, 0); 1300 delay(100); /* delay 100us */ 1301 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1302 1303 /* Enable AC-link sync generation */ 1304 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1305 delay(50*1000); /* delay 50ms */ 1306 1307 /* Set the serial port timing configuration */ 1308 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1309 1310 /* Setup clock control */ 1311 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1312 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1313 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1314 1315 /* Power up the PLL */ 1316 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1317 delay(50*1000); /* delay 50ms */ 1318 1319 /* Turn on clock */ 1320 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1321 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1322 1323 /* Set the serial port FIFO pointer to the 1324 * first sample in FIFO. (not documented) */ 1325 cs4280_clear_fifos(sc); 1326 1327 #if 0 1328 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1329 BA0WRITE4(sc, CS4280_SERBSP, 0); 1330 #endif 1331 1332 /* Configure the serial port */ 1333 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1334 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1335 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1336 1337 /* Wait for CODEC ready */ 1338 n = 0; 1339 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1340 delay(125); 1341 if (++n > 1000) { 1342 printf("%s: codec ready timeout\n", 1343 sc->sc_dev.dv_xname); 1344 return 1; 1345 } 1346 } 1347 1348 /* Assert valid frame signal */ 1349 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1350 1351 /* Wait for valid AC97 input slot */ 1352 n = 0; 1353 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1354 (ACISV_ISV3 | ACISV_ISV4)) { 1355 delay(1000); 1356 if (++n > 1000) { 1357 printf("AC97 inputs slot ready timeout\n"); 1358 return 1; 1359 } 1360 } 1361 1362 /* Set AC97 output slot valid signals */ 1363 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1364 1365 /* reset the processor */ 1366 cs4280_reset(sc); 1367 1368 /* Download the image to the processor */ 1369 if (cs4280_download_image(sc) != 0) { 1370 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1371 return 1; 1372 } 1373 1374 /* Save playback parameter and then write zero. 1375 * this ensures that DMA doesn't immediately occur upon 1376 * starting the processor core 1377 */ 1378 mem = BA1READ4(sc, CS4280_PCTL); 1379 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1380 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1381 if (init != 0) 1382 sc->sc_prun = 0; 1383 1384 /* Save capture parameter and then write zero. 1385 * this ensures that DMA doesn't immediately occur upon 1386 * starting the processor core 1387 */ 1388 mem = BA1READ4(sc, CS4280_CCTL); 1389 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1390 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1391 if (init != 0) 1392 sc->sc_rrun = 0; 1393 1394 /* Processor Startup Procedure */ 1395 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1396 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1397 1398 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1399 n = 0; 1400 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1401 delay(10); 1402 if (++n > 1000) { 1403 printf("SPCR 1->0 transition timeout\n"); 1404 return 1; 1405 } 1406 } 1407 1408 n = 0; 1409 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1410 delay(10); 1411 if (++n > 1000) { 1412 printf("SPCS 0->1 transition timeout\n"); 1413 return 1; 1414 } 1415 } 1416 /* Processor is now running !!! */ 1417 1418 /* Setup volume */ 1419 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1420 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1421 1422 /* Interrupt enable */ 1423 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1424 1425 /* playback interrupt enable */ 1426 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1427 mem |= PFIE_PI_ENABLE; 1428 BA1WRITE4(sc, CS4280_PFIE, mem); 1429 /* capture interrupt enable */ 1430 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1431 mem |= CIE_CI_ENABLE; 1432 BA1WRITE4(sc, CS4280_CIE, mem); 1433 1434 #if NMIDI > 0 1435 /* Reset midi port */ 1436 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1437 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1438 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1439 /* midi interrupt enable */ 1440 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1441 BA0WRITE4(sc, CS4280_MIDCR, mem); 1442 #endif 1443 return 0; 1444 } 1445 1446 static void 1447 cs4280_clear_fifos(struct cs428x_softc *sc) 1448 { 1449 int pd, cnt, n; 1450 uint32_t mem; 1451 1452 pd = 0; 1453 /* 1454 * If device power down, power up the device and keep power down 1455 * state. 1456 */ 1457 mem = BA0READ4(sc, CS4280_CLKCR1); 1458 if (!(mem & CLKCR1_SWCE)) { 1459 printf("cs4280_clear_fifo: power down found.\n"); 1460 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1461 pd = 1; 1462 } 1463 BA0WRITE4(sc, CS4280_SERBWP, 0); 1464 for (cnt = 0; cnt < 256; cnt++) { 1465 n = 0; 1466 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1467 delay(1000); 1468 if (++n > 1000) { 1469 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1470 break; 1471 } 1472 } 1473 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1474 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1475 } 1476 if (pd) 1477 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1478 } 1479 1480 #if NMIDI > 0 1481 static int 1482 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1483 void (*ointr)(void *), void *arg) 1484 { 1485 struct cs428x_softc *sc; 1486 uint32_t mem; 1487 1488 DPRINTF(("midi_open\n")); 1489 sc = addr; 1490 sc->sc_iintr = iintr; 1491 sc->sc_ointr = ointr; 1492 sc->sc_arg = arg; 1493 1494 /* midi interrupt enable */ 1495 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1496 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1497 BA0WRITE4(sc, CS4280_MIDCR, mem); 1498 #ifdef CS4280_DEBUG 1499 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1500 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1501 return(EINVAL); 1502 } 1503 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1504 #endif 1505 return 0; 1506 } 1507 1508 static void 1509 cs4280_midi_close(void *addr) 1510 { 1511 struct cs428x_softc *sc; 1512 uint32_t mem; 1513 1514 DPRINTF(("midi_close\n")); 1515 sc = addr; 1516 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1517 mem = BA0READ4(sc, CS4280_MIDCR); 1518 mem &= ~MIDCR_MASK; 1519 BA0WRITE4(sc, CS4280_MIDCR, mem); 1520 1521 sc->sc_iintr = 0; 1522 sc->sc_ointr = 0; 1523 } 1524 1525 static int 1526 cs4280_midi_output(void *addr, int d) 1527 { 1528 struct cs428x_softc *sc; 1529 uint32_t mem; 1530 int x; 1531 1532 sc = addr; 1533 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1534 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1535 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1536 mem |= d & MIDWP_MASK; 1537 DPRINTFN(5,("midi_output d=0x%08x",d)); 1538 BA0WRITE4(sc, CS4280_MIDWP, mem); 1539 #ifdef DIAGNOSTIC 1540 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1541 DPRINTF(("Bad write data: %d %d", 1542 mem, BA0READ4(sc, CS4280_MIDWP))); 1543 return EIO; 1544 } 1545 #endif 1546 return 0; 1547 } 1548 delay(MIDI_BUSY_DELAY); 1549 } 1550 return EIO; 1551 } 1552 1553 static void 1554 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1555 { 1556 1557 mi->name = "CS4280 MIDI UART"; 1558 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1559 } 1560 1561 #endif /* NMIDI */ 1562 1563 /* DEBUG functions */ 1564 #if CS4280_DEBUG > 10 1565 static int 1566 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1567 uint32_t offset, uint32_t len) 1568 { 1569 uint32_t ctr, data; 1570 int err; 1571 1572 if ((offset & 3) || (len & 3)) 1573 return -1; 1574 1575 err = 0; 1576 len /= sizeof(uint32_t); 1577 for (ctr = 0; ctr < len; ctr++) { 1578 /* I cannot confirm this is the right thing 1579 * on BIG-ENDIAN machines 1580 */ 1581 data = BA1READ4(sc, offset+ctr*4); 1582 if (data != htole32(*(src+ctr))) { 1583 printf("0x%06x: 0x%08x(0x%08x)\n", 1584 offset+ctr*4, data, *(src+ctr)); 1585 *(src+ctr) = data; 1586 ++err; 1587 } 1588 } 1589 return err; 1590 } 1591 1592 static int 1593 cs4280_check_images(struct cs428x_softc *sc) 1594 { 1595 int idx, err; 1596 uint32_t offset; 1597 1598 offset = 0; 1599 err = 0; 1600 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1601 for (idx = 0; idx < 1; ++idx) { 1602 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1603 BA1Struct.memory[idx].offset, 1604 BA1Struct.memory[idx].size); 1605 if (err != 0) { 1606 printf("%s: check_image failed at %d\n", 1607 sc->sc_dev.dv_xname, idx); 1608 } 1609 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1610 } 1611 return err; 1612 } 1613 1614 #endif /* CS4280_DEBUG */ 1615
Indexes created Thu Oct 02 14:10:14 GMT 2025