cs4280.c revision 1.4
1 /* $NetBSD: cs4280.c,v 1.4 2000/05/15 01:35:29 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 */ 41 42 /* 43 * TODO 44 * Implement MIDI 45 * Joystick support 46 */ 47 48 #ifdef CS4280_DEBUG 49 #ifndef MIDI_READY 50 #define MIDI_READY 51 #endif /* ! MIDI_READY */ 52 #endif 53 54 #ifdef MIDI_READY 55 #include "midi.h" 56 #endif 57 58 #if defined(CS4280_DEBUG) 59 #define DPRINTF(x) if (cs4280debug) printf x 60 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 61 int cs4280debug = 0; 62 #else 63 #define DPRINTF(x) 64 #define DPRINTFN(n,x) 65 #endif 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/fcntl.h> 71 #include <sys/malloc.h> 72 #include <sys/device.h> 73 #include <sys/types.h> 74 #include <sys/systm.h> 75 76 #include <dev/pci/pcidevs.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/cs4280reg.h> 79 #include <dev/pci/cs4280_image.h> 80 81 #include <sys/audioio.h> 82 #include <dev/audio_if.h> 83 #include <dev/midi_if.h> 84 #include <dev/mulaw.h> 85 #include <dev/auconv.h> 86 87 #include <dev/ic/ac97reg.h> 88 #include <dev/ic/ac97var.h> 89 90 #include <machine/bus.h> 91 #include <machine/bswap.h> 92 93 #define CSCC_PCI_BA0 0x10 94 #define CSCC_PCI_BA1 0x14 95 96 struct cs4280_dma { 97 bus_dmamap_t map; 98 caddr_t addr; /* real dma buffer */ 99 caddr_t dum; /* dummy buffer for audio driver */ 100 bus_dma_segment_t segs[1]; 101 int nsegs; 102 size_t size; 103 struct cs4280_dma *next; 104 }; 105 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 106 #define BUFADDR(p) ((void *)((p)->dum)) 107 #define KERNADDR(p) ((void *)((p)->addr)) 108 109 /* 110 * Software state 111 */ 112 struct cs4280_softc { 113 struct device sc_dev; 114 115 pci_intr_handle_t * sc_ih; 116 117 /* I/O (BA0) */ 118 bus_space_tag_t ba0t; 119 bus_space_handle_t ba0h; 120 121 /* BA1 */ 122 bus_space_tag_t ba1t; 123 bus_space_handle_t ba1h; 124 125 /* DMA */ 126 bus_dma_tag_t sc_dmatag; 127 struct cs4280_dma *sc_dmas; 128 129 void (*sc_pintr)(void *); /* dma completion intr handler */ 130 void *sc_parg; /* arg for sc_intr() */ 131 char *sc_ps, *sc_pe, *sc_pn; 132 int sc_pcount; 133 int sc_pi; 134 struct cs4280_dma *sc_pdma; 135 char *sc_pbuf; 136 #ifdef DIAGNOSTIC 137 char sc_prun; 138 #endif 139 140 void (*sc_rintr)(void *); /* dma completion intr handler */ 141 void *sc_rarg; /* arg for sc_intr() */ 142 char *sc_rs, *sc_re, *sc_rn; 143 int sc_rcount; 144 int sc_ri; 145 struct cs4280_dma *sc_rdma; 146 char *sc_rbuf; 147 int sc_rparam; /* record format */ 148 #ifdef DIAGNOSTIC 149 char sc_rrun; 150 #endif 151 152 #if NMIDI > 0 153 void (*sc_iintr)(void *, int); /* midi input ready handler */ 154 void (*sc_ointr)(void *); /* midi output ready handler */ 155 void *sc_arg; 156 #endif 157 158 u_int32_t pctl; 159 u_int32_t cctl; 160 161 struct ac97_codec_if *codec_if; 162 struct ac97_host_if host_if; 163 164 char sc_suspend; 165 void *sc_powerhook; /* Power Hook */ 166 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 167 }; 168 169 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 170 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 171 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 172 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 173 174 int cs4280_match __P((struct device *, struct cfdata *, void *)); 175 void cs4280_attach __P((struct device *, struct device *, void *)); 176 int cs4280_intr __P((void *)); 177 void cs4280_reset __P((void *)); 178 int cs4280_download_image __P((struct cs4280_softc *)); 179 180 int cs4280_download(struct cs4280_softc *, u_int32_t *, u_int32_t, u_int32_t); 181 int cs4280_allocmem __P((struct cs4280_softc *, size_t, size_t, 182 struct cs4280_dma *)); 183 int cs4280_freemem __P((struct cs4280_softc *, struct cs4280_dma *)); 184 185 #ifdef CS4280_DEBUG 186 int cs4280_check_images __P((struct cs4280_softc *)); 187 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 188 u_int32_t); 189 #endif 190 191 struct cfattach clcs_ca = { 192 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 193 }; 194 195 int cs4280_init __P((struct cs4280_softc *, int)); 196 int cs4280_open __P((void *, int)); 197 void cs4280_close __P((void *)); 198 199 int cs4280_query_encoding __P((void *, struct audio_encoding *)); 200 int cs4280_set_params __P((void *, int, int, struct audio_params *, struct audio_params *)); 201 int cs4280_round_blocksize __P((void *, int)); 202 203 int cs4280_halt_output __P((void *)); 204 int cs4280_halt_input __P((void *)); 205 206 int cs4280_getdev __P((void *, struct audio_device *)); 207 208 int cs4280_mixer_set_port __P((void *, mixer_ctrl_t *)); 209 int cs4280_mixer_get_port __P((void *, mixer_ctrl_t *)); 210 int cs4280_query_devinfo __P((void *addr, mixer_devinfo_t *dip)); 211 void *cs4280_malloc __P((void *, int, size_t, int, int)); 212 void cs4280_free __P((void *, void *, int)); 213 size_t cs4280_round_buffersize __P((void *, int, size_t)); 214 int cs4280_mappage __P((void *, void *, int, int)); 215 int cs4280_get_props __P((void *)); 216 int cs4280_trigger_output __P((void *, void *, void *, int, void (*)(void *), 217 void *, struct audio_params *)); 218 int cs4280_trigger_input __P((void *, void *, void *, int, void (*)(void *), 219 void *, struct audio_params *)); 220 221 222 void cs4280_set_dac_rate __P((struct cs4280_softc *, int )); 223 void cs4280_set_adc_rate __P((struct cs4280_softc *, int )); 224 int cs4280_get_portnum_by_name __P((struct cs4280_softc *, char *, char *, 225 char *)); 226 int cs4280_src_wait __P((struct cs4280_softc *)); 227 int cs4280_attach_codec __P((void *sc, struct ac97_codec_if *)); 228 int cs4280_read_codec __P((void *sc, u_int8_t a, u_int16_t *d)); 229 int cs4280_write_codec __P((void *sc, u_int8_t a, u_int16_t d)); 230 void cs4280_reset_codec __P((void *sc)); 231 232 void cs4280_power __P((int, void *)); 233 234 void cs4280_clear_fifos __P((struct cs4280_softc *)); 235 236 #if NMIDI > 0 237 void cs4280_midi_close __P((void*)); 238 void cs4280_midi_getinfo __P((void *, struct midi_info *)); 239 int cs4280_midi_open __P((void *, int, void (*)(void *, int), 240 void (*)(void *), void *)); 241 int cs4280_midi_output __P((void *, int)); 242 #endif 243 244 struct audio_hw_if cs4280_hw_if = { 245 cs4280_open, 246 cs4280_close, 247 NULL, 248 cs4280_query_encoding, 249 cs4280_set_params, 250 cs4280_round_blocksize, 251 NULL, 252 NULL, 253 NULL, 254 NULL, 255 NULL, 256 cs4280_halt_output, 257 cs4280_halt_input, 258 NULL, 259 cs4280_getdev, 260 NULL, 261 cs4280_mixer_set_port, 262 cs4280_mixer_get_port, 263 cs4280_query_devinfo, 264 cs4280_malloc, 265 cs4280_free, 266 cs4280_round_buffersize, 267 cs4280_mappage, 268 cs4280_get_props, 269 cs4280_trigger_output, 270 cs4280_trigger_input, 271 }; 272 273 #if NMIDI > 0 274 struct midi_hw_if cs4280_midi_hw_if = { 275 cs4280_midi_open, 276 cs4280_midi_close, 277 cs4280_midi_output, 278 cs4280_midi_getinfo, 279 0, 280 }; 281 #endif 282 283 284 285 struct audio_device cs4280_device = { 286 "CS4280", 287 "", 288 "cs4280" 289 }; 290 291 292 int 293 cs4280_match(parent, match, aux) 294 struct device *parent; 295 struct cfdata *match; 296 void *aux; 297 { 298 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 299 300 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 301 return (0); 302 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 303 #if 0 /* I can't confirm */ 304 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 305 #endif 306 307 ) { 308 return (1); 309 } 310 return (0); 311 } 312 313 int 314 cs4280_read_codec(sc_, add, data) 315 void *sc_; 316 u_int8_t add; 317 u_int16_t *data; 318 { 319 struct cs4280_softc *sc = sc_; 320 int n; 321 322 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 323 /* 324 * Make sure that there is not data sitting around from a preivous 325 * uncompleted access. 326 */ 327 BA0READ4(sc, CS4280_ACSDA); 328 329 /* Set up AC97 control registers. */ 330 BA0WRITE4(sc, CS4280_ACCAD, add); 331 BA0WRITE4(sc, CS4280_ACCDA, 0); 332 BA0WRITE4(sc, CS4280_ACCTL, 333 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 334 335 if (cs4280_src_wait(sc) < 0) { 336 printf("%s: AC97 read prob. (DCV!=0) for add=0x%0x\n", 337 sc->sc_dev.dv_xname, add); 338 return (1); 339 } 340 341 /* wait for valid status bit is active */ 342 n = 0; 343 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 344 delay(1); 345 while (++n > 1000) { 346 printf("%s: AC97 read fail (VSTS==0) for add=0x%0x\n", 347 sc->sc_dev.dv_xname, add); 348 return (1); 349 } 350 } 351 *data = BA0READ4(sc, CS4280_ACSDA); 352 DPRINTFN(5,("data=0x%04x\n", *data)); 353 return (0); 354 } 355 356 int 357 cs4280_write_codec(sc_, add, data) 358 void *sc_; 359 u_int8_t add; 360 u_int16_t data; 361 { 362 struct cs4280_softc *sc = sc_; 363 364 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 365 BA0WRITE4(sc, CS4280_ACCAD, add); 366 BA0WRITE4(sc, CS4280_ACCDA, data); 367 BA0WRITE4(sc, CS4280_ACCTL, 368 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 369 370 if (cs4280_src_wait(sc) < 0) { 371 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 372 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 373 return (1); 374 } 375 return (0); 376 } 377 378 int 379 cs4280_src_wait(sc) 380 struct cs4280_softc *sc; 381 { 382 int n; 383 n = 0; 384 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 385 delay(1000); 386 while (++n > 1000) 387 return (-1); 388 } 389 return (0); 390 } 391 392 393 void 394 cs4280_set_adc_rate(sc, rate) 395 struct cs4280_softc *sc; 396 int rate; 397 { 398 /* calculate capture rate: 399 * 400 * capture_coefficient_increment = -round(rate*128*65536/48000; 401 * capture_phase_increment = floor(48000*65536*1024/rate); 402 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 403 * cy = floor(cx/200); 404 * capture_sample_rate_correction = cx - 200*cy; 405 * capture_delay = ceil(24*48000/rate); 406 * capture_num_triplets = floor(65536*rate/24000); 407 * capture_group_length = 24000/GCD(rate, 24000); 408 * where GCD means "Greatest Common Divisor". 409 * 410 * capture_coefficient_increment, capture_phase_increment and 411 * capture_num_triplets are 32-bit signed quantities. 412 * capture_sample_rate_correction and capture_group_length are 413 * 16-bit signed quantities. 414 * capture_delay is a 14-bit unsigned quantity. 415 */ 416 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 417 u_int16_t csrc, cgl, cdlay; 418 419 /* XXX 420 * Even though, embedded_audio_spec says capture rate range 11025 to 421 * 48000, dhwiface.cpp says, 422 * 423 * "We can only decimate by up to a factor of 1/9th the hardware rate. 424 * Return an error if an attempt is made to stray outside that limit." 425 * 426 * so assume range as 48000/9 to 48000 427 */ 428 429 if (rate < 8000) 430 rate = 8000; 431 if (rate > 48000) 432 rate = 48000; 433 434 cx = rate << 16; 435 cci = cx / 48000; 436 cx -= cci * 48000; 437 cx <<= 7; 438 cci <<= 7; 439 cci += cx / 48000; 440 cci = - cci; 441 442 cx = 48000 << 16; 443 cpi = cx / rate; 444 cx -= cpi * rate; 445 cx <<= 10; 446 cpi <<= 10; 447 cy = cx / rate; 448 cpi += cy; 449 cx -= cy * rate; 450 451 cy = cx / 200; 452 csrc = cx - 200*cy; 453 454 cdlay = ((48000 * 24) + rate - 1) / rate; 455 #if 0 456 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 457 #endif 458 459 cnt = rate << 16; 460 cnt /= 24000; 461 462 cgl = 1; 463 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 464 if (((rate / tmp1) * tmp1) != rate) 465 cgl *= 2; 466 } 467 if (((rate / 3) * 3) != rate) 468 cgl *= 3; 469 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 470 if (((rate / tmp1) * tmp1) != rate) 471 cgl *= 5; 472 } 473 #if 0 474 /* XXX what manual says */ 475 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 476 tmp1 |= csrc<<16; 477 BA1WRITE4(sc, CS4280_CSRC, tmp1); 478 #else 479 /* suggested by cs461x.c (ALSA driver) */ 480 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 481 #endif 482 483 #if 0 484 /* I am confused. The sample rate calculation section says 485 * cci *is* 32-bit signed quantity but in the parameter description 486 * section, CCI only assigned 16bit. 487 * I believe size of the variable. 488 */ 489 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 490 tmp1 |= cci<<16; 491 BA1WRITE4(sc, CS4280_CCI, tmp1); 492 #else 493 BA1WRITE4(sc, CS4280_CCI, cci); 494 #endif 495 496 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 497 tmp1 |= cdlay <<18; 498 BA1WRITE4(sc, CS4280_CD, tmp1); 499 500 BA1WRITE4(sc, CS4280_CPI, cpi); 501 502 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 503 tmp1 |= cgl; 504 BA1WRITE4(sc, CS4280_CGL, tmp1); 505 506 BA1WRITE4(sc, CS4280_CNT, cnt); 507 508 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 509 tmp1 |= cgl; 510 BA1WRITE4(sc, CS4280_CGC, tmp1); 511 } 512 513 void 514 cs4280_set_dac_rate(sc, rate) 515 struct cs4280_softc *sc; 516 int rate; 517 { 518 /* 519 * playback rate may range from 8000Hz to 48000Hz 520 * 521 * play_phase_increment = floor(rate*65536*1024/48000) 522 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 523 * py=floor(px/200) 524 * play_sample_rate_correction = px - 200*py 525 * 526 * play_phase_increment is a 32bit signed quantity. 527 * play_sample_rate_correction is a 16bit signed quantity. 528 */ 529 int32_t ppi; 530 int16_t psrc; 531 u_int32_t px, py; 532 533 if (rate < 8000) 534 rate = 8000; 535 if (rate > 48000) 536 rate = 48000; 537 px = rate << 16; 538 ppi = px/48000; 539 px -= ppi*48000; 540 ppi <<= 10; 541 px <<= 10; 542 py = px / 48000; 543 ppi += py; 544 px -= py*48000; 545 py = px/200; 546 px -= py*200; 547 psrc = px; 548 #if 0 549 /* what manual says */ 550 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 551 BA1WRITE4(sc, CS4280_PSRC, 552 ( ((psrc<<16) & PSRC_MASK) | px )); 553 #else 554 /* suggested by cs461x.c (ALSA driver) */ 555 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 556 #endif 557 BA1WRITE4(sc, CS4280_PPI, ppi); 558 } 559 560 void 561 cs4280_attach(parent, self, aux) 562 struct device *parent; 563 struct device *self; 564 void *aux; 565 { 566 struct cs4280_softc *sc = (struct cs4280_softc *)self; 567 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 568 pci_chipset_tag_t pc = pa->pa_pc; 569 char const *intrstr; 570 pci_intr_handle_t ih; 571 pcireg_t csr; 572 char devinfo[256]; 573 mixer_ctrl_t ctl; 574 u_int32_t mem; 575 576 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 577 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 578 579 /* Map I/O register */ 580 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 581 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 582 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 583 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 584 return; 585 } 586 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 587 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 588 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 589 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 590 return; 591 } 592 593 sc->sc_dmatag = pa->pa_dmat; 594 595 /* Enable the device (set bus master flag) */ 596 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 597 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 598 csr | PCI_COMMAND_MASTER_ENABLE); 599 600 /* LATENCY_TIMER setting */ 601 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 602 if ( PCI_LATTIMER(mem) < 32 ) { 603 mem &= 0xffff00ff; 604 mem |= 0x00002000; 605 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 606 } 607 608 /* Map and establish the interrupt. */ 609 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 610 pa->pa_intrline, &ih)) { 611 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 612 return; 613 } 614 intrstr = pci_intr_string(pc, ih); 615 616 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 617 if (sc->sc_ih == NULL) { 618 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 619 if (intrstr != NULL) 620 printf(" at %s", intrstr); 621 printf("\n"); 622 return; 623 } 624 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 625 626 /* Initialization */ 627 if(cs4280_init(sc, 1) != 0) 628 return; 629 630 /* AC 97 attachement */ 631 sc->host_if.arg = sc; 632 sc->host_if.attach = cs4280_attach_codec; 633 sc->host_if.read = cs4280_read_codec; 634 sc->host_if.write = cs4280_write_codec; 635 sc->host_if.reset = cs4280_reset_codec; 636 637 if (ac97_attach(&sc->host_if) != 0) { 638 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 639 return; 640 } 641 642 /* Turn mute off of DAC, CD and master volumes by default */ 643 ctl.type = AUDIO_MIXER_ENUM; 644 ctl.un.ord = 0; /* off */ 645 646 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 647 AudioNmaster, AudioNmute); 648 cs4280_mixer_set_port(sc, &ctl); 649 650 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 651 AudioNdac, AudioNmute); 652 cs4280_mixer_set_port(sc, &ctl); 653 654 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 655 AudioNcd, AudioNmute); 656 cs4280_mixer_set_port(sc, &ctl); 657 658 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 659 660 #if NMIDI > 0 661 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 662 #endif 663 sc->sc_suspend = PWR_RESUME; 664 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 665 } 666 667 int 668 cs4280_intr(p) 669 void *p; 670 { 671 /* 672 * XXX 673 * 674 * Since CS4280 has only 4kB dma buffer and 675 * interrupt occurs every 2kB block, I create dummy buffer 676 * which returns to audio driver and actual dma buffer 677 * using in DMA transfer. 678 * 679 * 680 * ring buffer in audio.c is pointed by BUFADDR 681 * <------ ring buffer size == 64kB ------> 682 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 683 * |= = = =|= = = =|= = = =|= = = =|= = = =| 684 * | | | | | | <- call audio_intp every 685 * sc->sc_[pr]_count time. 686 * 687 * actual dma buffer is pointed by KERNADDR 688 * <-> dma buffer size = 4kB 689 * |= =| 690 * 691 * 692 */ 693 struct cs4280_softc *sc = p; 694 u_int32_t intr, mem; 695 char * empty_dma; 696 697 intr = BA0READ4(sc, CS4280_HISR); 698 699 if ((intr & HISR_INTENA) == 0) { 700 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 701 return (0); 702 } 703 704 /* Playback Interrupt */ 705 if (intr & HISR_PINT) { 706 mem = BA1READ4(sc, CS4280_PFIE); 707 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 708 if (sc->sc_pintr) { 709 if ((sc->sc_pi%sc->sc_pcount) == 0) 710 sc->sc_pintr(sc->sc_parg); 711 } else { 712 printf("unexpected play intr\n"); 713 } 714 /* copy buffer */ 715 ++sc->sc_pi; 716 empty_dma = sc->sc_pdma->addr; 717 if (sc->sc_pi&1) 718 empty_dma += CS4280_ICHUNK; 719 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 720 sc->sc_pn += CS4280_ICHUNK; 721 if (sc->sc_pn >= sc->sc_pe) 722 sc->sc_pn = sc->sc_ps; 723 BA1WRITE4(sc, CS4280_PFIE, mem); 724 } 725 /* Capture Interrupt */ 726 if (intr & HISR_CINT) { 727 int i; 728 int16_t rdata; 729 730 mem = BA1READ4(sc, CS4280_CIE); 731 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 732 ++sc->sc_ri; 733 empty_dma = sc->sc_rdma->addr; 734 if ((sc->sc_ri&1) == 0) 735 empty_dma += CS4280_ICHUNK; 736 737 /* 738 * XXX 739 * I think this audio data conversion should be 740 * happend in upper layer, but I put this here 741 * since there is no conversion function available. 742 */ 743 switch(sc->sc_rparam) { 744 case CF_16BIT_STEREO: 745 /* just copy it */ 746 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 747 sc->sc_rn += CS4280_ICHUNK; 748 break; 749 case CF_16BIT_MONO: 750 for (i = 0; i < 512; i++) { 751 rdata = *((int16_t *)empty_dma)++>>1; 752 rdata += *((int16_t *)empty_dma)++>>1; 753 *((int16_t *)sc->sc_rn)++ = rdata; 754 } 755 break; 756 case CF_8BIT_STEREO: 757 for (i = 0; i < 512; i++) { 758 rdata = *((int16_t*)empty_dma)++; 759 *sc->sc_rn++ = rdata >> 8; 760 rdata = *((int16_t*)empty_dma)++; 761 *sc->sc_rn++ = rdata >> 8; 762 } 763 break; 764 case CF_8BIT_MONO: 765 for (i = 0; i < 512; i++) { 766 rdata = *((int16_t*)empty_dma)++ >>1; 767 rdata += *((int16_t*)empty_dma)++ >>1; 768 *sc->sc_rn++ = rdata >>8; 769 } 770 break; 771 default: 772 /* Should not reach here */ 773 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 774 } 775 if (sc->sc_rn >= sc->sc_re) 776 sc->sc_rn = sc->sc_rs; 777 BA1WRITE4(sc, CS4280_CIE, mem); 778 if (sc->sc_rintr) { 779 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 780 sc->sc_rintr(sc->sc_rarg); 781 } else { 782 printf("unexpected record intr\n"); 783 } 784 } 785 786 #if NMIDI > 0 787 /* Midi port Interrupt */ 788 if (intr & HISR_MIDI) { 789 int data; 790 791 DPRINTF(("i: %d: ", 792 BA0READ4(sc, CS4280_MIDSR))); 793 /* Read the received data */ 794 while ((sc->sc_iintr != NULL) && 795 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 796 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 797 DPRINTF(("r:%x\n",data)); 798 sc->sc_iintr(sc->sc_arg, data); 799 } 800 801 /* Write the data */ 802 #if 1 803 /* XXX: 804 * It seems "Transmit Buffer Full" never activate until EOI 805 * is deliverd. Shall I throw EOI top of this routine ? 806 */ 807 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 808 DPRINTF(("w: ")); 809 if (sc->sc_ointr != NULL) 810 sc->sc_ointr(sc->sc_arg); 811 } 812 #else 813 while ((sc->sc_ointr != NULL) && 814 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 815 DPRINTF(("w: ")); 816 sc->sc_ointr(sc->sc_arg); 817 } 818 #endif 819 DPRINTF(("\n")); 820 } 821 #endif 822 /* Throw EOI */ 823 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 824 return (0); 825 } 826 827 828 /* Download Proceessor Code and Data image */ 829 830 int 831 cs4280_download(sc, src, offset, len) 832 struct cs4280_softc *sc; 833 u_int32_t *src; 834 u_int32_t offset, len; 835 { 836 u_int32_t ctr; 837 838 #ifdef CS4280_DEBUG 839 u_int32_t con, data; 840 u_int8_t c0,c1,c2,c3; 841 #endif 842 if ((offset&3) || (len&3)) 843 return (-1); 844 845 len /= sizeof(u_int32_t); 846 for (ctr = 0; ctr < len; ctr++) { 847 /* XXX: 848 * I cannot confirm this is the right thing or not 849 * on BIG-ENDIAN machines. 850 */ 851 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 852 #ifdef CS4280_DEBUG 853 data = htole32(*(src+ctr)); 854 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 855 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 856 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 857 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 858 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 859 if (data != con ) { 860 printf("0x%06x: write=0x%08x read=0x%08x\n", 861 offset+ctr*4, data, con); 862 return (-1); 863 } 864 #endif 865 } 866 return (0); 867 } 868 869 int 870 cs4280_download_image(sc) 871 struct cs4280_softc *sc; 872 { 873 int idx, err; 874 u_int32_t offset = 0; 875 876 err = 0; 877 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 878 err = cs4280_download(sc, &BA1Struct.map[offset], 879 BA1Struct.memory[idx].offset, 880 BA1Struct.memory[idx].size); 881 if (err != 0) { 882 printf("%s: load_image failed at %d\n", 883 sc->sc_dev.dv_xname, idx); 884 return (-1); 885 } 886 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 887 } 888 return (err); 889 } 890 891 #ifdef CS4280_DEBUG 892 int 893 cs4280_checkimage(sc, src, offset, len) 894 struct cs4280_softc *sc; 895 u_int32_t *src; 896 u_int32_t offset, len; 897 { 898 u_int32_t ctr, data; 899 int err = 0; 900 901 if ((offset&3) || (len&3)) 902 return -1; 903 904 len /= sizeof(u_int32_t); 905 for (ctr = 0; ctr < len; ctr++) { 906 /* I cannot confirm this is the right thing 907 * on BIG-ENDIAN machines 908 */ 909 data = BA1READ4(sc, offset+ctr*4); 910 if (data != htole32(*(src+ctr))) { 911 printf("0x%06x: 0x%08x(0x%08x)\n", 912 offset+ctr*4, data, *(src+ctr)); 913 *(src+ctr) = data; 914 ++err; 915 } 916 } 917 return (err); 918 } 919 920 int 921 cs4280_check_images(sc) 922 struct cs4280_softc *sc; 923 { 924 int idx, err; 925 u_int32_t offset = 0; 926 927 err = 0; 928 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 929 for (idx = 0; idx < 1; ++idx) { 930 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 931 BA1Struct.memory[idx].offset, 932 BA1Struct.memory[idx].size); 933 if (err != 0) { 934 printf("%s: check_image failed at %d\n", 935 sc->sc_dev.dv_xname, idx); 936 } 937 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 938 } 939 return (err); 940 } 941 942 #endif 943 944 int 945 cs4280_attach_codec(sc_, codec_if) 946 void *sc_; 947 struct ac97_codec_if *codec_if; 948 { 949 struct cs4280_softc *sc = sc_; 950 951 sc->codec_if = codec_if; 952 return (0); 953 } 954 955 void 956 cs4280_reset_codec(sc_) 957 void *sc_; 958 { 959 struct cs4280_softc *sc = sc_; 960 int n; 961 962 /* Reset codec */ 963 BA0WRITE4(sc, CS4280_ACCTL, 0); 964 delay(100); /* delay 100us */ 965 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 966 967 /* 968 * It looks like we do the following procedure, too 969 */ 970 971 /* Enable AC-link sync generation */ 972 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 973 delay(50*1000); /* XXX delay 50ms */ 974 975 /* Assert valid frame signal */ 976 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 977 978 /* Wait for valid AC97 input slot */ 979 n = 0; 980 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 981 delay(1000); 982 if (++n > 1000) { 983 printf("reset_codec: AC97 inputs slot ready timeout\n"); 984 return; 985 } 986 } 987 } 988 989 990 /* Processor Soft Reset */ 991 void 992 cs4280_reset(sc_) 993 void *sc_; 994 { 995 struct cs4280_softc *sc = sc_; 996 997 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 998 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 999 delay(100); 1000 /* Clear RSTSP bit in SPCR */ 1001 BA1WRITE4(sc, CS4280_SPCR, 0); 1002 /* enable DMA reqest */ 1003 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1004 } 1005 1006 int 1007 cs4280_open(addr, flags) 1008 void *addr; 1009 int flags; 1010 { 1011 return (0); 1012 } 1013 1014 void 1015 cs4280_close(addr) 1016 void *addr; 1017 { 1018 struct cs4280_softc *sc = addr; 1019 1020 cs4280_halt_output(sc); 1021 cs4280_halt_input(sc); 1022 1023 sc->sc_pintr = 0; 1024 sc->sc_rintr = 0; 1025 } 1026 1027 int 1028 cs4280_query_encoding(addr, fp) 1029 void *addr; 1030 struct audio_encoding *fp; 1031 { 1032 switch (fp->index) { 1033 case 0: 1034 strcpy(fp->name, AudioEulinear); 1035 fp->encoding = AUDIO_ENCODING_ULINEAR; 1036 fp->precision = 8; 1037 fp->flags = 0; 1038 break; 1039 case 1: 1040 strcpy(fp->name, AudioEmulaw); 1041 fp->encoding = AUDIO_ENCODING_ULAW; 1042 fp->precision = 8; 1043 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1044 break; 1045 case 2: 1046 strcpy(fp->name, AudioEalaw); 1047 fp->encoding = AUDIO_ENCODING_ALAW; 1048 fp->precision = 8; 1049 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1050 break; 1051 case 3: 1052 strcpy(fp->name, AudioEslinear); 1053 fp->encoding = AUDIO_ENCODING_SLINEAR; 1054 fp->precision = 8; 1055 fp->flags = 0; 1056 break; 1057 case 4: 1058 strcpy(fp->name, AudioEslinear_le); 1059 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1060 fp->precision = 16; 1061 fp->flags = 0; 1062 break; 1063 case 5: 1064 strcpy(fp->name, AudioEulinear_le); 1065 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1066 fp->precision = 16; 1067 fp->flags = 0; 1068 break; 1069 case 6: 1070 strcpy(fp->name, AudioEslinear_be); 1071 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1072 fp->precision = 16; 1073 fp->flags = 0; 1074 break; 1075 case 7: 1076 strcpy(fp->name, AudioEulinear_be); 1077 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1078 fp->precision = 16; 1079 fp->flags = 0; 1080 break; 1081 default: 1082 return (EINVAL); 1083 } 1084 return (0); 1085 } 1086 1087 int 1088 cs4280_set_params(addr, setmode, usemode, play, rec) 1089 void *addr; 1090 int setmode, usemode; 1091 struct audio_params *play, *rec; 1092 { 1093 struct cs4280_softc *sc = addr; 1094 struct audio_params *p; 1095 int mode; 1096 1097 for (mode = AUMODE_RECORD; mode != -1; 1098 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1099 if ((setmode & mode) == 0) 1100 continue; 1101 1102 p = mode == AUMODE_PLAY ? play : rec; 1103 1104 if (p == play) { 1105 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1106 p->sample_rate, p->precision, p->channels)); 1107 /* play back data format may be 8- or 16-bit and 1108 * either stereo or mono. 1109 * playback rate may range from 8000Hz to 48000Hz 1110 */ 1111 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1112 (p->precision != 8 && p->precision != 16) || 1113 (p->channels != 1 && p->channels != 2) ) { 1114 return (EINVAL); 1115 } 1116 } else { 1117 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1118 p->sample_rate, p->precision, p->channels)); 1119 /* capture data format must be 16bit stereo 1120 * and sample rate range from 11025Hz to 48000Hz. 1121 * 1122 * XXX: it looks like to work with 8000Hz, 1123 * although data sheets say lower limit is 1124 * 11025 Hz. 1125 */ 1126 1127 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1128 (p->precision != 8 && p->precision != 16) || 1129 (p->channels != 1 && p->channels != 2) ) { 1130 return (EINVAL); 1131 } 1132 } 1133 p->factor = 1; 1134 p->sw_code = 0; 1135 1136 /* capturing data is slinear */ 1137 switch (p->encoding) { 1138 case AUDIO_ENCODING_SLINEAR_BE: 1139 if (mode == AUMODE_RECORD) { 1140 if (p->precision == 16) 1141 p->sw_code = swap_bytes; 1142 } 1143 break; 1144 case AUDIO_ENCODING_SLINEAR_LE: 1145 break; 1146 case AUDIO_ENCODING_ULINEAR_BE: 1147 if (mode == AUMODE_RECORD) { 1148 if (p->precision == 16) 1149 p->sw_code = change_sign16_swap_bytes_le; 1150 else 1151 p->sw_code = change_sign8; 1152 } 1153 break; 1154 case AUDIO_ENCODING_ULINEAR_LE: 1155 if (mode == AUMODE_RECORD) { 1156 if (p->precision == 16) 1157 p->sw_code = change_sign16_le; 1158 else 1159 p->sw_code = change_sign8; 1160 } 1161 break; 1162 case AUDIO_ENCODING_ULAW: 1163 if (mode == AUMODE_PLAY) { 1164 p->factor = 2; 1165 p->sw_code = mulaw_to_slinear16_le; 1166 } else { 1167 p->sw_code = slinear8_to_mulaw; 1168 } 1169 break; 1170 case AUDIO_ENCODING_ALAW: 1171 if (mode == AUMODE_PLAY) { 1172 p->factor = 2; 1173 p->sw_code = alaw_to_slinear16_le; 1174 } else { 1175 p->sw_code = slinear8_to_alaw; 1176 } 1177 break; 1178 default: 1179 return (EINVAL); 1180 } 1181 } 1182 1183 /* set sample rate */ 1184 cs4280_set_dac_rate(sc, play->sample_rate); 1185 cs4280_set_adc_rate(sc, rec->sample_rate); 1186 return (0); 1187 } 1188 1189 int 1190 cs4280_round_blocksize(hdl, blk) 1191 void *hdl; 1192 int blk; 1193 { 1194 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1195 } 1196 1197 size_t 1198 cs4280_round_buffersize(addr, direction, size) 1199 void *addr; 1200 int direction; 1201 size_t size; 1202 { 1203 /* although real dma buffer size is 4KB, 1204 * let the audio.c driver use a larger buffer. 1205 * ( suggested by Lennart Augustsson. ) 1206 */ 1207 return (size); 1208 } 1209 1210 int 1211 cs4280_get_props(hdl) 1212 void *hdl; 1213 { 1214 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1215 #ifdef notyet 1216 /* XXX 1217 * How can I mmap ? 1218 */ 1219 AUDIO_PROP_MMAP 1220 #endif 1221 1222 } 1223 1224 int 1225 cs4280_mixer_get_port(addr, cp) 1226 void *addr; 1227 mixer_ctrl_t *cp; 1228 { 1229 struct cs4280_softc *sc = addr; 1230 1231 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1232 } 1233 1234 int 1235 cs4280_mappage(addr, mem, off, prot) 1236 void *addr; 1237 void *mem; 1238 int off; 1239 int prot; 1240 { 1241 struct cs4280_softc *sc = addr; 1242 struct cs4280_dma *p; 1243 1244 if (off < 0) 1245 return (-1); 1246 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1247 ; 1248 if (!p) { 1249 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1250 return (-1); 1251 } 1252 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1253 off, prot, BUS_DMA_WAITOK)); 1254 } 1255 1256 1257 int 1258 cs4280_query_devinfo(addr, dip) 1259 void *addr; 1260 mixer_devinfo_t *dip; 1261 { 1262 struct cs4280_softc *sc = addr; 1263 1264 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1265 } 1266 1267 int 1268 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1269 struct cs4280_softc *sc; 1270 char *class, *device, *qualifier; 1271 { 1272 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1273 device, qualifier)); 1274 } 1275 1276 int 1277 cs4280_halt_output(addr) 1278 void *addr; 1279 { 1280 struct cs4280_softc *sc = addr; 1281 u_int32_t mem; 1282 1283 mem = BA1READ4(sc, CS4280_PCTL); 1284 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1285 #ifdef DIAGNOSTIC 1286 sc->sc_prun = 0; 1287 #endif 1288 return (0); 1289 } 1290 1291 int 1292 cs4280_halt_input(addr) 1293 void *addr; 1294 { 1295 struct cs4280_softc *sc = addr; 1296 u_int32_t mem; 1297 1298 mem = BA1READ4(sc, CS4280_CCTL); 1299 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1300 #ifdef DIAGNOSTIC 1301 sc->sc_rrun = 0; 1302 #endif 1303 return (0); 1304 } 1305 1306 int 1307 cs4280_getdev(addr, retp) 1308 void *addr; 1309 struct audio_device *retp; 1310 { 1311 *retp = cs4280_device; 1312 return (0); 1313 } 1314 1315 int 1316 cs4280_mixer_set_port(addr, cp) 1317 void *addr; 1318 mixer_ctrl_t *cp; 1319 { 1320 struct cs4280_softc *sc = addr; 1321 int val; 1322 1323 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1324 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1325 return (val); 1326 } 1327 1328 1329 int 1330 cs4280_freemem(sc, p) 1331 struct cs4280_softc *sc; 1332 struct cs4280_dma *p; 1333 { 1334 bus_dmamap_unload(sc->sc_dmatag, p->map); 1335 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1336 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1337 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1338 return (0); 1339 } 1340 1341 int 1342 cs4280_allocmem(sc, size, align, p) 1343 struct cs4280_softc *sc; 1344 size_t size; 1345 size_t align; 1346 struct cs4280_dma *p; 1347 { 1348 int error; 1349 1350 /* XXX */ 1351 p->size = size; 1352 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1353 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1354 &p->nsegs, BUS_DMA_NOWAIT); 1355 if (error) { 1356 printf("%s: unable to allocate dma, error=%d\n", 1357 sc->sc_dev.dv_xname, error); 1358 return (error); 1359 } 1360 1361 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1362 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1363 if (error) { 1364 printf("%s: unable to map dma, error=%d\n", 1365 sc->sc_dev.dv_xname, error); 1366 goto free; 1367 } 1368 1369 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1370 0, BUS_DMA_NOWAIT, &p->map); 1371 if (error) { 1372 printf("%s: unable to create dma map, error=%d\n", 1373 sc->sc_dev.dv_xname, error); 1374 goto unmap; 1375 } 1376 1377 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1378 BUS_DMA_NOWAIT); 1379 if (error) { 1380 printf("%s: unable to load dma map, error=%d\n", 1381 sc->sc_dev.dv_xname, error); 1382 goto destroy; 1383 } 1384 return (0); 1385 1386 destroy: 1387 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1388 unmap: 1389 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1390 free: 1391 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1392 return (error); 1393 } 1394 1395 1396 void * 1397 cs4280_malloc(addr, direction, size, pool, flags) 1398 void *addr; 1399 int direction; 1400 size_t size; 1401 int pool, flags; 1402 { 1403 struct cs4280_softc *sc = addr; 1404 struct cs4280_dma *p; 1405 caddr_t q; 1406 int error; 1407 1408 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1409 q = malloc(size, pool, flags); 1410 if (!q) 1411 return (0); 1412 p = malloc(sizeof(*p), pool, flags); 1413 if (!p) { 1414 free(q,pool); 1415 return (0); 1416 } 1417 /* 1418 * cs4280 has fixed 4kB buffer 1419 */ 1420 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1421 1422 if (error) { 1423 free(q, pool); 1424 free(p, pool); 1425 return (0); 1426 } 1427 1428 p->next = sc->sc_dmas; 1429 sc->sc_dmas = p; 1430 p->dum = q; /* return to audio driver */ 1431 1432 return (p->dum); 1433 } 1434 1435 void 1436 cs4280_free(addr, ptr, pool) 1437 void *addr; 1438 void *ptr; 1439 int pool; 1440 { 1441 struct cs4280_softc *sc = addr; 1442 struct cs4280_dma **pp, *p; 1443 1444 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1445 if (BUFADDR(p) == ptr) { 1446 cs4280_freemem(sc, p); 1447 *pp = p->next; 1448 free(p->dum, pool); 1449 free(p, pool); 1450 return; 1451 } 1452 } 1453 } 1454 1455 int 1456 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1457 void *addr; 1458 void *start, *end; 1459 int blksize; 1460 void (*intr) __P((void *)); 1461 void *arg; 1462 struct audio_params *param; 1463 { 1464 struct cs4280_softc *sc = addr; 1465 u_int32_t pfie, pctl, mem, pdtc; 1466 struct cs4280_dma *p; 1467 1468 #ifdef DIAGNOSTIC 1469 if (sc->sc_prun) 1470 printf("cs4280_trigger_output: already running\n"); 1471 sc->sc_prun = 1; 1472 #endif 1473 1474 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1475 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1476 sc->sc_pintr = intr; 1477 sc->sc_parg = arg; 1478 1479 /* stop playback DMA */ 1480 mem = BA1READ4(sc, CS4280_PCTL); 1481 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1482 1483 /* setup PDTC */ 1484 pdtc = BA1READ4(sc, CS4280_PDTC); 1485 pdtc &= ~PDTC_MASK; 1486 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1487 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1488 1489 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1490 param->precision, param->factor, param->channels, 1491 param->encoding)); 1492 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1493 ; 1494 if (p == NULL) { 1495 printf("cs4280_trigger_output: bad addr %p\n", start); 1496 return (EINVAL); 1497 } 1498 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1499 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1500 "4kB align\n", DMAADDR(p)); 1501 return (EINVAL); 1502 } 1503 1504 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1505 sc->sc_ps = (char *)start; 1506 sc->sc_pe = (char *)end; 1507 sc->sc_pdma = p; 1508 sc->sc_pbuf = KERNADDR(p); 1509 sc->sc_pi = 0; 1510 sc->sc_pn = sc->sc_ps; 1511 if (blksize >= CS4280_DCHUNK) { 1512 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1513 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1514 ++sc->sc_pi; 1515 } else { 1516 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1517 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1518 } 1519 1520 /* initiate playback dma */ 1521 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1522 1523 /* set PFIE */ 1524 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1525 1526 if (param->precision * param->factor == 8) 1527 pfie |= PFIE_8BIT; 1528 if (param->channels == 1) 1529 pfie |= PFIE_MONO; 1530 1531 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1532 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1533 pfie |= PFIE_SWAPPED; 1534 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1535 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1536 pfie |= PFIE_UNSIGNED; 1537 1538 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1539 1540 cs4280_set_dac_rate(sc, param->sample_rate); 1541 1542 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1543 pctl |= sc->pctl; 1544 BA1WRITE4(sc, CS4280_PCTL, pctl); 1545 return (0); 1546 } 1547 1548 int 1549 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1550 void *addr; 1551 void *start, *end; 1552 int blksize; 1553 void (*intr) __P((void *)); 1554 void *arg; 1555 struct audio_params *param; 1556 { 1557 struct cs4280_softc *sc = addr; 1558 u_int32_t cctl, cie; 1559 struct cs4280_dma *p; 1560 1561 #ifdef DIAGNOSTIC 1562 if (sc->sc_rrun) 1563 printf("cs4280_trigger_input: already running\n"); 1564 sc->sc_rrun = 1; 1565 #endif 1566 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1567 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1568 sc->sc_rintr = intr; 1569 sc->sc_rarg = arg; 1570 1571 sc->sc_ri = 0; 1572 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1573 sc->sc_rs = (char *)start; 1574 sc->sc_re = (char *)end; 1575 sc->sc_rn = sc->sc_rs; 1576 1577 /* setup format information for internal converter */ 1578 sc->sc_rparam = 0; 1579 if (param->precision == 8) { 1580 sc->sc_rparam += CF_8BIT; 1581 sc->sc_rcount <<= 1; 1582 } 1583 if (param->channels == 1) { 1584 sc->sc_rparam += CF_MONO; 1585 sc->sc_rcount <<= 1; 1586 } 1587 1588 /* stop capture DMA */ 1589 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1590 BA1WRITE4(sc, CS4280_CCTL, cctl); 1591 1592 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1593 ; 1594 if (!p) { 1595 printf("cs4280_trigger_input: bad addr %p\n", start); 1596 return (EINVAL); 1597 } 1598 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1599 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1600 "4kB align\n", DMAADDR(p)); 1601 return (EINVAL); 1602 } 1603 sc->sc_rdma = p; 1604 sc->sc_rbuf = KERNADDR(p); 1605 1606 /* initiate capture dma */ 1607 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1608 1609 /* set CIE */ 1610 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1611 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1612 1613 cs4280_set_adc_rate(sc, param->sample_rate); 1614 1615 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1616 cctl |= sc->cctl; 1617 BA1WRITE4(sc, CS4280_CCTL, cctl); 1618 return (0); 1619 } 1620 1621 int 1622 cs4280_init(sc, init) 1623 struct cs4280_softc *sc; 1624 int init; 1625 { 1626 int n; 1627 u_int32_t mem; 1628 1629 /* Start PLL out in known state */ 1630 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1631 /* Start serial ports out in known state */ 1632 BA0WRITE4(sc, CS4280_SERMC1, 0); 1633 1634 /* Specify type of CODEC */ 1635 /* XXX should no be here */ 1636 #define SERACC_CODEC_TYPE_1_03 1637 #ifdef SERACC_CODEC_TYPE_1_03 1638 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1639 #else 1640 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1641 #endif 1642 1643 /* Reset codec */ 1644 BA0WRITE4(sc, CS4280_ACCTL, 0); 1645 delay(100); /* delay 100us */ 1646 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1647 1648 /* Enable AC-link sync generation */ 1649 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1650 delay(50*1000); /* delay 50ms */ 1651 1652 /* Set the serial port timing configuration */ 1653 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1654 1655 /* Setup clock control */ 1656 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1657 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1658 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1659 1660 /* Power up the PLL */ 1661 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1662 delay(50*1000); /* delay 50ms */ 1663 1664 /* Turn on clock */ 1665 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE); 1666 1667 /* Set the serial port FIFO pointer to the 1668 * first sample in FIFO. (not documented) */ 1669 cs4280_clear_fifos(sc); 1670 1671 #if 0 1672 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1673 BA0WRITE4(sc, CS4280_SERBSP, 0); 1674 #endif 1675 1676 /* Configure the serial port */ 1677 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1678 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1679 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1680 1681 /* Wait for CODEC ready */ 1682 n = 0; 1683 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1684 delay(125); 1685 if (++n > 1000) { 1686 printf("%s: codec ready timeout\n", 1687 sc->sc_dev.dv_xname); 1688 return(1); 1689 } 1690 } 1691 1692 /* Assert valid frame signal */ 1693 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1694 1695 /* Wait for valid AC97 input slot */ 1696 n = 0; 1697 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 1698 delay(1000); 1699 if (++n > 1000) { 1700 printf("AC97 inputs slot ready timeout\n"); 1701 return(1); 1702 } 1703 } 1704 1705 /* Set AC97 output slot valid signals */ 1706 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1707 1708 /* reset the processor */ 1709 cs4280_reset(sc); 1710 1711 /* Download the image to the processor */ 1712 if (cs4280_download_image(sc) != 0) { 1713 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1714 return(1); 1715 } 1716 1717 /* Save playback parameter and then write zero. 1718 * this ensures that DMA doesn't immediately occur upon 1719 * starting the processor core 1720 */ 1721 mem = BA1READ4(sc, CS4280_PCTL); 1722 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1723 cs4280_halt_output(sc); 1724 1725 /* Save capture parameter and then write zero. 1726 * this ensures that DMA doesn't immediately occur upon 1727 * starting the processor core 1728 */ 1729 mem = BA1READ4(sc, CS4280_CCTL); 1730 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1731 cs4280_halt_input(sc); 1732 1733 /* Processor Startup Procedure */ 1734 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1735 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1736 1737 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1738 n = 0; 1739 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1740 delay(10); 1741 if (++n > 1000) { 1742 printf("SPCR 1->0 transition timeout\n"); 1743 return(1); 1744 } 1745 } 1746 1747 n = 0; 1748 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1749 delay(10); 1750 if (++n > 1000) { 1751 printf("SPCS 0->1 transition timeout\n"); 1752 return(1); 1753 } 1754 } 1755 /* Processor is now running !!! */ 1756 1757 /* Setup volume */ 1758 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1759 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1760 1761 /* Interrupt enable */ 1762 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1763 1764 /* playback interrupt enable */ 1765 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1766 mem |= PFIE_PI_ENABLE; 1767 BA1WRITE4(sc, CS4280_PFIE, mem); 1768 /* capture interrupt enable */ 1769 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1770 mem |= CIE_CI_ENABLE; 1771 BA1WRITE4(sc, CS4280_CIE, mem); 1772 1773 #if NMIDI > 0 1774 /* Reset midi port */ 1775 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1776 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1777 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1778 /* midi interrupt enable */ 1779 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1780 BA0WRITE4(sc, CS4280_MIDCR, mem); 1781 #endif 1782 return(0); 1783 } 1784 1785 void 1786 cs4280_power(why, v) 1787 int why; 1788 void *v; 1789 { 1790 struct cs4280_softc *sc = (struct cs4280_softc *)v; 1791 int i; 1792 1793 DPRINTF(("%s: cs4280_power why=%d\n", 1794 sc->sc_dev.dv_xname, why)); 1795 if (why != PWR_RESUME) { 1796 sc->sc_suspend = why; 1797 1798 cs4280_halt_output(sc); 1799 cs4280_halt_input(sc); 1800 /* Save AC97 registers */ 1801 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1802 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1803 continue; 1804 cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i>>1]); 1805 } 1806 /* should I powerdown here ? */ 1807 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1808 } else { 1809 if (sc->sc_suspend == PWR_RESUME) { 1810 printf("cs4280_power: odd, resume without suspend.\n"); 1811 sc->sc_suspend = why; 1812 return; 1813 } 1814 sc->sc_suspend = why; 1815 cs4280_init(sc, 0); 1816 cs4280_reset_codec(sc); 1817 1818 /* restore ac97 registers */ 1819 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1820 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1821 continue; 1822 cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]); 1823 } 1824 } 1825 } 1826 1827 void 1828 cs4280_clear_fifos(sc) 1829 struct cs4280_softc *sc; 1830 { 1831 int pd = 0, cnt, n; 1832 u_int32_t mem; 1833 1834 /* 1835 * If device power down, power up the device and keep power down 1836 * state. 1837 */ 1838 mem = BA0READ4(sc, CS4280_CLKCR1); 1839 if (!(mem & CLKCR1_SWCE)) { 1840 printf("cs4280_clear_fifo: power down found.\n"); 1841 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1842 pd = 1; 1843 } 1844 BA0WRITE4(sc, CS4280_SERBWP, 0); 1845 for (cnt = 0; cnt < 256; cnt++) { 1846 n = 0; 1847 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1848 delay(1000); 1849 if (++n > 1000) { 1850 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1851 break; 1852 } 1853 } 1854 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1855 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1856 } 1857 if (pd) 1858 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1859 } 1860 1861 #if NMIDI > 0 1862 int 1863 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1864 void *addr; 1865 int flags; 1866 void (*iintr)__P((void *, int)); 1867 void (*ointr)__P((void *)); 1868 void *arg; 1869 { 1870 struct cs4280_softc *sc = addr; 1871 u_int32_t mem; 1872 1873 DPRINTF(("midi_open\n")); 1874 sc->sc_iintr = iintr; 1875 sc->sc_ointr = ointr; 1876 sc->sc_arg = arg; 1877 1878 /* midi interrupt enable */ 1879 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1880 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1881 BA0WRITE4(sc, CS4280_MIDCR, mem); 1882 #ifdef CS4280_DEBUG 1883 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1884 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1885 return(EINVAL); 1886 } 1887 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1888 #endif 1889 return (0); 1890 } 1891 1892 void 1893 cs4280_midi_close(addr) 1894 void *addr; 1895 { 1896 struct cs4280_softc *sc = addr; 1897 u_int32_t mem; 1898 1899 DPRINTF(("midi_close\n")); 1900 mem = BA0READ4(sc, CS4280_MIDCR); 1901 mem &= ~MIDCR_MASK; 1902 BA0WRITE4(sc, CS4280_MIDCR, mem); 1903 1904 sc->sc_iintr = 0; 1905 sc->sc_ointr = 0; 1906 } 1907 1908 int 1909 cs4280_midi_output(addr, d) 1910 void *addr; 1911 int d; 1912 { 1913 struct cs4280_softc *sc = addr; 1914 u_int32_t mem; 1915 int x; 1916 1917 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1918 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1919 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1920 mem |= d & MIDWP_MASK; 1921 DPRINTFN(5,("midi_output d=0x%08x",d)); 1922 BA0WRITE4(sc, CS4280_MIDWP, mem); 1923 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1924 DPRINTF(("Bad write data: %d %d", 1925 mem, BA0READ4(sc, CS4280_MIDWP))); 1926 return(EIO); 1927 } 1928 return (0); 1929 } 1930 delay(MIDI_BUSY_DELAY); 1931 } 1932 return (EIO); 1933 } 1934 1935 void 1936 cs4280_midi_getinfo(addr, mi) 1937 void *addr; 1938 struct midi_info *mi; 1939 { 1940 mi->name = "CS4280 MIDI UART"; 1941 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1942 } 1943 1944 #endif 1945
Indexes created Thu Oct 02 14:10:14 GMT 2025