cs4280.c revision 1.4.4.7
1 /* $NetBSD: cs4280.c,v 1.4.4.7 2001/03/13 21:01:14 he Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * 44 */ 45 46 /* 47 * TODO 48 * Joystick support 49 */ 50 51 #if defined(CS4280_DEBUG) 52 #define DPRINTF(x) if (cs4280debug) printf x 53 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 54 int cs4280debug = 0; 55 #else 56 #define DPRINTF(x) 57 #define DPRINTFN(n,x) 58 #endif 59 60 #include "midi.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/fcntl.h> 66 #include <sys/malloc.h> 67 #include <sys/device.h> 68 #include <sys/types.h> 69 #include <sys/systm.h> 70 71 #include <dev/pci/pcidevs.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/cs4280reg.h> 74 #include <dev/pci/cs4280_image.h> 75 76 #include <sys/audioio.h> 77 #include <dev/audio_if.h> 78 #include <dev/midi_if.h> 79 #include <dev/mulaw.h> 80 #include <dev/auconv.h> 81 82 #include <dev/ic/ac97reg.h> 83 #include <dev/ic/ac97var.h> 84 85 #include <machine/bus.h> 86 #include <machine/bswap.h> 87 88 #define CSCC_PCI_BA0 0x10 89 #define CSCC_PCI_BA1 0x14 90 91 struct cs4280_dma { 92 bus_dmamap_t map; 93 caddr_t addr; /* real dma buffer */ 94 caddr_t dum; /* dummy buffer for audio driver */ 95 bus_dma_segment_t segs[1]; 96 int nsegs; 97 size_t size; 98 struct cs4280_dma *next; 99 }; 100 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 101 #define BUFADDR(p) ((void *)((p)->dum)) 102 #define KERNADDR(p) ((void *)((p)->addr)) 103 104 /* 105 * Software state 106 */ 107 struct cs4280_softc { 108 struct device sc_dev; 109 110 pci_intr_handle_t * sc_ih; 111 112 /* I/O (BA0) */ 113 bus_space_tag_t ba0t; 114 bus_space_handle_t ba0h; 115 116 /* BA1 */ 117 bus_space_tag_t ba1t; 118 bus_space_handle_t ba1h; 119 120 /* DMA */ 121 bus_dma_tag_t sc_dmatag; 122 struct cs4280_dma *sc_dmas; 123 124 void (*sc_pintr)(void *); /* dma completion intr handler */ 125 void *sc_parg; /* arg for sc_intr() */ 126 char *sc_ps, *sc_pe, *sc_pn; 127 int sc_pcount; 128 int sc_pi; 129 struct cs4280_dma *sc_pdma; 130 char *sc_pbuf; 131 #ifdef DIAGNOSTIC 132 char sc_prun; 133 #endif 134 135 void (*sc_rintr)(void *); /* dma completion intr handler */ 136 void *sc_rarg; /* arg for sc_intr() */ 137 char *sc_rs, *sc_re, *sc_rn; 138 int sc_rcount; 139 int sc_ri; 140 struct cs4280_dma *sc_rdma; 141 char *sc_rbuf; 142 int sc_rparam; /* record format */ 143 #ifdef DIAGNOSTIC 144 char sc_rrun; 145 #endif 146 147 #if NMIDI > 0 148 void (*sc_iintr)(void *, int); /* midi input ready handler */ 149 void (*sc_ointr)(void *); /* midi output ready handler */ 150 void *sc_arg; 151 #endif 152 153 u_int32_t pctl; 154 u_int32_t cctl; 155 156 struct ac97_codec_if *codec_if; 157 struct ac97_host_if host_if; 158 159 char sc_suspend; 160 void *sc_powerhook; /* Power Hook */ 161 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 162 }; 163 164 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 165 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 166 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 167 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 168 169 int cs4280_match __P((struct device *, struct cfdata *, void *)); 170 void cs4280_attach __P((struct device *, struct device *, void *)); 171 int cs4280_intr __P((void *)); 172 void cs4280_reset __P((void *)); 173 int cs4280_download_image __P((struct cs4280_softc *)); 174 175 int cs4280_download(struct cs4280_softc *, u_int32_t *, u_int32_t, u_int32_t); 176 int cs4280_allocmem __P((struct cs4280_softc *, size_t, size_t, 177 struct cs4280_dma *)); 178 int cs4280_freemem __P((struct cs4280_softc *, struct cs4280_dma *)); 179 180 #ifdef CS4280_DEBUG 181 int cs4280_check_images __P((struct cs4280_softc *)); 182 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 183 u_int32_t); 184 #endif 185 186 struct cfattach clcs_ca = { 187 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 188 }; 189 190 int cs4280_init __P((struct cs4280_softc *, int)); 191 int cs4280_open __P((void *, int)); 192 void cs4280_close __P((void *)); 193 194 int cs4280_query_encoding __P((void *, struct audio_encoding *)); 195 int cs4280_set_params __P((void *, int, int, struct audio_params *, struct audio_params *)); 196 int cs4280_round_blocksize __P((void *, int)); 197 198 int cs4280_halt_output __P((void *)); 199 int cs4280_halt_input __P((void *)); 200 201 int cs4280_getdev __P((void *, struct audio_device *)); 202 203 int cs4280_mixer_set_port __P((void *, mixer_ctrl_t *)); 204 int cs4280_mixer_get_port __P((void *, mixer_ctrl_t *)); 205 int cs4280_query_devinfo __P((void *addr, mixer_devinfo_t *dip)); 206 void *cs4280_malloc __P((void *, int, size_t, int, int)); 207 void cs4280_free __P((void *, void *, int)); 208 size_t cs4280_round_buffersize __P((void *, int, size_t)); 209 paddr_t cs4280_mappage __P((void *, void *, off_t, int)); 210 int cs4280_get_props __P((void *)); 211 int cs4280_trigger_output __P((void *, void *, void *, int, void (*)(void *), 212 void *, struct audio_params *)); 213 int cs4280_trigger_input __P((void *, void *, void *, int, void (*)(void *), 214 void *, struct audio_params *)); 215 216 217 void cs4280_set_dac_rate __P((struct cs4280_softc *, int )); 218 void cs4280_set_adc_rate __P((struct cs4280_softc *, int )); 219 int cs4280_get_portnum_by_name __P((struct cs4280_softc *, char *, char *, 220 char *)); 221 int cs4280_src_wait __P((struct cs4280_softc *)); 222 int cs4280_attach_codec __P((void *sc, struct ac97_codec_if *)); 223 int cs4280_read_codec __P((void *sc, u_int8_t a, u_int16_t *d)); 224 int cs4280_write_codec __P((void *sc, u_int8_t a, u_int16_t d)); 225 void cs4280_reset_codec __P((void *sc)); 226 227 void cs4280_power __P((int, void *)); 228 229 void cs4280_clear_fifos __P((struct cs4280_softc *)); 230 231 #if NMIDI > 0 232 void cs4280_midi_close __P((void*)); 233 void cs4280_midi_getinfo __P((void *, struct midi_info *)); 234 int cs4280_midi_open __P((void *, int, void (*)(void *, int), 235 void (*)(void *), void *)); 236 int cs4280_midi_output __P((void *, int)); 237 #endif 238 239 struct audio_hw_if cs4280_hw_if = { 240 cs4280_open, 241 cs4280_close, 242 NULL, 243 cs4280_query_encoding, 244 cs4280_set_params, 245 cs4280_round_blocksize, 246 NULL, 247 NULL, 248 NULL, 249 NULL, 250 NULL, 251 cs4280_halt_output, 252 cs4280_halt_input, 253 NULL, 254 cs4280_getdev, 255 NULL, 256 cs4280_mixer_set_port, 257 cs4280_mixer_get_port, 258 cs4280_query_devinfo, 259 cs4280_malloc, 260 cs4280_free, 261 cs4280_round_buffersize, 262 cs4280_mappage, 263 cs4280_get_props, 264 cs4280_trigger_output, 265 cs4280_trigger_input, 266 }; 267 268 #if NMIDI > 0 269 struct midi_hw_if cs4280_midi_hw_if = { 270 cs4280_midi_open, 271 cs4280_midi_close, 272 cs4280_midi_output, 273 cs4280_midi_getinfo, 274 0, 275 }; 276 #endif 277 278 279 280 struct audio_device cs4280_device = { 281 "CS4280", 282 "", 283 "cs4280" 284 }; 285 286 287 int 288 cs4280_match(parent, match, aux) 289 struct device *parent; 290 struct cfdata *match; 291 void *aux; 292 { 293 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 294 295 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 296 return (0); 297 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 298 #if 0 /* I can't confirm */ 299 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 300 #endif 301 ) 302 return (1); 303 return (0); 304 } 305 306 int 307 cs4280_read_codec(sc_, add, data) 308 void *sc_; 309 u_int8_t add; 310 u_int16_t *data; 311 { 312 struct cs4280_softc *sc = sc_; 313 int n; 314 315 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 316 /* 317 * Make sure that there is not data sitting around from a preivous 318 * uncompleted access. 319 */ 320 BA0READ4(sc, CS4280_ACSDA); 321 322 /* Set up AC97 control registers. */ 323 BA0WRITE4(sc, CS4280_ACCAD, add); 324 BA0WRITE4(sc, CS4280_ACCDA, 0); 325 BA0WRITE4(sc, CS4280_ACCTL, 326 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 327 328 if (cs4280_src_wait(sc) < 0) { 329 printf("%s: AC97 read prob. (DCV!=0) for add=0x%0x\n", 330 sc->sc_dev.dv_xname, add); 331 return (1); 332 } 333 334 /* wait for valid status bit is active */ 335 n = 0; 336 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 337 delay(1); 338 while (++n > 1000) { 339 printf("%s: AC97 read fail (VSTS==0) for add=0x%0x\n", 340 sc->sc_dev.dv_xname, add); 341 return (1); 342 } 343 } 344 *data = BA0READ4(sc, CS4280_ACSDA); 345 DPRINTFN(5,("data=0x%04x\n", *data)); 346 return (0); 347 } 348 349 int 350 cs4280_write_codec(sc_, add, data) 351 void *sc_; 352 u_int8_t add; 353 u_int16_t data; 354 { 355 struct cs4280_softc *sc = sc_; 356 357 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 358 BA0WRITE4(sc, CS4280_ACCAD, add); 359 BA0WRITE4(sc, CS4280_ACCDA, data); 360 BA0WRITE4(sc, CS4280_ACCTL, 361 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 362 363 if (cs4280_src_wait(sc) < 0) { 364 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 365 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 366 return (1); 367 } 368 return (0); 369 } 370 371 int 372 cs4280_src_wait(sc) 373 struct cs4280_softc *sc; 374 { 375 int n; 376 n = 0; 377 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 378 delay(1000); 379 while (++n > 1000) 380 return (-1); 381 } 382 return (0); 383 } 384 385 386 void 387 cs4280_set_adc_rate(sc, rate) 388 struct cs4280_softc *sc; 389 int rate; 390 { 391 /* calculate capture rate: 392 * 393 * capture_coefficient_increment = -round(rate*128*65536/48000; 394 * capture_phase_increment = floor(48000*65536*1024/rate); 395 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 396 * cy = floor(cx/200); 397 * capture_sample_rate_correction = cx - 200*cy; 398 * capture_delay = ceil(24*48000/rate); 399 * capture_num_triplets = floor(65536*rate/24000); 400 * capture_group_length = 24000/GCD(rate, 24000); 401 * where GCD means "Greatest Common Divisor". 402 * 403 * capture_coefficient_increment, capture_phase_increment and 404 * capture_num_triplets are 32-bit signed quantities. 405 * capture_sample_rate_correction and capture_group_length are 406 * 16-bit signed quantities. 407 * capture_delay is a 14-bit unsigned quantity. 408 */ 409 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 410 u_int16_t csrc, cgl, cdlay; 411 412 /* XXX 413 * Even though, embedded_audio_spec says capture rate range 11025 to 414 * 48000, dhwiface.cpp says, 415 * 416 * "We can only decimate by up to a factor of 1/9th the hardware rate. 417 * Return an error if an attempt is made to stray outside that limit." 418 * 419 * so assume range as 48000/9 to 48000 420 */ 421 422 if (rate < 8000) 423 rate = 8000; 424 if (rate > 48000) 425 rate = 48000; 426 427 cx = rate << 16; 428 cci = cx / 48000; 429 cx -= cci * 48000; 430 cx <<= 7; 431 cci <<= 7; 432 cci += cx / 48000; 433 cci = - cci; 434 435 cx = 48000 << 16; 436 cpi = cx / rate; 437 cx -= cpi * rate; 438 cx <<= 10; 439 cpi <<= 10; 440 cy = cx / rate; 441 cpi += cy; 442 cx -= cy * rate; 443 444 cy = cx / 200; 445 csrc = cx - 200*cy; 446 447 cdlay = ((48000 * 24) + rate - 1) / rate; 448 #if 0 449 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 450 #endif 451 452 cnt = rate << 16; 453 cnt /= 24000; 454 455 cgl = 1; 456 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 457 if (((rate / tmp1) * tmp1) != rate) 458 cgl *= 2; 459 } 460 if (((rate / 3) * 3) != rate) 461 cgl *= 3; 462 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 463 if (((rate / tmp1) * tmp1) != rate) 464 cgl *= 5; 465 } 466 #if 0 467 /* XXX what manual says */ 468 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 469 tmp1 |= csrc<<16; 470 BA1WRITE4(sc, CS4280_CSRC, tmp1); 471 #else 472 /* suggested by cs461x.c (ALSA driver) */ 473 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 474 #endif 475 476 #if 0 477 /* I am confused. The sample rate calculation section says 478 * cci *is* 32-bit signed quantity but in the parameter description 479 * section, CCI only assigned 16bit. 480 * I believe size of the variable. 481 */ 482 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 483 tmp1 |= cci<<16; 484 BA1WRITE4(sc, CS4280_CCI, tmp1); 485 #else 486 BA1WRITE4(sc, CS4280_CCI, cci); 487 #endif 488 489 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 490 tmp1 |= cdlay <<18; 491 BA1WRITE4(sc, CS4280_CD, tmp1); 492 493 BA1WRITE4(sc, CS4280_CPI, cpi); 494 495 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 496 tmp1 |= cgl; 497 BA1WRITE4(sc, CS4280_CGL, tmp1); 498 499 BA1WRITE4(sc, CS4280_CNT, cnt); 500 501 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 502 tmp1 |= cgl; 503 BA1WRITE4(sc, CS4280_CGC, tmp1); 504 } 505 506 void 507 cs4280_set_dac_rate(sc, rate) 508 struct cs4280_softc *sc; 509 int rate; 510 { 511 /* 512 * playback rate may range from 8000Hz to 48000Hz 513 * 514 * play_phase_increment = floor(rate*65536*1024/48000) 515 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 516 * py=floor(px/200) 517 * play_sample_rate_correction = px - 200*py 518 * 519 * play_phase_increment is a 32bit signed quantity. 520 * play_sample_rate_correction is a 16bit signed quantity. 521 */ 522 int32_t ppi; 523 int16_t psrc; 524 u_int32_t px, py; 525 526 if (rate < 8000) 527 rate = 8000; 528 if (rate > 48000) 529 rate = 48000; 530 px = rate << 16; 531 ppi = px/48000; 532 px -= ppi*48000; 533 ppi <<= 10; 534 px <<= 10; 535 py = px / 48000; 536 ppi += py; 537 px -= py*48000; 538 py = px/200; 539 px -= py*200; 540 psrc = px; 541 #if 0 542 /* what manual says */ 543 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 544 BA1WRITE4(sc, CS4280_PSRC, 545 ( ((psrc<<16) & PSRC_MASK) | px )); 546 #else 547 /* suggested by cs461x.c (ALSA driver) */ 548 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 549 #endif 550 BA1WRITE4(sc, CS4280_PPI, ppi); 551 } 552 553 void 554 cs4280_attach(parent, self, aux) 555 struct device *parent; 556 struct device *self; 557 void *aux; 558 { 559 struct cs4280_softc *sc = (struct cs4280_softc *)self; 560 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 561 pci_chipset_tag_t pc = pa->pa_pc; 562 char const *intrstr; 563 pci_intr_handle_t ih; 564 pcireg_t reg; 565 char devinfo[256]; 566 mixer_ctrl_t ctl; 567 u_int32_t mem; 568 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 569 570 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 571 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 572 573 /* Map I/O register */ 574 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 575 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 576 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 577 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 578 return; 579 } 580 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 581 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 582 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 583 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 584 return; 585 } 586 587 sc->sc_dmatag = pa->pa_dmat; 588 589 /* Check and set Power State */ 590 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 591 &pci_pwrmgmt_cap_reg, 0)) { 592 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 593 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 594 pci_pwrmgmt_csr_reg); 595 DPRINTF(("%s: Power State is %d\n", 596 sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK)); 597 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 598 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 599 (reg & ~PCI_PMCSR_STATE_MASK) | 600 PCI_PMCSR_STATE_D0); 601 } 602 } 603 604 /* Enable the device (set bus master flag) */ 605 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 606 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 607 reg | PCI_COMMAND_MASTER_ENABLE); 608 609 /* LATENCY_TIMER setting */ 610 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 611 if ( PCI_LATTIMER(mem) < 32 ) { 612 mem &= 0xffff00ff; 613 mem |= 0x00002000; 614 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 615 } 616 617 /* Map and establish the interrupt. */ 618 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 619 pa->pa_intrline, &ih)) { 620 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 621 return; 622 } 623 intrstr = pci_intr_string(pc, ih); 624 625 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 626 if (sc->sc_ih == NULL) { 627 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 628 if (intrstr != NULL) 629 printf(" at %s", intrstr); 630 printf("\n"); 631 return; 632 } 633 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 634 635 /* Initialization */ 636 if(cs4280_init(sc, 1) != 0) 637 return; 638 639 /* AC 97 attachement */ 640 sc->host_if.arg = sc; 641 sc->host_if.attach = cs4280_attach_codec; 642 sc->host_if.read = cs4280_read_codec; 643 sc->host_if.write = cs4280_write_codec; 644 sc->host_if.reset = cs4280_reset_codec; 645 646 if (ac97_attach(&sc->host_if) != 0) { 647 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 648 return; 649 } 650 651 /* Turn mute off of DAC, CD and master volumes by default */ 652 ctl.type = AUDIO_MIXER_ENUM; 653 ctl.un.ord = 0; /* off */ 654 655 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 656 AudioNmaster, AudioNmute); 657 cs4280_mixer_set_port(sc, &ctl); 658 659 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 660 AudioNdac, AudioNmute); 661 cs4280_mixer_set_port(sc, &ctl); 662 663 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 664 AudioNcd, AudioNmute); 665 cs4280_mixer_set_port(sc, &ctl); 666 667 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 668 669 #if NMIDI > 0 670 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 671 #endif 672 sc->sc_suspend = PWR_RESUME; 673 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 674 } 675 676 int 677 cs4280_intr(p) 678 void *p; 679 { 680 /* 681 * XXX 682 * 683 * Since CS4280 has only 4kB dma buffer and 684 * interrupt occurs every 2kB block, I create dummy buffer 685 * which returns to audio driver and actual dma buffer 686 * using in DMA transfer. 687 * 688 * 689 * ring buffer in audio.c is pointed by BUFADDR 690 * <------ ring buffer size == 64kB ------> 691 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 692 * |= = = =|= = = =|= = = =|= = = =|= = = =| 693 * | | | | | | <- call audio_intp every 694 * sc->sc_[pr]_count time. 695 * 696 * actual dma buffer is pointed by KERNADDR 697 * <-> dma buffer size = 4kB 698 * |= =| 699 * 700 * 701 */ 702 struct cs4280_softc *sc = p; 703 u_int32_t intr, mem; 704 char * empty_dma; 705 706 intr = BA0READ4(sc, CS4280_HISR); 707 708 if ((intr & HISR_INTENA) == 0) { 709 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 710 return (0); 711 } 712 713 /* Playback Interrupt */ 714 if (intr & HISR_PINT) { 715 mem = BA1READ4(sc, CS4280_PFIE); 716 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 717 if (sc->sc_pintr) { 718 if ((sc->sc_pi%sc->sc_pcount) == 0) 719 sc->sc_pintr(sc->sc_parg); 720 } else { 721 printf("unexpected play intr\n"); 722 } 723 /* copy buffer */ 724 ++sc->sc_pi; 725 empty_dma = sc->sc_pdma->addr; 726 if (sc->sc_pi&1) 727 empty_dma += CS4280_ICHUNK; 728 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 729 sc->sc_pn += CS4280_ICHUNK; 730 if (sc->sc_pn >= sc->sc_pe) 731 sc->sc_pn = sc->sc_ps; 732 BA1WRITE4(sc, CS4280_PFIE, mem); 733 } 734 /* Capture Interrupt */ 735 if (intr & HISR_CINT) { 736 int i; 737 int16_t rdata; 738 739 mem = BA1READ4(sc, CS4280_CIE); 740 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 741 ++sc->sc_ri; 742 empty_dma = sc->sc_rdma->addr; 743 if ((sc->sc_ri&1) == 0) 744 empty_dma += CS4280_ICHUNK; 745 746 /* 747 * XXX 748 * I think this audio data conversion should be 749 * happend in upper layer, but I put this here 750 * since there is no conversion function available. 751 */ 752 switch(sc->sc_rparam) { 753 case CF_16BIT_STEREO: 754 /* just copy it */ 755 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 756 sc->sc_rn += CS4280_ICHUNK; 757 break; 758 case CF_16BIT_MONO: 759 for (i = 0; i < 512; i++) { 760 rdata = *((int16_t *)empty_dma)++>>1; 761 rdata += *((int16_t *)empty_dma)++>>1; 762 *((int16_t *)sc->sc_rn)++ = rdata; 763 } 764 break; 765 case CF_8BIT_STEREO: 766 for (i = 0; i < 512; i++) { 767 rdata = *((int16_t*)empty_dma)++; 768 *sc->sc_rn++ = rdata >> 8; 769 rdata = *((int16_t*)empty_dma)++; 770 *sc->sc_rn++ = rdata >> 8; 771 } 772 break; 773 case CF_8BIT_MONO: 774 for (i = 0; i < 512; i++) { 775 rdata = *((int16_t*)empty_dma)++ >>1; 776 rdata += *((int16_t*)empty_dma)++ >>1; 777 *sc->sc_rn++ = rdata >>8; 778 } 779 break; 780 default: 781 /* Should not reach here */ 782 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 783 } 784 if (sc->sc_rn >= sc->sc_re) 785 sc->sc_rn = sc->sc_rs; 786 BA1WRITE4(sc, CS4280_CIE, mem); 787 if (sc->sc_rintr) { 788 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 789 sc->sc_rintr(sc->sc_rarg); 790 } else { 791 printf("unexpected record intr\n"); 792 } 793 } 794 795 #if NMIDI > 0 796 /* Midi port Interrupt */ 797 if (intr & HISR_MIDI) { 798 int data; 799 800 DPRINTF(("i: %d: ", 801 BA0READ4(sc, CS4280_MIDSR))); 802 /* Read the received data */ 803 while ((sc->sc_iintr != NULL) && 804 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 805 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 806 DPRINTF(("r:%x\n",data)); 807 sc->sc_iintr(sc->sc_arg, data); 808 } 809 810 /* Write the data */ 811 #if 1 812 /* XXX: 813 * It seems "Transmit Buffer Full" never activate until EOI 814 * is deliverd. Shall I throw EOI top of this routine ? 815 */ 816 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 817 DPRINTF(("w: ")); 818 if (sc->sc_ointr != NULL) 819 sc->sc_ointr(sc->sc_arg); 820 } 821 #else 822 while ((sc->sc_ointr != NULL) && 823 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 824 DPRINTF(("w: ")); 825 sc->sc_ointr(sc->sc_arg); 826 } 827 #endif 828 DPRINTF(("\n")); 829 } 830 #endif 831 /* Throw EOI */ 832 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 833 return (1); 834 } 835 836 837 /* Download Proceessor Code and Data image */ 838 839 int 840 cs4280_download(sc, src, offset, len) 841 struct cs4280_softc *sc; 842 u_int32_t *src; 843 u_int32_t offset, len; 844 { 845 u_int32_t ctr; 846 847 #ifdef CS4280_DEBUG 848 u_int32_t con, data; 849 u_int8_t c0,c1,c2,c3; 850 #endif 851 if ((offset&3) || (len&3)) 852 return (-1); 853 854 len /= sizeof(u_int32_t); 855 for (ctr = 0; ctr < len; ctr++) { 856 /* XXX: 857 * I cannot confirm this is the right thing or not 858 * on BIG-ENDIAN machines. 859 */ 860 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 861 #ifdef CS4280_DEBUG 862 data = htole32(*(src+ctr)); 863 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 864 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 865 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 866 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 867 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 868 if (data != con ) { 869 printf("0x%06x: write=0x%08x read=0x%08x\n", 870 offset+ctr*4, data, con); 871 return (-1); 872 } 873 #endif 874 } 875 return (0); 876 } 877 878 int 879 cs4280_download_image(sc) 880 struct cs4280_softc *sc; 881 { 882 int idx, err; 883 u_int32_t offset = 0; 884 885 err = 0; 886 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 887 err = cs4280_download(sc, &BA1Struct.map[offset], 888 BA1Struct.memory[idx].offset, 889 BA1Struct.memory[idx].size); 890 if (err != 0) { 891 printf("%s: load_image failed at %d\n", 892 sc->sc_dev.dv_xname, idx); 893 return (-1); 894 } 895 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 896 } 897 return (err); 898 } 899 900 #ifdef CS4280_DEBUG 901 int 902 cs4280_checkimage(sc, src, offset, len) 903 struct cs4280_softc *sc; 904 u_int32_t *src; 905 u_int32_t offset, len; 906 { 907 u_int32_t ctr, data; 908 int err = 0; 909 910 if ((offset&3) || (len&3)) 911 return -1; 912 913 len /= sizeof(u_int32_t); 914 for (ctr = 0; ctr < len; ctr++) { 915 /* I cannot confirm this is the right thing 916 * on BIG-ENDIAN machines 917 */ 918 data = BA1READ4(sc, offset+ctr*4); 919 if (data != htole32(*(src+ctr))) { 920 printf("0x%06x: 0x%08x(0x%08x)\n", 921 offset+ctr*4, data, *(src+ctr)); 922 *(src+ctr) = data; 923 ++err; 924 } 925 } 926 return (err); 927 } 928 929 int 930 cs4280_check_images(sc) 931 struct cs4280_softc *sc; 932 { 933 int idx, err; 934 u_int32_t offset = 0; 935 936 err = 0; 937 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 938 for (idx = 0; idx < 1; ++idx) { 939 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 940 BA1Struct.memory[idx].offset, 941 BA1Struct.memory[idx].size); 942 if (err != 0) { 943 printf("%s: check_image failed at %d\n", 944 sc->sc_dev.dv_xname, idx); 945 } 946 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 947 } 948 return (err); 949 } 950 951 #endif 952 953 int 954 cs4280_attach_codec(sc_, codec_if) 955 void *sc_; 956 struct ac97_codec_if *codec_if; 957 { 958 struct cs4280_softc *sc = sc_; 959 960 sc->codec_if = codec_if; 961 return (0); 962 } 963 964 void 965 cs4280_reset_codec(sc_) 966 void *sc_; 967 { 968 struct cs4280_softc *sc = sc_; 969 int n; 970 971 /* Reset codec */ 972 BA0WRITE4(sc, CS4280_ACCTL, 0); 973 delay(100); /* delay 100us */ 974 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 975 976 /* 977 * It looks like we do the following procedure, too 978 */ 979 980 /* Enable AC-link sync generation */ 981 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 982 delay(50*1000); /* XXX delay 50ms */ 983 984 /* Assert valid frame signal */ 985 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 986 987 /* Wait for valid AC97 input slot */ 988 n = 0; 989 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 990 (ACISV_ISV3 | ACISV_ISV4)) { 991 delay(1000); 992 if (++n > 1000) { 993 printf("reset_codec: AC97 inputs slot ready timeout\n"); 994 return; 995 } 996 } 997 } 998 999 1000 /* Processor Soft Reset */ 1001 void 1002 cs4280_reset(sc_) 1003 void *sc_; 1004 { 1005 struct cs4280_softc *sc = sc_; 1006 1007 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1008 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1009 delay(100); 1010 /* Clear RSTSP bit in SPCR */ 1011 BA1WRITE4(sc, CS4280_SPCR, 0); 1012 /* enable DMA reqest */ 1013 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1014 } 1015 1016 int 1017 cs4280_open(addr, flags) 1018 void *addr; 1019 int flags; 1020 { 1021 return (0); 1022 } 1023 1024 void 1025 cs4280_close(addr) 1026 void *addr; 1027 { 1028 struct cs4280_softc *sc = addr; 1029 1030 cs4280_halt_output(sc); 1031 cs4280_halt_input(sc); 1032 1033 sc->sc_pintr = 0; 1034 sc->sc_rintr = 0; 1035 } 1036 1037 int 1038 cs4280_query_encoding(addr, fp) 1039 void *addr; 1040 struct audio_encoding *fp; 1041 { 1042 switch (fp->index) { 1043 case 0: 1044 strcpy(fp->name, AudioEulinear); 1045 fp->encoding = AUDIO_ENCODING_ULINEAR; 1046 fp->precision = 8; 1047 fp->flags = 0; 1048 break; 1049 case 1: 1050 strcpy(fp->name, AudioEmulaw); 1051 fp->encoding = AUDIO_ENCODING_ULAW; 1052 fp->precision = 8; 1053 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1054 break; 1055 case 2: 1056 strcpy(fp->name, AudioEalaw); 1057 fp->encoding = AUDIO_ENCODING_ALAW; 1058 fp->precision = 8; 1059 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1060 break; 1061 case 3: 1062 strcpy(fp->name, AudioEslinear); 1063 fp->encoding = AUDIO_ENCODING_SLINEAR; 1064 fp->precision = 8; 1065 fp->flags = 0; 1066 break; 1067 case 4: 1068 strcpy(fp->name, AudioEslinear_le); 1069 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1070 fp->precision = 16; 1071 fp->flags = 0; 1072 break; 1073 case 5: 1074 strcpy(fp->name, AudioEulinear_le); 1075 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1076 fp->precision = 16; 1077 fp->flags = 0; 1078 break; 1079 case 6: 1080 strcpy(fp->name, AudioEslinear_be); 1081 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1082 fp->precision = 16; 1083 fp->flags = 0; 1084 break; 1085 case 7: 1086 strcpy(fp->name, AudioEulinear_be); 1087 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1088 fp->precision = 16; 1089 fp->flags = 0; 1090 break; 1091 default: 1092 return (EINVAL); 1093 } 1094 return (0); 1095 } 1096 1097 int 1098 cs4280_set_params(addr, setmode, usemode, play, rec) 1099 void *addr; 1100 int setmode, usemode; 1101 struct audio_params *play, *rec; 1102 { 1103 struct cs4280_softc *sc = addr; 1104 struct audio_params *p; 1105 int mode; 1106 1107 for (mode = AUMODE_RECORD; mode != -1; 1108 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1109 if ((setmode & mode) == 0) 1110 continue; 1111 1112 p = mode == AUMODE_PLAY ? play : rec; 1113 1114 if (p == play) { 1115 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1116 p->sample_rate, p->precision, p->channels)); 1117 /* play back data format may be 8- or 16-bit and 1118 * either stereo or mono. 1119 * playback rate may range from 8000Hz to 48000Hz 1120 */ 1121 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1122 (p->precision != 8 && p->precision != 16) || 1123 (p->channels != 1 && p->channels != 2) ) { 1124 return (EINVAL); 1125 } 1126 } else { 1127 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1128 p->sample_rate, p->precision, p->channels)); 1129 /* capture data format must be 16bit stereo 1130 * and sample rate range from 11025Hz to 48000Hz. 1131 * 1132 * XXX: it looks like to work with 8000Hz, 1133 * although data sheets say lower limit is 1134 * 11025 Hz. 1135 */ 1136 1137 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1138 (p->precision != 8 && p->precision != 16) || 1139 (p->channels != 1 && p->channels != 2) ) { 1140 return (EINVAL); 1141 } 1142 } 1143 p->factor = 1; 1144 p->sw_code = 0; 1145 1146 /* capturing data is slinear */ 1147 switch (p->encoding) { 1148 case AUDIO_ENCODING_SLINEAR_BE: 1149 if (mode == AUMODE_RECORD) { 1150 if (p->precision == 16) 1151 p->sw_code = swap_bytes; 1152 } 1153 break; 1154 case AUDIO_ENCODING_SLINEAR_LE: 1155 break; 1156 case AUDIO_ENCODING_ULINEAR_BE: 1157 if (mode == AUMODE_RECORD) { 1158 if (p->precision == 16) 1159 p->sw_code = change_sign16_swap_bytes_le; 1160 else 1161 p->sw_code = change_sign8; 1162 } 1163 break; 1164 case AUDIO_ENCODING_ULINEAR_LE: 1165 if (mode == AUMODE_RECORD) { 1166 if (p->precision == 16) 1167 p->sw_code = change_sign16_le; 1168 else 1169 p->sw_code = change_sign8; 1170 } 1171 break; 1172 case AUDIO_ENCODING_ULAW: 1173 if (mode == AUMODE_PLAY) { 1174 p->factor = 2; 1175 p->sw_code = mulaw_to_slinear16_le; 1176 } else { 1177 p->sw_code = slinear8_to_mulaw; 1178 } 1179 break; 1180 case AUDIO_ENCODING_ALAW: 1181 if (mode == AUMODE_PLAY) { 1182 p->factor = 2; 1183 p->sw_code = alaw_to_slinear16_le; 1184 } else { 1185 p->sw_code = slinear8_to_alaw; 1186 } 1187 break; 1188 default: 1189 return (EINVAL); 1190 } 1191 } 1192 1193 /* set sample rate */ 1194 cs4280_set_dac_rate(sc, play->sample_rate); 1195 cs4280_set_adc_rate(sc, rec->sample_rate); 1196 return (0); 1197 } 1198 1199 int 1200 cs4280_round_blocksize(hdl, blk) 1201 void *hdl; 1202 int blk; 1203 { 1204 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1205 } 1206 1207 size_t 1208 cs4280_round_buffersize(addr, direction, size) 1209 void *addr; 1210 int direction; 1211 size_t size; 1212 { 1213 /* although real dma buffer size is 4KB, 1214 * let the audio.c driver use a larger buffer. 1215 * ( suggested by Lennart Augustsson. ) 1216 */ 1217 return (size); 1218 } 1219 1220 int 1221 cs4280_get_props(hdl) 1222 void *hdl; 1223 { 1224 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1225 #ifdef notyet 1226 /* XXX 1227 * How can I mmap ? 1228 */ 1229 AUDIO_PROP_MMAP 1230 #endif 1231 1232 } 1233 1234 int 1235 cs4280_mixer_get_port(addr, cp) 1236 void *addr; 1237 mixer_ctrl_t *cp; 1238 { 1239 struct cs4280_softc *sc = addr; 1240 1241 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1242 } 1243 1244 paddr_t 1245 cs4280_mappage(addr, mem, off, prot) 1246 void *addr; 1247 void *mem; 1248 off_t off; 1249 int prot; 1250 { 1251 struct cs4280_softc *sc = addr; 1252 struct cs4280_dma *p; 1253 1254 if (off < 0) 1255 return (-1); 1256 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1257 ; 1258 if (!p) { 1259 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1260 return (-1); 1261 } 1262 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1263 off, prot, BUS_DMA_WAITOK)); 1264 } 1265 1266 1267 int 1268 cs4280_query_devinfo(addr, dip) 1269 void *addr; 1270 mixer_devinfo_t *dip; 1271 { 1272 struct cs4280_softc *sc = addr; 1273 1274 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1275 } 1276 1277 int 1278 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1279 struct cs4280_softc *sc; 1280 char *class, *device, *qualifier; 1281 { 1282 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1283 device, qualifier)); 1284 } 1285 1286 int 1287 cs4280_halt_output(addr) 1288 void *addr; 1289 { 1290 struct cs4280_softc *sc = addr; 1291 u_int32_t mem; 1292 1293 mem = BA1READ4(sc, CS4280_PCTL); 1294 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1295 #ifdef DIAGNOSTIC 1296 sc->sc_prun = 0; 1297 #endif 1298 return (0); 1299 } 1300 1301 int 1302 cs4280_halt_input(addr) 1303 void *addr; 1304 { 1305 struct cs4280_softc *sc = addr; 1306 u_int32_t mem; 1307 1308 mem = BA1READ4(sc, CS4280_CCTL); 1309 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1310 #ifdef DIAGNOSTIC 1311 sc->sc_rrun = 0; 1312 #endif 1313 return (0); 1314 } 1315 1316 int 1317 cs4280_getdev(addr, retp) 1318 void *addr; 1319 struct audio_device *retp; 1320 { 1321 *retp = cs4280_device; 1322 return (0); 1323 } 1324 1325 int 1326 cs4280_mixer_set_port(addr, cp) 1327 void *addr; 1328 mixer_ctrl_t *cp; 1329 { 1330 struct cs4280_softc *sc = addr; 1331 int val; 1332 1333 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1334 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1335 return (val); 1336 } 1337 1338 1339 int 1340 cs4280_freemem(sc, p) 1341 struct cs4280_softc *sc; 1342 struct cs4280_dma *p; 1343 { 1344 bus_dmamap_unload(sc->sc_dmatag, p->map); 1345 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1346 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1347 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1348 return (0); 1349 } 1350 1351 int 1352 cs4280_allocmem(sc, size, align, p) 1353 struct cs4280_softc *sc; 1354 size_t size; 1355 size_t align; 1356 struct cs4280_dma *p; 1357 { 1358 int error; 1359 1360 /* XXX */ 1361 p->size = size; 1362 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1363 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1364 &p->nsegs, BUS_DMA_NOWAIT); 1365 if (error) { 1366 printf("%s: unable to allocate dma, error=%d\n", 1367 sc->sc_dev.dv_xname, error); 1368 return (error); 1369 } 1370 1371 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1372 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1373 if (error) { 1374 printf("%s: unable to map dma, error=%d\n", 1375 sc->sc_dev.dv_xname, error); 1376 goto free; 1377 } 1378 1379 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1380 0, BUS_DMA_NOWAIT, &p->map); 1381 if (error) { 1382 printf("%s: unable to create dma map, error=%d\n", 1383 sc->sc_dev.dv_xname, error); 1384 goto unmap; 1385 } 1386 1387 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1388 BUS_DMA_NOWAIT); 1389 if (error) { 1390 printf("%s: unable to load dma map, error=%d\n", 1391 sc->sc_dev.dv_xname, error); 1392 goto destroy; 1393 } 1394 return (0); 1395 1396 destroy: 1397 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1398 unmap: 1399 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1400 free: 1401 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1402 return (error); 1403 } 1404 1405 1406 void * 1407 cs4280_malloc(addr, direction, size, pool, flags) 1408 void *addr; 1409 int direction; 1410 size_t size; 1411 int pool, flags; 1412 { 1413 struct cs4280_softc *sc = addr; 1414 struct cs4280_dma *p; 1415 caddr_t q; 1416 int error; 1417 1418 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1419 q = malloc(size, pool, flags); 1420 if (!q) 1421 return (0); 1422 p = malloc(sizeof(*p), pool, flags); 1423 if (!p) { 1424 free(q,pool); 1425 return (0); 1426 } 1427 /* 1428 * cs4280 has fixed 4kB buffer 1429 */ 1430 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1431 1432 if (error) { 1433 free(q, pool); 1434 free(p, pool); 1435 return (0); 1436 } 1437 1438 p->next = sc->sc_dmas; 1439 sc->sc_dmas = p; 1440 p->dum = q; /* return to audio driver */ 1441 1442 return (p->dum); 1443 } 1444 1445 void 1446 cs4280_free(addr, ptr, pool) 1447 void *addr; 1448 void *ptr; 1449 int pool; 1450 { 1451 struct cs4280_softc *sc = addr; 1452 struct cs4280_dma **pp, *p; 1453 1454 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1455 if (BUFADDR(p) == ptr) { 1456 cs4280_freemem(sc, p); 1457 *pp = p->next; 1458 free(p->dum, pool); 1459 free(p, pool); 1460 return; 1461 } 1462 } 1463 } 1464 1465 int 1466 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1467 void *addr; 1468 void *start, *end; 1469 int blksize; 1470 void (*intr) __P((void *)); 1471 void *arg; 1472 struct audio_params *param; 1473 { 1474 struct cs4280_softc *sc = addr; 1475 u_int32_t pfie, pctl, mem, pdtc; 1476 struct cs4280_dma *p; 1477 1478 #ifdef DIAGNOSTIC 1479 if (sc->sc_prun) 1480 printf("cs4280_trigger_output: already running\n"); 1481 sc->sc_prun = 1; 1482 #endif 1483 1484 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1485 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1486 sc->sc_pintr = intr; 1487 sc->sc_parg = arg; 1488 1489 /* stop playback DMA */ 1490 mem = BA1READ4(sc, CS4280_PCTL); 1491 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1492 1493 /* setup PDTC */ 1494 pdtc = BA1READ4(sc, CS4280_PDTC); 1495 pdtc &= ~PDTC_MASK; 1496 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1497 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1498 1499 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1500 param->precision, param->factor, param->channels, 1501 param->encoding)); 1502 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1503 ; 1504 if (p == NULL) { 1505 printf("cs4280_trigger_output: bad addr %p\n", start); 1506 return (EINVAL); 1507 } 1508 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1509 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1510 "4kB align\n", DMAADDR(p)); 1511 return (EINVAL); 1512 } 1513 1514 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1515 sc->sc_ps = (char *)start; 1516 sc->sc_pe = (char *)end; 1517 sc->sc_pdma = p; 1518 sc->sc_pbuf = KERNADDR(p); 1519 sc->sc_pi = 0; 1520 sc->sc_pn = sc->sc_ps; 1521 if (blksize >= CS4280_DCHUNK) { 1522 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1523 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1524 ++sc->sc_pi; 1525 } else { 1526 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1527 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1528 } 1529 1530 /* initiate playback dma */ 1531 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1532 1533 /* set PFIE */ 1534 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1535 1536 if (param->precision * param->factor == 8) 1537 pfie |= PFIE_8BIT; 1538 if (param->channels == 1) 1539 pfie |= PFIE_MONO; 1540 1541 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1542 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1543 pfie |= PFIE_SWAPPED; 1544 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1545 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1546 pfie |= PFIE_UNSIGNED; 1547 1548 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1549 1550 cs4280_set_dac_rate(sc, param->sample_rate); 1551 1552 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1553 pctl |= sc->pctl; 1554 BA1WRITE4(sc, CS4280_PCTL, pctl); 1555 return (0); 1556 } 1557 1558 int 1559 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1560 void *addr; 1561 void *start, *end; 1562 int blksize; 1563 void (*intr) __P((void *)); 1564 void *arg; 1565 struct audio_params *param; 1566 { 1567 struct cs4280_softc *sc = addr; 1568 u_int32_t cctl, cie; 1569 struct cs4280_dma *p; 1570 1571 #ifdef DIAGNOSTIC 1572 if (sc->sc_rrun) 1573 printf("cs4280_trigger_input: already running\n"); 1574 sc->sc_rrun = 1; 1575 #endif 1576 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1577 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1578 sc->sc_rintr = intr; 1579 sc->sc_rarg = arg; 1580 1581 sc->sc_ri = 0; 1582 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1583 sc->sc_rs = (char *)start; 1584 sc->sc_re = (char *)end; 1585 sc->sc_rn = sc->sc_rs; 1586 1587 /* setup format information for internal converter */ 1588 sc->sc_rparam = 0; 1589 if (param->precision == 8) { 1590 sc->sc_rparam += CF_8BIT; 1591 sc->sc_rcount <<= 1; 1592 } 1593 if (param->channels == 1) { 1594 sc->sc_rparam += CF_MONO; 1595 sc->sc_rcount <<= 1; 1596 } 1597 1598 /* stop capture DMA */ 1599 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1600 BA1WRITE4(sc, CS4280_CCTL, cctl); 1601 1602 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1603 ; 1604 if (!p) { 1605 printf("cs4280_trigger_input: bad addr %p\n", start); 1606 return (EINVAL); 1607 } 1608 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1609 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1610 "4kB align\n", DMAADDR(p)); 1611 return (EINVAL); 1612 } 1613 sc->sc_rdma = p; 1614 sc->sc_rbuf = KERNADDR(p); 1615 1616 /* initiate capture dma */ 1617 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1618 1619 /* set CIE */ 1620 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1621 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1622 1623 cs4280_set_adc_rate(sc, param->sample_rate); 1624 1625 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1626 cctl |= sc->cctl; 1627 BA1WRITE4(sc, CS4280_CCTL, cctl); 1628 return (0); 1629 } 1630 1631 int 1632 cs4280_init(sc, init) 1633 struct cs4280_softc *sc; 1634 int init; 1635 { 1636 int n; 1637 u_int32_t mem; 1638 1639 /* Start PLL out in known state */ 1640 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1641 /* Start serial ports out in known state */ 1642 BA0WRITE4(sc, CS4280_SERMC1, 0); 1643 1644 /* Specify type of CODEC */ 1645 /* XXX should not be here */ 1646 #define SERACC_CODEC_TYPE_1_03 1647 #ifdef SERACC_CODEC_TYPE_1_03 1648 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1649 #else 1650 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1651 #endif 1652 1653 /* Reset codec */ 1654 BA0WRITE4(sc, CS4280_ACCTL, 0); 1655 delay(100); /* delay 100us */ 1656 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1657 1658 /* Enable AC-link sync generation */ 1659 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1660 delay(50*1000); /* delay 50ms */ 1661 1662 /* Set the serial port timing configuration */ 1663 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1664 1665 /* Setup clock control */ 1666 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1667 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1668 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1669 1670 /* Power up the PLL */ 1671 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1672 delay(50*1000); /* delay 50ms */ 1673 1674 /* Turn on clock */ 1675 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE); 1676 1677 /* Set the serial port FIFO pointer to the 1678 * first sample in FIFO. (not documented) */ 1679 cs4280_clear_fifos(sc); 1680 1681 #if 0 1682 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1683 BA0WRITE4(sc, CS4280_SERBSP, 0); 1684 #endif 1685 1686 /* Configure the serial port */ 1687 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1688 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1689 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1690 1691 /* Wait for CODEC ready */ 1692 n = 0; 1693 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1694 delay(125); 1695 if (++n > 1000) { 1696 printf("%s: codec ready timeout\n", 1697 sc->sc_dev.dv_xname); 1698 return(1); 1699 } 1700 } 1701 1702 /* Assert valid frame signal */ 1703 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1704 1705 /* Wait for valid AC97 input slot */ 1706 n = 0; 1707 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1708 (ACISV_ISV3 | ACISV_ISV4)) { 1709 delay(1000); 1710 if (++n > 1000) { 1711 printf("AC97 inputs slot ready timeout\n"); 1712 return(1); 1713 } 1714 } 1715 1716 /* Set AC97 output slot valid signals */ 1717 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1718 1719 /* reset the processor */ 1720 cs4280_reset(sc); 1721 1722 /* Download the image to the processor */ 1723 if (cs4280_download_image(sc) != 0) { 1724 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1725 return(1); 1726 } 1727 1728 /* Save playback parameter and then write zero. 1729 * this ensures that DMA doesn't immediately occur upon 1730 * starting the processor core 1731 */ 1732 mem = BA1READ4(sc, CS4280_PCTL); 1733 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1734 cs4280_halt_output(sc); 1735 1736 /* Save capture parameter and then write zero. 1737 * this ensures that DMA doesn't immediately occur upon 1738 * starting the processor core 1739 */ 1740 mem = BA1READ4(sc, CS4280_CCTL); 1741 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1742 cs4280_halt_input(sc); 1743 1744 /* Processor Startup Procedure */ 1745 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1746 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1747 1748 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1749 n = 0; 1750 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1751 delay(10); 1752 if (++n > 1000) { 1753 printf("SPCR 1->0 transition timeout\n"); 1754 return(1); 1755 } 1756 } 1757 1758 n = 0; 1759 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1760 delay(10); 1761 if (++n > 1000) { 1762 printf("SPCS 0->1 transition timeout\n"); 1763 return(1); 1764 } 1765 } 1766 /* Processor is now running !!! */ 1767 1768 /* Setup volume */ 1769 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1770 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1771 1772 /* Interrupt enable */ 1773 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1774 1775 /* playback interrupt enable */ 1776 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1777 mem |= PFIE_PI_ENABLE; 1778 BA1WRITE4(sc, CS4280_PFIE, mem); 1779 /* capture interrupt enable */ 1780 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1781 mem |= CIE_CI_ENABLE; 1782 BA1WRITE4(sc, CS4280_CIE, mem); 1783 1784 #if NMIDI > 0 1785 /* Reset midi port */ 1786 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1787 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1788 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1789 /* midi interrupt enable */ 1790 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1791 BA0WRITE4(sc, CS4280_MIDCR, mem); 1792 #endif 1793 return(0); 1794 } 1795 1796 void 1797 cs4280_power(why, v) 1798 int why; 1799 void *v; 1800 { 1801 struct cs4280_softc *sc = (struct cs4280_softc *)v; 1802 int i; 1803 1804 DPRINTF(("%s: cs4280_power why=%d\n", 1805 sc->sc_dev.dv_xname, why)); 1806 if (why != PWR_RESUME) { 1807 sc->sc_suspend = why; 1808 1809 cs4280_halt_output(sc); 1810 cs4280_halt_input(sc); 1811 /* Save AC97 registers */ 1812 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1813 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1814 continue; 1815 cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i]); 1816 } 1817 /* should I powerdown here ? */ 1818 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1819 } else { 1820 if (sc->sc_suspend == PWR_RESUME) { 1821 printf("cs4280_power: odd, resume without suspend.\n"); 1822 sc->sc_suspend = why; 1823 return; 1824 } 1825 sc->sc_suspend = why; 1826 cs4280_init(sc, 0); 1827 cs4280_reset_codec(sc); 1828 1829 /* restore ac97 registers */ 1830 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1831 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1832 continue; 1833 cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]); 1834 } 1835 } 1836 } 1837 1838 void 1839 cs4280_clear_fifos(sc) 1840 struct cs4280_softc *sc; 1841 { 1842 int pd = 0, cnt, n; 1843 u_int32_t mem; 1844 1845 /* 1846 * If device power down, power up the device and keep power down 1847 * state. 1848 */ 1849 mem = BA0READ4(sc, CS4280_CLKCR1); 1850 if (!(mem & CLKCR1_SWCE)) { 1851 printf("cs4280_clear_fifo: power down found.\n"); 1852 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1853 pd = 1; 1854 } 1855 BA0WRITE4(sc, CS4280_SERBWP, 0); 1856 for (cnt = 0; cnt < 256; cnt++) { 1857 n = 0; 1858 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1859 delay(1000); 1860 if (++n > 1000) { 1861 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1862 break; 1863 } 1864 } 1865 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1866 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1867 } 1868 if (pd) 1869 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1870 } 1871 1872 #if NMIDI > 0 1873 int 1874 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1875 void *addr; 1876 int flags; 1877 void (*iintr)__P((void *, int)); 1878 void (*ointr)__P((void *)); 1879 void *arg; 1880 { 1881 struct cs4280_softc *sc = addr; 1882 u_int32_t mem; 1883 1884 DPRINTF(("midi_open\n")); 1885 sc->sc_iintr = iintr; 1886 sc->sc_ointr = ointr; 1887 sc->sc_arg = arg; 1888 1889 /* midi interrupt enable */ 1890 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1891 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1892 BA0WRITE4(sc, CS4280_MIDCR, mem); 1893 #ifdef CS4280_DEBUG 1894 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1895 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1896 return(EINVAL); 1897 } 1898 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1899 #endif 1900 return (0); 1901 } 1902 1903 void 1904 cs4280_midi_close(addr) 1905 void *addr; 1906 { 1907 struct cs4280_softc *sc = addr; 1908 u_int32_t mem; 1909 1910 DPRINTF(("midi_close\n")); 1911 mem = BA0READ4(sc, CS4280_MIDCR); 1912 mem &= ~MIDCR_MASK; 1913 BA0WRITE4(sc, CS4280_MIDCR, mem); 1914 1915 sc->sc_iintr = 0; 1916 sc->sc_ointr = 0; 1917 } 1918 1919 int 1920 cs4280_midi_output(addr, d) 1921 void *addr; 1922 int d; 1923 { 1924 struct cs4280_softc *sc = addr; 1925 u_int32_t mem; 1926 int x; 1927 1928 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1929 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1930 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1931 mem |= d & MIDWP_MASK; 1932 DPRINTFN(5,("midi_output d=0x%08x",d)); 1933 BA0WRITE4(sc, CS4280_MIDWP, mem); 1934 #ifdef DIAGNOSTIC 1935 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1936 DPRINTF(("Bad write data: %d %d", 1937 mem, BA0READ4(sc, CS4280_MIDWP))); 1938 return(EIO); 1939 } 1940 #endif 1941 return (0); 1942 } 1943 delay(MIDI_BUSY_DELAY); 1944 } 1945 return (EIO); 1946 } 1947 1948 void 1949 cs4280_midi_getinfo(addr, mi) 1950 void *addr; 1951 struct midi_info *mi; 1952 { 1953 mi->name = "CS4280 MIDI UART"; 1954 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1955 } 1956 1957 #endif 1958
Indexes created Thu Oct 02 14:10:14 GMT 2025