cs4280.c revision 1.41
1 /* $NetBSD: cs4280.c,v 1.41 2006/08/17 17:11:28 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.41 2006/08/17 17:11:28 christos Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <sys/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(struct device *, struct cfdata *, void *); 93 static void cs4280_attach(struct device *, struct device *, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 107 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 108 #if 0 109 static int cs4280_reset_codec(void *); 110 #endif 111 static enum ac97_host_flags cs4280_flags_codec(void *); 112 113 /* For PowerHook */ 114 static void cs4280_power(int, void *); 115 116 /* Internal functions */ 117 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *); 118 static int cs4280_piix4_match(struct pci_attach_args *); 119 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 120 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 121 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 122 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 123 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 124 uint32_t); 125 static int cs4280_download_image(struct cs428x_softc *); 126 static void cs4280_reset(void *); 127 static int cs4280_init(struct cs428x_softc *, int); 128 static void cs4280_clear_fifos(struct cs428x_softc *); 129 130 #if CS4280_DEBUG > 10 131 /* Thease two function is only for checking image loading is succeeded or not. */ 132 static int cs4280_check_images(struct cs428x_softc *); 133 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 134 uint32_t); 135 #endif 136 137 /* Special cards */ 138 struct cs4280_card_t 139 { 140 pcireg_t id; 141 enum cs428x_flags flags; 142 }; 143 144 #define _card(vend, prod, flags) \ 145 {PCI_ID_CODE(vend, prod), flags} 146 147 static const struct cs4280_card_t cs4280_cards[] = { 148 #if 0 /* untested, from ALSA driver */ 149 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 150 CS428X_FLAG_INVAC97EAMP), 151 #endif 152 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 153 CS428X_FLAG_INVAC97EAMP), 154 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 155 CS428X_FLAG_CLKRUNHACK) 156 }; 157 158 #undef _card 159 160 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 161 162 static const struct audio_hw_if cs4280_hw_if = { 163 NULL, /* open */ 164 NULL, /* close */ 165 NULL, 166 cs4280_query_encoding, 167 cs4280_set_params, 168 cs428x_round_blocksize, 169 NULL, 170 NULL, 171 NULL, 172 NULL, 173 NULL, 174 cs4280_halt_output, 175 cs4280_halt_input, 176 NULL, 177 cs4280_getdev, 178 NULL, 179 cs428x_mixer_set_port, 180 cs428x_mixer_get_port, 181 cs428x_query_devinfo, 182 cs428x_malloc, 183 cs428x_free, 184 cs428x_round_buffersize, 185 cs428x_mappage, 186 cs428x_get_props, 187 cs4280_trigger_output, 188 cs4280_trigger_input, 189 NULL, 190 }; 191 192 #if NMIDI > 0 193 /* Midi Interface */ 194 static int cs4280_midi_open(void *, int, void (*)(void *, int), 195 void (*)(void *), void *); 196 static void cs4280_midi_close(void*); 197 static int cs4280_midi_output(void *, int); 198 static void cs4280_midi_getinfo(void *, struct midi_info *); 199 200 static const struct midi_hw_if cs4280_midi_hw_if = { 201 cs4280_midi_open, 202 cs4280_midi_close, 203 cs4280_midi_output, 204 cs4280_midi_getinfo, 205 0, 206 }; 207 #endif 208 209 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 210 cs4280_match, cs4280_attach, NULL, NULL); 211 212 static struct audio_device cs4280_device = { 213 "CS4280", 214 "", 215 "cs4280" 216 }; 217 218 219 static int 220 cs4280_match(struct device *parent, struct cfdata *match, void *aux) 221 { 222 struct pci_attach_args *pa; 223 224 pa = (struct pci_attach_args *)aux; 225 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 226 return 0; 227 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 228 #if 0 /* I can't confirm */ 229 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 230 #endif 231 ) 232 return 1; 233 return 0; 234 } 235 236 static void 237 cs4280_attach(struct device *parent, struct device *self, void *aux) 238 { 239 struct cs428x_softc *sc; 240 struct pci_attach_args *pa; 241 pci_chipset_tag_t pc; 242 const struct cs4280_card_t *cs_card; 243 char const *intrstr; 244 pci_intr_handle_t ih; 245 pcireg_t reg; 246 char devinfo[256]; 247 uint32_t mem; 248 int error; 249 250 sc = (struct cs428x_softc *)self; 251 pa = (struct pci_attach_args *)aux; 252 pc = pa->pa_pc; 253 aprint_naive(": Audio controller\n"); 254 255 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 256 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 257 PCI_REVISION(pa->pa_class)); 258 259 cs_card = cs4280_identify_card(pa); 260 if (cs_card != NULL) { 261 aprint_normal("%s: %s %s\n",sc->sc_dev.dv_xname, 262 pci_findvendor(cs_card->id), 263 pci_findproduct(cs_card->id)); 264 sc->sc_flags = cs_card->flags; 265 } else { 266 sc->sc_flags = CS428X_FLAG_NONE; 267 } 268 269 /* Map I/O register */ 270 if (pci_mapreg_map(pa, PCI_BA0, 271 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 272 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 273 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 274 return; 275 } 276 if (pci_mapreg_map(pa, PCI_BA1, 277 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 278 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 279 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 280 return; 281 } 282 283 sc->sc_dmatag = pa->pa_dmat; 284 285 /* power up chip */ 286 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 287 pci_activate_null)) && error != EOPNOTSUPP) { 288 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 289 error); 290 return; 291 } 292 293 /* Enable the device (set bus master flag) */ 294 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 295 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 296 reg | PCI_COMMAND_MASTER_ENABLE); 297 298 /* LATENCY_TIMER setting */ 299 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 300 if ( PCI_LATTIMER(mem) < 32 ) { 301 mem &= 0xffff00ff; 302 mem |= 0x00002000; 303 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 304 } 305 306 /* CLKRUN hack initialization */ 307 cs4280_clkrun_hack_init(sc); 308 309 /* Map and establish the interrupt. */ 310 if (pci_intr_map(pa, &ih)) { 311 aprint_error("%s: couldn't map interrupt\n", 312 sc->sc_dev.dv_xname); 313 return; 314 } 315 intrstr = pci_intr_string(pc, ih); 316 317 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 318 if (sc->sc_ih == NULL) { 319 aprint_error("%s: couldn't establish interrupt", 320 sc->sc_dev.dv_xname); 321 if (intrstr != NULL) 322 aprint_normal(" at %s", intrstr); 323 aprint_normal("\n"); 324 return; 325 } 326 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 327 328 /* Initialization */ 329 if(cs4280_init(sc, 1) != 0) 330 return; 331 332 sc->type = TYPE_CS4280; 333 sc->halt_input = cs4280_halt_input; 334 sc->halt_output = cs4280_halt_output; 335 336 /* setup buffer related parameters */ 337 sc->dma_size = CS4280_DCHUNK; 338 sc->dma_align = CS4280_DALIGN; 339 sc->hw_blocksize = CS4280_ICHUNK; 340 341 /* AC 97 attachment */ 342 sc->host_if.arg = sc; 343 sc->host_if.attach = cs428x_attach_codec; 344 sc->host_if.read = cs4280_read_codec; 345 sc->host_if.write = cs4280_write_codec; 346 #if 0 347 sc->host_if.reset = cs4280_reset_codec; 348 #else 349 sc->host_if.reset = NULL; 350 #endif 351 sc->host_if.flags = cs4280_flags_codec; 352 if (ac97_attach(&sc->host_if, self) != 0) { 353 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 354 return; 355 } 356 357 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 358 359 #if NMIDI > 0 360 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 361 #endif 362 363 sc->sc_suspend = PWR_RESUME; 364 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 365 } 366 367 /* Interrupt handling function */ 368 static int 369 cs4280_intr(void *p) 370 { 371 /* 372 * XXX 373 * 374 * Since CS4280 has only 4kB DMA buffer and 375 * interrupt occurs every 2kB block, I create dummy buffer 376 * which returns to audio driver and actual DMA buffer 377 * using in DMA transfer. 378 * 379 * 380 * ring buffer in audio.c is pointed by BUFADDR 381 * <------ ring buffer size == 64kB ------> 382 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 383 * |= = = =|= = = =|= = = =|= = = =|= = = =| 384 * | | | | | | <- call audio_intp every 385 * sc->sc_[pr]_count time. 386 * 387 * actual DMA buffer is pointed by KERNADDR 388 * <-> DMA buffer size = 4kB 389 * |= =| 390 * 391 * 392 */ 393 struct cs428x_softc *sc; 394 uint32_t intr, mem; 395 char * empty_dma; 396 int handled; 397 398 sc = p; 399 handled = 0; 400 /* grab interrupt register then clear it */ 401 intr = BA0READ4(sc, CS4280_HISR); 402 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 403 404 /* not for us ? */ 405 if ((intr & HISR_INTENA) == 0) 406 return 0; 407 408 /* Playback Interrupt */ 409 if (intr & HISR_PINT) { 410 handled = 1; 411 mem = BA1READ4(sc, CS4280_PFIE); 412 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 413 if (sc->sc_prun) { 414 if ((sc->sc_pi%sc->sc_pcount) == 0) 415 sc->sc_pintr(sc->sc_parg); 416 /* copy buffer */ 417 ++sc->sc_pi; 418 empty_dma = sc->sc_pdma->addr; 419 if (sc->sc_pi&1) 420 empty_dma += sc->hw_blocksize; 421 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 422 sc->sc_pn += sc->hw_blocksize; 423 if (sc->sc_pn >= sc->sc_pe) 424 sc->sc_pn = sc->sc_ps; 425 } else { 426 printf("%s: unexpected play intr\n", 427 sc->sc_dev.dv_xname); 428 } 429 BA1WRITE4(sc, CS4280_PFIE, mem); 430 } 431 /* Capture Interrupt */ 432 if (intr & HISR_CINT) { 433 int i; 434 int16_t rdata; 435 436 handled = 1; 437 mem = BA1READ4(sc, CS4280_CIE); 438 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 439 440 if (sc->sc_rrun) { 441 ++sc->sc_ri; 442 empty_dma = sc->sc_rdma->addr; 443 if ((sc->sc_ri&1) == 0) 444 empty_dma += sc->hw_blocksize; 445 446 /* 447 * XXX 448 * I think this audio data conversion should be 449 * happend in upper layer, but I put this here 450 * since there is no conversion function available. 451 */ 452 switch(sc->sc_rparam) { 453 case CF_16BIT_STEREO: 454 /* just copy it */ 455 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 456 sc->sc_rn += sc->hw_blocksize; 457 break; 458 case CF_16BIT_MONO: 459 for (i = 0; i < 512; i++) { 460 rdata = *((int16_t *)empty_dma)>>1; 461 empty_dma += 2; 462 rdata += *((int16_t *)empty_dma)>>1; 463 empty_dma += 2; 464 *((int16_t *)sc->sc_rn) = rdata; 465 sc->sc_rn += 2; 466 } 467 break; 468 case CF_8BIT_STEREO: 469 for (i = 0; i < 512; i++) { 470 rdata = *((int16_t*)empty_dma); 471 empty_dma += 2; 472 *sc->sc_rn++ = rdata >> 8; 473 rdata = *((int16_t*)empty_dma); 474 empty_dma += 2; 475 *sc->sc_rn++ = rdata >> 8; 476 } 477 break; 478 case CF_8BIT_MONO: 479 for (i = 0; i < 512; i++) { 480 rdata = *((int16_t*)empty_dma) >>1; 481 empty_dma += 2; 482 rdata += *((int16_t*)empty_dma) >>1; 483 empty_dma += 2; 484 *sc->sc_rn++ = rdata >>8; 485 } 486 break; 487 default: 488 /* Should not reach here */ 489 printf("%s: unknown sc->sc_rparam: %d\n", 490 sc->sc_dev.dv_xname, sc->sc_rparam); 491 } 492 if (sc->sc_rn >= sc->sc_re) 493 sc->sc_rn = sc->sc_rs; 494 } 495 BA1WRITE4(sc, CS4280_CIE, mem); 496 497 if (sc->sc_rrun) { 498 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 499 sc->sc_rintr(sc->sc_rarg); 500 } else { 501 printf("%s: unexpected record intr\n", 502 sc->sc_dev.dv_xname); 503 } 504 } 505 506 #if NMIDI > 0 507 /* Midi port Interrupt */ 508 if (intr & HISR_MIDI) { 509 int data; 510 511 handled = 1; 512 DPRINTF(("i: %d: ", 513 BA0READ4(sc, CS4280_MIDSR))); 514 /* Read the received data */ 515 while ((sc->sc_iintr != NULL) && 516 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 517 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 518 DPRINTF(("r:%x\n",data)); 519 sc->sc_iintr(sc->sc_arg, data); 520 } 521 522 /* Write the data */ 523 #if 1 524 /* XXX: 525 * It seems "Transmit Buffer Full" never activate until EOI 526 * is deliverd. Shall I throw EOI top of this routine ? 527 */ 528 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 529 DPRINTF(("w: ")); 530 if (sc->sc_ointr != NULL) 531 sc->sc_ointr(sc->sc_arg); 532 } 533 #else 534 while ((sc->sc_ointr != NULL) && 535 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 536 DPRINTF(("w: ")); 537 sc->sc_ointr(sc->sc_arg); 538 } 539 #endif 540 DPRINTF(("\n")); 541 } 542 #endif 543 544 return handled; 545 } 546 547 static int 548 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 549 { 550 switch (fp->index) { 551 case 0: 552 strcpy(fp->name, AudioEulinear); 553 fp->encoding = AUDIO_ENCODING_ULINEAR; 554 fp->precision = 8; 555 fp->flags = 0; 556 break; 557 case 1: 558 strcpy(fp->name, AudioEmulaw); 559 fp->encoding = AUDIO_ENCODING_ULAW; 560 fp->precision = 8; 561 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 562 break; 563 case 2: 564 strcpy(fp->name, AudioEalaw); 565 fp->encoding = AUDIO_ENCODING_ALAW; 566 fp->precision = 8; 567 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 568 break; 569 case 3: 570 strcpy(fp->name, AudioEslinear); 571 fp->encoding = AUDIO_ENCODING_SLINEAR; 572 fp->precision = 8; 573 fp->flags = 0; 574 break; 575 case 4: 576 strcpy(fp->name, AudioEslinear_le); 577 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 578 fp->precision = 16; 579 fp->flags = 0; 580 break; 581 case 5: 582 strcpy(fp->name, AudioEulinear_le); 583 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 584 fp->precision = 16; 585 fp->flags = 0; 586 break; 587 case 6: 588 strcpy(fp->name, AudioEslinear_be); 589 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 590 fp->precision = 16; 591 fp->flags = 0; 592 break; 593 case 7: 594 strcpy(fp->name, AudioEulinear_be); 595 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 596 fp->precision = 16; 597 fp->flags = 0; 598 break; 599 default: 600 return EINVAL; 601 } 602 return 0; 603 } 604 605 static int 606 cs4280_set_params(void *addr, int setmode, int usemode, 607 audio_params_t *play, audio_params_t *rec, 608 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 609 { 610 audio_params_t hw; 611 struct cs428x_softc *sc; 612 struct audio_params *p; 613 stream_filter_list_t *fil; 614 int mode; 615 616 sc = addr; 617 for (mode = AUMODE_RECORD; mode != -1; 618 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 619 if ((setmode & mode) == 0) 620 continue; 621 622 p = mode == AUMODE_PLAY ? play : rec; 623 624 if (p == play) { 625 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 626 p->sample_rate, p->precision, p->channels)); 627 /* play back data format may be 8- or 16-bit and 628 * either stereo or mono. 629 * playback rate may range from 8000Hz to 48000Hz 630 */ 631 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 632 (p->precision != 8 && p->precision != 16) || 633 (p->channels != 1 && p->channels != 2) ) { 634 return EINVAL; 635 } 636 } else { 637 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 638 p->sample_rate, p->precision, p->channels)); 639 /* capture data format must be 16bit stereo 640 * and sample rate range from 11025Hz to 48000Hz. 641 * 642 * XXX: it looks like to work with 8000Hz, 643 * although data sheets say lower limit is 644 * 11025 Hz. 645 */ 646 647 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 648 (p->precision != 8 && p->precision != 16) || 649 (p->channels != 1 && p->channels != 2) ) { 650 return EINVAL; 651 } 652 } 653 fil = mode == AUMODE_PLAY ? pfil : rfil; 654 hw = *p; 655 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 656 657 /* capturing data is slinear */ 658 switch (p->encoding) { 659 case AUDIO_ENCODING_SLINEAR_BE: 660 if (mode == AUMODE_RECORD && p->precision == 16) { 661 fil->append(fil, swap_bytes, &hw); 662 } 663 break; 664 case AUDIO_ENCODING_SLINEAR_LE: 665 break; 666 case AUDIO_ENCODING_ULINEAR_BE: 667 if (mode == AUMODE_RECORD) { 668 fil->append(fil, p->precision == 16 669 ? swap_bytes_change_sign16 670 : change_sign8, &hw); 671 } 672 break; 673 case AUDIO_ENCODING_ULINEAR_LE: 674 if (mode == AUMODE_RECORD) { 675 fil->append(fil, p->precision == 16 676 ? change_sign16 : change_sign8, 677 &hw); 678 } 679 break; 680 case AUDIO_ENCODING_ULAW: 681 if (mode == AUMODE_PLAY) { 682 hw.precision = 16; 683 hw.validbits = 16; 684 fil->append(fil, mulaw_to_linear16, &hw); 685 } else { 686 fil->append(fil, linear8_to_mulaw, &hw); 687 } 688 break; 689 case AUDIO_ENCODING_ALAW: 690 if (mode == AUMODE_PLAY) { 691 hw.precision = 16; 692 hw.validbits = 16; 693 fil->append(fil, alaw_to_linear16, &hw); 694 } else { 695 fil->append(fil, linear8_to_alaw, &hw); 696 } 697 break; 698 default: 699 return EINVAL; 700 } 701 } 702 703 /* set sample rate */ 704 cs4280_set_dac_rate(sc, play->sample_rate); 705 cs4280_set_adc_rate(sc, rec->sample_rate); 706 return 0; 707 } 708 709 static int 710 cs4280_halt_output(void *addr) 711 { 712 struct cs428x_softc *sc; 713 uint32_t mem; 714 715 sc = addr; 716 mem = BA1READ4(sc, CS4280_PCTL); 717 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 718 sc->sc_prun = 0; 719 cs4280_clkrun_hack(sc, -1); 720 721 return 0; 722 } 723 724 static int 725 cs4280_halt_input(void *addr) 726 { 727 struct cs428x_softc *sc; 728 uint32_t mem; 729 730 sc = addr; 731 mem = BA1READ4(sc, CS4280_CCTL); 732 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 733 sc->sc_rrun = 0; 734 cs4280_clkrun_hack(sc, -1); 735 736 return 0; 737 } 738 739 static int 740 cs4280_getdev(void *addr, struct audio_device *retp) 741 { 742 743 *retp = cs4280_device; 744 return 0; 745 } 746 747 static int 748 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 749 void (*intr)(void *), void *arg, 750 const audio_params_t *param) 751 { 752 struct cs428x_softc *sc; 753 uint32_t pfie, pctl, pdtc; 754 struct cs428x_dma *p; 755 756 sc = addr; 757 #ifdef DIAGNOSTIC 758 if (sc->sc_prun) 759 printf("cs4280_trigger_output: already running\n"); 760 #endif 761 sc->sc_prun = 1; 762 cs4280_clkrun_hack(sc, 1); 763 764 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 765 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 766 sc->sc_pintr = intr; 767 sc->sc_parg = arg; 768 769 /* stop playback DMA */ 770 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 771 772 /* setup PDTC */ 773 pdtc = BA1READ4(sc, CS4280_PDTC); 774 pdtc &= ~PDTC_MASK; 775 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 776 BA1WRITE4(sc, CS4280_PDTC, pdtc); 777 778 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 779 param->precision, param->channels, param->encoding)); 780 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 781 continue; 782 if (p == NULL) { 783 printf("cs4280_trigger_output: bad addr %p\n", start); 784 return EINVAL; 785 } 786 if (DMAADDR(p) % sc->dma_align != 0 ) { 787 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 788 "4kB align\n", (ulong)DMAADDR(p)); 789 return EINVAL; 790 } 791 792 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 793 sc->sc_ps = (char *)start; 794 sc->sc_pe = (char *)end; 795 sc->sc_pdma = p; 796 sc->sc_pbuf = KERNADDR(p); 797 sc->sc_pi = 0; 798 sc->sc_pn = sc->sc_ps; 799 if (blksize >= sc->dma_size) { 800 sc->sc_pn = sc->sc_ps + sc->dma_size; 801 memcpy(sc->sc_pbuf, start, sc->dma_size); 802 ++sc->sc_pi; 803 } else { 804 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 805 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 806 } 807 808 /* initiate playback DMA */ 809 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 810 811 /* set PFIE */ 812 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 813 814 if (param->precision == 8) 815 pfie |= PFIE_8BIT; 816 if (param->channels == 1) 817 pfie |= PFIE_MONO; 818 819 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 820 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 821 pfie |= PFIE_SWAPPED; 822 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 823 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 824 pfie |= PFIE_UNSIGNED; 825 826 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 827 828 sc->sc_prate = param->sample_rate; 829 cs4280_set_dac_rate(sc, param->sample_rate); 830 831 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 832 pctl |= sc->pctl; 833 BA1WRITE4(sc, CS4280_PCTL, pctl); 834 return 0; 835 } 836 837 static int 838 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 839 void (*intr)(void *), void *arg, 840 const audio_params_t *param) 841 { 842 struct cs428x_softc *sc; 843 uint32_t cctl, cie; 844 struct cs428x_dma *p; 845 846 sc = addr; 847 #ifdef DIAGNOSTIC 848 if (sc->sc_rrun) 849 printf("cs4280_trigger_input: already running\n"); 850 #endif 851 sc->sc_rrun = 1; 852 cs4280_clkrun_hack(sc, 1); 853 854 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 855 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 856 sc->sc_rintr = intr; 857 sc->sc_rarg = arg; 858 859 /* stop capture DMA */ 860 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 861 862 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 863 continue; 864 if (p == NULL) { 865 printf("cs4280_trigger_input: bad addr %p\n", start); 866 return EINVAL; 867 } 868 if (DMAADDR(p) % sc->dma_align != 0) { 869 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 870 "4kB align\n", (ulong)DMAADDR(p)); 871 return EINVAL; 872 } 873 874 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 875 sc->sc_rs = (char *)start; 876 sc->sc_re = (char *)end; 877 sc->sc_rdma = p; 878 sc->sc_rbuf = KERNADDR(p); 879 sc->sc_ri = 0; 880 sc->sc_rn = sc->sc_rs; 881 882 /* initiate capture DMA */ 883 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 884 885 /* setup format information for internal converter */ 886 sc->sc_rparam = 0; 887 if (param->precision == 8) { 888 sc->sc_rparam += CF_8BIT; 889 sc->sc_rcount <<= 1; 890 } 891 if (param->channels == 1) { 892 sc->sc_rparam += CF_MONO; 893 sc->sc_rcount <<= 1; 894 } 895 896 /* set CIE */ 897 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 898 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 899 900 sc->sc_rrate = param->sample_rate; 901 cs4280_set_adc_rate(sc, param->sample_rate); 902 903 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 904 cctl |= sc->cctl; 905 BA1WRITE4(sc, CS4280_CCTL, cctl); 906 return 0; 907 } 908 909 /* Power Hook */ 910 static void 911 cs4280_power(int why, void *v) 912 { 913 static uint32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 914 static uint32_t cctl = 0, cba = 0, cie = 0; 915 struct cs428x_softc *sc; 916 917 sc = (struct cs428x_softc *)v; 918 DPRINTF(("%s: cs4280_power why=%d\n", sc->sc_dev.dv_xname, why)); 919 switch (why) { 920 case PWR_SUSPEND: 921 case PWR_STANDBY: 922 sc->sc_suspend = why; 923 924 /* save current playback status */ 925 if (sc->sc_prun) { 926 pctl = BA1READ4(sc, CS4280_PCTL); 927 pfie = BA1READ4(sc, CS4280_PFIE); 928 pba = BA1READ4(sc, CS4280_PBA); 929 pdtc = BA1READ4(sc, CS4280_PDTC); 930 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 931 pctl, pfie, pba, pdtc)); 932 } 933 934 /* save current capture status */ 935 if (sc->sc_rrun) { 936 cctl = BA1READ4(sc, CS4280_CCTL); 937 cie = BA1READ4(sc, CS4280_CIE); 938 cba = BA1READ4(sc, CS4280_CBA); 939 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 940 cctl, cie, cba)); 941 } 942 943 /* Stop DMA */ 944 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 945 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 946 break; 947 case PWR_RESUME: 948 if (sc->sc_suspend == PWR_RESUME) { 949 printf("cs4280_power: odd, resume without suspend.\n"); 950 sc->sc_suspend = why; 951 return; 952 } 953 sc->sc_suspend = why; 954 cs4280_init(sc, 0); 955 #if 0 956 cs4280_reset_codec(sc); 957 #endif 958 /* restore ac97 registers */ 959 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 960 961 /* restore DMA related status */ 962 if(sc->sc_prun) { 963 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 964 pctl, pfie, pba, pdtc)); 965 cs4280_set_dac_rate(sc, sc->sc_prate); 966 BA1WRITE4(sc, CS4280_PDTC, pdtc); 967 BA1WRITE4(sc, CS4280_PBA, pba); 968 BA1WRITE4(sc, CS4280_PFIE, pfie); 969 BA1WRITE4(sc, CS4280_PCTL, pctl); 970 } 971 972 if (sc->sc_rrun) { 973 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 974 cctl, cie, cba)); 975 cs4280_set_adc_rate(sc, sc->sc_rrate); 976 BA1WRITE4(sc, CS4280_CBA, cba); 977 BA1WRITE4(sc, CS4280_CIE, cie); 978 BA1WRITE4(sc, CS4280_CCTL, cctl); 979 } 980 break; 981 case PWR_SOFTSUSPEND: 982 case PWR_SOFTSTANDBY: 983 case PWR_SOFTRESUME: 984 break; 985 } 986 } 987 988 static int 989 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 990 { 991 struct cs428x_softc *sc = addr; 992 int rv; 993 994 cs4280_clkrun_hack(sc, 1); 995 rv = cs428x_read_codec(addr, reg, result); 996 cs4280_clkrun_hack(sc, -1); 997 998 return rv; 999 } 1000 1001 static int 1002 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1003 { 1004 struct cs428x_softc *sc = addr; 1005 int rv; 1006 1007 cs4280_clkrun_hack(sc, 1); 1008 rv = cs428x_write_codec(addr, reg, data); 1009 cs4280_clkrun_hack(sc, -1); 1010 1011 return rv; 1012 } 1013 1014 #if 0 /* XXX buggy and not required */ 1015 /* control AC97 codec */ 1016 static int 1017 cs4280_reset_codec(void *addr) 1018 { 1019 struct cs428x_softc *sc; 1020 int n; 1021 1022 sc = addr; 1023 1024 /* Reset codec */ 1025 BA0WRITE4(sc, CS428X_ACCTL, 0); 1026 delay(100); /* delay 100us */ 1027 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1028 1029 /* 1030 * It looks like we do the following procedure, too 1031 */ 1032 1033 /* Enable AC-link sync generation */ 1034 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1035 delay(50*1000); /* XXX delay 50ms */ 1036 1037 /* Assert valid frame signal */ 1038 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1039 1040 /* Wait for valid AC97 input slot */ 1041 n = 0; 1042 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1043 (ACISV_ISV3 | ACISV_ISV4)) { 1044 delay(1000); 1045 if (++n > 1000) { 1046 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1047 return ETIMEDOUT; 1048 } 1049 } 1050 1051 return 0; 1052 } 1053 #endif 1054 1055 static enum ac97_host_flags cs4280_flags_codec(void *addr) 1056 { 1057 struct cs428x_softc *sc; 1058 1059 sc = addr; 1060 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1061 return AC97_HOST_INVERTED_EAMP; 1062 1063 return 0; 1064 } 1065 1066 /* Internal functions */ 1067 1068 static const struct cs4280_card_t * 1069 cs4280_identify_card(struct pci_attach_args *pa) 1070 { 1071 pcireg_t idreg; 1072 u_int16_t i; 1073 1074 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1075 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1076 if (idreg == cs4280_cards[i].id) 1077 return &cs4280_cards[i]; 1078 } 1079 1080 return NULL; 1081 } 1082 1083 static int 1084 cs4280_piix4_match(struct pci_attach_args *pa) 1085 { 1086 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1087 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1088 return 1; 1089 } 1090 1091 return 0; 1092 } 1093 1094 static void 1095 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1096 { 1097 uint16_t control, val; 1098 1099 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1100 return; 1101 1102 sc->sc_active += change; 1103 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1104 if (!sc->sc_active) 1105 val |= 0x2000; 1106 else 1107 val &= ~0x2000; 1108 if (val != control) 1109 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1110 } 1111 1112 static void 1113 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1114 { 1115 struct pci_attach_args smbuspa; 1116 uint16_t reg; 1117 pcireg_t port; 1118 1119 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1120 return; 1121 1122 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1123 sc->sc_active = 0; 1124 printf("%s: enabling CLKRUN hack\n", 1125 sc->sc_dev.dv_xname); 1126 1127 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1128 port = reg & 0xffc0; 1129 printf("%s: power management port 0x%x\n", sc->sc_dev.dv_xname, 1130 port); 1131 1132 sc->sc_pm_iot = smbuspa.pa_iot; 1133 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1134 &sc->sc_pm_ioh) == 0) 1135 return; 1136 } 1137 1138 /* handle error */ 1139 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1140 printf("%s: disabling CLKRUN hack\n", sc->sc_dev.dv_xname); 1141 } 1142 1143 static void 1144 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1145 { 1146 /* calculate capture rate: 1147 * 1148 * capture_coefficient_increment = -round(rate*128*65536/48000; 1149 * capture_phase_increment = floor(48000*65536*1024/rate); 1150 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1151 * cy = floor(cx/200); 1152 * capture_sample_rate_correction = cx - 200*cy; 1153 * capture_delay = ceil(24*48000/rate); 1154 * capture_num_triplets = floor(65536*rate/24000); 1155 * capture_group_length = 24000/GCD(rate, 24000); 1156 * where GCD means "Greatest Common Divisor". 1157 * 1158 * capture_coefficient_increment, capture_phase_increment and 1159 * capture_num_triplets are 32-bit signed quantities. 1160 * capture_sample_rate_correction and capture_group_length are 1161 * 16-bit signed quantities. 1162 * capture_delay is a 14-bit unsigned quantity. 1163 */ 1164 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1165 uint16_t csrc, cgl, cdlay; 1166 1167 /* XXX 1168 * Even though, embedded_audio_spec says capture rate range 11025 to 1169 * 48000, dhwiface.cpp says, 1170 * 1171 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1172 * Return an error if an attempt is made to stray outside that limit." 1173 * 1174 * so assume range as 48000/9 to 48000 1175 */ 1176 1177 if (rate < 8000) 1178 rate = 8000; 1179 if (rate > 48000) 1180 rate = 48000; 1181 1182 cx = rate << 16; 1183 cci = cx / 48000; 1184 cx -= cci * 48000; 1185 cx <<= 7; 1186 cci <<= 7; 1187 cci += cx / 48000; 1188 cci = - cci; 1189 1190 cx = 48000 << 16; 1191 cpi = cx / rate; 1192 cx -= cpi * rate; 1193 cx <<= 10; 1194 cpi <<= 10; 1195 cy = cx / rate; 1196 cpi += cy; 1197 cx -= cy * rate; 1198 1199 cy = cx / 200; 1200 csrc = cx - 200*cy; 1201 1202 cdlay = ((48000 * 24) + rate - 1) / rate; 1203 #if 0 1204 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1205 #endif 1206 1207 cnt = rate << 16; 1208 cnt /= 24000; 1209 1210 cgl = 1; 1211 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1212 if (((rate / tmp1) * tmp1) != rate) 1213 cgl *= 2; 1214 } 1215 if (((rate / 3) * 3) != rate) 1216 cgl *= 3; 1217 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1218 if (((rate / tmp1) * tmp1) != rate) 1219 cgl *= 5; 1220 } 1221 #if 0 1222 /* XXX what manual says */ 1223 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1224 tmp1 |= csrc<<16; 1225 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1226 #else 1227 /* suggested by cs461x.c (ALSA driver) */ 1228 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1229 #endif 1230 1231 #if 0 1232 /* I am confused. The sample rate calculation section says 1233 * cci *is* 32-bit signed quantity but in the parameter description 1234 * section, CCI only assigned 16bit. 1235 * I believe size of the variable. 1236 */ 1237 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1238 tmp1 |= cci<<16; 1239 BA1WRITE4(sc, CS4280_CCI, tmp1); 1240 #else 1241 BA1WRITE4(sc, CS4280_CCI, cci); 1242 #endif 1243 1244 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1245 tmp1 |= cdlay <<18; 1246 BA1WRITE4(sc, CS4280_CD, tmp1); 1247 1248 BA1WRITE4(sc, CS4280_CPI, cpi); 1249 1250 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1251 tmp1 |= cgl; 1252 BA1WRITE4(sc, CS4280_CGL, tmp1); 1253 1254 BA1WRITE4(sc, CS4280_CNT, cnt); 1255 1256 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1257 tmp1 |= cgl; 1258 BA1WRITE4(sc, CS4280_CGC, tmp1); 1259 } 1260 1261 static void 1262 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1263 { 1264 /* 1265 * playback rate may range from 8000Hz to 48000Hz 1266 * 1267 * play_phase_increment = floor(rate*65536*1024/48000) 1268 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1269 * py=floor(px/200) 1270 * play_sample_rate_correction = px - 200*py 1271 * 1272 * play_phase_increment is a 32bit signed quantity. 1273 * play_sample_rate_correction is a 16bit signed quantity. 1274 */ 1275 int32_t ppi; 1276 int16_t psrc; 1277 uint32_t px, py; 1278 1279 if (rate < 8000) 1280 rate = 8000; 1281 if (rate > 48000) 1282 rate = 48000; 1283 px = rate << 16; 1284 ppi = px/48000; 1285 px -= ppi*48000; 1286 ppi <<= 10; 1287 px <<= 10; 1288 py = px / 48000; 1289 ppi += py; 1290 px -= py*48000; 1291 py = px/200; 1292 px -= py*200; 1293 psrc = px; 1294 #if 0 1295 /* what manual says */ 1296 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1297 BA1WRITE4(sc, CS4280_PSRC, 1298 ( ((psrc<<16) & PSRC_MASK) | px )); 1299 #else 1300 /* suggested by cs461x.c (ALSA driver) */ 1301 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1302 #endif 1303 BA1WRITE4(sc, CS4280_PPI, ppi); 1304 } 1305 1306 /* Download Processor Code and Data image */ 1307 static int 1308 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1309 uint32_t offset, uint32_t len) 1310 { 1311 uint32_t ctr; 1312 #if CS4280_DEBUG > 10 1313 uint32_t con, data; 1314 uint8_t c0, c1, c2, c3; 1315 #endif 1316 if ((offset & 3) || (len & 3)) 1317 return -1; 1318 1319 len /= sizeof(uint32_t); 1320 for (ctr = 0; ctr < len; ctr++) { 1321 /* XXX: 1322 * I cannot confirm this is the right thing or not 1323 * on BIG-ENDIAN machines. 1324 */ 1325 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1326 #if CS4280_DEBUG > 10 1327 data = htole32(*(src+ctr)); 1328 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1329 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1330 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1331 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1332 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1333 if (data != con ) { 1334 printf("0x%06x: write=0x%08x read=0x%08x\n", 1335 offset+ctr*4, data, con); 1336 return -1; 1337 } 1338 #endif 1339 } 1340 return 0; 1341 } 1342 1343 static int 1344 cs4280_download_image(struct cs428x_softc *sc) 1345 { 1346 int idx, err; 1347 uint32_t offset = 0; 1348 1349 err = 0; 1350 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1351 err = cs4280_download(sc, &BA1Struct.map[offset], 1352 BA1Struct.memory[idx].offset, 1353 BA1Struct.memory[idx].size); 1354 if (err != 0) { 1355 printf("%s: load_image failed at %d\n", 1356 sc->sc_dev.dv_xname, idx); 1357 return -1; 1358 } 1359 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1360 } 1361 return err; 1362 } 1363 1364 /* Processor Soft Reset */ 1365 static void 1366 cs4280_reset(void *sc_) 1367 { 1368 struct cs428x_softc *sc; 1369 1370 sc = sc_; 1371 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1372 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1373 delay(100); 1374 /* Clear RSTSP bit in SPCR */ 1375 BA1WRITE4(sc, CS4280_SPCR, 0); 1376 /* enable DMA reqest */ 1377 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1378 } 1379 1380 static int 1381 cs4280_init(struct cs428x_softc *sc, int init) 1382 { 1383 int n; 1384 uint32_t mem; 1385 int rv; 1386 1387 rv = 1; 1388 cs4280_clkrun_hack(sc, 1); 1389 1390 /* Start PLL out in known state */ 1391 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1392 /* Start serial ports out in known state */ 1393 BA0WRITE4(sc, CS4280_SERMC1, 0); 1394 1395 /* Specify type of CODEC */ 1396 /* XXX should not be here */ 1397 #define SERACC_CODEC_TYPE_1_03 1398 #ifdef SERACC_CODEC_TYPE_1_03 1399 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1400 #else 1401 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1402 #endif 1403 1404 /* Reset codec */ 1405 BA0WRITE4(sc, CS428X_ACCTL, 0); 1406 delay(100); /* delay 100us */ 1407 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1408 1409 /* Enable AC-link sync generation */ 1410 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1411 delay(50*1000); /* delay 50ms */ 1412 1413 /* Set the serial port timing configuration */ 1414 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1415 1416 /* Setup clock control */ 1417 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1418 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1419 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1420 1421 /* Power up the PLL */ 1422 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1423 delay(50*1000); /* delay 50ms */ 1424 1425 /* Turn on clock */ 1426 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1427 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1428 1429 /* Set the serial port FIFO pointer to the 1430 * first sample in FIFO. (not documented) */ 1431 cs4280_clear_fifos(sc); 1432 1433 #if 0 1434 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1435 BA0WRITE4(sc, CS4280_SERBSP, 0); 1436 #endif 1437 1438 /* Configure the serial port */ 1439 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1440 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1441 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1442 1443 /* Wait for CODEC ready */ 1444 n = 0; 1445 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1446 delay(125); 1447 if (++n > 1000) { 1448 printf("%s: codec ready timeout\n", 1449 sc->sc_dev.dv_xname); 1450 goto exit; 1451 } 1452 } 1453 1454 /* Assert valid frame signal */ 1455 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1456 1457 /* Wait for valid AC97 input slot */ 1458 n = 0; 1459 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1460 (ACISV_ISV3 | ACISV_ISV4)) { 1461 delay(1000); 1462 if (++n > 1000) { 1463 printf("AC97 inputs slot ready timeout\n"); 1464 goto exit; 1465 } 1466 } 1467 1468 /* Set AC97 output slot valid signals */ 1469 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1470 1471 /* reset the processor */ 1472 cs4280_reset(sc); 1473 1474 /* Download the image to the processor */ 1475 if (cs4280_download_image(sc) != 0) { 1476 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1477 goto exit; 1478 } 1479 1480 /* Save playback parameter and then write zero. 1481 * this ensures that DMA doesn't immediately occur upon 1482 * starting the processor core 1483 */ 1484 mem = BA1READ4(sc, CS4280_PCTL); 1485 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1486 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1487 if (init != 0) 1488 sc->sc_prun = 0; 1489 1490 /* Save capture parameter and then write zero. 1491 * this ensures that DMA doesn't immediately occur upon 1492 * starting the processor core 1493 */ 1494 mem = BA1READ4(sc, CS4280_CCTL); 1495 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1496 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1497 if (init != 0) 1498 sc->sc_rrun = 0; 1499 1500 /* Processor Startup Procedure */ 1501 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1502 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1503 1504 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1505 n = 0; 1506 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1507 delay(10); 1508 if (++n > 1000) { 1509 printf("SPCR 1->0 transition timeout\n"); 1510 goto exit; 1511 } 1512 } 1513 1514 n = 0; 1515 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1516 delay(10); 1517 if (++n > 1000) { 1518 printf("SPCS 0->1 transition timeout\n"); 1519 goto exit; 1520 } 1521 } 1522 /* Processor is now running !!! */ 1523 1524 /* Setup volume */ 1525 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1526 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1527 1528 /* Interrupt enable */ 1529 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1530 1531 /* playback interrupt enable */ 1532 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1533 mem |= PFIE_PI_ENABLE; 1534 BA1WRITE4(sc, CS4280_PFIE, mem); 1535 /* capture interrupt enable */ 1536 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1537 mem |= CIE_CI_ENABLE; 1538 BA1WRITE4(sc, CS4280_CIE, mem); 1539 1540 #if NMIDI > 0 1541 /* Reset midi port */ 1542 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1543 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1544 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1545 /* midi interrupt enable */ 1546 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1547 BA0WRITE4(sc, CS4280_MIDCR, mem); 1548 #endif 1549 1550 rv = 0; 1551 1552 exit: 1553 cs4280_clkrun_hack(sc, -1); 1554 return rv; 1555 } 1556 1557 static void 1558 cs4280_clear_fifos(struct cs428x_softc *sc) 1559 { 1560 int pd, cnt, n; 1561 uint32_t mem; 1562 1563 pd = 0; 1564 /* 1565 * If device power down, power up the device and keep power down 1566 * state. 1567 */ 1568 mem = BA0READ4(sc, CS4280_CLKCR1); 1569 if (!(mem & CLKCR1_SWCE)) { 1570 printf("cs4280_clear_fifo: power down found.\n"); 1571 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1572 pd = 1; 1573 } 1574 BA0WRITE4(sc, CS4280_SERBWP, 0); 1575 for (cnt = 0; cnt < 256; cnt++) { 1576 n = 0; 1577 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1578 delay(1000); 1579 if (++n > 1000) { 1580 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1581 break; 1582 } 1583 } 1584 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1585 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1586 } 1587 if (pd) 1588 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1589 } 1590 1591 #if NMIDI > 0 1592 static int 1593 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1594 void (*ointr)(void *), void *arg) 1595 { 1596 struct cs428x_softc *sc; 1597 uint32_t mem; 1598 1599 DPRINTF(("midi_open\n")); 1600 sc = addr; 1601 sc->sc_iintr = iintr; 1602 sc->sc_ointr = ointr; 1603 sc->sc_arg = arg; 1604 1605 /* midi interrupt enable */ 1606 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1607 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1608 BA0WRITE4(sc, CS4280_MIDCR, mem); 1609 #ifdef CS4280_DEBUG 1610 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1611 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1612 return(EINVAL); 1613 } 1614 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1615 #endif 1616 return 0; 1617 } 1618 1619 static void 1620 cs4280_midi_close(void *addr) 1621 { 1622 struct cs428x_softc *sc; 1623 uint32_t mem; 1624 1625 DPRINTF(("midi_close\n")); 1626 sc = addr; 1627 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1628 mem = BA0READ4(sc, CS4280_MIDCR); 1629 mem &= ~MIDCR_MASK; 1630 BA0WRITE4(sc, CS4280_MIDCR, mem); 1631 1632 sc->sc_iintr = 0; 1633 sc->sc_ointr = 0; 1634 } 1635 1636 static int 1637 cs4280_midi_output(void *addr, int d) 1638 { 1639 struct cs428x_softc *sc; 1640 uint32_t mem; 1641 int x; 1642 1643 sc = addr; 1644 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1645 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1646 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1647 mem |= d & MIDWP_MASK; 1648 DPRINTFN(5,("midi_output d=0x%08x",d)); 1649 BA0WRITE4(sc, CS4280_MIDWP, mem); 1650 #ifdef DIAGNOSTIC 1651 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1652 DPRINTF(("Bad write data: %d %d", 1653 mem, BA0READ4(sc, CS4280_MIDWP))); 1654 return EIO; 1655 } 1656 #endif 1657 return 0; 1658 } 1659 delay(MIDI_BUSY_DELAY); 1660 } 1661 return EIO; 1662 } 1663 1664 static void 1665 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1666 { 1667 1668 mi->name = "CS4280 MIDI UART"; 1669 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1670 } 1671 1672 #endif /* NMIDI */ 1673 1674 /* DEBUG functions */ 1675 #if CS4280_DEBUG > 10 1676 static int 1677 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1678 uint32_t offset, uint32_t len) 1679 { 1680 uint32_t ctr, data; 1681 int err; 1682 1683 if ((offset & 3) || (len & 3)) 1684 return -1; 1685 1686 err = 0; 1687 len /= sizeof(uint32_t); 1688 for (ctr = 0; ctr < len; ctr++) { 1689 /* I cannot confirm this is the right thing 1690 * on BIG-ENDIAN machines 1691 */ 1692 data = BA1READ4(sc, offset+ctr*4); 1693 if (data != htole32(*(src+ctr))) { 1694 printf("0x%06x: 0x%08x(0x%08x)\n", 1695 offset+ctr*4, data, *(src+ctr)); 1696 *(src+ctr) = data; 1697 ++err; 1698 } 1699 } 1700 return err; 1701 } 1702 1703 static int 1704 cs4280_check_images(struct cs428x_softc *sc) 1705 { 1706 int idx, err; 1707 uint32_t offset; 1708 1709 offset = 0; 1710 err = 0; 1711 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1712 for (idx = 0; idx < 1; ++idx) { 1713 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1714 BA1Struct.memory[idx].offset, 1715 BA1Struct.memory[idx].size); 1716 if (err != 0) { 1717 printf("%s: check_image failed at %d\n", 1718 sc->sc_dev.dv_xname, idx); 1719 } 1720 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1721 } 1722 return err; 1723 } 1724 1725 #endif /* CS4280_DEBUG */ 1726
Indexes created Thu Oct 02 14:10:14 GMT 2025