cs4280.c revision 1.42
1 /* $NetBSD: cs4280.c,v 1.42 2006/08/29 23:53:06 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.42 2006/08/29 23:53:06 christos Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <sys/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(struct device *, struct cfdata *, void *); 93 static void cs4280_attach(struct device *, struct device *, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 107 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 108 #if 0 109 static int cs4280_reset_codec(void *); 110 #endif 111 static enum ac97_host_flags cs4280_flags_codec(void *); 112 113 /* For PowerHook */ 114 static void cs4280_power(int, void *); 115 116 /* Internal functions */ 117 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *); 118 static int cs4280_piix4_match(struct pci_attach_args *); 119 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 120 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 121 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 122 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 123 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 124 uint32_t); 125 static int cs4280_download_image(struct cs428x_softc *); 126 static void cs4280_reset(void *); 127 static int cs4280_init(struct cs428x_softc *, int); 128 static void cs4280_clear_fifos(struct cs428x_softc *); 129 130 #if CS4280_DEBUG > 10 131 /* Thease two function is only for checking image loading is succeeded or not. */ 132 static int cs4280_check_images(struct cs428x_softc *); 133 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 134 uint32_t); 135 #endif 136 137 /* Special cards */ 138 struct cs4280_card_t 139 { 140 pcireg_t id; 141 enum cs428x_flags flags; 142 }; 143 144 #define _card(vend, prod, flags) \ 145 {PCI_ID_CODE(vend, prod), flags} 146 147 static const struct cs4280_card_t cs4280_cards[] = { 148 #if 0 /* untested, from ALSA driver */ 149 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 150 CS428X_FLAG_INVAC97EAMP), 151 #endif 152 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 153 CS428X_FLAG_INVAC97EAMP), 154 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 155 CS428X_FLAG_CLKRUNHACK) 156 }; 157 158 #undef _card 159 160 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 161 162 static const struct audio_hw_if cs4280_hw_if = { 163 NULL, /* open */ 164 NULL, /* close */ 165 NULL, 166 cs4280_query_encoding, 167 cs4280_set_params, 168 cs428x_round_blocksize, 169 NULL, 170 NULL, 171 NULL, 172 NULL, 173 NULL, 174 cs4280_halt_output, 175 cs4280_halt_input, 176 NULL, 177 cs4280_getdev, 178 NULL, 179 cs428x_mixer_set_port, 180 cs428x_mixer_get_port, 181 cs428x_query_devinfo, 182 cs428x_malloc, 183 cs428x_free, 184 cs428x_round_buffersize, 185 cs428x_mappage, 186 cs428x_get_props, 187 cs4280_trigger_output, 188 cs4280_trigger_input, 189 NULL, 190 NULL, 191 }; 192 193 #if NMIDI > 0 194 /* Midi Interface */ 195 static int cs4280_midi_open(void *, int, void (*)(void *, int), 196 void (*)(void *), void *); 197 static void cs4280_midi_close(void*); 198 static int cs4280_midi_output(void *, int); 199 static void cs4280_midi_getinfo(void *, struct midi_info *); 200 201 static const struct midi_hw_if cs4280_midi_hw_if = { 202 cs4280_midi_open, 203 cs4280_midi_close, 204 cs4280_midi_output, 205 cs4280_midi_getinfo, 206 0, 207 }; 208 #endif 209 210 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 211 cs4280_match, cs4280_attach, NULL, NULL); 212 213 static struct audio_device cs4280_device = { 214 "CS4280", 215 "", 216 "cs4280" 217 }; 218 219 220 static int 221 cs4280_match(struct device *parent, struct cfdata *match, void *aux) 222 { 223 struct pci_attach_args *pa; 224 225 pa = (struct pci_attach_args *)aux; 226 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 227 return 0; 228 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 229 #if 0 /* I can't confirm */ 230 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 231 #endif 232 ) 233 return 1; 234 return 0; 235 } 236 237 static void 238 cs4280_attach(struct device *parent, struct device *self, void *aux) 239 { 240 struct cs428x_softc *sc; 241 struct pci_attach_args *pa; 242 pci_chipset_tag_t pc; 243 const struct cs4280_card_t *cs_card; 244 char const *intrstr; 245 pci_intr_handle_t ih; 246 pcireg_t reg; 247 char devinfo[256]; 248 uint32_t mem; 249 int error; 250 251 sc = (struct cs428x_softc *)self; 252 pa = (struct pci_attach_args *)aux; 253 pc = pa->pa_pc; 254 aprint_naive(": Audio controller\n"); 255 256 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 257 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 258 PCI_REVISION(pa->pa_class)); 259 260 cs_card = cs4280_identify_card(pa); 261 if (cs_card != NULL) { 262 aprint_normal("%s: %s %s\n",sc->sc_dev.dv_xname, 263 pci_findvendor(cs_card->id), 264 pci_findproduct(cs_card->id)); 265 sc->sc_flags = cs_card->flags; 266 } else { 267 sc->sc_flags = CS428X_FLAG_NONE; 268 } 269 270 /* Map I/O register */ 271 if (pci_mapreg_map(pa, PCI_BA0, 272 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 273 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 274 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 275 return; 276 } 277 if (pci_mapreg_map(pa, PCI_BA1, 278 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 279 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 280 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 281 return; 282 } 283 284 sc->sc_dmatag = pa->pa_dmat; 285 286 /* power up chip */ 287 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 288 pci_activate_null)) && error != EOPNOTSUPP) { 289 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 290 error); 291 return; 292 } 293 294 /* Enable the device (set bus master flag) */ 295 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 296 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 297 reg | PCI_COMMAND_MASTER_ENABLE); 298 299 /* LATENCY_TIMER setting */ 300 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 301 if ( PCI_LATTIMER(mem) < 32 ) { 302 mem &= 0xffff00ff; 303 mem |= 0x00002000; 304 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 305 } 306 307 /* CLKRUN hack initialization */ 308 cs4280_clkrun_hack_init(sc); 309 310 /* Map and establish the interrupt. */ 311 if (pci_intr_map(pa, &ih)) { 312 aprint_error("%s: couldn't map interrupt\n", 313 sc->sc_dev.dv_xname); 314 return; 315 } 316 intrstr = pci_intr_string(pc, ih); 317 318 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 319 if (sc->sc_ih == NULL) { 320 aprint_error("%s: couldn't establish interrupt", 321 sc->sc_dev.dv_xname); 322 if (intrstr != NULL) 323 aprint_normal(" at %s", intrstr); 324 aprint_normal("\n"); 325 return; 326 } 327 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 328 329 /* Initialization */ 330 if(cs4280_init(sc, 1) != 0) 331 return; 332 333 sc->type = TYPE_CS4280; 334 sc->halt_input = cs4280_halt_input; 335 sc->halt_output = cs4280_halt_output; 336 337 /* setup buffer related parameters */ 338 sc->dma_size = CS4280_DCHUNK; 339 sc->dma_align = CS4280_DALIGN; 340 sc->hw_blocksize = CS4280_ICHUNK; 341 342 /* AC 97 attachment */ 343 sc->host_if.arg = sc; 344 sc->host_if.attach = cs428x_attach_codec; 345 sc->host_if.read = cs4280_read_codec; 346 sc->host_if.write = cs4280_write_codec; 347 #if 0 348 sc->host_if.reset = cs4280_reset_codec; 349 #else 350 sc->host_if.reset = NULL; 351 #endif 352 sc->host_if.flags = cs4280_flags_codec; 353 if (ac97_attach(&sc->host_if, self) != 0) { 354 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 355 return; 356 } 357 358 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 359 360 #if NMIDI > 0 361 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 362 #endif 363 364 sc->sc_suspend = PWR_RESUME; 365 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 366 } 367 368 /* Interrupt handling function */ 369 static int 370 cs4280_intr(void *p) 371 { 372 /* 373 * XXX 374 * 375 * Since CS4280 has only 4kB DMA buffer and 376 * interrupt occurs every 2kB block, I create dummy buffer 377 * which returns to audio driver and actual DMA buffer 378 * using in DMA transfer. 379 * 380 * 381 * ring buffer in audio.c is pointed by BUFADDR 382 * <------ ring buffer size == 64kB ------> 383 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 384 * |= = = =|= = = =|= = = =|= = = =|= = = =| 385 * | | | | | | <- call audio_intp every 386 * sc->sc_[pr]_count time. 387 * 388 * actual DMA buffer is pointed by KERNADDR 389 * <-> DMA buffer size = 4kB 390 * |= =| 391 * 392 * 393 */ 394 struct cs428x_softc *sc; 395 uint32_t intr, mem; 396 char * empty_dma; 397 int handled; 398 399 sc = p; 400 handled = 0; 401 /* grab interrupt register then clear it */ 402 intr = BA0READ4(sc, CS4280_HISR); 403 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 404 405 /* not for us ? */ 406 if ((intr & HISR_INTENA) == 0) 407 return 0; 408 409 /* Playback Interrupt */ 410 if (intr & HISR_PINT) { 411 handled = 1; 412 mem = BA1READ4(sc, CS4280_PFIE); 413 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 414 if (sc->sc_prun) { 415 if ((sc->sc_pi%sc->sc_pcount) == 0) 416 sc->sc_pintr(sc->sc_parg); 417 /* copy buffer */ 418 ++sc->sc_pi; 419 empty_dma = sc->sc_pdma->addr; 420 if (sc->sc_pi&1) 421 empty_dma += sc->hw_blocksize; 422 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 423 sc->sc_pn += sc->hw_blocksize; 424 if (sc->sc_pn >= sc->sc_pe) 425 sc->sc_pn = sc->sc_ps; 426 } else { 427 printf("%s: unexpected play intr\n", 428 sc->sc_dev.dv_xname); 429 } 430 BA1WRITE4(sc, CS4280_PFIE, mem); 431 } 432 /* Capture Interrupt */ 433 if (intr & HISR_CINT) { 434 int i; 435 int16_t rdata; 436 437 handled = 1; 438 mem = BA1READ4(sc, CS4280_CIE); 439 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 440 441 if (sc->sc_rrun) { 442 ++sc->sc_ri; 443 empty_dma = sc->sc_rdma->addr; 444 if ((sc->sc_ri&1) == 0) 445 empty_dma += sc->hw_blocksize; 446 447 /* 448 * XXX 449 * I think this audio data conversion should be 450 * happend in upper layer, but I put this here 451 * since there is no conversion function available. 452 */ 453 switch(sc->sc_rparam) { 454 case CF_16BIT_STEREO: 455 /* just copy it */ 456 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 457 sc->sc_rn += sc->hw_blocksize; 458 break; 459 case CF_16BIT_MONO: 460 for (i = 0; i < 512; i++) { 461 rdata = *((int16_t *)empty_dma)>>1; 462 empty_dma += 2; 463 rdata += *((int16_t *)empty_dma)>>1; 464 empty_dma += 2; 465 *((int16_t *)sc->sc_rn) = rdata; 466 sc->sc_rn += 2; 467 } 468 break; 469 case CF_8BIT_STEREO: 470 for (i = 0; i < 512; i++) { 471 rdata = *((int16_t*)empty_dma); 472 empty_dma += 2; 473 *sc->sc_rn++ = rdata >> 8; 474 rdata = *((int16_t*)empty_dma); 475 empty_dma += 2; 476 *sc->sc_rn++ = rdata >> 8; 477 } 478 break; 479 case CF_8BIT_MONO: 480 for (i = 0; i < 512; i++) { 481 rdata = *((int16_t*)empty_dma) >>1; 482 empty_dma += 2; 483 rdata += *((int16_t*)empty_dma) >>1; 484 empty_dma += 2; 485 *sc->sc_rn++ = rdata >>8; 486 } 487 break; 488 default: 489 /* Should not reach here */ 490 printf("%s: unknown sc->sc_rparam: %d\n", 491 sc->sc_dev.dv_xname, sc->sc_rparam); 492 } 493 if (sc->sc_rn >= sc->sc_re) 494 sc->sc_rn = sc->sc_rs; 495 } 496 BA1WRITE4(sc, CS4280_CIE, mem); 497 498 if (sc->sc_rrun) { 499 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 500 sc->sc_rintr(sc->sc_rarg); 501 } else { 502 printf("%s: unexpected record intr\n", 503 sc->sc_dev.dv_xname); 504 } 505 } 506 507 #if NMIDI > 0 508 /* Midi port Interrupt */ 509 if (intr & HISR_MIDI) { 510 int data; 511 512 handled = 1; 513 DPRINTF(("i: %d: ", 514 BA0READ4(sc, CS4280_MIDSR))); 515 /* Read the received data */ 516 while ((sc->sc_iintr != NULL) && 517 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 518 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 519 DPRINTF(("r:%x\n",data)); 520 sc->sc_iintr(sc->sc_arg, data); 521 } 522 523 /* Write the data */ 524 #if 1 525 /* XXX: 526 * It seems "Transmit Buffer Full" never activate until EOI 527 * is deliverd. Shall I throw EOI top of this routine ? 528 */ 529 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 530 DPRINTF(("w: ")); 531 if (sc->sc_ointr != NULL) 532 sc->sc_ointr(sc->sc_arg); 533 } 534 #else 535 while ((sc->sc_ointr != NULL) && 536 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 537 DPRINTF(("w: ")); 538 sc->sc_ointr(sc->sc_arg); 539 } 540 #endif 541 DPRINTF(("\n")); 542 } 543 #endif 544 545 return handled; 546 } 547 548 static int 549 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 550 { 551 switch (fp->index) { 552 case 0: 553 strcpy(fp->name, AudioEulinear); 554 fp->encoding = AUDIO_ENCODING_ULINEAR; 555 fp->precision = 8; 556 fp->flags = 0; 557 break; 558 case 1: 559 strcpy(fp->name, AudioEmulaw); 560 fp->encoding = AUDIO_ENCODING_ULAW; 561 fp->precision = 8; 562 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 563 break; 564 case 2: 565 strcpy(fp->name, AudioEalaw); 566 fp->encoding = AUDIO_ENCODING_ALAW; 567 fp->precision = 8; 568 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 569 break; 570 case 3: 571 strcpy(fp->name, AudioEslinear); 572 fp->encoding = AUDIO_ENCODING_SLINEAR; 573 fp->precision = 8; 574 fp->flags = 0; 575 break; 576 case 4: 577 strcpy(fp->name, AudioEslinear_le); 578 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 579 fp->precision = 16; 580 fp->flags = 0; 581 break; 582 case 5: 583 strcpy(fp->name, AudioEulinear_le); 584 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 585 fp->precision = 16; 586 fp->flags = 0; 587 break; 588 case 6: 589 strcpy(fp->name, AudioEslinear_be); 590 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 591 fp->precision = 16; 592 fp->flags = 0; 593 break; 594 case 7: 595 strcpy(fp->name, AudioEulinear_be); 596 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 597 fp->precision = 16; 598 fp->flags = 0; 599 break; 600 default: 601 return EINVAL; 602 } 603 return 0; 604 } 605 606 static int 607 cs4280_set_params(void *addr, int setmode, int usemode, 608 audio_params_t *play, audio_params_t *rec, 609 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 610 { 611 audio_params_t hw; 612 struct cs428x_softc *sc; 613 struct audio_params *p; 614 stream_filter_list_t *fil; 615 int mode; 616 617 sc = addr; 618 for (mode = AUMODE_RECORD; mode != -1; 619 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 620 if ((setmode & mode) == 0) 621 continue; 622 623 p = mode == AUMODE_PLAY ? play : rec; 624 625 if (p == play) { 626 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 627 p->sample_rate, p->precision, p->channels)); 628 /* play back data format may be 8- or 16-bit and 629 * either stereo or mono. 630 * playback rate may range from 8000Hz to 48000Hz 631 */ 632 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 633 (p->precision != 8 && p->precision != 16) || 634 (p->channels != 1 && p->channels != 2) ) { 635 return EINVAL; 636 } 637 } else { 638 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 639 p->sample_rate, p->precision, p->channels)); 640 /* capture data format must be 16bit stereo 641 * and sample rate range from 11025Hz to 48000Hz. 642 * 643 * XXX: it looks like to work with 8000Hz, 644 * although data sheets say lower limit is 645 * 11025 Hz. 646 */ 647 648 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 649 (p->precision != 8 && p->precision != 16) || 650 (p->channels != 1 && p->channels != 2) ) { 651 return EINVAL; 652 } 653 } 654 fil = mode == AUMODE_PLAY ? pfil : rfil; 655 hw = *p; 656 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 657 658 /* capturing data is slinear */ 659 switch (p->encoding) { 660 case AUDIO_ENCODING_SLINEAR_BE: 661 if (mode == AUMODE_RECORD && p->precision == 16) { 662 fil->append(fil, swap_bytes, &hw); 663 } 664 break; 665 case AUDIO_ENCODING_SLINEAR_LE: 666 break; 667 case AUDIO_ENCODING_ULINEAR_BE: 668 if (mode == AUMODE_RECORD) { 669 fil->append(fil, p->precision == 16 670 ? swap_bytes_change_sign16 671 : change_sign8, &hw); 672 } 673 break; 674 case AUDIO_ENCODING_ULINEAR_LE: 675 if (mode == AUMODE_RECORD) { 676 fil->append(fil, p->precision == 16 677 ? change_sign16 : change_sign8, 678 &hw); 679 } 680 break; 681 case AUDIO_ENCODING_ULAW: 682 if (mode == AUMODE_PLAY) { 683 hw.precision = 16; 684 hw.validbits = 16; 685 fil->append(fil, mulaw_to_linear16, &hw); 686 } else { 687 fil->append(fil, linear8_to_mulaw, &hw); 688 } 689 break; 690 case AUDIO_ENCODING_ALAW: 691 if (mode == AUMODE_PLAY) { 692 hw.precision = 16; 693 hw.validbits = 16; 694 fil->append(fil, alaw_to_linear16, &hw); 695 } else { 696 fil->append(fil, linear8_to_alaw, &hw); 697 } 698 break; 699 default: 700 return EINVAL; 701 } 702 } 703 704 /* set sample rate */ 705 cs4280_set_dac_rate(sc, play->sample_rate); 706 cs4280_set_adc_rate(sc, rec->sample_rate); 707 return 0; 708 } 709 710 static int 711 cs4280_halt_output(void *addr) 712 { 713 struct cs428x_softc *sc; 714 uint32_t mem; 715 716 sc = addr; 717 mem = BA1READ4(sc, CS4280_PCTL); 718 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 719 sc->sc_prun = 0; 720 cs4280_clkrun_hack(sc, -1); 721 722 return 0; 723 } 724 725 static int 726 cs4280_halt_input(void *addr) 727 { 728 struct cs428x_softc *sc; 729 uint32_t mem; 730 731 sc = addr; 732 mem = BA1READ4(sc, CS4280_CCTL); 733 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 734 sc->sc_rrun = 0; 735 cs4280_clkrun_hack(sc, -1); 736 737 return 0; 738 } 739 740 static int 741 cs4280_getdev(void *addr, struct audio_device *retp) 742 { 743 744 *retp = cs4280_device; 745 return 0; 746 } 747 748 static int 749 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 750 void (*intr)(void *), void *arg, 751 const audio_params_t *param) 752 { 753 struct cs428x_softc *sc; 754 uint32_t pfie, pctl, pdtc; 755 struct cs428x_dma *p; 756 757 sc = addr; 758 #ifdef DIAGNOSTIC 759 if (sc->sc_prun) 760 printf("cs4280_trigger_output: already running\n"); 761 #endif 762 sc->sc_prun = 1; 763 cs4280_clkrun_hack(sc, 1); 764 765 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 766 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 767 sc->sc_pintr = intr; 768 sc->sc_parg = arg; 769 770 /* stop playback DMA */ 771 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 772 773 /* setup PDTC */ 774 pdtc = BA1READ4(sc, CS4280_PDTC); 775 pdtc &= ~PDTC_MASK; 776 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 777 BA1WRITE4(sc, CS4280_PDTC, pdtc); 778 779 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 780 param->precision, param->channels, param->encoding)); 781 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 782 continue; 783 if (p == NULL) { 784 printf("cs4280_trigger_output: bad addr %p\n", start); 785 return EINVAL; 786 } 787 if (DMAADDR(p) % sc->dma_align != 0 ) { 788 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 789 "4kB align\n", (ulong)DMAADDR(p)); 790 return EINVAL; 791 } 792 793 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 794 sc->sc_ps = (char *)start; 795 sc->sc_pe = (char *)end; 796 sc->sc_pdma = p; 797 sc->sc_pbuf = KERNADDR(p); 798 sc->sc_pi = 0; 799 sc->sc_pn = sc->sc_ps; 800 if (blksize >= sc->dma_size) { 801 sc->sc_pn = sc->sc_ps + sc->dma_size; 802 memcpy(sc->sc_pbuf, start, sc->dma_size); 803 ++sc->sc_pi; 804 } else { 805 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 806 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 807 } 808 809 /* initiate playback DMA */ 810 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 811 812 /* set PFIE */ 813 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 814 815 if (param->precision == 8) 816 pfie |= PFIE_8BIT; 817 if (param->channels == 1) 818 pfie |= PFIE_MONO; 819 820 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 821 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 822 pfie |= PFIE_SWAPPED; 823 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 824 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 825 pfie |= PFIE_UNSIGNED; 826 827 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 828 829 sc->sc_prate = param->sample_rate; 830 cs4280_set_dac_rate(sc, param->sample_rate); 831 832 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 833 pctl |= sc->pctl; 834 BA1WRITE4(sc, CS4280_PCTL, pctl); 835 return 0; 836 } 837 838 static int 839 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 840 void (*intr)(void *), void *arg, 841 const audio_params_t *param) 842 { 843 struct cs428x_softc *sc; 844 uint32_t cctl, cie; 845 struct cs428x_dma *p; 846 847 sc = addr; 848 #ifdef DIAGNOSTIC 849 if (sc->sc_rrun) 850 printf("cs4280_trigger_input: already running\n"); 851 #endif 852 sc->sc_rrun = 1; 853 cs4280_clkrun_hack(sc, 1); 854 855 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 856 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 857 sc->sc_rintr = intr; 858 sc->sc_rarg = arg; 859 860 /* stop capture DMA */ 861 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 862 863 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 864 continue; 865 if (p == NULL) { 866 printf("cs4280_trigger_input: bad addr %p\n", start); 867 return EINVAL; 868 } 869 if (DMAADDR(p) % sc->dma_align != 0) { 870 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 871 "4kB align\n", (ulong)DMAADDR(p)); 872 return EINVAL; 873 } 874 875 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 876 sc->sc_rs = (char *)start; 877 sc->sc_re = (char *)end; 878 sc->sc_rdma = p; 879 sc->sc_rbuf = KERNADDR(p); 880 sc->sc_ri = 0; 881 sc->sc_rn = sc->sc_rs; 882 883 /* initiate capture DMA */ 884 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 885 886 /* setup format information for internal converter */ 887 sc->sc_rparam = 0; 888 if (param->precision == 8) { 889 sc->sc_rparam += CF_8BIT; 890 sc->sc_rcount <<= 1; 891 } 892 if (param->channels == 1) { 893 sc->sc_rparam += CF_MONO; 894 sc->sc_rcount <<= 1; 895 } 896 897 /* set CIE */ 898 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 899 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 900 901 sc->sc_rrate = param->sample_rate; 902 cs4280_set_adc_rate(sc, param->sample_rate); 903 904 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 905 cctl |= sc->cctl; 906 BA1WRITE4(sc, CS4280_CCTL, cctl); 907 return 0; 908 } 909 910 /* Power Hook */ 911 static void 912 cs4280_power(int why, void *v) 913 { 914 static uint32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 915 static uint32_t cctl = 0, cba = 0, cie = 0; 916 struct cs428x_softc *sc; 917 918 sc = (struct cs428x_softc *)v; 919 DPRINTF(("%s: cs4280_power why=%d\n", sc->sc_dev.dv_xname, why)); 920 switch (why) { 921 case PWR_SUSPEND: 922 case PWR_STANDBY: 923 sc->sc_suspend = why; 924 925 /* save current playback status */ 926 if (sc->sc_prun) { 927 pctl = BA1READ4(sc, CS4280_PCTL); 928 pfie = BA1READ4(sc, CS4280_PFIE); 929 pba = BA1READ4(sc, CS4280_PBA); 930 pdtc = BA1READ4(sc, CS4280_PDTC); 931 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 932 pctl, pfie, pba, pdtc)); 933 } 934 935 /* save current capture status */ 936 if (sc->sc_rrun) { 937 cctl = BA1READ4(sc, CS4280_CCTL); 938 cie = BA1READ4(sc, CS4280_CIE); 939 cba = BA1READ4(sc, CS4280_CBA); 940 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 941 cctl, cie, cba)); 942 } 943 944 /* Stop DMA */ 945 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 946 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 947 break; 948 case PWR_RESUME: 949 if (sc->sc_suspend == PWR_RESUME) { 950 printf("cs4280_power: odd, resume without suspend.\n"); 951 sc->sc_suspend = why; 952 return; 953 } 954 sc->sc_suspend = why; 955 cs4280_init(sc, 0); 956 #if 0 957 cs4280_reset_codec(sc); 958 #endif 959 /* restore ac97 registers */ 960 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 961 962 /* restore DMA related status */ 963 if(sc->sc_prun) { 964 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 965 pctl, pfie, pba, pdtc)); 966 cs4280_set_dac_rate(sc, sc->sc_prate); 967 BA1WRITE4(sc, CS4280_PDTC, pdtc); 968 BA1WRITE4(sc, CS4280_PBA, pba); 969 BA1WRITE4(sc, CS4280_PFIE, pfie); 970 BA1WRITE4(sc, CS4280_PCTL, pctl); 971 } 972 973 if (sc->sc_rrun) { 974 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 975 cctl, cie, cba)); 976 cs4280_set_adc_rate(sc, sc->sc_rrate); 977 BA1WRITE4(sc, CS4280_CBA, cba); 978 BA1WRITE4(sc, CS4280_CIE, cie); 979 BA1WRITE4(sc, CS4280_CCTL, cctl); 980 } 981 break; 982 case PWR_SOFTSUSPEND: 983 case PWR_SOFTSTANDBY: 984 case PWR_SOFTRESUME: 985 break; 986 } 987 } 988 989 static int 990 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 991 { 992 struct cs428x_softc *sc = addr; 993 int rv; 994 995 cs4280_clkrun_hack(sc, 1); 996 rv = cs428x_read_codec(addr, reg, result); 997 cs4280_clkrun_hack(sc, -1); 998 999 return rv; 1000 } 1001 1002 static int 1003 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1004 { 1005 struct cs428x_softc *sc = addr; 1006 int rv; 1007 1008 cs4280_clkrun_hack(sc, 1); 1009 rv = cs428x_write_codec(addr, reg, data); 1010 cs4280_clkrun_hack(sc, -1); 1011 1012 return rv; 1013 } 1014 1015 #if 0 /* XXX buggy and not required */ 1016 /* control AC97 codec */ 1017 static int 1018 cs4280_reset_codec(void *addr) 1019 { 1020 struct cs428x_softc *sc; 1021 int n; 1022 1023 sc = addr; 1024 1025 /* Reset codec */ 1026 BA0WRITE4(sc, CS428X_ACCTL, 0); 1027 delay(100); /* delay 100us */ 1028 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1029 1030 /* 1031 * It looks like we do the following procedure, too 1032 */ 1033 1034 /* Enable AC-link sync generation */ 1035 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1036 delay(50*1000); /* XXX delay 50ms */ 1037 1038 /* Assert valid frame signal */ 1039 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1040 1041 /* Wait for valid AC97 input slot */ 1042 n = 0; 1043 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1044 (ACISV_ISV3 | ACISV_ISV4)) { 1045 delay(1000); 1046 if (++n > 1000) { 1047 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1048 return ETIMEDOUT; 1049 } 1050 } 1051 1052 return 0; 1053 } 1054 #endif 1055 1056 static enum ac97_host_flags cs4280_flags_codec(void *addr) 1057 { 1058 struct cs428x_softc *sc; 1059 1060 sc = addr; 1061 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1062 return AC97_HOST_INVERTED_EAMP; 1063 1064 return 0; 1065 } 1066 1067 /* Internal functions */ 1068 1069 static const struct cs4280_card_t * 1070 cs4280_identify_card(struct pci_attach_args *pa) 1071 { 1072 pcireg_t idreg; 1073 u_int16_t i; 1074 1075 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1076 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1077 if (idreg == cs4280_cards[i].id) 1078 return &cs4280_cards[i]; 1079 } 1080 1081 return NULL; 1082 } 1083 1084 static int 1085 cs4280_piix4_match(struct pci_attach_args *pa) 1086 { 1087 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1088 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1089 return 1; 1090 } 1091 1092 return 0; 1093 } 1094 1095 static void 1096 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1097 { 1098 uint16_t control, val; 1099 1100 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1101 return; 1102 1103 sc->sc_active += change; 1104 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1105 if (!sc->sc_active) 1106 val |= 0x2000; 1107 else 1108 val &= ~0x2000; 1109 if (val != control) 1110 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1111 } 1112 1113 static void 1114 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1115 { 1116 struct pci_attach_args smbuspa; 1117 uint16_t reg; 1118 pcireg_t port; 1119 1120 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1121 return; 1122 1123 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1124 sc->sc_active = 0; 1125 printf("%s: enabling CLKRUN hack\n", 1126 sc->sc_dev.dv_xname); 1127 1128 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1129 port = reg & 0xffc0; 1130 printf("%s: power management port 0x%x\n", sc->sc_dev.dv_xname, 1131 port); 1132 1133 sc->sc_pm_iot = smbuspa.pa_iot; 1134 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1135 &sc->sc_pm_ioh) == 0) 1136 return; 1137 } 1138 1139 /* handle error */ 1140 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1141 printf("%s: disabling CLKRUN hack\n", sc->sc_dev.dv_xname); 1142 } 1143 1144 static void 1145 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1146 { 1147 /* calculate capture rate: 1148 * 1149 * capture_coefficient_increment = -round(rate*128*65536/48000; 1150 * capture_phase_increment = floor(48000*65536*1024/rate); 1151 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1152 * cy = floor(cx/200); 1153 * capture_sample_rate_correction = cx - 200*cy; 1154 * capture_delay = ceil(24*48000/rate); 1155 * capture_num_triplets = floor(65536*rate/24000); 1156 * capture_group_length = 24000/GCD(rate, 24000); 1157 * where GCD means "Greatest Common Divisor". 1158 * 1159 * capture_coefficient_increment, capture_phase_increment and 1160 * capture_num_triplets are 32-bit signed quantities. 1161 * capture_sample_rate_correction and capture_group_length are 1162 * 16-bit signed quantities. 1163 * capture_delay is a 14-bit unsigned quantity. 1164 */ 1165 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1166 uint16_t csrc, cgl, cdlay; 1167 1168 /* XXX 1169 * Even though, embedded_audio_spec says capture rate range 11025 to 1170 * 48000, dhwiface.cpp says, 1171 * 1172 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1173 * Return an error if an attempt is made to stray outside that limit." 1174 * 1175 * so assume range as 48000/9 to 48000 1176 */ 1177 1178 if (rate < 8000) 1179 rate = 8000; 1180 if (rate > 48000) 1181 rate = 48000; 1182 1183 cx = rate << 16; 1184 cci = cx / 48000; 1185 cx -= cci * 48000; 1186 cx <<= 7; 1187 cci <<= 7; 1188 cci += cx / 48000; 1189 cci = - cci; 1190 1191 cx = 48000 << 16; 1192 cpi = cx / rate; 1193 cx -= cpi * rate; 1194 cx <<= 10; 1195 cpi <<= 10; 1196 cy = cx / rate; 1197 cpi += cy; 1198 cx -= cy * rate; 1199 1200 cy = cx / 200; 1201 csrc = cx - 200*cy; 1202 1203 cdlay = ((48000 * 24) + rate - 1) / rate; 1204 #if 0 1205 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1206 #endif 1207 1208 cnt = rate << 16; 1209 cnt /= 24000; 1210 1211 cgl = 1; 1212 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1213 if (((rate / tmp1) * tmp1) != rate) 1214 cgl *= 2; 1215 } 1216 if (((rate / 3) * 3) != rate) 1217 cgl *= 3; 1218 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1219 if (((rate / tmp1) * tmp1) != rate) 1220 cgl *= 5; 1221 } 1222 #if 0 1223 /* XXX what manual says */ 1224 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1225 tmp1 |= csrc<<16; 1226 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1227 #else 1228 /* suggested by cs461x.c (ALSA driver) */ 1229 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1230 #endif 1231 1232 #if 0 1233 /* I am confused. The sample rate calculation section says 1234 * cci *is* 32-bit signed quantity but in the parameter description 1235 * section, CCI only assigned 16bit. 1236 * I believe size of the variable. 1237 */ 1238 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1239 tmp1 |= cci<<16; 1240 BA1WRITE4(sc, CS4280_CCI, tmp1); 1241 #else 1242 BA1WRITE4(sc, CS4280_CCI, cci); 1243 #endif 1244 1245 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1246 tmp1 |= cdlay <<18; 1247 BA1WRITE4(sc, CS4280_CD, tmp1); 1248 1249 BA1WRITE4(sc, CS4280_CPI, cpi); 1250 1251 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1252 tmp1 |= cgl; 1253 BA1WRITE4(sc, CS4280_CGL, tmp1); 1254 1255 BA1WRITE4(sc, CS4280_CNT, cnt); 1256 1257 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1258 tmp1 |= cgl; 1259 BA1WRITE4(sc, CS4280_CGC, tmp1); 1260 } 1261 1262 static void 1263 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1264 { 1265 /* 1266 * playback rate may range from 8000Hz to 48000Hz 1267 * 1268 * play_phase_increment = floor(rate*65536*1024/48000) 1269 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1270 * py=floor(px/200) 1271 * play_sample_rate_correction = px - 200*py 1272 * 1273 * play_phase_increment is a 32bit signed quantity. 1274 * play_sample_rate_correction is a 16bit signed quantity. 1275 */ 1276 int32_t ppi; 1277 int16_t psrc; 1278 uint32_t px, py; 1279 1280 if (rate < 8000) 1281 rate = 8000; 1282 if (rate > 48000) 1283 rate = 48000; 1284 px = rate << 16; 1285 ppi = px/48000; 1286 px -= ppi*48000; 1287 ppi <<= 10; 1288 px <<= 10; 1289 py = px / 48000; 1290 ppi += py; 1291 px -= py*48000; 1292 py = px/200; 1293 px -= py*200; 1294 psrc = px; 1295 #if 0 1296 /* what manual says */ 1297 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1298 BA1WRITE4(sc, CS4280_PSRC, 1299 ( ((psrc<<16) & PSRC_MASK) | px )); 1300 #else 1301 /* suggested by cs461x.c (ALSA driver) */ 1302 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1303 #endif 1304 BA1WRITE4(sc, CS4280_PPI, ppi); 1305 } 1306 1307 /* Download Processor Code and Data image */ 1308 static int 1309 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1310 uint32_t offset, uint32_t len) 1311 { 1312 uint32_t ctr; 1313 #if CS4280_DEBUG > 10 1314 uint32_t con, data; 1315 uint8_t c0, c1, c2, c3; 1316 #endif 1317 if ((offset & 3) || (len & 3)) 1318 return -1; 1319 1320 len /= sizeof(uint32_t); 1321 for (ctr = 0; ctr < len; ctr++) { 1322 /* XXX: 1323 * I cannot confirm this is the right thing or not 1324 * on BIG-ENDIAN machines. 1325 */ 1326 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1327 #if CS4280_DEBUG > 10 1328 data = htole32(*(src+ctr)); 1329 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1330 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1331 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1332 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1333 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1334 if (data != con ) { 1335 printf("0x%06x: write=0x%08x read=0x%08x\n", 1336 offset+ctr*4, data, con); 1337 return -1; 1338 } 1339 #endif 1340 } 1341 return 0; 1342 } 1343 1344 static int 1345 cs4280_download_image(struct cs428x_softc *sc) 1346 { 1347 int idx, err; 1348 uint32_t offset = 0; 1349 1350 err = 0; 1351 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1352 err = cs4280_download(sc, &BA1Struct.map[offset], 1353 BA1Struct.memory[idx].offset, 1354 BA1Struct.memory[idx].size); 1355 if (err != 0) { 1356 printf("%s: load_image failed at %d\n", 1357 sc->sc_dev.dv_xname, idx); 1358 return -1; 1359 } 1360 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1361 } 1362 return err; 1363 } 1364 1365 /* Processor Soft Reset */ 1366 static void 1367 cs4280_reset(void *sc_) 1368 { 1369 struct cs428x_softc *sc; 1370 1371 sc = sc_; 1372 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1373 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1374 delay(100); 1375 /* Clear RSTSP bit in SPCR */ 1376 BA1WRITE4(sc, CS4280_SPCR, 0); 1377 /* enable DMA reqest */ 1378 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1379 } 1380 1381 static int 1382 cs4280_init(struct cs428x_softc *sc, int init) 1383 { 1384 int n; 1385 uint32_t mem; 1386 int rv; 1387 1388 rv = 1; 1389 cs4280_clkrun_hack(sc, 1); 1390 1391 /* Start PLL out in known state */ 1392 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1393 /* Start serial ports out in known state */ 1394 BA0WRITE4(sc, CS4280_SERMC1, 0); 1395 1396 /* Specify type of CODEC */ 1397 /* XXX should not be here */ 1398 #define SERACC_CODEC_TYPE_1_03 1399 #ifdef SERACC_CODEC_TYPE_1_03 1400 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1401 #else 1402 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1403 #endif 1404 1405 /* Reset codec */ 1406 BA0WRITE4(sc, CS428X_ACCTL, 0); 1407 delay(100); /* delay 100us */ 1408 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1409 1410 /* Enable AC-link sync generation */ 1411 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1412 delay(50*1000); /* delay 50ms */ 1413 1414 /* Set the serial port timing configuration */ 1415 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1416 1417 /* Setup clock control */ 1418 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1419 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1420 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1421 1422 /* Power up the PLL */ 1423 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1424 delay(50*1000); /* delay 50ms */ 1425 1426 /* Turn on clock */ 1427 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1428 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1429 1430 /* Set the serial port FIFO pointer to the 1431 * first sample in FIFO. (not documented) */ 1432 cs4280_clear_fifos(sc); 1433 1434 #if 0 1435 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1436 BA0WRITE4(sc, CS4280_SERBSP, 0); 1437 #endif 1438 1439 /* Configure the serial port */ 1440 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1441 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1442 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1443 1444 /* Wait for CODEC ready */ 1445 n = 0; 1446 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1447 delay(125); 1448 if (++n > 1000) { 1449 printf("%s: codec ready timeout\n", 1450 sc->sc_dev.dv_xname); 1451 goto exit; 1452 } 1453 } 1454 1455 /* Assert valid frame signal */ 1456 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1457 1458 /* Wait for valid AC97 input slot */ 1459 n = 0; 1460 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1461 (ACISV_ISV3 | ACISV_ISV4)) { 1462 delay(1000); 1463 if (++n > 1000) { 1464 printf("AC97 inputs slot ready timeout\n"); 1465 goto exit; 1466 } 1467 } 1468 1469 /* Set AC97 output slot valid signals */ 1470 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1471 1472 /* reset the processor */ 1473 cs4280_reset(sc); 1474 1475 /* Download the image to the processor */ 1476 if (cs4280_download_image(sc) != 0) { 1477 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1478 goto exit; 1479 } 1480 1481 /* Save playback parameter and then write zero. 1482 * this ensures that DMA doesn't immediately occur upon 1483 * starting the processor core 1484 */ 1485 mem = BA1READ4(sc, CS4280_PCTL); 1486 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1487 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1488 if (init != 0) 1489 sc->sc_prun = 0; 1490 1491 /* Save capture parameter and then write zero. 1492 * this ensures that DMA doesn't immediately occur upon 1493 * starting the processor core 1494 */ 1495 mem = BA1READ4(sc, CS4280_CCTL); 1496 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1497 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1498 if (init != 0) 1499 sc->sc_rrun = 0; 1500 1501 /* Processor Startup Procedure */ 1502 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1503 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1504 1505 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1506 n = 0; 1507 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1508 delay(10); 1509 if (++n > 1000) { 1510 printf("SPCR 1->0 transition timeout\n"); 1511 goto exit; 1512 } 1513 } 1514 1515 n = 0; 1516 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1517 delay(10); 1518 if (++n > 1000) { 1519 printf("SPCS 0->1 transition timeout\n"); 1520 goto exit; 1521 } 1522 } 1523 /* Processor is now running !!! */ 1524 1525 /* Setup volume */ 1526 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1527 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1528 1529 /* Interrupt enable */ 1530 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1531 1532 /* playback interrupt enable */ 1533 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1534 mem |= PFIE_PI_ENABLE; 1535 BA1WRITE4(sc, CS4280_PFIE, mem); 1536 /* capture interrupt enable */ 1537 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1538 mem |= CIE_CI_ENABLE; 1539 BA1WRITE4(sc, CS4280_CIE, mem); 1540 1541 #if NMIDI > 0 1542 /* Reset midi port */ 1543 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1544 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1545 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1546 /* midi interrupt enable */ 1547 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1548 BA0WRITE4(sc, CS4280_MIDCR, mem); 1549 #endif 1550 1551 rv = 0; 1552 1553 exit: 1554 cs4280_clkrun_hack(sc, -1); 1555 return rv; 1556 } 1557 1558 static void 1559 cs4280_clear_fifos(struct cs428x_softc *sc) 1560 { 1561 int pd, cnt, n; 1562 uint32_t mem; 1563 1564 pd = 0; 1565 /* 1566 * If device power down, power up the device and keep power down 1567 * state. 1568 */ 1569 mem = BA0READ4(sc, CS4280_CLKCR1); 1570 if (!(mem & CLKCR1_SWCE)) { 1571 printf("cs4280_clear_fifo: power down found.\n"); 1572 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1573 pd = 1; 1574 } 1575 BA0WRITE4(sc, CS4280_SERBWP, 0); 1576 for (cnt = 0; cnt < 256; cnt++) { 1577 n = 0; 1578 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1579 delay(1000); 1580 if (++n > 1000) { 1581 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1582 break; 1583 } 1584 } 1585 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1586 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1587 } 1588 if (pd) 1589 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1590 } 1591 1592 #if NMIDI > 0 1593 static int 1594 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1595 void (*ointr)(void *), void *arg) 1596 { 1597 struct cs428x_softc *sc; 1598 uint32_t mem; 1599 1600 DPRINTF(("midi_open\n")); 1601 sc = addr; 1602 sc->sc_iintr = iintr; 1603 sc->sc_ointr = ointr; 1604 sc->sc_arg = arg; 1605 1606 /* midi interrupt enable */ 1607 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1608 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1609 BA0WRITE4(sc, CS4280_MIDCR, mem); 1610 #ifdef CS4280_DEBUG 1611 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1612 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1613 return(EINVAL); 1614 } 1615 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1616 #endif 1617 return 0; 1618 } 1619 1620 static void 1621 cs4280_midi_close(void *addr) 1622 { 1623 struct cs428x_softc *sc; 1624 uint32_t mem; 1625 1626 DPRINTF(("midi_close\n")); 1627 sc = addr; 1628 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1629 mem = BA0READ4(sc, CS4280_MIDCR); 1630 mem &= ~MIDCR_MASK; 1631 BA0WRITE4(sc, CS4280_MIDCR, mem); 1632 1633 sc->sc_iintr = 0; 1634 sc->sc_ointr = 0; 1635 } 1636 1637 static int 1638 cs4280_midi_output(void *addr, int d) 1639 { 1640 struct cs428x_softc *sc; 1641 uint32_t mem; 1642 int x; 1643 1644 sc = addr; 1645 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1646 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1647 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1648 mem |= d & MIDWP_MASK; 1649 DPRINTFN(5,("midi_output d=0x%08x",d)); 1650 BA0WRITE4(sc, CS4280_MIDWP, mem); 1651 #ifdef DIAGNOSTIC 1652 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1653 DPRINTF(("Bad write data: %d %d", 1654 mem, BA0READ4(sc, CS4280_MIDWP))); 1655 return EIO; 1656 } 1657 #endif 1658 return 0; 1659 } 1660 delay(MIDI_BUSY_DELAY); 1661 } 1662 return EIO; 1663 } 1664 1665 static void 1666 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1667 { 1668 1669 mi->name = "CS4280 MIDI UART"; 1670 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1671 } 1672 1673 #endif /* NMIDI */ 1674 1675 /* DEBUG functions */ 1676 #if CS4280_DEBUG > 10 1677 static int 1678 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1679 uint32_t offset, uint32_t len) 1680 { 1681 uint32_t ctr, data; 1682 int err; 1683 1684 if ((offset & 3) || (len & 3)) 1685 return -1; 1686 1687 err = 0; 1688 len /= sizeof(uint32_t); 1689 for (ctr = 0; ctr < len; ctr++) { 1690 /* I cannot confirm this is the right thing 1691 * on BIG-ENDIAN machines 1692 */ 1693 data = BA1READ4(sc, offset+ctr*4); 1694 if (data != htole32(*(src+ctr))) { 1695 printf("0x%06x: 0x%08x(0x%08x)\n", 1696 offset+ctr*4, data, *(src+ctr)); 1697 *(src+ctr) = data; 1698 ++err; 1699 } 1700 } 1701 return err; 1702 } 1703 1704 static int 1705 cs4280_check_images(struct cs428x_softc *sc) 1706 { 1707 int idx, err; 1708 uint32_t offset; 1709 1710 offset = 0; 1711 err = 0; 1712 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1713 for (idx = 0; idx < 1; ++idx) { 1714 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1715 BA1Struct.memory[idx].offset, 1716 BA1Struct.memory[idx].size); 1717 if (err != 0) { 1718 printf("%s: check_image failed at %d\n", 1719 sc->sc_dev.dv_xname, idx); 1720 } 1721 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1722 } 1723 return err; 1724 } 1725 1726 #endif /* CS4280_DEBUG */ 1727
Indexes created Thu Oct 02 14:10:14 GMT 2025