cs4280.c revision 1.45.2.1
1 /* $NetBSD: cs4280.c,v 1.45.2.1 2007/06/18 11:45:33 liamjfoy Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.45.2.1 2007/06/18 11:45:33 liamjfoy Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <sys/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(struct device *, struct cfdata *, void *); 93 static void cs4280_attach(struct device *, struct device *, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 107 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 108 #if 0 109 static int cs4280_reset_codec(void *); 110 #endif 111 static enum ac97_host_flags cs4280_flags_codec(void *); 112 113 /* For PowerHook */ 114 static void cs4280_power(int, void *); 115 116 /* Internal functions */ 117 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *); 118 static int cs4280_piix4_match(struct pci_attach_args *); 119 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 120 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 121 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 122 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 123 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 124 uint32_t); 125 static int cs4280_download_image(struct cs428x_softc *); 126 static void cs4280_reset(void *); 127 static int cs4280_init(struct cs428x_softc *, int); 128 static void cs4280_clear_fifos(struct cs428x_softc *); 129 130 #if CS4280_DEBUG > 10 131 /* Thease two function is only for checking image loading is succeeded or not. */ 132 static int cs4280_check_images(struct cs428x_softc *); 133 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 134 uint32_t); 135 #endif 136 137 /* Special cards */ 138 struct cs4280_card_t 139 { 140 pcireg_t id; 141 enum cs428x_flags flags; 142 }; 143 144 #define _card(vend, prod, flags) \ 145 {PCI_ID_CODE(vend, prod), flags} 146 147 static const struct cs4280_card_t cs4280_cards[] = { 148 #if 0 /* untested, from ALSA driver */ 149 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 150 CS428X_FLAG_INVAC97EAMP), 151 #endif 152 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 153 CS428X_FLAG_INVAC97EAMP), 154 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 155 CS428X_FLAG_CLKRUNHACK) 156 }; 157 158 #undef _card 159 160 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 161 162 static const struct audio_hw_if cs4280_hw_if = { 163 NULL, /* open */ 164 NULL, /* close */ 165 NULL, 166 cs4280_query_encoding, 167 cs4280_set_params, 168 cs428x_round_blocksize, 169 NULL, 170 NULL, 171 NULL, 172 NULL, 173 NULL, 174 cs4280_halt_output, 175 cs4280_halt_input, 176 NULL, 177 cs4280_getdev, 178 NULL, 179 cs428x_mixer_set_port, 180 cs428x_mixer_get_port, 181 cs428x_query_devinfo, 182 cs428x_malloc, 183 cs428x_free, 184 cs428x_round_buffersize, 185 cs428x_mappage, 186 cs428x_get_props, 187 cs4280_trigger_output, 188 cs4280_trigger_input, 189 NULL, 190 NULL, 191 }; 192 193 #if NMIDI > 0 194 /* Midi Interface */ 195 static int cs4280_midi_open(void *, int, void (*)(void *, int), 196 void (*)(void *), void *); 197 static void cs4280_midi_close(void*); 198 static int cs4280_midi_output(void *, int); 199 static void cs4280_midi_getinfo(void *, struct midi_info *); 200 201 static const struct midi_hw_if cs4280_midi_hw_if = { 202 cs4280_midi_open, 203 cs4280_midi_close, 204 cs4280_midi_output, 205 cs4280_midi_getinfo, 206 0, 207 }; 208 #endif 209 210 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 211 cs4280_match, cs4280_attach, NULL, NULL); 212 213 static struct audio_device cs4280_device = { 214 "CS4280", 215 "", 216 "cs4280" 217 }; 218 219 220 static int 221 cs4280_match(struct device *parent, struct cfdata *match, 222 void *aux) 223 { 224 struct pci_attach_args *pa; 225 226 pa = (struct pci_attach_args *)aux; 227 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 228 return 0; 229 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 230 #if 0 /* I can't confirm */ 231 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 232 #endif 233 ) 234 return 1; 235 return 0; 236 } 237 238 static void 239 cs4280_attach(struct device *parent, struct device *self, void *aux) 240 { 241 struct cs428x_softc *sc; 242 struct pci_attach_args *pa; 243 pci_chipset_tag_t pc; 244 const struct cs4280_card_t *cs_card; 245 char const *intrstr; 246 pcireg_t reg; 247 char devinfo[256]; 248 uint32_t mem; 249 int error; 250 251 sc = (struct cs428x_softc *)self; 252 pa = (struct pci_attach_args *)aux; 253 pc = pa->pa_pc; 254 aprint_naive(": Audio controller\n"); 255 256 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 257 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 258 PCI_REVISION(pa->pa_class)); 259 260 cs_card = cs4280_identify_card(pa); 261 if (cs_card != NULL) { 262 aprint_normal("%s: %s %s\n",sc->sc_dev.dv_xname, 263 pci_findvendor(cs_card->id), 264 pci_findproduct(cs_card->id)); 265 sc->sc_flags = cs_card->flags; 266 } else { 267 sc->sc_flags = CS428X_FLAG_NONE; 268 } 269 270 sc->sc_pc = pa->pa_pc; 271 sc->sc_pt = pa->pa_tag; 272 273 /* Map I/O register */ 274 if (pci_mapreg_map(pa, PCI_BA0, 275 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 276 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 277 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 278 return; 279 } 280 if (pci_mapreg_map(pa, PCI_BA1, 281 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 282 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 283 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 284 return; 285 } 286 287 sc->sc_dmatag = pa->pa_dmat; 288 289 /* power up chip */ 290 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 291 pci_activate_null)) && error != EOPNOTSUPP) { 292 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 293 error); 294 return; 295 } 296 297 /* Enable the device (set bus master flag) */ 298 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 299 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 300 reg | PCI_COMMAND_MASTER_ENABLE); 301 302 /* LATENCY_TIMER setting */ 303 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 304 if ( PCI_LATTIMER(mem) < 32 ) { 305 mem &= 0xffff00ff; 306 mem |= 0x00002000; 307 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 308 } 309 310 /* CLKRUN hack initialization */ 311 cs4280_clkrun_hack_init(sc); 312 313 /* Map and establish the interrupt. */ 314 if (pci_intr_map(pa, &sc->intrh)) { 315 aprint_error("%s: couldn't map interrupt\n", 316 sc->sc_dev.dv_xname); 317 return; 318 } 319 intrstr = pci_intr_string(pc, sc->intrh); 320 321 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 322 cs4280_intr, sc); 323 if (sc->sc_ih == NULL) { 324 aprint_error("%s: couldn't establish interrupt", 325 sc->sc_dev.dv_xname); 326 if (intrstr != NULL) 327 aprint_normal(" at %s", intrstr); 328 aprint_normal("\n"); 329 return; 330 } 331 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 332 333 /* Initialization */ 334 if(cs4280_init(sc, 1) != 0) 335 return; 336 337 sc->type = TYPE_CS4280; 338 sc->halt_input = cs4280_halt_input; 339 sc->halt_output = cs4280_halt_output; 340 341 /* setup buffer related parameters */ 342 sc->dma_size = CS4280_DCHUNK; 343 sc->dma_align = CS4280_DALIGN; 344 sc->hw_blocksize = CS4280_ICHUNK; 345 346 /* AC 97 attachment */ 347 sc->host_if.arg = sc; 348 sc->host_if.attach = cs428x_attach_codec; 349 sc->host_if.read = cs4280_read_codec; 350 sc->host_if.write = cs4280_write_codec; 351 #if 0 352 sc->host_if.reset = cs4280_reset_codec; 353 #else 354 sc->host_if.reset = NULL; 355 #endif 356 sc->host_if.flags = cs4280_flags_codec; 357 if (ac97_attach(&sc->host_if, self) != 0) { 358 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 359 return; 360 } 361 362 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 363 364 #if NMIDI > 0 365 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 366 #endif 367 368 sc->sc_suspend = PWR_RESUME; 369 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 370 cs4280_power, sc); 371 } 372 373 /* Interrupt handling function */ 374 static int 375 cs4280_intr(void *p) 376 { 377 /* 378 * XXX 379 * 380 * Since CS4280 has only 4kB DMA buffer and 381 * interrupt occurs every 2kB block, I create dummy buffer 382 * which returns to audio driver and actual DMA buffer 383 * using in DMA transfer. 384 * 385 * 386 * ring buffer in audio.c is pointed by BUFADDR 387 * <------ ring buffer size == 64kB ------> 388 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 389 * |= = = =|= = = =|= = = =|= = = =|= = = =| 390 * | | | | | | <- call audio_intp every 391 * sc->sc_[pr]_count time. 392 * 393 * actual DMA buffer is pointed by KERNADDR 394 * <-> DMA buffer size = 4kB 395 * |= =| 396 * 397 * 398 */ 399 struct cs428x_softc *sc; 400 uint32_t intr, mem; 401 char * empty_dma; 402 int handled; 403 404 sc = p; 405 handled = 0; 406 /* grab interrupt register then clear it */ 407 intr = BA0READ4(sc, CS4280_HISR); 408 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 409 410 /* not for us ? */ 411 if ((intr & HISR_INTENA) == 0) 412 return 0; 413 414 /* Playback Interrupt */ 415 if (intr & HISR_PINT) { 416 handled = 1; 417 mem = BA1READ4(sc, CS4280_PFIE); 418 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 419 if (sc->sc_prun) { 420 if ((sc->sc_pi%sc->sc_pcount) == 0) 421 sc->sc_pintr(sc->sc_parg); 422 /* copy buffer */ 423 ++sc->sc_pi; 424 empty_dma = sc->sc_pdma->addr; 425 if (sc->sc_pi&1) 426 empty_dma += sc->hw_blocksize; 427 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 428 sc->sc_pn += sc->hw_blocksize; 429 if (sc->sc_pn >= sc->sc_pe) 430 sc->sc_pn = sc->sc_ps; 431 } else { 432 printf("%s: unexpected play intr\n", 433 sc->sc_dev.dv_xname); 434 } 435 BA1WRITE4(sc, CS4280_PFIE, mem); 436 } 437 /* Capture Interrupt */ 438 if (intr & HISR_CINT) { 439 int i; 440 int16_t rdata; 441 442 handled = 1; 443 mem = BA1READ4(sc, CS4280_CIE); 444 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 445 446 if (sc->sc_rrun) { 447 ++sc->sc_ri; 448 empty_dma = sc->sc_rdma->addr; 449 if ((sc->sc_ri&1) == 0) 450 empty_dma += sc->hw_blocksize; 451 452 /* 453 * XXX 454 * I think this audio data conversion should be 455 * happend in upper layer, but I put this here 456 * since there is no conversion function available. 457 */ 458 switch(sc->sc_rparam) { 459 case CF_16BIT_STEREO: 460 /* just copy it */ 461 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 462 sc->sc_rn += sc->hw_blocksize; 463 break; 464 case CF_16BIT_MONO: 465 for (i = 0; i < 512; i++) { 466 rdata = *((int16_t *)empty_dma)>>1; 467 empty_dma += 2; 468 rdata += *((int16_t *)empty_dma)>>1; 469 empty_dma += 2; 470 *((int16_t *)sc->sc_rn) = rdata; 471 sc->sc_rn += 2; 472 } 473 break; 474 case CF_8BIT_STEREO: 475 for (i = 0; i < 512; i++) { 476 rdata = *((int16_t*)empty_dma); 477 empty_dma += 2; 478 *sc->sc_rn++ = rdata >> 8; 479 rdata = *((int16_t*)empty_dma); 480 empty_dma += 2; 481 *sc->sc_rn++ = rdata >> 8; 482 } 483 break; 484 case CF_8BIT_MONO: 485 for (i = 0; i < 512; i++) { 486 rdata = *((int16_t*)empty_dma) >>1; 487 empty_dma += 2; 488 rdata += *((int16_t*)empty_dma) >>1; 489 empty_dma += 2; 490 *sc->sc_rn++ = rdata >>8; 491 } 492 break; 493 default: 494 /* Should not reach here */ 495 printf("%s: unknown sc->sc_rparam: %d\n", 496 sc->sc_dev.dv_xname, sc->sc_rparam); 497 } 498 if (sc->sc_rn >= sc->sc_re) 499 sc->sc_rn = sc->sc_rs; 500 } 501 BA1WRITE4(sc, CS4280_CIE, mem); 502 503 if (sc->sc_rrun) { 504 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 505 sc->sc_rintr(sc->sc_rarg); 506 } else { 507 printf("%s: unexpected record intr\n", 508 sc->sc_dev.dv_xname); 509 } 510 } 511 512 #if NMIDI > 0 513 /* Midi port Interrupt */ 514 if (intr & HISR_MIDI) { 515 int data; 516 517 handled = 1; 518 DPRINTF(("i: %d: ", 519 BA0READ4(sc, CS4280_MIDSR))); 520 /* Read the received data */ 521 while ((sc->sc_iintr != NULL) && 522 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 523 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 524 DPRINTF(("r:%x\n",data)); 525 sc->sc_iintr(sc->sc_arg, data); 526 } 527 528 /* Write the data */ 529 #if 1 530 /* XXX: 531 * It seems "Transmit Buffer Full" never activate until EOI 532 * is deliverd. Shall I throw EOI top of this routine ? 533 */ 534 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 535 DPRINTF(("w: ")); 536 if (sc->sc_ointr != NULL) 537 sc->sc_ointr(sc->sc_arg); 538 } 539 #else 540 while ((sc->sc_ointr != NULL) && 541 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 542 DPRINTF(("w: ")); 543 sc->sc_ointr(sc->sc_arg); 544 } 545 #endif 546 DPRINTF(("\n")); 547 } 548 #endif 549 550 return handled; 551 } 552 553 static int 554 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 555 { 556 switch (fp->index) { 557 case 0: 558 strcpy(fp->name, AudioEulinear); 559 fp->encoding = AUDIO_ENCODING_ULINEAR; 560 fp->precision = 8; 561 fp->flags = 0; 562 break; 563 case 1: 564 strcpy(fp->name, AudioEmulaw); 565 fp->encoding = AUDIO_ENCODING_ULAW; 566 fp->precision = 8; 567 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 568 break; 569 case 2: 570 strcpy(fp->name, AudioEalaw); 571 fp->encoding = AUDIO_ENCODING_ALAW; 572 fp->precision = 8; 573 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 574 break; 575 case 3: 576 strcpy(fp->name, AudioEslinear); 577 fp->encoding = AUDIO_ENCODING_SLINEAR; 578 fp->precision = 8; 579 fp->flags = 0; 580 break; 581 case 4: 582 strcpy(fp->name, AudioEslinear_le); 583 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 584 fp->precision = 16; 585 fp->flags = 0; 586 break; 587 case 5: 588 strcpy(fp->name, AudioEulinear_le); 589 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 590 fp->precision = 16; 591 fp->flags = 0; 592 break; 593 case 6: 594 strcpy(fp->name, AudioEslinear_be); 595 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 596 fp->precision = 16; 597 fp->flags = 0; 598 break; 599 case 7: 600 strcpy(fp->name, AudioEulinear_be); 601 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 602 fp->precision = 16; 603 fp->flags = 0; 604 break; 605 default: 606 return EINVAL; 607 } 608 return 0; 609 } 610 611 static int 612 cs4280_set_params(void *addr, int setmode, int usemode, 613 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 614 stream_filter_list_t *rfil) 615 { 616 audio_params_t hw; 617 struct cs428x_softc *sc; 618 struct audio_params *p; 619 stream_filter_list_t *fil; 620 int mode; 621 622 sc = addr; 623 for (mode = AUMODE_RECORD; mode != -1; 624 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 625 if ((setmode & mode) == 0) 626 continue; 627 628 p = mode == AUMODE_PLAY ? play : rec; 629 630 if (p == play) { 631 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 632 p->sample_rate, p->precision, p->channels)); 633 /* play back data format may be 8- or 16-bit and 634 * either stereo or mono. 635 * playback rate may range from 8000Hz to 48000Hz 636 */ 637 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 638 (p->precision != 8 && p->precision != 16) || 639 (p->channels != 1 && p->channels != 2) ) { 640 return EINVAL; 641 } 642 } else { 643 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 644 p->sample_rate, p->precision, p->channels)); 645 /* capture data format must be 16bit stereo 646 * and sample rate range from 11025Hz to 48000Hz. 647 * 648 * XXX: it looks like to work with 8000Hz, 649 * although data sheets say lower limit is 650 * 11025 Hz. 651 */ 652 653 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 654 (p->precision != 8 && p->precision != 16) || 655 (p->channels != 1 && p->channels != 2) ) { 656 return EINVAL; 657 } 658 } 659 fil = mode == AUMODE_PLAY ? pfil : rfil; 660 hw = *p; 661 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 662 663 /* capturing data is slinear */ 664 switch (p->encoding) { 665 case AUDIO_ENCODING_SLINEAR_BE: 666 if (mode == AUMODE_RECORD && p->precision == 16) { 667 fil->append(fil, swap_bytes, &hw); 668 } 669 break; 670 case AUDIO_ENCODING_SLINEAR_LE: 671 break; 672 case AUDIO_ENCODING_ULINEAR_BE: 673 if (mode == AUMODE_RECORD) { 674 fil->append(fil, p->precision == 16 675 ? swap_bytes_change_sign16 676 : change_sign8, &hw); 677 } 678 break; 679 case AUDIO_ENCODING_ULINEAR_LE: 680 if (mode == AUMODE_RECORD) { 681 fil->append(fil, p->precision == 16 682 ? change_sign16 : change_sign8, 683 &hw); 684 } 685 break; 686 case AUDIO_ENCODING_ULAW: 687 if (mode == AUMODE_PLAY) { 688 hw.precision = 16; 689 hw.validbits = 16; 690 fil->append(fil, mulaw_to_linear16, &hw); 691 } else { 692 fil->append(fil, linear8_to_mulaw, &hw); 693 } 694 break; 695 case AUDIO_ENCODING_ALAW: 696 if (mode == AUMODE_PLAY) { 697 hw.precision = 16; 698 hw.validbits = 16; 699 fil->append(fil, alaw_to_linear16, &hw); 700 } else { 701 fil->append(fil, linear8_to_alaw, &hw); 702 } 703 break; 704 default: 705 return EINVAL; 706 } 707 } 708 709 /* set sample rate */ 710 cs4280_set_dac_rate(sc, play->sample_rate); 711 cs4280_set_adc_rate(sc, rec->sample_rate); 712 return 0; 713 } 714 715 static int 716 cs4280_halt_output(void *addr) 717 { 718 struct cs428x_softc *sc; 719 uint32_t mem; 720 721 sc = addr; 722 mem = BA1READ4(sc, CS4280_PCTL); 723 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 724 sc->sc_prun = 0; 725 cs4280_clkrun_hack(sc, -1); 726 727 return 0; 728 } 729 730 static int 731 cs4280_halt_input(void *addr) 732 { 733 struct cs428x_softc *sc; 734 uint32_t mem; 735 736 sc = addr; 737 mem = BA1READ4(sc, CS4280_CCTL); 738 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 739 sc->sc_rrun = 0; 740 cs4280_clkrun_hack(sc, -1); 741 742 return 0; 743 } 744 745 static int 746 cs4280_getdev(void *addr, struct audio_device *retp) 747 { 748 749 *retp = cs4280_device; 750 return 0; 751 } 752 753 static int 754 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 755 void (*intr)(void *), void *arg, 756 const audio_params_t *param) 757 { 758 struct cs428x_softc *sc; 759 uint32_t pfie, pctl, pdtc; 760 struct cs428x_dma *p; 761 762 sc = addr; 763 #ifdef DIAGNOSTIC 764 if (sc->sc_prun) 765 printf("cs4280_trigger_output: already running\n"); 766 #endif 767 sc->sc_prun = 1; 768 cs4280_clkrun_hack(sc, 1); 769 770 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 771 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 772 sc->sc_pintr = intr; 773 sc->sc_parg = arg; 774 775 /* stop playback DMA */ 776 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 777 778 /* setup PDTC */ 779 pdtc = BA1READ4(sc, CS4280_PDTC); 780 pdtc &= ~PDTC_MASK; 781 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 782 BA1WRITE4(sc, CS4280_PDTC, pdtc); 783 784 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 785 param->precision, param->channels, param->encoding)); 786 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 787 continue; 788 if (p == NULL) { 789 printf("cs4280_trigger_output: bad addr %p\n", start); 790 return EINVAL; 791 } 792 if (DMAADDR(p) % sc->dma_align != 0 ) { 793 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 794 "4kB align\n", (ulong)DMAADDR(p)); 795 return EINVAL; 796 } 797 798 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 799 sc->sc_ps = (char *)start; 800 sc->sc_pe = (char *)end; 801 sc->sc_pdma = p; 802 sc->sc_pbuf = KERNADDR(p); 803 sc->sc_pi = 0; 804 sc->sc_pn = sc->sc_ps; 805 if (blksize >= sc->dma_size) { 806 sc->sc_pn = sc->sc_ps + sc->dma_size; 807 memcpy(sc->sc_pbuf, start, sc->dma_size); 808 ++sc->sc_pi; 809 } else { 810 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 811 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 812 } 813 814 /* initiate playback DMA */ 815 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 816 817 /* set PFIE */ 818 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 819 820 if (param->precision == 8) 821 pfie |= PFIE_8BIT; 822 if (param->channels == 1) 823 pfie |= PFIE_MONO; 824 825 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 826 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 827 pfie |= PFIE_SWAPPED; 828 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 829 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 830 pfie |= PFIE_UNSIGNED; 831 832 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 833 834 sc->sc_prate = param->sample_rate; 835 cs4280_set_dac_rate(sc, param->sample_rate); 836 837 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 838 pctl |= sc->pctl; 839 BA1WRITE4(sc, CS4280_PCTL, pctl); 840 return 0; 841 } 842 843 static int 844 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 845 void (*intr)(void *), void *arg, 846 const audio_params_t *param) 847 { 848 struct cs428x_softc *sc; 849 uint32_t cctl, cie; 850 struct cs428x_dma *p; 851 852 sc = addr; 853 #ifdef DIAGNOSTIC 854 if (sc->sc_rrun) 855 printf("cs4280_trigger_input: already running\n"); 856 #endif 857 sc->sc_rrun = 1; 858 cs4280_clkrun_hack(sc, 1); 859 860 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 861 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 862 sc->sc_rintr = intr; 863 sc->sc_rarg = arg; 864 865 /* stop capture DMA */ 866 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 867 868 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 869 continue; 870 if (p == NULL) { 871 printf("cs4280_trigger_input: bad addr %p\n", start); 872 return EINVAL; 873 } 874 if (DMAADDR(p) % sc->dma_align != 0) { 875 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 876 "4kB align\n", (ulong)DMAADDR(p)); 877 return EINVAL; 878 } 879 880 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 881 sc->sc_rs = (char *)start; 882 sc->sc_re = (char *)end; 883 sc->sc_rdma = p; 884 sc->sc_rbuf = KERNADDR(p); 885 sc->sc_ri = 0; 886 sc->sc_rn = sc->sc_rs; 887 888 /* initiate capture DMA */ 889 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 890 891 /* setup format information for internal converter */ 892 sc->sc_rparam = 0; 893 if (param->precision == 8) { 894 sc->sc_rparam += CF_8BIT; 895 sc->sc_rcount <<= 1; 896 } 897 if (param->channels == 1) { 898 sc->sc_rparam += CF_MONO; 899 sc->sc_rcount <<= 1; 900 } 901 902 /* set CIE */ 903 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 904 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 905 906 sc->sc_rrate = param->sample_rate; 907 cs4280_set_adc_rate(sc, param->sample_rate); 908 909 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 910 cctl |= sc->cctl; 911 BA1WRITE4(sc, CS4280_CCTL, cctl); 912 return 0; 913 } 914 915 /* Power Hook */ 916 static void 917 cs4280_power(int why, void *v) 918 { 919 static uint32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 920 static uint32_t cctl = 0, cba = 0, cie = 0; 921 struct cs428x_softc *sc; 922 923 sc = (struct cs428x_softc *)v; 924 DPRINTF(("%s: cs4280_power why=%d\n", sc->sc_dev.dv_xname, why)); 925 switch (why) { 926 case PWR_SUSPEND: 927 case PWR_STANDBY: 928 sc->sc_suspend = why; 929 930 /* save current playback status */ 931 if (sc->sc_prun) { 932 pctl = BA1READ4(sc, CS4280_PCTL); 933 pfie = BA1READ4(sc, CS4280_PFIE); 934 pba = BA1READ4(sc, CS4280_PBA); 935 pdtc = BA1READ4(sc, CS4280_PDTC); 936 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 937 pctl, pfie, pba, pdtc)); 938 } 939 940 /* save current capture status */ 941 if (sc->sc_rrun) { 942 cctl = BA1READ4(sc, CS4280_CCTL); 943 cie = BA1READ4(sc, CS4280_CIE); 944 cba = BA1READ4(sc, CS4280_CBA); 945 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 946 cctl, cie, cba)); 947 } 948 949 /* Stop DMA */ 950 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 951 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 952 953 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 954 if (sc->sc_ih != NULL) 955 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 956 957 break; 958 case PWR_RESUME: 959 if (sc->sc_suspend == PWR_RESUME) { 960 printf("cs4280_power: odd, resume without suspend.\n"); 961 sc->sc_suspend = why; 962 return; 963 } 964 965 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, 966 IPL_AUDIO, cs4280_intr, sc); 967 if (sc->sc_ih == NULL) { 968 aprint_error("%s: can't establish interrupt", 969 sc->sc_dev.dv_xname); 970 /* XXX jmcneill what should we do here? */ 971 return; 972 } 973 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 974 975 sc->sc_suspend = why; 976 cs4280_init(sc, 0); 977 #if 0 978 cs4280_reset_codec(sc); 979 #endif 980 /* restore ac97 registers */ 981 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 982 983 /* restore DMA related status */ 984 if(sc->sc_prun) { 985 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 986 pctl, pfie, pba, pdtc)); 987 cs4280_set_dac_rate(sc, sc->sc_prate); 988 BA1WRITE4(sc, CS4280_PDTC, pdtc); 989 BA1WRITE4(sc, CS4280_PBA, pba); 990 BA1WRITE4(sc, CS4280_PFIE, pfie); 991 BA1WRITE4(sc, CS4280_PCTL, pctl); 992 } 993 994 if (sc->sc_rrun) { 995 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 996 cctl, cie, cba)); 997 cs4280_set_adc_rate(sc, sc->sc_rrate); 998 BA1WRITE4(sc, CS4280_CBA, cba); 999 BA1WRITE4(sc, CS4280_CIE, cie); 1000 BA1WRITE4(sc, CS4280_CCTL, cctl); 1001 } 1002 break; 1003 case PWR_SOFTSUSPEND: 1004 case PWR_SOFTSTANDBY: 1005 case PWR_SOFTRESUME: 1006 break; 1007 } 1008 } 1009 1010 static int 1011 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 1012 { 1013 struct cs428x_softc *sc = addr; 1014 int rv; 1015 1016 cs4280_clkrun_hack(sc, 1); 1017 rv = cs428x_read_codec(addr, reg, result); 1018 cs4280_clkrun_hack(sc, -1); 1019 1020 return rv; 1021 } 1022 1023 static int 1024 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1025 { 1026 struct cs428x_softc *sc = addr; 1027 int rv; 1028 1029 cs4280_clkrun_hack(sc, 1); 1030 rv = cs428x_write_codec(addr, reg, data); 1031 cs4280_clkrun_hack(sc, -1); 1032 1033 return rv; 1034 } 1035 1036 #if 0 /* XXX buggy and not required */ 1037 /* control AC97 codec */ 1038 static int 1039 cs4280_reset_codec(void *addr) 1040 { 1041 struct cs428x_softc *sc; 1042 int n; 1043 1044 sc = addr; 1045 1046 /* Reset codec */ 1047 BA0WRITE4(sc, CS428X_ACCTL, 0); 1048 delay(100); /* delay 100us */ 1049 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1050 1051 /* 1052 * It looks like we do the following procedure, too 1053 */ 1054 1055 /* Enable AC-link sync generation */ 1056 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1057 delay(50*1000); /* XXX delay 50ms */ 1058 1059 /* Assert valid frame signal */ 1060 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1061 1062 /* Wait for valid AC97 input slot */ 1063 n = 0; 1064 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1065 (ACISV_ISV3 | ACISV_ISV4)) { 1066 delay(1000); 1067 if (++n > 1000) { 1068 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1069 return ETIMEDOUT; 1070 } 1071 } 1072 1073 return 0; 1074 } 1075 #endif 1076 1077 static enum ac97_host_flags cs4280_flags_codec(void *addr) 1078 { 1079 struct cs428x_softc *sc; 1080 1081 sc = addr; 1082 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1083 return AC97_HOST_INVERTED_EAMP; 1084 1085 return 0; 1086 } 1087 1088 /* Internal functions */ 1089 1090 static const struct cs4280_card_t * 1091 cs4280_identify_card(struct pci_attach_args *pa) 1092 { 1093 pcireg_t idreg; 1094 u_int16_t i; 1095 1096 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1097 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1098 if (idreg == cs4280_cards[i].id) 1099 return &cs4280_cards[i]; 1100 } 1101 1102 return NULL; 1103 } 1104 1105 static int 1106 cs4280_piix4_match(struct pci_attach_args *pa) 1107 { 1108 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1109 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1110 return 1; 1111 } 1112 1113 return 0; 1114 } 1115 1116 static void 1117 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1118 { 1119 uint16_t control, val; 1120 1121 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1122 return; 1123 1124 sc->sc_active += change; 1125 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1126 if (!sc->sc_active) 1127 val |= 0x2000; 1128 else 1129 val &= ~0x2000; 1130 if (val != control) 1131 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1132 } 1133 1134 static void 1135 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1136 { 1137 struct pci_attach_args smbuspa; 1138 uint16_t reg; 1139 pcireg_t port; 1140 1141 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1142 return; 1143 1144 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1145 sc->sc_active = 0; 1146 printf("%s: enabling CLKRUN hack\n", 1147 sc->sc_dev.dv_xname); 1148 1149 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1150 port = reg & 0xffc0; 1151 printf("%s: power management port 0x%x\n", sc->sc_dev.dv_xname, 1152 port); 1153 1154 sc->sc_pm_iot = smbuspa.pa_iot; 1155 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1156 &sc->sc_pm_ioh) == 0) 1157 return; 1158 } 1159 1160 /* handle error */ 1161 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1162 printf("%s: disabling CLKRUN hack\n", sc->sc_dev.dv_xname); 1163 } 1164 1165 static void 1166 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1167 { 1168 /* calculate capture rate: 1169 * 1170 * capture_coefficient_increment = -round(rate*128*65536/48000; 1171 * capture_phase_increment = floor(48000*65536*1024/rate); 1172 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1173 * cy = floor(cx/200); 1174 * capture_sample_rate_correction = cx - 200*cy; 1175 * capture_delay = ceil(24*48000/rate); 1176 * capture_num_triplets = floor(65536*rate/24000); 1177 * capture_group_length = 24000/GCD(rate, 24000); 1178 * where GCD means "Greatest Common Divisor". 1179 * 1180 * capture_coefficient_increment, capture_phase_increment and 1181 * capture_num_triplets are 32-bit signed quantities. 1182 * capture_sample_rate_correction and capture_group_length are 1183 * 16-bit signed quantities. 1184 * capture_delay is a 14-bit unsigned quantity. 1185 */ 1186 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1187 uint16_t csrc, cgl, cdlay; 1188 1189 /* XXX 1190 * Even though, embedded_audio_spec says capture rate range 11025 to 1191 * 48000, dhwiface.cpp says, 1192 * 1193 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1194 * Return an error if an attempt is made to stray outside that limit." 1195 * 1196 * so assume range as 48000/9 to 48000 1197 */ 1198 1199 if (rate < 8000) 1200 rate = 8000; 1201 if (rate > 48000) 1202 rate = 48000; 1203 1204 cx = rate << 16; 1205 cci = cx / 48000; 1206 cx -= cci * 48000; 1207 cx <<= 7; 1208 cci <<= 7; 1209 cci += cx / 48000; 1210 cci = - cci; 1211 1212 cx = 48000 << 16; 1213 cpi = cx / rate; 1214 cx -= cpi * rate; 1215 cx <<= 10; 1216 cpi <<= 10; 1217 cy = cx / rate; 1218 cpi += cy; 1219 cx -= cy * rate; 1220 1221 cy = cx / 200; 1222 csrc = cx - 200*cy; 1223 1224 cdlay = ((48000 * 24) + rate - 1) / rate; 1225 #if 0 1226 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1227 #endif 1228 1229 cnt = rate << 16; 1230 cnt /= 24000; 1231 1232 cgl = 1; 1233 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1234 if (((rate / tmp1) * tmp1) != rate) 1235 cgl *= 2; 1236 } 1237 if (((rate / 3) * 3) != rate) 1238 cgl *= 3; 1239 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1240 if (((rate / tmp1) * tmp1) != rate) 1241 cgl *= 5; 1242 } 1243 #if 0 1244 /* XXX what manual says */ 1245 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1246 tmp1 |= csrc<<16; 1247 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1248 #else 1249 /* suggested by cs461x.c (ALSA driver) */ 1250 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1251 #endif 1252 1253 #if 0 1254 /* I am confused. The sample rate calculation section says 1255 * cci *is* 32-bit signed quantity but in the parameter description 1256 * section, CCI only assigned 16bit. 1257 * I believe size of the variable. 1258 */ 1259 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1260 tmp1 |= cci<<16; 1261 BA1WRITE4(sc, CS4280_CCI, tmp1); 1262 #else 1263 BA1WRITE4(sc, CS4280_CCI, cci); 1264 #endif 1265 1266 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1267 tmp1 |= cdlay <<18; 1268 BA1WRITE4(sc, CS4280_CD, tmp1); 1269 1270 BA1WRITE4(sc, CS4280_CPI, cpi); 1271 1272 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1273 tmp1 |= cgl; 1274 BA1WRITE4(sc, CS4280_CGL, tmp1); 1275 1276 BA1WRITE4(sc, CS4280_CNT, cnt); 1277 1278 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1279 tmp1 |= cgl; 1280 BA1WRITE4(sc, CS4280_CGC, tmp1); 1281 } 1282 1283 static void 1284 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1285 { 1286 /* 1287 * playback rate may range from 8000Hz to 48000Hz 1288 * 1289 * play_phase_increment = floor(rate*65536*1024/48000) 1290 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1291 * py=floor(px/200) 1292 * play_sample_rate_correction = px - 200*py 1293 * 1294 * play_phase_increment is a 32bit signed quantity. 1295 * play_sample_rate_correction is a 16bit signed quantity. 1296 */ 1297 int32_t ppi; 1298 int16_t psrc; 1299 uint32_t px, py; 1300 1301 if (rate < 8000) 1302 rate = 8000; 1303 if (rate > 48000) 1304 rate = 48000; 1305 px = rate << 16; 1306 ppi = px/48000; 1307 px -= ppi*48000; 1308 ppi <<= 10; 1309 px <<= 10; 1310 py = px / 48000; 1311 ppi += py; 1312 px -= py*48000; 1313 py = px/200; 1314 px -= py*200; 1315 psrc = px; 1316 #if 0 1317 /* what manual says */ 1318 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1319 BA1WRITE4(sc, CS4280_PSRC, 1320 ( ((psrc<<16) & PSRC_MASK) | px )); 1321 #else 1322 /* suggested by cs461x.c (ALSA driver) */ 1323 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1324 #endif 1325 BA1WRITE4(sc, CS4280_PPI, ppi); 1326 } 1327 1328 /* Download Processor Code and Data image */ 1329 static int 1330 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1331 uint32_t offset, uint32_t len) 1332 { 1333 uint32_t ctr; 1334 #if CS4280_DEBUG > 10 1335 uint32_t con, data; 1336 uint8_t c0, c1, c2, c3; 1337 #endif 1338 if ((offset & 3) || (len & 3)) 1339 return -1; 1340 1341 len /= sizeof(uint32_t); 1342 for (ctr = 0; ctr < len; ctr++) { 1343 /* XXX: 1344 * I cannot confirm this is the right thing or not 1345 * on BIG-ENDIAN machines. 1346 */ 1347 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1348 #if CS4280_DEBUG > 10 1349 data = htole32(*(src+ctr)); 1350 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1351 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1352 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1353 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1354 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1355 if (data != con ) { 1356 printf("0x%06x: write=0x%08x read=0x%08x\n", 1357 offset+ctr*4, data, con); 1358 return -1; 1359 } 1360 #endif 1361 } 1362 return 0; 1363 } 1364 1365 static int 1366 cs4280_download_image(struct cs428x_softc *sc) 1367 { 1368 int idx, err; 1369 uint32_t offset = 0; 1370 1371 err = 0; 1372 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1373 err = cs4280_download(sc, &BA1Struct.map[offset], 1374 BA1Struct.memory[idx].offset, 1375 BA1Struct.memory[idx].size); 1376 if (err != 0) { 1377 printf("%s: load_image failed at %d\n", 1378 sc->sc_dev.dv_xname, idx); 1379 return -1; 1380 } 1381 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1382 } 1383 return err; 1384 } 1385 1386 /* Processor Soft Reset */ 1387 static void 1388 cs4280_reset(void *sc_) 1389 { 1390 struct cs428x_softc *sc; 1391 1392 sc = sc_; 1393 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1394 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1395 delay(100); 1396 /* Clear RSTSP bit in SPCR */ 1397 BA1WRITE4(sc, CS4280_SPCR, 0); 1398 /* enable DMA reqest */ 1399 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1400 } 1401 1402 static int 1403 cs4280_init(struct cs428x_softc *sc, int init) 1404 { 1405 int n; 1406 uint32_t mem; 1407 int rv; 1408 1409 rv = 1; 1410 cs4280_clkrun_hack(sc, 1); 1411 1412 /* Start PLL out in known state */ 1413 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1414 /* Start serial ports out in known state */ 1415 BA0WRITE4(sc, CS4280_SERMC1, 0); 1416 1417 /* Specify type of CODEC */ 1418 /* XXX should not be here */ 1419 #define SERACC_CODEC_TYPE_1_03 1420 #ifdef SERACC_CODEC_TYPE_1_03 1421 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1422 #else 1423 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1424 #endif 1425 1426 /* Reset codec */ 1427 BA0WRITE4(sc, CS428X_ACCTL, 0); 1428 delay(100); /* delay 100us */ 1429 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1430 1431 /* Enable AC-link sync generation */ 1432 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1433 delay(50*1000); /* delay 50ms */ 1434 1435 /* Set the serial port timing configuration */ 1436 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1437 1438 /* Setup clock control */ 1439 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1440 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1441 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1442 1443 /* Power up the PLL */ 1444 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1445 delay(50*1000); /* delay 50ms */ 1446 1447 /* Turn on clock */ 1448 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1449 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1450 1451 /* Set the serial port FIFO pointer to the 1452 * first sample in FIFO. (not documented) */ 1453 cs4280_clear_fifos(sc); 1454 1455 #if 0 1456 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1457 BA0WRITE4(sc, CS4280_SERBSP, 0); 1458 #endif 1459 1460 /* Configure the serial port */ 1461 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1462 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1463 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1464 1465 /* Wait for CODEC ready */ 1466 n = 0; 1467 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1468 delay(125); 1469 if (++n > 1000) { 1470 printf("%s: codec ready timeout\n", 1471 sc->sc_dev.dv_xname); 1472 goto exit; 1473 } 1474 } 1475 1476 /* Assert valid frame signal */ 1477 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1478 1479 /* Wait for valid AC97 input slot */ 1480 n = 0; 1481 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1482 (ACISV_ISV3 | ACISV_ISV4)) { 1483 delay(1000); 1484 if (++n > 1000) { 1485 printf("AC97 inputs slot ready timeout\n"); 1486 goto exit; 1487 } 1488 } 1489 1490 /* Set AC97 output slot valid signals */ 1491 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1492 1493 /* reset the processor */ 1494 cs4280_reset(sc); 1495 1496 /* Download the image to the processor */ 1497 if (cs4280_download_image(sc) != 0) { 1498 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1499 goto exit; 1500 } 1501 1502 /* Save playback parameter and then write zero. 1503 * this ensures that DMA doesn't immediately occur upon 1504 * starting the processor core 1505 */ 1506 mem = BA1READ4(sc, CS4280_PCTL); 1507 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1508 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1509 if (init != 0) 1510 sc->sc_prun = 0; 1511 1512 /* Save capture parameter and then write zero. 1513 * this ensures that DMA doesn't immediately occur upon 1514 * starting the processor core 1515 */ 1516 mem = BA1READ4(sc, CS4280_CCTL); 1517 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1518 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1519 if (init != 0) 1520 sc->sc_rrun = 0; 1521 1522 /* Processor Startup Procedure */ 1523 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1524 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1525 1526 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1527 n = 0; 1528 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1529 delay(10); 1530 if (++n > 1000) { 1531 printf("SPCR 1->0 transition timeout\n"); 1532 goto exit; 1533 } 1534 } 1535 1536 n = 0; 1537 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1538 delay(10); 1539 if (++n > 1000) { 1540 printf("SPCS 0->1 transition timeout\n"); 1541 goto exit; 1542 } 1543 } 1544 /* Processor is now running !!! */ 1545 1546 /* Setup volume */ 1547 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1548 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1549 1550 /* Interrupt enable */ 1551 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1552 1553 /* playback interrupt enable */ 1554 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1555 mem |= PFIE_PI_ENABLE; 1556 BA1WRITE4(sc, CS4280_PFIE, mem); 1557 /* capture interrupt enable */ 1558 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1559 mem |= CIE_CI_ENABLE; 1560 BA1WRITE4(sc, CS4280_CIE, mem); 1561 1562 #if NMIDI > 0 1563 /* Reset midi port */ 1564 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1565 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1566 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1567 /* midi interrupt enable */ 1568 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1569 BA0WRITE4(sc, CS4280_MIDCR, mem); 1570 #endif 1571 1572 rv = 0; 1573 1574 exit: 1575 cs4280_clkrun_hack(sc, -1); 1576 return rv; 1577 } 1578 1579 static void 1580 cs4280_clear_fifos(struct cs428x_softc *sc) 1581 { 1582 int pd, cnt, n; 1583 uint32_t mem; 1584 1585 pd = 0; 1586 /* 1587 * If device power down, power up the device and keep power down 1588 * state. 1589 */ 1590 mem = BA0READ4(sc, CS4280_CLKCR1); 1591 if (!(mem & CLKCR1_SWCE)) { 1592 printf("cs4280_clear_fifo: power down found.\n"); 1593 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1594 pd = 1; 1595 } 1596 BA0WRITE4(sc, CS4280_SERBWP, 0); 1597 for (cnt = 0; cnt < 256; cnt++) { 1598 n = 0; 1599 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1600 delay(1000); 1601 if (++n > 1000) { 1602 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1603 break; 1604 } 1605 } 1606 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1607 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1608 } 1609 if (pd) 1610 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1611 } 1612 1613 #if NMIDI > 0 1614 static int 1615 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1616 void (*ointr)(void *), void *arg) 1617 { 1618 struct cs428x_softc *sc; 1619 uint32_t mem; 1620 1621 DPRINTF(("midi_open\n")); 1622 sc = addr; 1623 sc->sc_iintr = iintr; 1624 sc->sc_ointr = ointr; 1625 sc->sc_arg = arg; 1626 1627 /* midi interrupt enable */ 1628 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1629 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1630 BA0WRITE4(sc, CS4280_MIDCR, mem); 1631 #ifdef CS4280_DEBUG 1632 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1633 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1634 return(EINVAL); 1635 } 1636 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1637 #endif 1638 return 0; 1639 } 1640 1641 static void 1642 cs4280_midi_close(void *addr) 1643 { 1644 struct cs428x_softc *sc; 1645 uint32_t mem; 1646 1647 DPRINTF(("midi_close\n")); 1648 sc = addr; 1649 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1650 mem = BA0READ4(sc, CS4280_MIDCR); 1651 mem &= ~MIDCR_MASK; 1652 BA0WRITE4(sc, CS4280_MIDCR, mem); 1653 1654 sc->sc_iintr = 0; 1655 sc->sc_ointr = 0; 1656 } 1657 1658 static int 1659 cs4280_midi_output(void *addr, int d) 1660 { 1661 struct cs428x_softc *sc; 1662 uint32_t mem; 1663 int x; 1664 1665 sc = addr; 1666 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1667 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1668 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1669 mem |= d & MIDWP_MASK; 1670 DPRINTFN(5,("midi_output d=0x%08x",d)); 1671 BA0WRITE4(sc, CS4280_MIDWP, mem); 1672 #ifdef DIAGNOSTIC 1673 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1674 DPRINTF(("Bad write data: %d %d", 1675 mem, BA0READ4(sc, CS4280_MIDWP))); 1676 return EIO; 1677 } 1678 #endif 1679 return 0; 1680 } 1681 delay(MIDI_BUSY_DELAY); 1682 } 1683 return EIO; 1684 } 1685 1686 static void 1687 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1688 { 1689 1690 mi->name = "CS4280 MIDI UART"; 1691 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1692 } 1693 1694 #endif /* NMIDI */ 1695 1696 /* DEBUG functions */ 1697 #if CS4280_DEBUG > 10 1698 static int 1699 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1700 uint32_t offset, uint32_t len) 1701 { 1702 uint32_t ctr, data; 1703 int err; 1704 1705 if ((offset & 3) || (len & 3)) 1706 return -1; 1707 1708 err = 0; 1709 len /= sizeof(uint32_t); 1710 for (ctr = 0; ctr < len; ctr++) { 1711 /* I cannot confirm this is the right thing 1712 * on BIG-ENDIAN machines 1713 */ 1714 data = BA1READ4(sc, offset+ctr*4); 1715 if (data != htole32(*(src+ctr))) { 1716 printf("0x%06x: 0x%08x(0x%08x)\n", 1717 offset+ctr*4, data, *(src+ctr)); 1718 *(src+ctr) = data; 1719 ++err; 1720 } 1721 } 1722 return err; 1723 } 1724 1725 static int 1726 cs4280_check_images(struct cs428x_softc *sc) 1727 { 1728 int idx, err; 1729 uint32_t offset; 1730 1731 offset = 0; 1732 err = 0; 1733 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1734 for (idx = 0; idx < 1; ++idx) { 1735 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1736 BA1Struct.memory[idx].offset, 1737 BA1Struct.memory[idx].size); 1738 if (err != 0) { 1739 printf("%s: check_image failed at %d\n", 1740 sc->sc_dev.dv_xname, idx); 1741 } 1742 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1743 } 1744 return err; 1745 } 1746 1747 #endif /* CS4280_DEBUG */ 1748
Indexes created Thu Oct 02 14:10:14 GMT 2025