cs4280.c revision 1.45.6.1
1 /* $NetBSD: cs4280.c,v 1.45.6.1 2007/02/27 14:16:23 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.45.6.1 2007/02/27 14:16:23 ad Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <sys/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(struct device *, struct cfdata *, void *); 93 static void cs4280_attach(struct device *, struct device *, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 107 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 108 #if 0 109 static int cs4280_reset_codec(void *); 110 #endif 111 static enum ac97_host_flags cs4280_flags_codec(void *); 112 113 /* For PowerHook */ 114 static void cs4280_power(int, void *); 115 116 /* Internal functions */ 117 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *); 118 static int cs4280_piix4_match(struct pci_attach_args *); 119 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 120 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 121 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 122 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 123 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 124 uint32_t); 125 static int cs4280_download_image(struct cs428x_softc *); 126 static void cs4280_reset(void *); 127 static int cs4280_init(struct cs428x_softc *, int); 128 static void cs4280_clear_fifos(struct cs428x_softc *); 129 130 #if CS4280_DEBUG > 10 131 /* Thease two function is only for checking image loading is succeeded or not. */ 132 static int cs4280_check_images(struct cs428x_softc *); 133 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 134 uint32_t); 135 #endif 136 137 /* Special cards */ 138 struct cs4280_card_t 139 { 140 pcireg_t id; 141 enum cs428x_flags flags; 142 }; 143 144 #define _card(vend, prod, flags) \ 145 {PCI_ID_CODE(vend, prod), flags} 146 147 static const struct cs4280_card_t cs4280_cards[] = { 148 #if 0 /* untested, from ALSA driver */ 149 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 150 CS428X_FLAG_INVAC97EAMP), 151 #endif 152 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 153 CS428X_FLAG_INVAC97EAMP), 154 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 155 CS428X_FLAG_CLKRUNHACK) 156 }; 157 158 #undef _card 159 160 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 161 162 static const struct audio_hw_if cs4280_hw_if = { 163 NULL, /* open */ 164 NULL, /* close */ 165 NULL, 166 cs4280_query_encoding, 167 cs4280_set_params, 168 cs428x_round_blocksize, 169 NULL, 170 NULL, 171 NULL, 172 NULL, 173 NULL, 174 cs4280_halt_output, 175 cs4280_halt_input, 176 NULL, 177 cs4280_getdev, 178 NULL, 179 cs428x_mixer_set_port, 180 cs428x_mixer_get_port, 181 cs428x_query_devinfo, 182 cs428x_malloc, 183 cs428x_free, 184 cs428x_round_buffersize, 185 cs428x_mappage, 186 cs428x_get_props, 187 cs4280_trigger_output, 188 cs4280_trigger_input, 189 NULL, 190 NULL, 191 cs428x_get_locks, 192 }; 193 194 #if NMIDI > 0 195 /* Midi Interface */ 196 static int cs4280_midi_open(void *, int, void (*)(void *, int), 197 void (*)(void *), void *); 198 static void cs4280_midi_close(void*); 199 static int cs4280_midi_output(void *, int); 200 static void cs4280_midi_getinfo(void *, struct midi_info *); 201 202 static const struct midi_hw_if cs4280_midi_hw_if = { 203 cs4280_midi_open, 204 cs4280_midi_close, 205 cs4280_midi_output, 206 cs4280_midi_getinfo, 207 0, 208 cs428x_get_locks, 209 }; 210 #endif 211 212 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 213 cs4280_match, cs4280_attach, NULL, NULL); 214 215 static struct audio_device cs4280_device = { 216 "CS4280", 217 "", 218 "cs4280" 219 }; 220 221 222 static int 223 cs4280_match(struct device *parent, struct cfdata *match, 224 void *aux) 225 { 226 struct pci_attach_args *pa; 227 228 pa = (struct pci_attach_args *)aux; 229 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 230 return 0; 231 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 232 #if 0 /* I can't confirm */ 233 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 234 #endif 235 ) 236 return 1; 237 return 0; 238 } 239 240 static void 241 cs4280_attach(struct device *parent, struct device *self, void *aux) 242 { 243 struct cs428x_softc *sc; 244 struct pci_attach_args *pa; 245 pci_chipset_tag_t pc; 246 const struct cs4280_card_t *cs_card; 247 char const *intrstr; 248 pci_intr_handle_t ih; 249 pcireg_t reg; 250 char devinfo[256]; 251 uint32_t mem; 252 int error; 253 254 sc = (struct cs428x_softc *)self; 255 pa = (struct pci_attach_args *)aux; 256 pc = pa->pa_pc; 257 aprint_naive(": Audio controller\n"); 258 259 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 260 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 261 PCI_REVISION(pa->pa_class)); 262 263 cs_card = cs4280_identify_card(pa); 264 if (cs_card != NULL) { 265 aprint_normal("%s: %s %s\n",sc->sc_dev.dv_xname, 266 pci_findvendor(cs_card->id), 267 pci_findproduct(cs_card->id)); 268 sc->sc_flags = cs_card->flags; 269 } else { 270 sc->sc_flags = CS428X_FLAG_NONE; 271 } 272 273 /* Map I/O register */ 274 if (pci_mapreg_map(pa, PCI_BA0, 275 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 276 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 277 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 278 return; 279 } 280 if (pci_mapreg_map(pa, PCI_BA1, 281 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 282 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 283 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 284 return; 285 } 286 287 sc->sc_dmatag = pa->pa_dmat; 288 289 /* power up chip */ 290 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 291 pci_activate_null)) && error != EOPNOTSUPP) { 292 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 293 error); 294 return; 295 } 296 297 /* Enable the device (set bus master flag) */ 298 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 299 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 300 reg | PCI_COMMAND_MASTER_ENABLE); 301 302 /* LATENCY_TIMER setting */ 303 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 304 if ( PCI_LATTIMER(mem) < 32 ) { 305 mem &= 0xffff00ff; 306 mem |= 0x00002000; 307 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 308 } 309 310 /* CLKRUN hack initialization */ 311 cs4280_clkrun_hack_init(sc); 312 313 /* Map and establish the interrupt. */ 314 if (pci_intr_map(pa, &ih)) { 315 aprint_error("%s: couldn't map interrupt\n", 316 sc->sc_dev.dv_xname); 317 return; 318 } 319 intrstr = pci_intr_string(pc, ih); 320 321 mutex_init(&sc->sc_lock, MUTEX_DRIVER, IPL_NONE); 322 mutex_init(&sc->sc_intr_lock, MUTEX_DRIVER, IPL_AUDIO); 323 324 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 325 if (sc->sc_ih == NULL) { 326 aprint_error("%s: couldn't establish interrupt", 327 sc->sc_dev.dv_xname); 328 if (intrstr != NULL) 329 aprint_normal(" at %s", intrstr); 330 aprint_normal("\n"); 331 return; 332 } 333 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 334 335 /* Initialization */ 336 if(cs4280_init(sc, 1) != 0) 337 return; 338 339 sc->type = TYPE_CS4280; 340 sc->halt_input = cs4280_halt_input; 341 sc->halt_output = cs4280_halt_output; 342 343 /* setup buffer related parameters */ 344 sc->dma_size = CS4280_DCHUNK; 345 sc->dma_align = CS4280_DALIGN; 346 sc->hw_blocksize = CS4280_ICHUNK; 347 348 /* AC 97 attachment */ 349 sc->host_if.arg = sc; 350 sc->host_if.attach = cs428x_attach_codec; 351 sc->host_if.read = cs4280_read_codec; 352 sc->host_if.write = cs4280_write_codec; 353 #if 0 354 sc->host_if.reset = cs4280_reset_codec; 355 #else 356 sc->host_if.reset = NULL; 357 #endif 358 sc->host_if.flags = cs4280_flags_codec; 359 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 360 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 361 return; 362 } 363 364 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 365 366 #if NMIDI > 0 367 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 368 #endif 369 370 sc->sc_suspend = PWR_RESUME; 371 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 372 cs4280_power, sc); 373 } 374 375 /* Interrupt handling function */ 376 static int 377 cs4280_intr(void *p) 378 { 379 /* 380 * XXX 381 * 382 * Since CS4280 has only 4kB DMA buffer and 383 * interrupt occurs every 2kB block, I create dummy buffer 384 * which returns to audio driver and actual DMA buffer 385 * using in DMA transfer. 386 * 387 * 388 * ring buffer in audio.c is pointed by BUFADDR 389 * <------ ring buffer size == 64kB ------> 390 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 391 * |= = = =|= = = =|= = = =|= = = =|= = = =| 392 * | | | | | | <- call audio_intp every 393 * sc->sc_[pr]_count time. 394 * 395 * actual DMA buffer is pointed by KERNADDR 396 * <-> DMA buffer size = 4kB 397 * |= =| 398 * 399 * 400 */ 401 struct cs428x_softc *sc; 402 uint32_t intr, mem; 403 char * empty_dma; 404 int handled; 405 406 sc = p; 407 handled = 0; 408 409 mutex_enter(&sc->sc_intr_lock); 410 411 /* grab interrupt register then clear it */ 412 intr = BA0READ4(sc, CS4280_HISR); 413 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 414 415 /* not for us ? */ 416 if ((intr & HISR_INTENA) == 0) { 417 mutex_exit(&sc->sc_intr_lock); 418 return 0; 419 } 420 421 /* Playback Interrupt */ 422 if (intr & HISR_PINT) { 423 handled = 1; 424 mem = BA1READ4(sc, CS4280_PFIE); 425 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 426 if (sc->sc_prun) { 427 if ((sc->sc_pi%sc->sc_pcount) == 0) 428 sc->sc_pintr(sc->sc_parg); 429 /* copy buffer */ 430 ++sc->sc_pi; 431 empty_dma = sc->sc_pdma->addr; 432 if (sc->sc_pi&1) 433 empty_dma += sc->hw_blocksize; 434 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 435 sc->sc_pn += sc->hw_blocksize; 436 if (sc->sc_pn >= sc->sc_pe) 437 sc->sc_pn = sc->sc_ps; 438 } else { 439 printf("%s: unexpected play intr\n", 440 sc->sc_dev.dv_xname); 441 } 442 BA1WRITE4(sc, CS4280_PFIE, mem); 443 } 444 /* Capture Interrupt */ 445 if (intr & HISR_CINT) { 446 int i; 447 int16_t rdata; 448 449 handled = 1; 450 mem = BA1READ4(sc, CS4280_CIE); 451 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 452 453 if (sc->sc_rrun) { 454 ++sc->sc_ri; 455 empty_dma = sc->sc_rdma->addr; 456 if ((sc->sc_ri&1) == 0) 457 empty_dma += sc->hw_blocksize; 458 459 /* 460 * XXX 461 * I think this audio data conversion should be 462 * happend in upper layer, but I put this here 463 * since there is no conversion function available. 464 */ 465 switch(sc->sc_rparam) { 466 case CF_16BIT_STEREO: 467 /* just copy it */ 468 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 469 sc->sc_rn += sc->hw_blocksize; 470 break; 471 case CF_16BIT_MONO: 472 for (i = 0; i < 512; i++) { 473 rdata = *((int16_t *)empty_dma)>>1; 474 empty_dma += 2; 475 rdata += *((int16_t *)empty_dma)>>1; 476 empty_dma += 2; 477 *((int16_t *)sc->sc_rn) = rdata; 478 sc->sc_rn += 2; 479 } 480 break; 481 case CF_8BIT_STEREO: 482 for (i = 0; i < 512; i++) { 483 rdata = *((int16_t*)empty_dma); 484 empty_dma += 2; 485 *sc->sc_rn++ = rdata >> 8; 486 rdata = *((int16_t*)empty_dma); 487 empty_dma += 2; 488 *sc->sc_rn++ = rdata >> 8; 489 } 490 break; 491 case CF_8BIT_MONO: 492 for (i = 0; i < 512; i++) { 493 rdata = *((int16_t*)empty_dma) >>1; 494 empty_dma += 2; 495 rdata += *((int16_t*)empty_dma) >>1; 496 empty_dma += 2; 497 *sc->sc_rn++ = rdata >>8; 498 } 499 break; 500 default: 501 /* Should not reach here */ 502 printf("%s: unknown sc->sc_rparam: %d\n", 503 sc->sc_dev.dv_xname, sc->sc_rparam); 504 } 505 if (sc->sc_rn >= sc->sc_re) 506 sc->sc_rn = sc->sc_rs; 507 } 508 BA1WRITE4(sc, CS4280_CIE, mem); 509 510 if (sc->sc_rrun) { 511 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 512 sc->sc_rintr(sc->sc_rarg); 513 } else { 514 printf("%s: unexpected record intr\n", 515 sc->sc_dev.dv_xname); 516 } 517 } 518 519 #if NMIDI > 0 520 /* Midi port Interrupt */ 521 if (intr & HISR_MIDI) { 522 int data; 523 524 handled = 1; 525 DPRINTF(("i: %d: ", 526 BA0READ4(sc, CS4280_MIDSR))); 527 /* Read the received data */ 528 while ((sc->sc_iintr != NULL) && 529 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 530 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 531 DPRINTF(("r:%x\n",data)); 532 sc->sc_iintr(sc->sc_arg, data); 533 } 534 535 /* Write the data */ 536 #if 1 537 /* XXX: 538 * It seems "Transmit Buffer Full" never activate until EOI 539 * is deliverd. Shall I throw EOI top of this routine ? 540 */ 541 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 542 DPRINTF(("w: ")); 543 if (sc->sc_ointr != NULL) 544 sc->sc_ointr(sc->sc_arg); 545 } 546 #else 547 while ((sc->sc_ointr != NULL) && 548 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 549 DPRINTF(("w: ")); 550 sc->sc_ointr(sc->sc_arg); 551 } 552 #endif 553 DPRINTF(("\n")); 554 } 555 #endif 556 557 mutex_exit(&sc->sc_intr_lock); 558 return handled; 559 } 560 561 static int 562 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 563 { 564 switch (fp->index) { 565 case 0: 566 strcpy(fp->name, AudioEulinear); 567 fp->encoding = AUDIO_ENCODING_ULINEAR; 568 fp->precision = 8; 569 fp->flags = 0; 570 break; 571 case 1: 572 strcpy(fp->name, AudioEmulaw); 573 fp->encoding = AUDIO_ENCODING_ULAW; 574 fp->precision = 8; 575 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 576 break; 577 case 2: 578 strcpy(fp->name, AudioEalaw); 579 fp->encoding = AUDIO_ENCODING_ALAW; 580 fp->precision = 8; 581 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 582 break; 583 case 3: 584 strcpy(fp->name, AudioEslinear); 585 fp->encoding = AUDIO_ENCODING_SLINEAR; 586 fp->precision = 8; 587 fp->flags = 0; 588 break; 589 case 4: 590 strcpy(fp->name, AudioEslinear_le); 591 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 592 fp->precision = 16; 593 fp->flags = 0; 594 break; 595 case 5: 596 strcpy(fp->name, AudioEulinear_le); 597 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 598 fp->precision = 16; 599 fp->flags = 0; 600 break; 601 case 6: 602 strcpy(fp->name, AudioEslinear_be); 603 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 604 fp->precision = 16; 605 fp->flags = 0; 606 break; 607 case 7: 608 strcpy(fp->name, AudioEulinear_be); 609 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 610 fp->precision = 16; 611 fp->flags = 0; 612 break; 613 default: 614 return EINVAL; 615 } 616 return 0; 617 } 618 619 static int 620 cs4280_set_params(void *addr, int setmode, int usemode, 621 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 622 stream_filter_list_t *rfil) 623 { 624 audio_params_t hw; 625 struct cs428x_softc *sc; 626 struct audio_params *p; 627 stream_filter_list_t *fil; 628 int mode; 629 630 sc = addr; 631 for (mode = AUMODE_RECORD; mode != -1; 632 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 633 if ((setmode & mode) == 0) 634 continue; 635 636 p = mode == AUMODE_PLAY ? play : rec; 637 638 if (p == play) { 639 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 640 p->sample_rate, p->precision, p->channels)); 641 /* play back data format may be 8- or 16-bit and 642 * either stereo or mono. 643 * playback rate may range from 8000Hz to 48000Hz 644 */ 645 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 646 (p->precision != 8 && p->precision != 16) || 647 (p->channels != 1 && p->channels != 2) ) { 648 return EINVAL; 649 } 650 } else { 651 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 652 p->sample_rate, p->precision, p->channels)); 653 /* capture data format must be 16bit stereo 654 * and sample rate range from 11025Hz to 48000Hz. 655 * 656 * XXX: it looks like to work with 8000Hz, 657 * although data sheets say lower limit is 658 * 11025 Hz. 659 */ 660 661 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 662 (p->precision != 8 && p->precision != 16) || 663 (p->channels != 1 && p->channels != 2) ) { 664 return EINVAL; 665 } 666 } 667 fil = mode == AUMODE_PLAY ? pfil : rfil; 668 hw = *p; 669 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 670 671 /* capturing data is slinear */ 672 switch (p->encoding) { 673 case AUDIO_ENCODING_SLINEAR_BE: 674 if (mode == AUMODE_RECORD && p->precision == 16) { 675 fil->append(fil, swap_bytes, &hw); 676 } 677 break; 678 case AUDIO_ENCODING_SLINEAR_LE: 679 break; 680 case AUDIO_ENCODING_ULINEAR_BE: 681 if (mode == AUMODE_RECORD) { 682 fil->append(fil, p->precision == 16 683 ? swap_bytes_change_sign16 684 : change_sign8, &hw); 685 } 686 break; 687 case AUDIO_ENCODING_ULINEAR_LE: 688 if (mode == AUMODE_RECORD) { 689 fil->append(fil, p->precision == 16 690 ? change_sign16 : change_sign8, 691 &hw); 692 } 693 break; 694 case AUDIO_ENCODING_ULAW: 695 if (mode == AUMODE_PLAY) { 696 hw.precision = 16; 697 hw.validbits = 16; 698 fil->append(fil, mulaw_to_linear16, &hw); 699 } else { 700 fil->append(fil, linear8_to_mulaw, &hw); 701 } 702 break; 703 case AUDIO_ENCODING_ALAW: 704 if (mode == AUMODE_PLAY) { 705 hw.precision = 16; 706 hw.validbits = 16; 707 fil->append(fil, alaw_to_linear16, &hw); 708 } else { 709 fil->append(fil, linear8_to_alaw, &hw); 710 } 711 break; 712 default: 713 return EINVAL; 714 } 715 } 716 717 /* set sample rate */ 718 cs4280_set_dac_rate(sc, play->sample_rate); 719 cs4280_set_adc_rate(sc, rec->sample_rate); 720 return 0; 721 } 722 723 static int 724 cs4280_halt_output(void *addr) 725 { 726 struct cs428x_softc *sc; 727 uint32_t mem; 728 729 sc = addr; 730 mem = BA1READ4(sc, CS4280_PCTL); 731 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 732 sc->sc_prun = 0; 733 cs4280_clkrun_hack(sc, -1); 734 735 return 0; 736 } 737 738 static int 739 cs4280_halt_input(void *addr) 740 { 741 struct cs428x_softc *sc; 742 uint32_t mem; 743 744 sc = addr; 745 mem = BA1READ4(sc, CS4280_CCTL); 746 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 747 sc->sc_rrun = 0; 748 cs4280_clkrun_hack(sc, -1); 749 750 return 0; 751 } 752 753 static int 754 cs4280_getdev(void *addr, struct audio_device *retp) 755 { 756 757 *retp = cs4280_device; 758 return 0; 759 } 760 761 static int 762 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 763 void (*intr)(void *), void *arg, 764 const audio_params_t *param) 765 { 766 struct cs428x_softc *sc; 767 uint32_t pfie, pctl, pdtc; 768 struct cs428x_dma *p; 769 770 sc = addr; 771 #ifdef DIAGNOSTIC 772 if (sc->sc_prun) 773 printf("cs4280_trigger_output: already running\n"); 774 #endif 775 sc->sc_prun = 1; 776 cs4280_clkrun_hack(sc, 1); 777 778 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 779 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 780 sc->sc_pintr = intr; 781 sc->sc_parg = arg; 782 783 /* stop playback DMA */ 784 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 785 786 /* setup PDTC */ 787 pdtc = BA1READ4(sc, CS4280_PDTC); 788 pdtc &= ~PDTC_MASK; 789 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 790 BA1WRITE4(sc, CS4280_PDTC, pdtc); 791 792 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 793 param->precision, param->channels, param->encoding)); 794 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 795 continue; 796 if (p == NULL) { 797 printf("cs4280_trigger_output: bad addr %p\n", start); 798 return EINVAL; 799 } 800 if (DMAADDR(p) % sc->dma_align != 0 ) { 801 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 802 "4kB align\n", (ulong)DMAADDR(p)); 803 return EINVAL; 804 } 805 806 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 807 sc->sc_ps = (char *)start; 808 sc->sc_pe = (char *)end; 809 sc->sc_pdma = p; 810 sc->sc_pbuf = KERNADDR(p); 811 sc->sc_pi = 0; 812 sc->sc_pn = sc->sc_ps; 813 if (blksize >= sc->dma_size) { 814 sc->sc_pn = sc->sc_ps + sc->dma_size; 815 memcpy(sc->sc_pbuf, start, sc->dma_size); 816 ++sc->sc_pi; 817 } else { 818 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 819 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 820 } 821 822 /* initiate playback DMA */ 823 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 824 825 /* set PFIE */ 826 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 827 828 if (param->precision == 8) 829 pfie |= PFIE_8BIT; 830 if (param->channels == 1) 831 pfie |= PFIE_MONO; 832 833 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 834 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 835 pfie |= PFIE_SWAPPED; 836 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 837 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 838 pfie |= PFIE_UNSIGNED; 839 840 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 841 842 sc->sc_prate = param->sample_rate; 843 cs4280_set_dac_rate(sc, param->sample_rate); 844 845 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 846 pctl |= sc->pctl; 847 BA1WRITE4(sc, CS4280_PCTL, pctl); 848 return 0; 849 } 850 851 static int 852 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 853 void (*intr)(void *), void *arg, 854 const audio_params_t *param) 855 { 856 struct cs428x_softc *sc; 857 uint32_t cctl, cie; 858 struct cs428x_dma *p; 859 860 sc = addr; 861 #ifdef DIAGNOSTIC 862 if (sc->sc_rrun) 863 printf("cs4280_trigger_input: already running\n"); 864 #endif 865 sc->sc_rrun = 1; 866 cs4280_clkrun_hack(sc, 1); 867 868 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 869 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 870 sc->sc_rintr = intr; 871 sc->sc_rarg = arg; 872 873 /* stop capture DMA */ 874 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 875 876 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 877 continue; 878 if (p == NULL) { 879 printf("cs4280_trigger_input: bad addr %p\n", start); 880 return EINVAL; 881 } 882 if (DMAADDR(p) % sc->dma_align != 0) { 883 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 884 "4kB align\n", (ulong)DMAADDR(p)); 885 return EINVAL; 886 } 887 888 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 889 sc->sc_rs = (char *)start; 890 sc->sc_re = (char *)end; 891 sc->sc_rdma = p; 892 sc->sc_rbuf = KERNADDR(p); 893 sc->sc_ri = 0; 894 sc->sc_rn = sc->sc_rs; 895 896 /* initiate capture DMA */ 897 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 898 899 /* setup format information for internal converter */ 900 sc->sc_rparam = 0; 901 if (param->precision == 8) { 902 sc->sc_rparam += CF_8BIT; 903 sc->sc_rcount <<= 1; 904 } 905 if (param->channels == 1) { 906 sc->sc_rparam += CF_MONO; 907 sc->sc_rcount <<= 1; 908 } 909 910 /* set CIE */ 911 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 912 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 913 914 sc->sc_rrate = param->sample_rate; 915 cs4280_set_adc_rate(sc, param->sample_rate); 916 917 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 918 cctl |= sc->cctl; 919 BA1WRITE4(sc, CS4280_CCTL, cctl); 920 return 0; 921 } 922 923 /* Power Hook */ 924 static void 925 cs4280_power(int why, void *v) 926 { 927 static uint32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 928 static uint32_t cctl = 0, cba = 0, cie = 0; 929 struct cs428x_softc *sc; 930 931 sc = (struct cs428x_softc *)v; 932 933 mutex_enter(&sc->sc_lock); 934 935 DPRINTF(("%s: cs4280_power why=%d\n", sc->sc_dev.dv_xname, why)); 936 switch (why) { 937 case PWR_SUSPEND: 938 case PWR_STANDBY: 939 sc->sc_suspend = why; 940 941 /* save current playback status */ 942 if (sc->sc_prun) { 943 pctl = BA1READ4(sc, CS4280_PCTL); 944 pfie = BA1READ4(sc, CS4280_PFIE); 945 pba = BA1READ4(sc, CS4280_PBA); 946 pdtc = BA1READ4(sc, CS4280_PDTC); 947 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 948 pctl, pfie, pba, pdtc)); 949 } 950 951 /* save current capture status */ 952 if (sc->sc_rrun) { 953 cctl = BA1READ4(sc, CS4280_CCTL); 954 cie = BA1READ4(sc, CS4280_CIE); 955 cba = BA1READ4(sc, CS4280_CBA); 956 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 957 cctl, cie, cba)); 958 } 959 960 /* Stop DMA */ 961 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 962 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 963 break; 964 case PWR_RESUME: 965 if (sc->sc_suspend == PWR_RESUME) { 966 printf("cs4280_power: odd, resume without suspend.\n"); 967 sc->sc_suspend = why; 968 break; 969 } 970 sc->sc_suspend = why; 971 cs4280_init(sc, 0); 972 #if 0 973 cs4280_reset_codec(sc); 974 #endif 975 /* restore ac97 registers */ 976 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 977 978 /* restore DMA related status */ 979 if(sc->sc_prun) { 980 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 981 pctl, pfie, pba, pdtc)); 982 cs4280_set_dac_rate(sc, sc->sc_prate); 983 BA1WRITE4(sc, CS4280_PDTC, pdtc); 984 BA1WRITE4(sc, CS4280_PBA, pba); 985 BA1WRITE4(sc, CS4280_PFIE, pfie); 986 BA1WRITE4(sc, CS4280_PCTL, pctl); 987 } 988 989 if (sc->sc_rrun) { 990 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 991 cctl, cie, cba)); 992 cs4280_set_adc_rate(sc, sc->sc_rrate); 993 BA1WRITE4(sc, CS4280_CBA, cba); 994 BA1WRITE4(sc, CS4280_CIE, cie); 995 BA1WRITE4(sc, CS4280_CCTL, cctl); 996 } 997 break; 998 case PWR_SOFTSUSPEND: 999 case PWR_SOFTSTANDBY: 1000 case PWR_SOFTRESUME: 1001 break; 1002 } 1003 1004 mutex_exit(&sc->sc_lock); 1005 } 1006 1007 static int 1008 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 1009 { 1010 struct cs428x_softc *sc = addr; 1011 int rv; 1012 1013 cs4280_clkrun_hack(sc, 1); 1014 rv = cs428x_read_codec(addr, reg, result); 1015 cs4280_clkrun_hack(sc, -1); 1016 1017 return rv; 1018 } 1019 1020 static int 1021 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1022 { 1023 struct cs428x_softc *sc = addr; 1024 int rv; 1025 1026 cs4280_clkrun_hack(sc, 1); 1027 rv = cs428x_write_codec(addr, reg, data); 1028 cs4280_clkrun_hack(sc, -1); 1029 1030 return rv; 1031 } 1032 1033 #if 0 /* XXX buggy and not required */ 1034 /* control AC97 codec */ 1035 static int 1036 cs4280_reset_codec(void *addr) 1037 { 1038 struct cs428x_softc *sc; 1039 int n; 1040 1041 sc = addr; 1042 1043 /* Reset codec */ 1044 BA0WRITE4(sc, CS428X_ACCTL, 0); 1045 delay(100); /* delay 100us */ 1046 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1047 1048 /* 1049 * It looks like we do the following procedure, too 1050 */ 1051 1052 /* Enable AC-link sync generation */ 1053 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1054 delay(50*1000); /* XXX delay 50ms */ 1055 1056 /* Assert valid frame signal */ 1057 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1058 1059 /* Wait for valid AC97 input slot */ 1060 n = 0; 1061 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1062 (ACISV_ISV3 | ACISV_ISV4)) { 1063 delay(1000); 1064 if (++n > 1000) { 1065 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1066 return ETIMEDOUT; 1067 } 1068 } 1069 1070 return 0; 1071 } 1072 #endif 1073 1074 static enum ac97_host_flags cs4280_flags_codec(void *addr) 1075 { 1076 struct cs428x_softc *sc; 1077 1078 sc = addr; 1079 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1080 return AC97_HOST_INVERTED_EAMP; 1081 1082 return 0; 1083 } 1084 1085 /* Internal functions */ 1086 1087 static const struct cs4280_card_t * 1088 cs4280_identify_card(struct pci_attach_args *pa) 1089 { 1090 pcireg_t idreg; 1091 u_int16_t i; 1092 1093 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1094 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1095 if (idreg == cs4280_cards[i].id) 1096 return &cs4280_cards[i]; 1097 } 1098 1099 return NULL; 1100 } 1101 1102 static int 1103 cs4280_piix4_match(struct pci_attach_args *pa) 1104 { 1105 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1106 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1107 return 1; 1108 } 1109 1110 return 0; 1111 } 1112 1113 static void 1114 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1115 { 1116 uint16_t control, val; 1117 1118 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1119 return; 1120 1121 sc->sc_active += change; 1122 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1123 if (!sc->sc_active) 1124 val |= 0x2000; 1125 else 1126 val &= ~0x2000; 1127 if (val != control) 1128 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1129 } 1130 1131 static void 1132 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1133 { 1134 struct pci_attach_args smbuspa; 1135 uint16_t reg; 1136 pcireg_t port; 1137 1138 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1139 return; 1140 1141 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1142 sc->sc_active = 0; 1143 printf("%s: enabling CLKRUN hack\n", 1144 sc->sc_dev.dv_xname); 1145 1146 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1147 port = reg & 0xffc0; 1148 printf("%s: power management port 0x%x\n", sc->sc_dev.dv_xname, 1149 port); 1150 1151 sc->sc_pm_iot = smbuspa.pa_iot; 1152 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1153 &sc->sc_pm_ioh) == 0) 1154 return; 1155 } 1156 1157 /* handle error */ 1158 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1159 printf("%s: disabling CLKRUN hack\n", sc->sc_dev.dv_xname); 1160 } 1161 1162 static void 1163 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1164 { 1165 /* calculate capture rate: 1166 * 1167 * capture_coefficient_increment = -round(rate*128*65536/48000; 1168 * capture_phase_increment = floor(48000*65536*1024/rate); 1169 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1170 * cy = floor(cx/200); 1171 * capture_sample_rate_correction = cx - 200*cy; 1172 * capture_delay = ceil(24*48000/rate); 1173 * capture_num_triplets = floor(65536*rate/24000); 1174 * capture_group_length = 24000/GCD(rate, 24000); 1175 * where GCD means "Greatest Common Divisor". 1176 * 1177 * capture_coefficient_increment, capture_phase_increment and 1178 * capture_num_triplets are 32-bit signed quantities. 1179 * capture_sample_rate_correction and capture_group_length are 1180 * 16-bit signed quantities. 1181 * capture_delay is a 14-bit unsigned quantity. 1182 */ 1183 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1184 uint16_t csrc, cgl, cdlay; 1185 1186 /* XXX 1187 * Even though, embedded_audio_spec says capture rate range 11025 to 1188 * 48000, dhwiface.cpp says, 1189 * 1190 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1191 * Return an error if an attempt is made to stray outside that limit." 1192 * 1193 * so assume range as 48000/9 to 48000 1194 */ 1195 1196 if (rate < 8000) 1197 rate = 8000; 1198 if (rate > 48000) 1199 rate = 48000; 1200 1201 cx = rate << 16; 1202 cci = cx / 48000; 1203 cx -= cci * 48000; 1204 cx <<= 7; 1205 cci <<= 7; 1206 cci += cx / 48000; 1207 cci = - cci; 1208 1209 cx = 48000 << 16; 1210 cpi = cx / rate; 1211 cx -= cpi * rate; 1212 cx <<= 10; 1213 cpi <<= 10; 1214 cy = cx / rate; 1215 cpi += cy; 1216 cx -= cy * rate; 1217 1218 cy = cx / 200; 1219 csrc = cx - 200*cy; 1220 1221 cdlay = ((48000 * 24) + rate - 1) / rate; 1222 #if 0 1223 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1224 #endif 1225 1226 cnt = rate << 16; 1227 cnt /= 24000; 1228 1229 cgl = 1; 1230 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1231 if (((rate / tmp1) * tmp1) != rate) 1232 cgl *= 2; 1233 } 1234 if (((rate / 3) * 3) != rate) 1235 cgl *= 3; 1236 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1237 if (((rate / tmp1) * tmp1) != rate) 1238 cgl *= 5; 1239 } 1240 #if 0 1241 /* XXX what manual says */ 1242 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1243 tmp1 |= csrc<<16; 1244 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1245 #else 1246 /* suggested by cs461x.c (ALSA driver) */ 1247 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1248 #endif 1249 1250 #if 0 1251 /* I am confused. The sample rate calculation section says 1252 * cci *is* 32-bit signed quantity but in the parameter description 1253 * section, CCI only assigned 16bit. 1254 * I believe size of the variable. 1255 */ 1256 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1257 tmp1 |= cci<<16; 1258 BA1WRITE4(sc, CS4280_CCI, tmp1); 1259 #else 1260 BA1WRITE4(sc, CS4280_CCI, cci); 1261 #endif 1262 1263 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1264 tmp1 |= cdlay <<18; 1265 BA1WRITE4(sc, CS4280_CD, tmp1); 1266 1267 BA1WRITE4(sc, CS4280_CPI, cpi); 1268 1269 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1270 tmp1 |= cgl; 1271 BA1WRITE4(sc, CS4280_CGL, tmp1); 1272 1273 BA1WRITE4(sc, CS4280_CNT, cnt); 1274 1275 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1276 tmp1 |= cgl; 1277 BA1WRITE4(sc, CS4280_CGC, tmp1); 1278 } 1279 1280 static void 1281 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1282 { 1283 /* 1284 * playback rate may range from 8000Hz to 48000Hz 1285 * 1286 * play_phase_increment = floor(rate*65536*1024/48000) 1287 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1288 * py=floor(px/200) 1289 * play_sample_rate_correction = px - 200*py 1290 * 1291 * play_phase_increment is a 32bit signed quantity. 1292 * play_sample_rate_correction is a 16bit signed quantity. 1293 */ 1294 int32_t ppi; 1295 int16_t psrc; 1296 uint32_t px, py; 1297 1298 if (rate < 8000) 1299 rate = 8000; 1300 if (rate > 48000) 1301 rate = 48000; 1302 px = rate << 16; 1303 ppi = px/48000; 1304 px -= ppi*48000; 1305 ppi <<= 10; 1306 px <<= 10; 1307 py = px / 48000; 1308 ppi += py; 1309 px -= py*48000; 1310 py = px/200; 1311 px -= py*200; 1312 psrc = px; 1313 #if 0 1314 /* what manual says */ 1315 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1316 BA1WRITE4(sc, CS4280_PSRC, 1317 ( ((psrc<<16) & PSRC_MASK) | px )); 1318 #else 1319 /* suggested by cs461x.c (ALSA driver) */ 1320 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1321 #endif 1322 BA1WRITE4(sc, CS4280_PPI, ppi); 1323 } 1324 1325 /* Download Processor Code and Data image */ 1326 static int 1327 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1328 uint32_t offset, uint32_t len) 1329 { 1330 uint32_t ctr; 1331 #if CS4280_DEBUG > 10 1332 uint32_t con, data; 1333 uint8_t c0, c1, c2, c3; 1334 #endif 1335 if ((offset & 3) || (len & 3)) 1336 return -1; 1337 1338 len /= sizeof(uint32_t); 1339 for (ctr = 0; ctr < len; ctr++) { 1340 /* XXX: 1341 * I cannot confirm this is the right thing or not 1342 * on BIG-ENDIAN machines. 1343 */ 1344 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1345 #if CS4280_DEBUG > 10 1346 data = htole32(*(src+ctr)); 1347 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1348 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1349 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1350 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1351 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1352 if (data != con ) { 1353 printf("0x%06x: write=0x%08x read=0x%08x\n", 1354 offset+ctr*4, data, con); 1355 return -1; 1356 } 1357 #endif 1358 } 1359 return 0; 1360 } 1361 1362 static int 1363 cs4280_download_image(struct cs428x_softc *sc) 1364 { 1365 int idx, err; 1366 uint32_t offset = 0; 1367 1368 err = 0; 1369 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1370 err = cs4280_download(sc, &BA1Struct.map[offset], 1371 BA1Struct.memory[idx].offset, 1372 BA1Struct.memory[idx].size); 1373 if (err != 0) { 1374 printf("%s: load_image failed at %d\n", 1375 sc->sc_dev.dv_xname, idx); 1376 return -1; 1377 } 1378 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1379 } 1380 return err; 1381 } 1382 1383 /* Processor Soft Reset */ 1384 static void 1385 cs4280_reset(void *sc_) 1386 { 1387 struct cs428x_softc *sc; 1388 1389 sc = sc_; 1390 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1391 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1392 delay(100); 1393 /* Clear RSTSP bit in SPCR */ 1394 BA1WRITE4(sc, CS4280_SPCR, 0); 1395 /* enable DMA reqest */ 1396 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1397 } 1398 1399 static int 1400 cs4280_init(struct cs428x_softc *sc, int init) 1401 { 1402 int n; 1403 uint32_t mem; 1404 int rv; 1405 1406 rv = 1; 1407 cs4280_clkrun_hack(sc, 1); 1408 1409 /* Start PLL out in known state */ 1410 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1411 /* Start serial ports out in known state */ 1412 BA0WRITE4(sc, CS4280_SERMC1, 0); 1413 1414 /* Specify type of CODEC */ 1415 /* XXX should not be here */ 1416 #define SERACC_CODEC_TYPE_1_03 1417 #ifdef SERACC_CODEC_TYPE_1_03 1418 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1419 #else 1420 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1421 #endif 1422 1423 /* Reset codec */ 1424 BA0WRITE4(sc, CS428X_ACCTL, 0); 1425 delay(100); /* delay 100us */ 1426 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1427 1428 /* Enable AC-link sync generation */ 1429 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1430 delay(50*1000); /* delay 50ms */ 1431 1432 /* Set the serial port timing configuration */ 1433 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1434 1435 /* Setup clock control */ 1436 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1437 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1438 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1439 1440 /* Power up the PLL */ 1441 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1442 delay(50*1000); /* delay 50ms */ 1443 1444 /* Turn on clock */ 1445 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1446 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1447 1448 /* Set the serial port FIFO pointer to the 1449 * first sample in FIFO. (not documented) */ 1450 cs4280_clear_fifos(sc); 1451 1452 #if 0 1453 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1454 BA0WRITE4(sc, CS4280_SERBSP, 0); 1455 #endif 1456 1457 /* Configure the serial port */ 1458 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1459 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1460 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1461 1462 /* Wait for CODEC ready */ 1463 n = 0; 1464 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1465 delay(125); 1466 if (++n > 1000) { 1467 printf("%s: codec ready timeout\n", 1468 sc->sc_dev.dv_xname); 1469 goto exit; 1470 } 1471 } 1472 1473 /* Assert valid frame signal */ 1474 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1475 1476 /* Wait for valid AC97 input slot */ 1477 n = 0; 1478 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1479 (ACISV_ISV3 | ACISV_ISV4)) { 1480 delay(1000); 1481 if (++n > 1000) { 1482 printf("AC97 inputs slot ready timeout\n"); 1483 goto exit; 1484 } 1485 } 1486 1487 /* Set AC97 output slot valid signals */ 1488 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1489 1490 /* reset the processor */ 1491 cs4280_reset(sc); 1492 1493 /* Download the image to the processor */ 1494 if (cs4280_download_image(sc) != 0) { 1495 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1496 goto exit; 1497 } 1498 1499 /* Save playback parameter and then write zero. 1500 * this ensures that DMA doesn't immediately occur upon 1501 * starting the processor core 1502 */ 1503 mem = BA1READ4(sc, CS4280_PCTL); 1504 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1505 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1506 if (init != 0) 1507 sc->sc_prun = 0; 1508 1509 /* Save capture parameter and then write zero. 1510 * this ensures that DMA doesn't immediately occur upon 1511 * starting the processor core 1512 */ 1513 mem = BA1READ4(sc, CS4280_CCTL); 1514 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1515 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1516 if (init != 0) 1517 sc->sc_rrun = 0; 1518 1519 /* Processor Startup Procedure */ 1520 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1521 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1522 1523 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1524 n = 0; 1525 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1526 delay(10); 1527 if (++n > 1000) { 1528 printf("SPCR 1->0 transition timeout\n"); 1529 goto exit; 1530 } 1531 } 1532 1533 n = 0; 1534 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1535 delay(10); 1536 if (++n > 1000) { 1537 printf("SPCS 0->1 transition timeout\n"); 1538 goto exit; 1539 } 1540 } 1541 /* Processor is now running !!! */ 1542 1543 /* Setup volume */ 1544 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1545 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1546 1547 /* Interrupt enable */ 1548 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1549 1550 /* playback interrupt enable */ 1551 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1552 mem |= PFIE_PI_ENABLE; 1553 BA1WRITE4(sc, CS4280_PFIE, mem); 1554 /* capture interrupt enable */ 1555 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1556 mem |= CIE_CI_ENABLE; 1557 BA1WRITE4(sc, CS4280_CIE, mem); 1558 1559 #if NMIDI > 0 1560 /* Reset midi port */ 1561 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1562 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1563 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1564 /* midi interrupt enable */ 1565 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1566 BA0WRITE4(sc, CS4280_MIDCR, mem); 1567 #endif 1568 1569 rv = 0; 1570 1571 exit: 1572 cs4280_clkrun_hack(sc, -1); 1573 return rv; 1574 } 1575 1576 static void 1577 cs4280_clear_fifos(struct cs428x_softc *sc) 1578 { 1579 int pd, cnt, n; 1580 uint32_t mem; 1581 1582 pd = 0; 1583 /* 1584 * If device power down, power up the device and keep power down 1585 * state. 1586 */ 1587 mem = BA0READ4(sc, CS4280_CLKCR1); 1588 if (!(mem & CLKCR1_SWCE)) { 1589 printf("cs4280_clear_fifo: power down found.\n"); 1590 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1591 pd = 1; 1592 } 1593 BA0WRITE4(sc, CS4280_SERBWP, 0); 1594 for (cnt = 0; cnt < 256; cnt++) { 1595 n = 0; 1596 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1597 delay(1000); 1598 if (++n > 1000) { 1599 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1600 break; 1601 } 1602 } 1603 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1604 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1605 } 1606 if (pd) 1607 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1608 } 1609 1610 #if NMIDI > 0 1611 static int 1612 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1613 void (*ointr)(void *), void *arg) 1614 { 1615 struct cs428x_softc *sc; 1616 uint32_t mem; 1617 1618 DPRINTF(("midi_open\n")); 1619 sc = addr; 1620 sc->sc_iintr = iintr; 1621 sc->sc_ointr = ointr; 1622 sc->sc_arg = arg; 1623 1624 /* midi interrupt enable */ 1625 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1626 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1627 BA0WRITE4(sc, CS4280_MIDCR, mem); 1628 #ifdef CS4280_DEBUG 1629 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1630 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1631 return(EINVAL); 1632 } 1633 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1634 #endif 1635 return 0; 1636 } 1637 1638 static void 1639 cs4280_midi_close(void *addr) 1640 { 1641 struct cs428x_softc *sc; 1642 uint32_t mem; 1643 1644 DPRINTF(("midi_close\n")); 1645 sc = addr; 1646 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1647 mem = BA0READ4(sc, CS4280_MIDCR); 1648 mem &= ~MIDCR_MASK; 1649 BA0WRITE4(sc, CS4280_MIDCR, mem); 1650 1651 sc->sc_iintr = 0; 1652 sc->sc_ointr = 0; 1653 } 1654 1655 static int 1656 cs4280_midi_output(void *addr, int d) 1657 { 1658 struct cs428x_softc *sc; 1659 uint32_t mem; 1660 int x; 1661 1662 sc = addr; 1663 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1664 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1665 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1666 mem |= d & MIDWP_MASK; 1667 DPRINTFN(5,("midi_output d=0x%08x",d)); 1668 BA0WRITE4(sc, CS4280_MIDWP, mem); 1669 #ifdef DIAGNOSTIC 1670 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1671 DPRINTF(("Bad write data: %d %d", 1672 mem, BA0READ4(sc, CS4280_MIDWP))); 1673 return EIO; 1674 } 1675 #endif 1676 return 0; 1677 } 1678 delay(MIDI_BUSY_DELAY); 1679 } 1680 return EIO; 1681 } 1682 1683 static void 1684 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1685 { 1686 1687 mi->name = "CS4280 MIDI UART"; 1688 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1689 } 1690 1691 #endif /* NMIDI */ 1692 1693 /* DEBUG functions */ 1694 #if CS4280_DEBUG > 10 1695 static int 1696 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1697 uint32_t offset, uint32_t len) 1698 { 1699 uint32_t ctr, data; 1700 int err; 1701 1702 if ((offset & 3) || (len & 3)) 1703 return -1; 1704 1705 err = 0; 1706 len /= sizeof(uint32_t); 1707 for (ctr = 0; ctr < len; ctr++) { 1708 /* I cannot confirm this is the right thing 1709 * on BIG-ENDIAN machines 1710 */ 1711 data = BA1READ4(sc, offset+ctr*4); 1712 if (data != htole32(*(src+ctr))) { 1713 printf("0x%06x: 0x%08x(0x%08x)\n", 1714 offset+ctr*4, data, *(src+ctr)); 1715 *(src+ctr) = data; 1716 ++err; 1717 } 1718 } 1719 return err; 1720 } 1721 1722 static int 1723 cs4280_check_images(struct cs428x_softc *sc) 1724 { 1725 int idx, err; 1726 uint32_t offset; 1727 1728 offset = 0; 1729 err = 0; 1730 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1731 for (idx = 0; idx < 1; ++idx) { 1732 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1733 BA1Struct.memory[idx].offset, 1734 BA1Struct.memory[idx].size); 1735 if (err != 0) { 1736 printf("%s: check_image failed at %d\n", 1737 sc->sc_dev.dv_xname, idx); 1738 } 1739 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1740 } 1741 return err; 1742 } 1743 1744 #endif /* CS4280_DEBUG */ 1745
Indexes created Thu Oct 02 14:10:14 GMT 2025