cs4280.c revision 1.46.6.2
1 /* $NetBSD: cs4280.c,v 1.46.6.2 2007/10/26 15:45:55 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.46.6.2 2007/10/26 15:45:55 joerg Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <sys/bus.h> 86 #include <sys/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(struct device *, struct cfdata *, void *); 93 static void cs4280_attach(struct device *, struct device *, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 107 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 108 #if 0 109 static int cs4280_reset_codec(void *); 110 #endif 111 static enum ac97_host_flags cs4280_flags_codec(void *); 112 113 static void cs4280_resume(device_t); 114 static void cs4280_suspend(device_t); 115 116 /* Internal functions */ 117 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *); 118 static int cs4280_piix4_match(struct pci_attach_args *); 119 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 120 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 121 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 122 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 123 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 124 uint32_t); 125 static int cs4280_download_image(struct cs428x_softc *); 126 static void cs4280_reset(void *); 127 static int cs4280_init(struct cs428x_softc *, int); 128 static void cs4280_clear_fifos(struct cs428x_softc *); 129 130 #if CS4280_DEBUG > 10 131 /* Thease two function is only for checking image loading is succeeded or not. */ 132 static int cs4280_check_images(struct cs428x_softc *); 133 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 134 uint32_t); 135 #endif 136 137 /* Special cards */ 138 struct cs4280_card_t 139 { 140 pcireg_t id; 141 enum cs428x_flags flags; 142 }; 143 144 #define _card(vend, prod, flags) \ 145 {PCI_ID_CODE(vend, prod), flags} 146 147 static const struct cs4280_card_t cs4280_cards[] = { 148 #if 0 /* untested, from ALSA driver */ 149 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 150 CS428X_FLAG_INVAC97EAMP), 151 #endif 152 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 153 CS428X_FLAG_INVAC97EAMP), 154 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 155 CS428X_FLAG_CLKRUNHACK) 156 }; 157 158 #undef _card 159 160 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 161 162 static const struct audio_hw_if cs4280_hw_if = { 163 NULL, /* open */ 164 NULL, /* close */ 165 NULL, 166 cs4280_query_encoding, 167 cs4280_set_params, 168 cs428x_round_blocksize, 169 NULL, 170 NULL, 171 NULL, 172 NULL, 173 NULL, 174 cs4280_halt_output, 175 cs4280_halt_input, 176 NULL, 177 cs4280_getdev, 178 NULL, 179 cs428x_mixer_set_port, 180 cs428x_mixer_get_port, 181 cs428x_query_devinfo, 182 cs428x_malloc, 183 cs428x_free, 184 cs428x_round_buffersize, 185 cs428x_mappage, 186 cs428x_get_props, 187 cs4280_trigger_output, 188 cs4280_trigger_input, 189 NULL, 190 NULL, 191 }; 192 193 #if NMIDI > 0 194 /* Midi Interface */ 195 static int cs4280_midi_open(void *, int, void (*)(void *, int), 196 void (*)(void *), void *); 197 static void cs4280_midi_close(void*); 198 static int cs4280_midi_output(void *, int); 199 static void cs4280_midi_getinfo(void *, struct midi_info *); 200 201 static const struct midi_hw_if cs4280_midi_hw_if = { 202 cs4280_midi_open, 203 cs4280_midi_close, 204 cs4280_midi_output, 205 cs4280_midi_getinfo, 206 0, 207 }; 208 #endif 209 210 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 211 cs4280_match, cs4280_attach, NULL, NULL); 212 213 static struct audio_device cs4280_device = { 214 "CS4280", 215 "", 216 "cs4280" 217 }; 218 219 220 static int 221 cs4280_match(struct device *parent, struct cfdata *match, 222 void *aux) 223 { 224 struct pci_attach_args *pa; 225 226 pa = (struct pci_attach_args *)aux; 227 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 228 return 0; 229 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 230 #if 0 /* I can't confirm */ 231 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 232 #endif 233 ) 234 return 1; 235 return 0; 236 } 237 238 static void 239 cs4280_attach(struct device *parent, struct device *self, void *aux) 240 { 241 struct cs428x_softc *sc; 242 struct pci_attach_args *pa; 243 pci_chipset_tag_t pc; 244 const struct cs4280_card_t *cs_card; 245 char const *intrstr; 246 pcireg_t reg; 247 char devinfo[256]; 248 uint32_t mem; 249 int error; 250 pnp_status_t pnp_status; 251 252 sc = (struct cs428x_softc *)self; 253 pa = (struct pci_attach_args *)aux; 254 pc = pa->pa_pc; 255 aprint_naive(": Audio controller\n"); 256 257 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 258 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 259 PCI_REVISION(pa->pa_class)); 260 261 cs_card = cs4280_identify_card(pa); 262 if (cs_card != NULL) { 263 aprint_normal("%s: %s %s\n",sc->sc_dev.dv_xname, 264 pci_findvendor(cs_card->id), 265 pci_findproduct(cs_card->id)); 266 sc->sc_flags = cs_card->flags; 267 } else { 268 sc->sc_flags = CS428X_FLAG_NONE; 269 } 270 271 sc->sc_pc = pa->pa_pc; 272 sc->sc_pt = pa->pa_tag; 273 274 /* Map I/O register */ 275 if (pci_mapreg_map(pa, PCI_BA0, 276 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 277 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 278 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 279 return; 280 } 281 if (pci_mapreg_map(pa, PCI_BA1, 282 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 283 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 284 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 285 return; 286 } 287 288 sc->sc_dmatag = pa->pa_dmat; 289 290 /* power up chip */ 291 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 292 pci_activate_null)) && error != EOPNOTSUPP) { 293 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 294 error); 295 return; 296 } 297 298 /* Enable the device (set bus master flag) */ 299 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 300 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 301 reg | PCI_COMMAND_MASTER_ENABLE); 302 303 /* LATENCY_TIMER setting */ 304 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 305 if ( PCI_LATTIMER(mem) < 32 ) { 306 mem &= 0xffff00ff; 307 mem |= 0x00002000; 308 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 309 } 310 311 /* CLKRUN hack initialization */ 312 cs4280_clkrun_hack_init(sc); 313 314 /* Map and establish the interrupt. */ 315 if (pci_intr_map(pa, &sc->intrh)) { 316 aprint_error("%s: couldn't map interrupt\n", 317 sc->sc_dev.dv_xname); 318 return; 319 } 320 intrstr = pci_intr_string(pc, sc->intrh); 321 322 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 323 cs4280_intr, sc); 324 if (sc->sc_ih == NULL) { 325 aprint_error("%s: couldn't establish interrupt", 326 sc->sc_dev.dv_xname); 327 if (intrstr != NULL) 328 aprint_normal(" at %s", intrstr); 329 aprint_normal("\n"); 330 return; 331 } 332 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 333 334 /* Initialization */ 335 if(cs4280_init(sc, 1) != 0) 336 return; 337 338 sc->type = TYPE_CS4280; 339 sc->halt_input = cs4280_halt_input; 340 sc->halt_output = cs4280_halt_output; 341 342 /* setup buffer related parameters */ 343 sc->dma_size = CS4280_DCHUNK; 344 sc->dma_align = CS4280_DALIGN; 345 sc->hw_blocksize = CS4280_ICHUNK; 346 347 /* AC 97 attachment */ 348 sc->host_if.arg = sc; 349 sc->host_if.attach = cs428x_attach_codec; 350 sc->host_if.read = cs4280_read_codec; 351 sc->host_if.write = cs4280_write_codec; 352 #if 0 353 sc->host_if.reset = cs4280_reset_codec; 354 #else 355 sc->host_if.reset = NULL; 356 #endif 357 sc->host_if.flags = cs4280_flags_codec; 358 if (ac97_attach(&sc->host_if, self) != 0) { 359 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 360 return; 361 } 362 363 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 364 365 #if NMIDI > 0 366 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 367 #endif 368 369 pnp_status = pci_generic_power_register(self, pa->pa_pc, pa->pa_tag, 370 cs4280_suspend, cs4280_resume); 371 if (pnp_status != PNP_STATUS_SUCCESS) { 372 aprint_error("%s: couldn't establish power handler\n", 373 device_xname(self)); 374 } 375 } 376 377 /* Interrupt handling function */ 378 static int 379 cs4280_intr(void *p) 380 { 381 /* 382 * XXX 383 * 384 * Since CS4280 has only 4kB DMA buffer and 385 * interrupt occurs every 2kB block, I create dummy buffer 386 * which returns to audio driver and actual DMA buffer 387 * using in DMA transfer. 388 * 389 * 390 * ring buffer in audio.c is pointed by BUFADDR 391 * <------ ring buffer size == 64kB ------> 392 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 393 * |= = = =|= = = =|= = = =|= = = =|= = = =| 394 * | | | | | | <- call audio_intp every 395 * sc->sc_[pr]_count time. 396 * 397 * actual DMA buffer is pointed by KERNADDR 398 * <-> DMA buffer size = 4kB 399 * |= =| 400 * 401 * 402 */ 403 struct cs428x_softc *sc; 404 uint32_t intr, mem; 405 char * empty_dma; 406 int handled; 407 408 sc = p; 409 handled = 0; 410 /* grab interrupt register then clear it */ 411 intr = BA0READ4(sc, CS4280_HISR); 412 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 413 414 /* not for us ? */ 415 if ((intr & HISR_INTENA) == 0) 416 return 0; 417 418 /* Playback Interrupt */ 419 if (intr & HISR_PINT) { 420 handled = 1; 421 mem = BA1READ4(sc, CS4280_PFIE); 422 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 423 if (sc->sc_prun) { 424 if ((sc->sc_pi%sc->sc_pcount) == 0) 425 sc->sc_pintr(sc->sc_parg); 426 /* copy buffer */ 427 ++sc->sc_pi; 428 empty_dma = sc->sc_pdma->addr; 429 if (sc->sc_pi&1) 430 empty_dma += sc->hw_blocksize; 431 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 432 sc->sc_pn += sc->hw_blocksize; 433 if (sc->sc_pn >= sc->sc_pe) 434 sc->sc_pn = sc->sc_ps; 435 } else { 436 printf("%s: unexpected play intr\n", 437 sc->sc_dev.dv_xname); 438 } 439 BA1WRITE4(sc, CS4280_PFIE, mem); 440 } 441 /* Capture Interrupt */ 442 if (intr & HISR_CINT) { 443 int i; 444 int16_t rdata; 445 446 handled = 1; 447 mem = BA1READ4(sc, CS4280_CIE); 448 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 449 450 if (sc->sc_rrun) { 451 ++sc->sc_ri; 452 empty_dma = sc->sc_rdma->addr; 453 if ((sc->sc_ri&1) == 0) 454 empty_dma += sc->hw_blocksize; 455 456 /* 457 * XXX 458 * I think this audio data conversion should be 459 * happend in upper layer, but I put this here 460 * since there is no conversion function available. 461 */ 462 switch(sc->sc_rparam) { 463 case CF_16BIT_STEREO: 464 /* just copy it */ 465 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 466 sc->sc_rn += sc->hw_blocksize; 467 break; 468 case CF_16BIT_MONO: 469 for (i = 0; i < 512; i++) { 470 rdata = *((int16_t *)empty_dma)>>1; 471 empty_dma += 2; 472 rdata += *((int16_t *)empty_dma)>>1; 473 empty_dma += 2; 474 *((int16_t *)sc->sc_rn) = rdata; 475 sc->sc_rn += 2; 476 } 477 break; 478 case CF_8BIT_STEREO: 479 for (i = 0; i < 512; i++) { 480 rdata = *((int16_t*)empty_dma); 481 empty_dma += 2; 482 *sc->sc_rn++ = rdata >> 8; 483 rdata = *((int16_t*)empty_dma); 484 empty_dma += 2; 485 *sc->sc_rn++ = rdata >> 8; 486 } 487 break; 488 case CF_8BIT_MONO: 489 for (i = 0; i < 512; i++) { 490 rdata = *((int16_t*)empty_dma) >>1; 491 empty_dma += 2; 492 rdata += *((int16_t*)empty_dma) >>1; 493 empty_dma += 2; 494 *sc->sc_rn++ = rdata >>8; 495 } 496 break; 497 default: 498 /* Should not reach here */ 499 printf("%s: unknown sc->sc_rparam: %d\n", 500 sc->sc_dev.dv_xname, sc->sc_rparam); 501 } 502 if (sc->sc_rn >= sc->sc_re) 503 sc->sc_rn = sc->sc_rs; 504 } 505 BA1WRITE4(sc, CS4280_CIE, mem); 506 507 if (sc->sc_rrun) { 508 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 509 sc->sc_rintr(sc->sc_rarg); 510 } else { 511 printf("%s: unexpected record intr\n", 512 sc->sc_dev.dv_xname); 513 } 514 } 515 516 #if NMIDI > 0 517 /* Midi port Interrupt */ 518 if (intr & HISR_MIDI) { 519 int data; 520 521 handled = 1; 522 DPRINTF(("i: %d: ", 523 BA0READ4(sc, CS4280_MIDSR))); 524 /* Read the received data */ 525 while ((sc->sc_iintr != NULL) && 526 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 527 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 528 DPRINTF(("r:%x\n",data)); 529 sc->sc_iintr(sc->sc_arg, data); 530 } 531 532 /* Write the data */ 533 #if 1 534 /* XXX: 535 * It seems "Transmit Buffer Full" never activate until EOI 536 * is deliverd. Shall I throw EOI top of this routine ? 537 */ 538 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 539 DPRINTF(("w: ")); 540 if (sc->sc_ointr != NULL) 541 sc->sc_ointr(sc->sc_arg); 542 } 543 #else 544 while ((sc->sc_ointr != NULL) && 545 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 546 DPRINTF(("w: ")); 547 sc->sc_ointr(sc->sc_arg); 548 } 549 #endif 550 DPRINTF(("\n")); 551 } 552 #endif 553 554 return handled; 555 } 556 557 static int 558 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 559 { 560 switch (fp->index) { 561 case 0: 562 strcpy(fp->name, AudioEulinear); 563 fp->encoding = AUDIO_ENCODING_ULINEAR; 564 fp->precision = 8; 565 fp->flags = 0; 566 break; 567 case 1: 568 strcpy(fp->name, AudioEmulaw); 569 fp->encoding = AUDIO_ENCODING_ULAW; 570 fp->precision = 8; 571 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 572 break; 573 case 2: 574 strcpy(fp->name, AudioEalaw); 575 fp->encoding = AUDIO_ENCODING_ALAW; 576 fp->precision = 8; 577 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 578 break; 579 case 3: 580 strcpy(fp->name, AudioEslinear); 581 fp->encoding = AUDIO_ENCODING_SLINEAR; 582 fp->precision = 8; 583 fp->flags = 0; 584 break; 585 case 4: 586 strcpy(fp->name, AudioEslinear_le); 587 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 588 fp->precision = 16; 589 fp->flags = 0; 590 break; 591 case 5: 592 strcpy(fp->name, AudioEulinear_le); 593 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 594 fp->precision = 16; 595 fp->flags = 0; 596 break; 597 case 6: 598 strcpy(fp->name, AudioEslinear_be); 599 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 600 fp->precision = 16; 601 fp->flags = 0; 602 break; 603 case 7: 604 strcpy(fp->name, AudioEulinear_be); 605 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 606 fp->precision = 16; 607 fp->flags = 0; 608 break; 609 default: 610 return EINVAL; 611 } 612 return 0; 613 } 614 615 static int 616 cs4280_set_params(void *addr, int setmode, int usemode, 617 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 618 stream_filter_list_t *rfil) 619 { 620 audio_params_t hw; 621 struct cs428x_softc *sc; 622 struct audio_params *p; 623 stream_filter_list_t *fil; 624 int mode; 625 626 sc = addr; 627 for (mode = AUMODE_RECORD; mode != -1; 628 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 629 if ((setmode & mode) == 0) 630 continue; 631 632 p = mode == AUMODE_PLAY ? play : rec; 633 634 if (p == play) { 635 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 636 p->sample_rate, p->precision, p->channels)); 637 /* play back data format may be 8- or 16-bit and 638 * either stereo or mono. 639 * playback rate may range from 8000Hz to 48000Hz 640 */ 641 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 642 (p->precision != 8 && p->precision != 16) || 643 (p->channels != 1 && p->channels != 2) ) { 644 return EINVAL; 645 } 646 } else { 647 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 648 p->sample_rate, p->precision, p->channels)); 649 /* capture data format must be 16bit stereo 650 * and sample rate range from 11025Hz to 48000Hz. 651 * 652 * XXX: it looks like to work with 8000Hz, 653 * although data sheets say lower limit is 654 * 11025 Hz. 655 */ 656 657 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 658 (p->precision != 8 && p->precision != 16) || 659 (p->channels != 1 && p->channels != 2) ) { 660 return EINVAL; 661 } 662 } 663 fil = mode == AUMODE_PLAY ? pfil : rfil; 664 hw = *p; 665 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 666 667 /* capturing data is slinear */ 668 switch (p->encoding) { 669 case AUDIO_ENCODING_SLINEAR_BE: 670 if (mode == AUMODE_RECORD && p->precision == 16) { 671 fil->append(fil, swap_bytes, &hw); 672 } 673 break; 674 case AUDIO_ENCODING_SLINEAR_LE: 675 break; 676 case AUDIO_ENCODING_ULINEAR_BE: 677 if (mode == AUMODE_RECORD) { 678 fil->append(fil, p->precision == 16 679 ? swap_bytes_change_sign16 680 : change_sign8, &hw); 681 } 682 break; 683 case AUDIO_ENCODING_ULINEAR_LE: 684 if (mode == AUMODE_RECORD) { 685 fil->append(fil, p->precision == 16 686 ? change_sign16 : change_sign8, 687 &hw); 688 } 689 break; 690 case AUDIO_ENCODING_ULAW: 691 if (mode == AUMODE_PLAY) { 692 hw.precision = 16; 693 hw.validbits = 16; 694 fil->append(fil, mulaw_to_linear16, &hw); 695 } else { 696 fil->append(fil, linear8_to_mulaw, &hw); 697 } 698 break; 699 case AUDIO_ENCODING_ALAW: 700 if (mode == AUMODE_PLAY) { 701 hw.precision = 16; 702 hw.validbits = 16; 703 fil->append(fil, alaw_to_linear16, &hw); 704 } else { 705 fil->append(fil, linear8_to_alaw, &hw); 706 } 707 break; 708 default: 709 return EINVAL; 710 } 711 } 712 713 /* set sample rate */ 714 cs4280_set_dac_rate(sc, play->sample_rate); 715 cs4280_set_adc_rate(sc, rec->sample_rate); 716 return 0; 717 } 718 719 static int 720 cs4280_halt_output(void *addr) 721 { 722 struct cs428x_softc *sc; 723 uint32_t mem; 724 725 sc = addr; 726 mem = BA1READ4(sc, CS4280_PCTL); 727 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 728 sc->sc_prun = 0; 729 cs4280_clkrun_hack(sc, -1); 730 731 return 0; 732 } 733 734 static int 735 cs4280_halt_input(void *addr) 736 { 737 struct cs428x_softc *sc; 738 uint32_t mem; 739 740 sc = addr; 741 mem = BA1READ4(sc, CS4280_CCTL); 742 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 743 sc->sc_rrun = 0; 744 cs4280_clkrun_hack(sc, -1); 745 746 return 0; 747 } 748 749 static int 750 cs4280_getdev(void *addr, struct audio_device *retp) 751 { 752 753 *retp = cs4280_device; 754 return 0; 755 } 756 757 static int 758 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 759 void (*intr)(void *), void *arg, 760 const audio_params_t *param) 761 { 762 struct cs428x_softc *sc; 763 uint32_t pfie, pctl, pdtc; 764 struct cs428x_dma *p; 765 766 sc = addr; 767 #ifdef DIAGNOSTIC 768 if (sc->sc_prun) 769 printf("cs4280_trigger_output: already running\n"); 770 #endif 771 sc->sc_prun = 1; 772 cs4280_clkrun_hack(sc, 1); 773 774 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 775 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 776 sc->sc_pintr = intr; 777 sc->sc_parg = arg; 778 779 /* stop playback DMA */ 780 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 781 782 /* setup PDTC */ 783 pdtc = BA1READ4(sc, CS4280_PDTC); 784 pdtc &= ~PDTC_MASK; 785 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 786 BA1WRITE4(sc, CS4280_PDTC, pdtc); 787 788 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 789 param->precision, param->channels, param->encoding)); 790 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 791 continue; 792 if (p == NULL) { 793 printf("cs4280_trigger_output: bad addr %p\n", start); 794 return EINVAL; 795 } 796 if (DMAADDR(p) % sc->dma_align != 0 ) { 797 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 798 "4kB align\n", (ulong)DMAADDR(p)); 799 return EINVAL; 800 } 801 802 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 803 sc->sc_ps = (char *)start; 804 sc->sc_pe = (char *)end; 805 sc->sc_pdma = p; 806 sc->sc_pbuf = KERNADDR(p); 807 sc->sc_pi = 0; 808 sc->sc_pn = sc->sc_ps; 809 if (blksize >= sc->dma_size) { 810 sc->sc_pn = sc->sc_ps + sc->dma_size; 811 memcpy(sc->sc_pbuf, start, sc->dma_size); 812 ++sc->sc_pi; 813 } else { 814 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 815 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 816 } 817 818 /* initiate playback DMA */ 819 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 820 821 /* set PFIE */ 822 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 823 824 if (param->precision == 8) 825 pfie |= PFIE_8BIT; 826 if (param->channels == 1) 827 pfie |= PFIE_MONO; 828 829 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 830 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 831 pfie |= PFIE_SWAPPED; 832 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 833 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 834 pfie |= PFIE_UNSIGNED; 835 836 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 837 838 sc->sc_prate = param->sample_rate; 839 cs4280_set_dac_rate(sc, param->sample_rate); 840 841 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 842 pctl |= sc->pctl; 843 BA1WRITE4(sc, CS4280_PCTL, pctl); 844 return 0; 845 } 846 847 static int 848 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 849 void (*intr)(void *), void *arg, 850 const audio_params_t *param) 851 { 852 struct cs428x_softc *sc; 853 uint32_t cctl, cie; 854 struct cs428x_dma *p; 855 856 sc = addr; 857 #ifdef DIAGNOSTIC 858 if (sc->sc_rrun) 859 printf("cs4280_trigger_input: already running\n"); 860 #endif 861 sc->sc_rrun = 1; 862 cs4280_clkrun_hack(sc, 1); 863 864 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 865 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 866 sc->sc_rintr = intr; 867 sc->sc_rarg = arg; 868 869 /* stop capture DMA */ 870 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 871 872 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 873 continue; 874 if (p == NULL) { 875 printf("cs4280_trigger_input: bad addr %p\n", start); 876 return EINVAL; 877 } 878 if (DMAADDR(p) % sc->dma_align != 0) { 879 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 880 "4kB align\n", (ulong)DMAADDR(p)); 881 return EINVAL; 882 } 883 884 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 885 sc->sc_rs = (char *)start; 886 sc->sc_re = (char *)end; 887 sc->sc_rdma = p; 888 sc->sc_rbuf = KERNADDR(p); 889 sc->sc_ri = 0; 890 sc->sc_rn = sc->sc_rs; 891 892 /* initiate capture DMA */ 893 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 894 895 /* setup format information for internal converter */ 896 sc->sc_rparam = 0; 897 if (param->precision == 8) { 898 sc->sc_rparam += CF_8BIT; 899 sc->sc_rcount <<= 1; 900 } 901 if (param->channels == 1) { 902 sc->sc_rparam += CF_MONO; 903 sc->sc_rcount <<= 1; 904 } 905 906 /* set CIE */ 907 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 908 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 909 910 sc->sc_rrate = param->sample_rate; 911 cs4280_set_adc_rate(sc, param->sample_rate); 912 913 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 914 cctl |= sc->cctl; 915 BA1WRITE4(sc, CS4280_CCTL, cctl); 916 return 0; 917 } 918 919 static void 920 cs4280_suspend(device_t dv) 921 { 922 struct cs428x_softc *sc = device_private(dv); 923 924 if (sc->sc_prun) { 925 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 926 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 927 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 928 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 929 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 930 sc->sc_suspend_state.cs4280.pctl, 931 sc->sc_suspend_state.cs4280.pfie, 932 sc->sc_suspend_state.cs4280.pba, 933 sc->sc_suspend_state.cs4280.pdtc)); 934 } 935 936 /* save current capture status */ 937 if (sc->sc_rrun) { 938 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 939 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 940 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 941 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 942 sc->sc_suspend_state.cs4280.cctl, 943 sc->sc_suspend_state.cs4280.cie, 944 sc->sc_suspend_state.cs4280.cba)); 945 } 946 947 /* Stop DMA */ 948 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 949 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 950 } 951 952 static void 953 cs4280_resume(device_t dv) 954 { 955 struct cs428x_softc *sc = device_private(dv); 956 957 cs4280_init(sc, 0); 958 #if 0 959 cs4280_reset_codec(sc); 960 #endif 961 /* restore ac97 registers */ 962 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 963 964 /* restore DMA related status */ 965 if(sc->sc_prun) { 966 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 967 sc->sc_suspend_state.cs4280.pctl, 968 sc->sc_suspend_state.cs4280.pfie, 969 sc->sc_suspend_state.cs4280.pba, 970 sc->sc_suspend_state.cs4280.pdtc)); 971 cs4280_set_dac_rate(sc, sc->sc_prate); 972 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 973 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 974 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 975 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 976 } 977 978 if (sc->sc_rrun) { 979 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 980 sc->sc_suspend_state.cs4280.cctl, 981 sc->sc_suspend_state.cs4280.cie, 982 sc->sc_suspend_state.cs4280.cba)); 983 cs4280_set_adc_rate(sc, sc->sc_rrate); 984 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 985 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 986 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 987 } 988 } 989 990 static int 991 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 992 { 993 struct cs428x_softc *sc = addr; 994 int rv; 995 996 cs4280_clkrun_hack(sc, 1); 997 rv = cs428x_read_codec(addr, reg, result); 998 cs4280_clkrun_hack(sc, -1); 999 1000 return rv; 1001 } 1002 1003 static int 1004 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1005 { 1006 struct cs428x_softc *sc = addr; 1007 int rv; 1008 1009 cs4280_clkrun_hack(sc, 1); 1010 rv = cs428x_write_codec(addr, reg, data); 1011 cs4280_clkrun_hack(sc, -1); 1012 1013 return rv; 1014 } 1015 1016 #if 0 /* XXX buggy and not required */ 1017 /* control AC97 codec */ 1018 static int 1019 cs4280_reset_codec(void *addr) 1020 { 1021 struct cs428x_softc *sc; 1022 int n; 1023 1024 sc = addr; 1025 1026 /* Reset codec */ 1027 BA0WRITE4(sc, CS428X_ACCTL, 0); 1028 delay(100); /* delay 100us */ 1029 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1030 1031 /* 1032 * It looks like we do the following procedure, too 1033 */ 1034 1035 /* Enable AC-link sync generation */ 1036 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1037 delay(50*1000); /* XXX delay 50ms */ 1038 1039 /* Assert valid frame signal */ 1040 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1041 1042 /* Wait for valid AC97 input slot */ 1043 n = 0; 1044 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1045 (ACISV_ISV3 | ACISV_ISV4)) { 1046 delay(1000); 1047 if (++n > 1000) { 1048 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1049 return ETIMEDOUT; 1050 } 1051 } 1052 1053 return 0; 1054 } 1055 #endif 1056 1057 static enum ac97_host_flags cs4280_flags_codec(void *addr) 1058 { 1059 struct cs428x_softc *sc; 1060 1061 sc = addr; 1062 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1063 return AC97_HOST_INVERTED_EAMP; 1064 1065 return 0; 1066 } 1067 1068 /* Internal functions */ 1069 1070 static const struct cs4280_card_t * 1071 cs4280_identify_card(struct pci_attach_args *pa) 1072 { 1073 pcireg_t idreg; 1074 u_int16_t i; 1075 1076 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1077 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1078 if (idreg == cs4280_cards[i].id) 1079 return &cs4280_cards[i]; 1080 } 1081 1082 return NULL; 1083 } 1084 1085 static int 1086 cs4280_piix4_match(struct pci_attach_args *pa) 1087 { 1088 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1089 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1090 return 1; 1091 } 1092 1093 return 0; 1094 } 1095 1096 static void 1097 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1098 { 1099 uint16_t control, val; 1100 1101 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1102 return; 1103 1104 sc->sc_active += change; 1105 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1106 if (!sc->sc_active) 1107 val |= 0x2000; 1108 else 1109 val &= ~0x2000; 1110 if (val != control) 1111 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1112 } 1113 1114 static void 1115 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1116 { 1117 struct pci_attach_args smbuspa; 1118 uint16_t reg; 1119 pcireg_t port; 1120 1121 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1122 return; 1123 1124 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1125 sc->sc_active = 0; 1126 printf("%s: enabling CLKRUN hack\n", 1127 sc->sc_dev.dv_xname); 1128 1129 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1130 port = reg & 0xffc0; 1131 printf("%s: power management port 0x%x\n", sc->sc_dev.dv_xname, 1132 port); 1133 1134 sc->sc_pm_iot = smbuspa.pa_iot; 1135 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1136 &sc->sc_pm_ioh) == 0) 1137 return; 1138 } 1139 1140 /* handle error */ 1141 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1142 printf("%s: disabling CLKRUN hack\n", sc->sc_dev.dv_xname); 1143 } 1144 1145 static void 1146 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1147 { 1148 /* calculate capture rate: 1149 * 1150 * capture_coefficient_increment = -round(rate*128*65536/48000; 1151 * capture_phase_increment = floor(48000*65536*1024/rate); 1152 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1153 * cy = floor(cx/200); 1154 * capture_sample_rate_correction = cx - 200*cy; 1155 * capture_delay = ceil(24*48000/rate); 1156 * capture_num_triplets = floor(65536*rate/24000); 1157 * capture_group_length = 24000/GCD(rate, 24000); 1158 * where GCD means "Greatest Common Divisor". 1159 * 1160 * capture_coefficient_increment, capture_phase_increment and 1161 * capture_num_triplets are 32-bit signed quantities. 1162 * capture_sample_rate_correction and capture_group_length are 1163 * 16-bit signed quantities. 1164 * capture_delay is a 14-bit unsigned quantity. 1165 */ 1166 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1167 uint16_t csrc, cgl, cdlay; 1168 1169 /* XXX 1170 * Even though, embedded_audio_spec says capture rate range 11025 to 1171 * 48000, dhwiface.cpp says, 1172 * 1173 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1174 * Return an error if an attempt is made to stray outside that limit." 1175 * 1176 * so assume range as 48000/9 to 48000 1177 */ 1178 1179 if (rate < 8000) 1180 rate = 8000; 1181 if (rate > 48000) 1182 rate = 48000; 1183 1184 cx = rate << 16; 1185 cci = cx / 48000; 1186 cx -= cci * 48000; 1187 cx <<= 7; 1188 cci <<= 7; 1189 cci += cx / 48000; 1190 cci = - cci; 1191 1192 cx = 48000 << 16; 1193 cpi = cx / rate; 1194 cx -= cpi * rate; 1195 cx <<= 10; 1196 cpi <<= 10; 1197 cy = cx / rate; 1198 cpi += cy; 1199 cx -= cy * rate; 1200 1201 cy = cx / 200; 1202 csrc = cx - 200*cy; 1203 1204 cdlay = ((48000 * 24) + rate - 1) / rate; 1205 #if 0 1206 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1207 #endif 1208 1209 cnt = rate << 16; 1210 cnt /= 24000; 1211 1212 cgl = 1; 1213 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1214 if (((rate / tmp1) * tmp1) != rate) 1215 cgl *= 2; 1216 } 1217 if (((rate / 3) * 3) != rate) 1218 cgl *= 3; 1219 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1220 if (((rate / tmp1) * tmp1) != rate) 1221 cgl *= 5; 1222 } 1223 #if 0 1224 /* XXX what manual says */ 1225 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1226 tmp1 |= csrc<<16; 1227 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1228 #else 1229 /* suggested by cs461x.c (ALSA driver) */ 1230 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1231 #endif 1232 1233 #if 0 1234 /* I am confused. The sample rate calculation section says 1235 * cci *is* 32-bit signed quantity but in the parameter description 1236 * section, CCI only assigned 16bit. 1237 * I believe size of the variable. 1238 */ 1239 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1240 tmp1 |= cci<<16; 1241 BA1WRITE4(sc, CS4280_CCI, tmp1); 1242 #else 1243 BA1WRITE4(sc, CS4280_CCI, cci); 1244 #endif 1245 1246 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1247 tmp1 |= cdlay <<18; 1248 BA1WRITE4(sc, CS4280_CD, tmp1); 1249 1250 BA1WRITE4(sc, CS4280_CPI, cpi); 1251 1252 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1253 tmp1 |= cgl; 1254 BA1WRITE4(sc, CS4280_CGL, tmp1); 1255 1256 BA1WRITE4(sc, CS4280_CNT, cnt); 1257 1258 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1259 tmp1 |= cgl; 1260 BA1WRITE4(sc, CS4280_CGC, tmp1); 1261 } 1262 1263 static void 1264 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1265 { 1266 /* 1267 * playback rate may range from 8000Hz to 48000Hz 1268 * 1269 * play_phase_increment = floor(rate*65536*1024/48000) 1270 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1271 * py=floor(px/200) 1272 * play_sample_rate_correction = px - 200*py 1273 * 1274 * play_phase_increment is a 32bit signed quantity. 1275 * play_sample_rate_correction is a 16bit signed quantity. 1276 */ 1277 int32_t ppi; 1278 int16_t psrc; 1279 uint32_t px, py; 1280 1281 if (rate < 8000) 1282 rate = 8000; 1283 if (rate > 48000) 1284 rate = 48000; 1285 px = rate << 16; 1286 ppi = px/48000; 1287 px -= ppi*48000; 1288 ppi <<= 10; 1289 px <<= 10; 1290 py = px / 48000; 1291 ppi += py; 1292 px -= py*48000; 1293 py = px/200; 1294 px -= py*200; 1295 psrc = px; 1296 #if 0 1297 /* what manual says */ 1298 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1299 BA1WRITE4(sc, CS4280_PSRC, 1300 ( ((psrc<<16) & PSRC_MASK) | px )); 1301 #else 1302 /* suggested by cs461x.c (ALSA driver) */ 1303 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1304 #endif 1305 BA1WRITE4(sc, CS4280_PPI, ppi); 1306 } 1307 1308 /* Download Processor Code and Data image */ 1309 static int 1310 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1311 uint32_t offset, uint32_t len) 1312 { 1313 uint32_t ctr; 1314 #if CS4280_DEBUG > 10 1315 uint32_t con, data; 1316 uint8_t c0, c1, c2, c3; 1317 #endif 1318 if ((offset & 3) || (len & 3)) 1319 return -1; 1320 1321 len /= sizeof(uint32_t); 1322 for (ctr = 0; ctr < len; ctr++) { 1323 /* XXX: 1324 * I cannot confirm this is the right thing or not 1325 * on BIG-ENDIAN machines. 1326 */ 1327 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1328 #if CS4280_DEBUG > 10 1329 data = htole32(*(src+ctr)); 1330 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1331 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1332 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1333 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1334 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1335 if (data != con ) { 1336 printf("0x%06x: write=0x%08x read=0x%08x\n", 1337 offset+ctr*4, data, con); 1338 return -1; 1339 } 1340 #endif 1341 } 1342 return 0; 1343 } 1344 1345 static int 1346 cs4280_download_image(struct cs428x_softc *sc) 1347 { 1348 int idx, err; 1349 uint32_t offset = 0; 1350 1351 err = 0; 1352 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1353 err = cs4280_download(sc, &BA1Struct.map[offset], 1354 BA1Struct.memory[idx].offset, 1355 BA1Struct.memory[idx].size); 1356 if (err != 0) { 1357 printf("%s: load_image failed at %d\n", 1358 sc->sc_dev.dv_xname, idx); 1359 return -1; 1360 } 1361 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1362 } 1363 return err; 1364 } 1365 1366 /* Processor Soft Reset */ 1367 static void 1368 cs4280_reset(void *sc_) 1369 { 1370 struct cs428x_softc *sc; 1371 1372 sc = sc_; 1373 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1374 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1375 delay(100); 1376 /* Clear RSTSP bit in SPCR */ 1377 BA1WRITE4(sc, CS4280_SPCR, 0); 1378 /* enable DMA reqest */ 1379 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1380 } 1381 1382 static int 1383 cs4280_init(struct cs428x_softc *sc, int init) 1384 { 1385 int n; 1386 uint32_t mem; 1387 int rv; 1388 1389 rv = 1; 1390 cs4280_clkrun_hack(sc, 1); 1391 1392 /* Start PLL out in known state */ 1393 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1394 /* Start serial ports out in known state */ 1395 BA0WRITE4(sc, CS4280_SERMC1, 0); 1396 1397 /* Specify type of CODEC */ 1398 /* XXX should not be here */ 1399 #define SERACC_CODEC_TYPE_1_03 1400 #ifdef SERACC_CODEC_TYPE_1_03 1401 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1402 #else 1403 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1404 #endif 1405 1406 /* Reset codec */ 1407 BA0WRITE4(sc, CS428X_ACCTL, 0); 1408 delay(100); /* delay 100us */ 1409 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1410 1411 /* Enable AC-link sync generation */ 1412 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1413 delay(50*1000); /* delay 50ms */ 1414 1415 /* Set the serial port timing configuration */ 1416 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1417 1418 /* Setup clock control */ 1419 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1420 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1421 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1422 1423 /* Power up the PLL */ 1424 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1425 delay(50*1000); /* delay 50ms */ 1426 1427 /* Turn on clock */ 1428 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1429 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1430 1431 /* Set the serial port FIFO pointer to the 1432 * first sample in FIFO. (not documented) */ 1433 cs4280_clear_fifos(sc); 1434 1435 #if 0 1436 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1437 BA0WRITE4(sc, CS4280_SERBSP, 0); 1438 #endif 1439 1440 /* Configure the serial port */ 1441 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1442 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1443 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1444 1445 /* Wait for CODEC ready */ 1446 n = 0; 1447 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1448 delay(125); 1449 if (++n > 1000) { 1450 printf("%s: codec ready timeout\n", 1451 sc->sc_dev.dv_xname); 1452 goto exit; 1453 } 1454 } 1455 1456 /* Assert valid frame signal */ 1457 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1458 1459 /* Wait for valid AC97 input slot */ 1460 n = 0; 1461 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1462 (ACISV_ISV3 | ACISV_ISV4)) { 1463 delay(1000); 1464 if (++n > 1000) { 1465 printf("AC97 inputs slot ready timeout\n"); 1466 goto exit; 1467 } 1468 } 1469 1470 /* Set AC97 output slot valid signals */ 1471 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1472 1473 /* reset the processor */ 1474 cs4280_reset(sc); 1475 1476 /* Download the image to the processor */ 1477 if (cs4280_download_image(sc) != 0) { 1478 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1479 goto exit; 1480 } 1481 1482 /* Save playback parameter and then write zero. 1483 * this ensures that DMA doesn't immediately occur upon 1484 * starting the processor core 1485 */ 1486 mem = BA1READ4(sc, CS4280_PCTL); 1487 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1488 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1489 if (init != 0) 1490 sc->sc_prun = 0; 1491 1492 /* Save capture parameter and then write zero. 1493 * this ensures that DMA doesn't immediately occur upon 1494 * starting the processor core 1495 */ 1496 mem = BA1READ4(sc, CS4280_CCTL); 1497 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1498 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1499 if (init != 0) 1500 sc->sc_rrun = 0; 1501 1502 /* Processor Startup Procedure */ 1503 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1504 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1505 1506 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1507 n = 0; 1508 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1509 delay(10); 1510 if (++n > 1000) { 1511 printf("SPCR 1->0 transition timeout\n"); 1512 goto exit; 1513 } 1514 } 1515 1516 n = 0; 1517 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1518 delay(10); 1519 if (++n > 1000) { 1520 printf("SPCS 0->1 transition timeout\n"); 1521 goto exit; 1522 } 1523 } 1524 /* Processor is now running !!! */ 1525 1526 /* Setup volume */ 1527 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1528 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1529 1530 /* Interrupt enable */ 1531 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1532 1533 /* playback interrupt enable */ 1534 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1535 mem |= PFIE_PI_ENABLE; 1536 BA1WRITE4(sc, CS4280_PFIE, mem); 1537 /* capture interrupt enable */ 1538 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1539 mem |= CIE_CI_ENABLE; 1540 BA1WRITE4(sc, CS4280_CIE, mem); 1541 1542 #if NMIDI > 0 1543 /* Reset midi port */ 1544 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1545 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1546 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1547 /* midi interrupt enable */ 1548 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1549 BA0WRITE4(sc, CS4280_MIDCR, mem); 1550 #endif 1551 1552 rv = 0; 1553 1554 exit: 1555 cs4280_clkrun_hack(sc, -1); 1556 return rv; 1557 } 1558 1559 static void 1560 cs4280_clear_fifos(struct cs428x_softc *sc) 1561 { 1562 int pd, cnt, n; 1563 uint32_t mem; 1564 1565 pd = 0; 1566 /* 1567 * If device power down, power up the device and keep power down 1568 * state. 1569 */ 1570 mem = BA0READ4(sc, CS4280_CLKCR1); 1571 if (!(mem & CLKCR1_SWCE)) { 1572 printf("cs4280_clear_fifo: power down found.\n"); 1573 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1574 pd = 1; 1575 } 1576 BA0WRITE4(sc, CS4280_SERBWP, 0); 1577 for (cnt = 0; cnt < 256; cnt++) { 1578 n = 0; 1579 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1580 delay(1000); 1581 if (++n > 1000) { 1582 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1583 break; 1584 } 1585 } 1586 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1587 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1588 } 1589 if (pd) 1590 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1591 } 1592 1593 #if NMIDI > 0 1594 static int 1595 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1596 void (*ointr)(void *), void *arg) 1597 { 1598 struct cs428x_softc *sc; 1599 uint32_t mem; 1600 1601 DPRINTF(("midi_open\n")); 1602 sc = addr; 1603 sc->sc_iintr = iintr; 1604 sc->sc_ointr = ointr; 1605 sc->sc_arg = arg; 1606 1607 /* midi interrupt enable */ 1608 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1609 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1610 BA0WRITE4(sc, CS4280_MIDCR, mem); 1611 #ifdef CS4280_DEBUG 1612 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1613 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1614 return(EINVAL); 1615 } 1616 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1617 #endif 1618 return 0; 1619 } 1620 1621 static void 1622 cs4280_midi_close(void *addr) 1623 { 1624 struct cs428x_softc *sc; 1625 uint32_t mem; 1626 1627 DPRINTF(("midi_close\n")); 1628 sc = addr; 1629 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1630 mem = BA0READ4(sc, CS4280_MIDCR); 1631 mem &= ~MIDCR_MASK; 1632 BA0WRITE4(sc, CS4280_MIDCR, mem); 1633 1634 sc->sc_iintr = 0; 1635 sc->sc_ointr = 0; 1636 } 1637 1638 static int 1639 cs4280_midi_output(void *addr, int d) 1640 { 1641 struct cs428x_softc *sc; 1642 uint32_t mem; 1643 int x; 1644 1645 sc = addr; 1646 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1647 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1648 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1649 mem |= d & MIDWP_MASK; 1650 DPRINTFN(5,("midi_output d=0x%08x",d)); 1651 BA0WRITE4(sc, CS4280_MIDWP, mem); 1652 #ifdef DIAGNOSTIC 1653 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1654 DPRINTF(("Bad write data: %d %d", 1655 mem, BA0READ4(sc, CS4280_MIDWP))); 1656 return EIO; 1657 } 1658 #endif 1659 return 0; 1660 } 1661 delay(MIDI_BUSY_DELAY); 1662 } 1663 return EIO; 1664 } 1665 1666 static void 1667 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1668 { 1669 1670 mi->name = "CS4280 MIDI UART"; 1671 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1672 } 1673 1674 #endif /* NMIDI */ 1675 1676 /* DEBUG functions */ 1677 #if CS4280_DEBUG > 10 1678 static int 1679 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1680 uint32_t offset, uint32_t len) 1681 { 1682 uint32_t ctr, data; 1683 int err; 1684 1685 if ((offset & 3) || (len & 3)) 1686 return -1; 1687 1688 err = 0; 1689 len /= sizeof(uint32_t); 1690 for (ctr = 0; ctr < len; ctr++) { 1691 /* I cannot confirm this is the right thing 1692 * on BIG-ENDIAN machines 1693 */ 1694 data = BA1READ4(sc, offset+ctr*4); 1695 if (data != htole32(*(src+ctr))) { 1696 printf("0x%06x: 0x%08x(0x%08x)\n", 1697 offset+ctr*4, data, *(src+ctr)); 1698 *(src+ctr) = data; 1699 ++err; 1700 } 1701 } 1702 return err; 1703 } 1704 1705 static int 1706 cs4280_check_images(struct cs428x_softc *sc) 1707 { 1708 int idx, err; 1709 uint32_t offset; 1710 1711 offset = 0; 1712 err = 0; 1713 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1714 for (idx = 0; idx < 1; ++idx) { 1715 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1716 BA1Struct.memory[idx].offset, 1717 BA1Struct.memory[idx].size); 1718 if (err != 0) { 1719 printf("%s: check_image failed at %d\n", 1720 sc->sc_dev.dv_xname, idx); 1721 } 1722 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1723 } 1724 return err; 1725 } 1726 1727 #endif /* CS4280_DEBUG */ 1728
Indexes created Thu Oct 02 14:10:14 GMT 2025