cs4280.c revision 1.46.6.3
1 /* $NetBSD: cs4280.c,v 1.46.6.3 2007/11/06 14:27:22 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.46.6.3 2007/11/06 14:27:22 joerg Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <sys/bus.h> 86 #include <sys/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(struct device *, struct cfdata *, void *); 93 static void cs4280_attach(struct device *, struct device *, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 107 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 108 #if 0 109 static int cs4280_reset_codec(void *); 110 #endif 111 static enum ac97_host_flags cs4280_flags_codec(void *); 112 113 static bool cs4280_resume(device_t); 114 static bool cs4280_suspend(device_t); 115 116 /* Internal functions */ 117 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *); 118 static int cs4280_piix4_match(struct pci_attach_args *); 119 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 120 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 121 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 122 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 123 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 124 uint32_t); 125 static int cs4280_download_image(struct cs428x_softc *); 126 static void cs4280_reset(void *); 127 static int cs4280_init(struct cs428x_softc *, int); 128 static void cs4280_clear_fifos(struct cs428x_softc *); 129 130 #if CS4280_DEBUG > 10 131 /* Thease two function is only for checking image loading is succeeded or not. */ 132 static int cs4280_check_images(struct cs428x_softc *); 133 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 134 uint32_t); 135 #endif 136 137 /* Special cards */ 138 struct cs4280_card_t 139 { 140 pcireg_t id; 141 enum cs428x_flags flags; 142 }; 143 144 #define _card(vend, prod, flags) \ 145 {PCI_ID_CODE(vend, prod), flags} 146 147 static const struct cs4280_card_t cs4280_cards[] = { 148 #if 0 /* untested, from ALSA driver */ 149 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 150 CS428X_FLAG_INVAC97EAMP), 151 #endif 152 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 153 CS428X_FLAG_INVAC97EAMP), 154 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 155 CS428X_FLAG_CLKRUNHACK) 156 }; 157 158 #undef _card 159 160 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 161 162 static const struct audio_hw_if cs4280_hw_if = { 163 NULL, /* open */ 164 NULL, /* close */ 165 NULL, 166 cs4280_query_encoding, 167 cs4280_set_params, 168 cs428x_round_blocksize, 169 NULL, 170 NULL, 171 NULL, 172 NULL, 173 NULL, 174 cs4280_halt_output, 175 cs4280_halt_input, 176 NULL, 177 cs4280_getdev, 178 NULL, 179 cs428x_mixer_set_port, 180 cs428x_mixer_get_port, 181 cs428x_query_devinfo, 182 cs428x_malloc, 183 cs428x_free, 184 cs428x_round_buffersize, 185 cs428x_mappage, 186 cs428x_get_props, 187 cs4280_trigger_output, 188 cs4280_trigger_input, 189 NULL, 190 NULL, 191 }; 192 193 #if NMIDI > 0 194 /* Midi Interface */ 195 static int cs4280_midi_open(void *, int, void (*)(void *, int), 196 void (*)(void *), void *); 197 static void cs4280_midi_close(void*); 198 static int cs4280_midi_output(void *, int); 199 static void cs4280_midi_getinfo(void *, struct midi_info *); 200 201 static const struct midi_hw_if cs4280_midi_hw_if = { 202 cs4280_midi_open, 203 cs4280_midi_close, 204 cs4280_midi_output, 205 cs4280_midi_getinfo, 206 0, 207 }; 208 #endif 209 210 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 211 cs4280_match, cs4280_attach, NULL, NULL); 212 213 static struct audio_device cs4280_device = { 214 "CS4280", 215 "", 216 "cs4280" 217 }; 218 219 220 static int 221 cs4280_match(struct device *parent, struct cfdata *match, 222 void *aux) 223 { 224 struct pci_attach_args *pa; 225 226 pa = (struct pci_attach_args *)aux; 227 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 228 return 0; 229 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 230 #if 0 /* I can't confirm */ 231 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 232 #endif 233 ) 234 return 1; 235 return 0; 236 } 237 238 static void 239 cs4280_attach(struct device *parent, struct device *self, void *aux) 240 { 241 struct cs428x_softc *sc; 242 struct pci_attach_args *pa; 243 pci_chipset_tag_t pc; 244 const struct cs4280_card_t *cs_card; 245 char const *intrstr; 246 pcireg_t reg; 247 char devinfo[256]; 248 uint32_t mem; 249 int error; 250 251 sc = (struct cs428x_softc *)self; 252 pa = (struct pci_attach_args *)aux; 253 pc = pa->pa_pc; 254 aprint_naive(": Audio controller\n"); 255 256 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 257 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 258 PCI_REVISION(pa->pa_class)); 259 260 cs_card = cs4280_identify_card(pa); 261 if (cs_card != NULL) { 262 aprint_normal("%s: %s %s\n",sc->sc_dev.dv_xname, 263 pci_findvendor(cs_card->id), 264 pci_findproduct(cs_card->id)); 265 sc->sc_flags = cs_card->flags; 266 } else { 267 sc->sc_flags = CS428X_FLAG_NONE; 268 } 269 270 sc->sc_pc = pa->pa_pc; 271 sc->sc_pt = pa->pa_tag; 272 273 /* Map I/O register */ 274 if (pci_mapreg_map(pa, PCI_BA0, 275 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 276 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 277 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 278 return; 279 } 280 if (pci_mapreg_map(pa, PCI_BA1, 281 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 282 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 283 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 284 return; 285 } 286 287 sc->sc_dmatag = pa->pa_dmat; 288 289 /* power up chip */ 290 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 291 pci_activate_null)) && error != EOPNOTSUPP) { 292 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 293 error); 294 return; 295 } 296 297 /* Enable the device (set bus master flag) */ 298 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 299 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 300 reg | PCI_COMMAND_MASTER_ENABLE); 301 302 /* LATENCY_TIMER setting */ 303 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 304 if ( PCI_LATTIMER(mem) < 32 ) { 305 mem &= 0xffff00ff; 306 mem |= 0x00002000; 307 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 308 } 309 310 /* CLKRUN hack initialization */ 311 cs4280_clkrun_hack_init(sc); 312 313 /* Map and establish the interrupt. */ 314 if (pci_intr_map(pa, &sc->intrh)) { 315 aprint_error("%s: couldn't map interrupt\n", 316 sc->sc_dev.dv_xname); 317 return; 318 } 319 intrstr = pci_intr_string(pc, sc->intrh); 320 321 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 322 cs4280_intr, sc); 323 if (sc->sc_ih == NULL) { 324 aprint_error("%s: couldn't establish interrupt", 325 sc->sc_dev.dv_xname); 326 if (intrstr != NULL) 327 aprint_normal(" at %s", intrstr); 328 aprint_normal("\n"); 329 return; 330 } 331 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 332 333 /* Initialization */ 334 if(cs4280_init(sc, 1) != 0) 335 return; 336 337 sc->type = TYPE_CS4280; 338 sc->halt_input = cs4280_halt_input; 339 sc->halt_output = cs4280_halt_output; 340 341 /* setup buffer related parameters */ 342 sc->dma_size = CS4280_DCHUNK; 343 sc->dma_align = CS4280_DALIGN; 344 sc->hw_blocksize = CS4280_ICHUNK; 345 346 /* AC 97 attachment */ 347 sc->host_if.arg = sc; 348 sc->host_if.attach = cs428x_attach_codec; 349 sc->host_if.read = cs4280_read_codec; 350 sc->host_if.write = cs4280_write_codec; 351 #if 0 352 sc->host_if.reset = cs4280_reset_codec; 353 #else 354 sc->host_if.reset = NULL; 355 #endif 356 sc->host_if.flags = cs4280_flags_codec; 357 if (ac97_attach(&sc->host_if, self) != 0) { 358 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 359 return; 360 } 361 362 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 363 364 #if NMIDI > 0 365 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 366 #endif 367 368 if (!pnp_device_register(self, cs4280_suspend, cs4280_resume)) 369 aprint_error_dev(self, "couldn't establish power handler\n"); 370 } 371 372 /* Interrupt handling function */ 373 static int 374 cs4280_intr(void *p) 375 { 376 /* 377 * XXX 378 * 379 * Since CS4280 has only 4kB DMA buffer and 380 * interrupt occurs every 2kB block, I create dummy buffer 381 * which returns to audio driver and actual DMA buffer 382 * using in DMA transfer. 383 * 384 * 385 * ring buffer in audio.c is pointed by BUFADDR 386 * <------ ring buffer size == 64kB ------> 387 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 388 * |= = = =|= = = =|= = = =|= = = =|= = = =| 389 * | | | | | | <- call audio_intp every 390 * sc->sc_[pr]_count time. 391 * 392 * actual DMA buffer is pointed by KERNADDR 393 * <-> DMA buffer size = 4kB 394 * |= =| 395 * 396 * 397 */ 398 struct cs428x_softc *sc; 399 uint32_t intr, mem; 400 char * empty_dma; 401 int handled; 402 403 sc = p; 404 handled = 0; 405 /* grab interrupt register then clear it */ 406 intr = BA0READ4(sc, CS4280_HISR); 407 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 408 409 /* not for us ? */ 410 if ((intr & HISR_INTENA) == 0) 411 return 0; 412 413 /* Playback Interrupt */ 414 if (intr & HISR_PINT) { 415 handled = 1; 416 mem = BA1READ4(sc, CS4280_PFIE); 417 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 418 if (sc->sc_prun) { 419 if ((sc->sc_pi%sc->sc_pcount) == 0) 420 sc->sc_pintr(sc->sc_parg); 421 /* copy buffer */ 422 ++sc->sc_pi; 423 empty_dma = sc->sc_pdma->addr; 424 if (sc->sc_pi&1) 425 empty_dma += sc->hw_blocksize; 426 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 427 sc->sc_pn += sc->hw_blocksize; 428 if (sc->sc_pn >= sc->sc_pe) 429 sc->sc_pn = sc->sc_ps; 430 } else { 431 printf("%s: unexpected play intr\n", 432 sc->sc_dev.dv_xname); 433 } 434 BA1WRITE4(sc, CS4280_PFIE, mem); 435 } 436 /* Capture Interrupt */ 437 if (intr & HISR_CINT) { 438 int i; 439 int16_t rdata; 440 441 handled = 1; 442 mem = BA1READ4(sc, CS4280_CIE); 443 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 444 445 if (sc->sc_rrun) { 446 ++sc->sc_ri; 447 empty_dma = sc->sc_rdma->addr; 448 if ((sc->sc_ri&1) == 0) 449 empty_dma += sc->hw_blocksize; 450 451 /* 452 * XXX 453 * I think this audio data conversion should be 454 * happend in upper layer, but I put this here 455 * since there is no conversion function available. 456 */ 457 switch(sc->sc_rparam) { 458 case CF_16BIT_STEREO: 459 /* just copy it */ 460 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 461 sc->sc_rn += sc->hw_blocksize; 462 break; 463 case CF_16BIT_MONO: 464 for (i = 0; i < 512; i++) { 465 rdata = *((int16_t *)empty_dma)>>1; 466 empty_dma += 2; 467 rdata += *((int16_t *)empty_dma)>>1; 468 empty_dma += 2; 469 *((int16_t *)sc->sc_rn) = rdata; 470 sc->sc_rn += 2; 471 } 472 break; 473 case CF_8BIT_STEREO: 474 for (i = 0; i < 512; i++) { 475 rdata = *((int16_t*)empty_dma); 476 empty_dma += 2; 477 *sc->sc_rn++ = rdata >> 8; 478 rdata = *((int16_t*)empty_dma); 479 empty_dma += 2; 480 *sc->sc_rn++ = rdata >> 8; 481 } 482 break; 483 case CF_8BIT_MONO: 484 for (i = 0; i < 512; i++) { 485 rdata = *((int16_t*)empty_dma) >>1; 486 empty_dma += 2; 487 rdata += *((int16_t*)empty_dma) >>1; 488 empty_dma += 2; 489 *sc->sc_rn++ = rdata >>8; 490 } 491 break; 492 default: 493 /* Should not reach here */ 494 printf("%s: unknown sc->sc_rparam: %d\n", 495 sc->sc_dev.dv_xname, sc->sc_rparam); 496 } 497 if (sc->sc_rn >= sc->sc_re) 498 sc->sc_rn = sc->sc_rs; 499 } 500 BA1WRITE4(sc, CS4280_CIE, mem); 501 502 if (sc->sc_rrun) { 503 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 504 sc->sc_rintr(sc->sc_rarg); 505 } else { 506 printf("%s: unexpected record intr\n", 507 sc->sc_dev.dv_xname); 508 } 509 } 510 511 #if NMIDI > 0 512 /* Midi port Interrupt */ 513 if (intr & HISR_MIDI) { 514 int data; 515 516 handled = 1; 517 DPRINTF(("i: %d: ", 518 BA0READ4(sc, CS4280_MIDSR))); 519 /* Read the received data */ 520 while ((sc->sc_iintr != NULL) && 521 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 522 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 523 DPRINTF(("r:%x\n",data)); 524 sc->sc_iintr(sc->sc_arg, data); 525 } 526 527 /* Write the data */ 528 #if 1 529 /* XXX: 530 * It seems "Transmit Buffer Full" never activate until EOI 531 * is deliverd. Shall I throw EOI top of this routine ? 532 */ 533 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 534 DPRINTF(("w: ")); 535 if (sc->sc_ointr != NULL) 536 sc->sc_ointr(sc->sc_arg); 537 } 538 #else 539 while ((sc->sc_ointr != NULL) && 540 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 541 DPRINTF(("w: ")); 542 sc->sc_ointr(sc->sc_arg); 543 } 544 #endif 545 DPRINTF(("\n")); 546 } 547 #endif 548 549 return handled; 550 } 551 552 static int 553 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 554 { 555 switch (fp->index) { 556 case 0: 557 strcpy(fp->name, AudioEulinear); 558 fp->encoding = AUDIO_ENCODING_ULINEAR; 559 fp->precision = 8; 560 fp->flags = 0; 561 break; 562 case 1: 563 strcpy(fp->name, AudioEmulaw); 564 fp->encoding = AUDIO_ENCODING_ULAW; 565 fp->precision = 8; 566 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 567 break; 568 case 2: 569 strcpy(fp->name, AudioEalaw); 570 fp->encoding = AUDIO_ENCODING_ALAW; 571 fp->precision = 8; 572 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 573 break; 574 case 3: 575 strcpy(fp->name, AudioEslinear); 576 fp->encoding = AUDIO_ENCODING_SLINEAR; 577 fp->precision = 8; 578 fp->flags = 0; 579 break; 580 case 4: 581 strcpy(fp->name, AudioEslinear_le); 582 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 583 fp->precision = 16; 584 fp->flags = 0; 585 break; 586 case 5: 587 strcpy(fp->name, AudioEulinear_le); 588 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 589 fp->precision = 16; 590 fp->flags = 0; 591 break; 592 case 6: 593 strcpy(fp->name, AudioEslinear_be); 594 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 595 fp->precision = 16; 596 fp->flags = 0; 597 break; 598 case 7: 599 strcpy(fp->name, AudioEulinear_be); 600 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 601 fp->precision = 16; 602 fp->flags = 0; 603 break; 604 default: 605 return EINVAL; 606 } 607 return 0; 608 } 609 610 static int 611 cs4280_set_params(void *addr, int setmode, int usemode, 612 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 613 stream_filter_list_t *rfil) 614 { 615 audio_params_t hw; 616 struct cs428x_softc *sc; 617 struct audio_params *p; 618 stream_filter_list_t *fil; 619 int mode; 620 621 sc = addr; 622 for (mode = AUMODE_RECORD; mode != -1; 623 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 624 if ((setmode & mode) == 0) 625 continue; 626 627 p = mode == AUMODE_PLAY ? play : rec; 628 629 if (p == play) { 630 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 631 p->sample_rate, p->precision, p->channels)); 632 /* play back data format may be 8- or 16-bit and 633 * either stereo or mono. 634 * playback rate may range from 8000Hz to 48000Hz 635 */ 636 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 637 (p->precision != 8 && p->precision != 16) || 638 (p->channels != 1 && p->channels != 2) ) { 639 return EINVAL; 640 } 641 } else { 642 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 643 p->sample_rate, p->precision, p->channels)); 644 /* capture data format must be 16bit stereo 645 * and sample rate range from 11025Hz to 48000Hz. 646 * 647 * XXX: it looks like to work with 8000Hz, 648 * although data sheets say lower limit is 649 * 11025 Hz. 650 */ 651 652 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 653 (p->precision != 8 && p->precision != 16) || 654 (p->channels != 1 && p->channels != 2) ) { 655 return EINVAL; 656 } 657 } 658 fil = mode == AUMODE_PLAY ? pfil : rfil; 659 hw = *p; 660 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 661 662 /* capturing data is slinear */ 663 switch (p->encoding) { 664 case AUDIO_ENCODING_SLINEAR_BE: 665 if (mode == AUMODE_RECORD && p->precision == 16) { 666 fil->append(fil, swap_bytes, &hw); 667 } 668 break; 669 case AUDIO_ENCODING_SLINEAR_LE: 670 break; 671 case AUDIO_ENCODING_ULINEAR_BE: 672 if (mode == AUMODE_RECORD) { 673 fil->append(fil, p->precision == 16 674 ? swap_bytes_change_sign16 675 : change_sign8, &hw); 676 } 677 break; 678 case AUDIO_ENCODING_ULINEAR_LE: 679 if (mode == AUMODE_RECORD) { 680 fil->append(fil, p->precision == 16 681 ? change_sign16 : change_sign8, 682 &hw); 683 } 684 break; 685 case AUDIO_ENCODING_ULAW: 686 if (mode == AUMODE_PLAY) { 687 hw.precision = 16; 688 hw.validbits = 16; 689 fil->append(fil, mulaw_to_linear16, &hw); 690 } else { 691 fil->append(fil, linear8_to_mulaw, &hw); 692 } 693 break; 694 case AUDIO_ENCODING_ALAW: 695 if (mode == AUMODE_PLAY) { 696 hw.precision = 16; 697 hw.validbits = 16; 698 fil->append(fil, alaw_to_linear16, &hw); 699 } else { 700 fil->append(fil, linear8_to_alaw, &hw); 701 } 702 break; 703 default: 704 return EINVAL; 705 } 706 } 707 708 /* set sample rate */ 709 cs4280_set_dac_rate(sc, play->sample_rate); 710 cs4280_set_adc_rate(sc, rec->sample_rate); 711 return 0; 712 } 713 714 static int 715 cs4280_halt_output(void *addr) 716 { 717 struct cs428x_softc *sc; 718 uint32_t mem; 719 720 sc = addr; 721 mem = BA1READ4(sc, CS4280_PCTL); 722 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 723 sc->sc_prun = 0; 724 cs4280_clkrun_hack(sc, -1); 725 726 return 0; 727 } 728 729 static int 730 cs4280_halt_input(void *addr) 731 { 732 struct cs428x_softc *sc; 733 uint32_t mem; 734 735 sc = addr; 736 mem = BA1READ4(sc, CS4280_CCTL); 737 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 738 sc->sc_rrun = 0; 739 cs4280_clkrun_hack(sc, -1); 740 741 return 0; 742 } 743 744 static int 745 cs4280_getdev(void *addr, struct audio_device *retp) 746 { 747 748 *retp = cs4280_device; 749 return 0; 750 } 751 752 static int 753 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 754 void (*intr)(void *), void *arg, 755 const audio_params_t *param) 756 { 757 struct cs428x_softc *sc; 758 uint32_t pfie, pctl, pdtc; 759 struct cs428x_dma *p; 760 761 sc = addr; 762 #ifdef DIAGNOSTIC 763 if (sc->sc_prun) 764 printf("cs4280_trigger_output: already running\n"); 765 #endif 766 sc->sc_prun = 1; 767 cs4280_clkrun_hack(sc, 1); 768 769 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 770 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 771 sc->sc_pintr = intr; 772 sc->sc_parg = arg; 773 774 /* stop playback DMA */ 775 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 776 777 /* setup PDTC */ 778 pdtc = BA1READ4(sc, CS4280_PDTC); 779 pdtc &= ~PDTC_MASK; 780 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 781 BA1WRITE4(sc, CS4280_PDTC, pdtc); 782 783 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 784 param->precision, param->channels, param->encoding)); 785 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 786 continue; 787 if (p == NULL) { 788 printf("cs4280_trigger_output: bad addr %p\n", start); 789 return EINVAL; 790 } 791 if (DMAADDR(p) % sc->dma_align != 0 ) { 792 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 793 "4kB align\n", (ulong)DMAADDR(p)); 794 return EINVAL; 795 } 796 797 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 798 sc->sc_ps = (char *)start; 799 sc->sc_pe = (char *)end; 800 sc->sc_pdma = p; 801 sc->sc_pbuf = KERNADDR(p); 802 sc->sc_pi = 0; 803 sc->sc_pn = sc->sc_ps; 804 if (blksize >= sc->dma_size) { 805 sc->sc_pn = sc->sc_ps + sc->dma_size; 806 memcpy(sc->sc_pbuf, start, sc->dma_size); 807 ++sc->sc_pi; 808 } else { 809 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 810 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 811 } 812 813 /* initiate playback DMA */ 814 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 815 816 /* set PFIE */ 817 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 818 819 if (param->precision == 8) 820 pfie |= PFIE_8BIT; 821 if (param->channels == 1) 822 pfie |= PFIE_MONO; 823 824 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 825 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 826 pfie |= PFIE_SWAPPED; 827 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 828 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 829 pfie |= PFIE_UNSIGNED; 830 831 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 832 833 sc->sc_prate = param->sample_rate; 834 cs4280_set_dac_rate(sc, param->sample_rate); 835 836 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 837 pctl |= sc->pctl; 838 BA1WRITE4(sc, CS4280_PCTL, pctl); 839 return 0; 840 } 841 842 static int 843 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 844 void (*intr)(void *), void *arg, 845 const audio_params_t *param) 846 { 847 struct cs428x_softc *sc; 848 uint32_t cctl, cie; 849 struct cs428x_dma *p; 850 851 sc = addr; 852 #ifdef DIAGNOSTIC 853 if (sc->sc_rrun) 854 printf("cs4280_trigger_input: already running\n"); 855 #endif 856 sc->sc_rrun = 1; 857 cs4280_clkrun_hack(sc, 1); 858 859 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 860 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 861 sc->sc_rintr = intr; 862 sc->sc_rarg = arg; 863 864 /* stop capture DMA */ 865 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 866 867 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 868 continue; 869 if (p == NULL) { 870 printf("cs4280_trigger_input: bad addr %p\n", start); 871 return EINVAL; 872 } 873 if (DMAADDR(p) % sc->dma_align != 0) { 874 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 875 "4kB align\n", (ulong)DMAADDR(p)); 876 return EINVAL; 877 } 878 879 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 880 sc->sc_rs = (char *)start; 881 sc->sc_re = (char *)end; 882 sc->sc_rdma = p; 883 sc->sc_rbuf = KERNADDR(p); 884 sc->sc_ri = 0; 885 sc->sc_rn = sc->sc_rs; 886 887 /* initiate capture DMA */ 888 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 889 890 /* setup format information for internal converter */ 891 sc->sc_rparam = 0; 892 if (param->precision == 8) { 893 sc->sc_rparam += CF_8BIT; 894 sc->sc_rcount <<= 1; 895 } 896 if (param->channels == 1) { 897 sc->sc_rparam += CF_MONO; 898 sc->sc_rcount <<= 1; 899 } 900 901 /* set CIE */ 902 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 903 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 904 905 sc->sc_rrate = param->sample_rate; 906 cs4280_set_adc_rate(sc, param->sample_rate); 907 908 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 909 cctl |= sc->cctl; 910 BA1WRITE4(sc, CS4280_CCTL, cctl); 911 return 0; 912 } 913 914 static bool 915 cs4280_suspend(device_t dv) 916 { 917 struct cs428x_softc *sc = device_private(dv); 918 919 if (sc->sc_prun) { 920 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 921 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 922 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 923 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 924 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 925 sc->sc_suspend_state.cs4280.pctl, 926 sc->sc_suspend_state.cs4280.pfie, 927 sc->sc_suspend_state.cs4280.pba, 928 sc->sc_suspend_state.cs4280.pdtc)); 929 } 930 931 /* save current capture status */ 932 if (sc->sc_rrun) { 933 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 934 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 935 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 936 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 937 sc->sc_suspend_state.cs4280.cctl, 938 sc->sc_suspend_state.cs4280.cie, 939 sc->sc_suspend_state.cs4280.cba)); 940 } 941 942 /* Stop DMA */ 943 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 944 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 945 946 return true; 947 } 948 949 static bool 950 cs4280_resume(device_t dv) 951 { 952 struct cs428x_softc *sc = device_private(dv); 953 954 cs4280_init(sc, 0); 955 #if 0 956 cs4280_reset_codec(sc); 957 #endif 958 /* restore ac97 registers */ 959 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 960 961 /* restore DMA related status */ 962 if(sc->sc_prun) { 963 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 964 sc->sc_suspend_state.cs4280.pctl, 965 sc->sc_suspend_state.cs4280.pfie, 966 sc->sc_suspend_state.cs4280.pba, 967 sc->sc_suspend_state.cs4280.pdtc)); 968 cs4280_set_dac_rate(sc, sc->sc_prate); 969 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 970 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 971 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 972 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 973 } 974 975 if (sc->sc_rrun) { 976 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 977 sc->sc_suspend_state.cs4280.cctl, 978 sc->sc_suspend_state.cs4280.cie, 979 sc->sc_suspend_state.cs4280.cba)); 980 cs4280_set_adc_rate(sc, sc->sc_rrate); 981 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 982 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 983 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 984 } 985 986 return true; 987 } 988 989 static int 990 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 991 { 992 struct cs428x_softc *sc = addr; 993 int rv; 994 995 cs4280_clkrun_hack(sc, 1); 996 rv = cs428x_read_codec(addr, reg, result); 997 cs4280_clkrun_hack(sc, -1); 998 999 return rv; 1000 } 1001 1002 static int 1003 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1004 { 1005 struct cs428x_softc *sc = addr; 1006 int rv; 1007 1008 cs4280_clkrun_hack(sc, 1); 1009 rv = cs428x_write_codec(addr, reg, data); 1010 cs4280_clkrun_hack(sc, -1); 1011 1012 return rv; 1013 } 1014 1015 #if 0 /* XXX buggy and not required */ 1016 /* control AC97 codec */ 1017 static int 1018 cs4280_reset_codec(void *addr) 1019 { 1020 struct cs428x_softc *sc; 1021 int n; 1022 1023 sc = addr; 1024 1025 /* Reset codec */ 1026 BA0WRITE4(sc, CS428X_ACCTL, 0); 1027 delay(100); /* delay 100us */ 1028 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1029 1030 /* 1031 * It looks like we do the following procedure, too 1032 */ 1033 1034 /* Enable AC-link sync generation */ 1035 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1036 delay(50*1000); /* XXX delay 50ms */ 1037 1038 /* Assert valid frame signal */ 1039 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1040 1041 /* Wait for valid AC97 input slot */ 1042 n = 0; 1043 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1044 (ACISV_ISV3 | ACISV_ISV4)) { 1045 delay(1000); 1046 if (++n > 1000) { 1047 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1048 return ETIMEDOUT; 1049 } 1050 } 1051 1052 return 0; 1053 } 1054 #endif 1055 1056 static enum ac97_host_flags cs4280_flags_codec(void *addr) 1057 { 1058 struct cs428x_softc *sc; 1059 1060 sc = addr; 1061 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1062 return AC97_HOST_INVERTED_EAMP; 1063 1064 return 0; 1065 } 1066 1067 /* Internal functions */ 1068 1069 static const struct cs4280_card_t * 1070 cs4280_identify_card(struct pci_attach_args *pa) 1071 { 1072 pcireg_t idreg; 1073 u_int16_t i; 1074 1075 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1076 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1077 if (idreg == cs4280_cards[i].id) 1078 return &cs4280_cards[i]; 1079 } 1080 1081 return NULL; 1082 } 1083 1084 static int 1085 cs4280_piix4_match(struct pci_attach_args *pa) 1086 { 1087 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1088 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1089 return 1; 1090 } 1091 1092 return 0; 1093 } 1094 1095 static void 1096 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1097 { 1098 uint16_t control, val; 1099 1100 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1101 return; 1102 1103 sc->sc_active += change; 1104 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1105 if (!sc->sc_active) 1106 val |= 0x2000; 1107 else 1108 val &= ~0x2000; 1109 if (val != control) 1110 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1111 } 1112 1113 static void 1114 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1115 { 1116 struct pci_attach_args smbuspa; 1117 uint16_t reg; 1118 pcireg_t port; 1119 1120 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1121 return; 1122 1123 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1124 sc->sc_active = 0; 1125 printf("%s: enabling CLKRUN hack\n", 1126 sc->sc_dev.dv_xname); 1127 1128 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1129 port = reg & 0xffc0; 1130 printf("%s: power management port 0x%x\n", sc->sc_dev.dv_xname, 1131 port); 1132 1133 sc->sc_pm_iot = smbuspa.pa_iot; 1134 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1135 &sc->sc_pm_ioh) == 0) 1136 return; 1137 } 1138 1139 /* handle error */ 1140 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1141 printf("%s: disabling CLKRUN hack\n", sc->sc_dev.dv_xname); 1142 } 1143 1144 static void 1145 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1146 { 1147 /* calculate capture rate: 1148 * 1149 * capture_coefficient_increment = -round(rate*128*65536/48000; 1150 * capture_phase_increment = floor(48000*65536*1024/rate); 1151 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1152 * cy = floor(cx/200); 1153 * capture_sample_rate_correction = cx - 200*cy; 1154 * capture_delay = ceil(24*48000/rate); 1155 * capture_num_triplets = floor(65536*rate/24000); 1156 * capture_group_length = 24000/GCD(rate, 24000); 1157 * where GCD means "Greatest Common Divisor". 1158 * 1159 * capture_coefficient_increment, capture_phase_increment and 1160 * capture_num_triplets are 32-bit signed quantities. 1161 * capture_sample_rate_correction and capture_group_length are 1162 * 16-bit signed quantities. 1163 * capture_delay is a 14-bit unsigned quantity. 1164 */ 1165 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1166 uint16_t csrc, cgl, cdlay; 1167 1168 /* XXX 1169 * Even though, embedded_audio_spec says capture rate range 11025 to 1170 * 48000, dhwiface.cpp says, 1171 * 1172 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1173 * Return an error if an attempt is made to stray outside that limit." 1174 * 1175 * so assume range as 48000/9 to 48000 1176 */ 1177 1178 if (rate < 8000) 1179 rate = 8000; 1180 if (rate > 48000) 1181 rate = 48000; 1182 1183 cx = rate << 16; 1184 cci = cx / 48000; 1185 cx -= cci * 48000; 1186 cx <<= 7; 1187 cci <<= 7; 1188 cci += cx / 48000; 1189 cci = - cci; 1190 1191 cx = 48000 << 16; 1192 cpi = cx / rate; 1193 cx -= cpi * rate; 1194 cx <<= 10; 1195 cpi <<= 10; 1196 cy = cx / rate; 1197 cpi += cy; 1198 cx -= cy * rate; 1199 1200 cy = cx / 200; 1201 csrc = cx - 200*cy; 1202 1203 cdlay = ((48000 * 24) + rate - 1) / rate; 1204 #if 0 1205 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1206 #endif 1207 1208 cnt = rate << 16; 1209 cnt /= 24000; 1210 1211 cgl = 1; 1212 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1213 if (((rate / tmp1) * tmp1) != rate) 1214 cgl *= 2; 1215 } 1216 if (((rate / 3) * 3) != rate) 1217 cgl *= 3; 1218 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1219 if (((rate / tmp1) * tmp1) != rate) 1220 cgl *= 5; 1221 } 1222 #if 0 1223 /* XXX what manual says */ 1224 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1225 tmp1 |= csrc<<16; 1226 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1227 #else 1228 /* suggested by cs461x.c (ALSA driver) */ 1229 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1230 #endif 1231 1232 #if 0 1233 /* I am confused. The sample rate calculation section says 1234 * cci *is* 32-bit signed quantity but in the parameter description 1235 * section, CCI only assigned 16bit. 1236 * I believe size of the variable. 1237 */ 1238 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1239 tmp1 |= cci<<16; 1240 BA1WRITE4(sc, CS4280_CCI, tmp1); 1241 #else 1242 BA1WRITE4(sc, CS4280_CCI, cci); 1243 #endif 1244 1245 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1246 tmp1 |= cdlay <<18; 1247 BA1WRITE4(sc, CS4280_CD, tmp1); 1248 1249 BA1WRITE4(sc, CS4280_CPI, cpi); 1250 1251 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1252 tmp1 |= cgl; 1253 BA1WRITE4(sc, CS4280_CGL, tmp1); 1254 1255 BA1WRITE4(sc, CS4280_CNT, cnt); 1256 1257 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1258 tmp1 |= cgl; 1259 BA1WRITE4(sc, CS4280_CGC, tmp1); 1260 } 1261 1262 static void 1263 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1264 { 1265 /* 1266 * playback rate may range from 8000Hz to 48000Hz 1267 * 1268 * play_phase_increment = floor(rate*65536*1024/48000) 1269 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1270 * py=floor(px/200) 1271 * play_sample_rate_correction = px - 200*py 1272 * 1273 * play_phase_increment is a 32bit signed quantity. 1274 * play_sample_rate_correction is a 16bit signed quantity. 1275 */ 1276 int32_t ppi; 1277 int16_t psrc; 1278 uint32_t px, py; 1279 1280 if (rate < 8000) 1281 rate = 8000; 1282 if (rate > 48000) 1283 rate = 48000; 1284 px = rate << 16; 1285 ppi = px/48000; 1286 px -= ppi*48000; 1287 ppi <<= 10; 1288 px <<= 10; 1289 py = px / 48000; 1290 ppi += py; 1291 px -= py*48000; 1292 py = px/200; 1293 px -= py*200; 1294 psrc = px; 1295 #if 0 1296 /* what manual says */ 1297 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1298 BA1WRITE4(sc, CS4280_PSRC, 1299 ( ((psrc<<16) & PSRC_MASK) | px )); 1300 #else 1301 /* suggested by cs461x.c (ALSA driver) */ 1302 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1303 #endif 1304 BA1WRITE4(sc, CS4280_PPI, ppi); 1305 } 1306 1307 /* Download Processor Code and Data image */ 1308 static int 1309 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1310 uint32_t offset, uint32_t len) 1311 { 1312 uint32_t ctr; 1313 #if CS4280_DEBUG > 10 1314 uint32_t con, data; 1315 uint8_t c0, c1, c2, c3; 1316 #endif 1317 if ((offset & 3) || (len & 3)) 1318 return -1; 1319 1320 len /= sizeof(uint32_t); 1321 for (ctr = 0; ctr < len; ctr++) { 1322 /* XXX: 1323 * I cannot confirm this is the right thing or not 1324 * on BIG-ENDIAN machines. 1325 */ 1326 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1327 #if CS4280_DEBUG > 10 1328 data = htole32(*(src+ctr)); 1329 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1330 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1331 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1332 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1333 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1334 if (data != con ) { 1335 printf("0x%06x: write=0x%08x read=0x%08x\n", 1336 offset+ctr*4, data, con); 1337 return -1; 1338 } 1339 #endif 1340 } 1341 return 0; 1342 } 1343 1344 static int 1345 cs4280_download_image(struct cs428x_softc *sc) 1346 { 1347 int idx, err; 1348 uint32_t offset = 0; 1349 1350 err = 0; 1351 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1352 err = cs4280_download(sc, &BA1Struct.map[offset], 1353 BA1Struct.memory[idx].offset, 1354 BA1Struct.memory[idx].size); 1355 if (err != 0) { 1356 printf("%s: load_image failed at %d\n", 1357 sc->sc_dev.dv_xname, idx); 1358 return -1; 1359 } 1360 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1361 } 1362 return err; 1363 } 1364 1365 /* Processor Soft Reset */ 1366 static void 1367 cs4280_reset(void *sc_) 1368 { 1369 struct cs428x_softc *sc; 1370 1371 sc = sc_; 1372 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1373 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1374 delay(100); 1375 /* Clear RSTSP bit in SPCR */ 1376 BA1WRITE4(sc, CS4280_SPCR, 0); 1377 /* enable DMA reqest */ 1378 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1379 } 1380 1381 static int 1382 cs4280_init(struct cs428x_softc *sc, int init) 1383 { 1384 int n; 1385 uint32_t mem; 1386 int rv; 1387 1388 rv = 1; 1389 cs4280_clkrun_hack(sc, 1); 1390 1391 /* Start PLL out in known state */ 1392 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1393 /* Start serial ports out in known state */ 1394 BA0WRITE4(sc, CS4280_SERMC1, 0); 1395 1396 /* Specify type of CODEC */ 1397 /* XXX should not be here */ 1398 #define SERACC_CODEC_TYPE_1_03 1399 #ifdef SERACC_CODEC_TYPE_1_03 1400 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1401 #else 1402 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1403 #endif 1404 1405 /* Reset codec */ 1406 BA0WRITE4(sc, CS428X_ACCTL, 0); 1407 delay(100); /* delay 100us */ 1408 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1409 1410 /* Enable AC-link sync generation */ 1411 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1412 delay(50*1000); /* delay 50ms */ 1413 1414 /* Set the serial port timing configuration */ 1415 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1416 1417 /* Setup clock control */ 1418 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1419 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1420 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1421 1422 /* Power up the PLL */ 1423 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1424 delay(50*1000); /* delay 50ms */ 1425 1426 /* Turn on clock */ 1427 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1428 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1429 1430 /* Set the serial port FIFO pointer to the 1431 * first sample in FIFO. (not documented) */ 1432 cs4280_clear_fifos(sc); 1433 1434 #if 0 1435 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1436 BA0WRITE4(sc, CS4280_SERBSP, 0); 1437 #endif 1438 1439 /* Configure the serial port */ 1440 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1441 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1442 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1443 1444 /* Wait for CODEC ready */ 1445 n = 0; 1446 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1447 delay(125); 1448 if (++n > 1000) { 1449 printf("%s: codec ready timeout\n", 1450 sc->sc_dev.dv_xname); 1451 goto exit; 1452 } 1453 } 1454 1455 /* Assert valid frame signal */ 1456 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1457 1458 /* Wait for valid AC97 input slot */ 1459 n = 0; 1460 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1461 (ACISV_ISV3 | ACISV_ISV4)) { 1462 delay(1000); 1463 if (++n > 1000) { 1464 printf("AC97 inputs slot ready timeout\n"); 1465 goto exit; 1466 } 1467 } 1468 1469 /* Set AC97 output slot valid signals */ 1470 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1471 1472 /* reset the processor */ 1473 cs4280_reset(sc); 1474 1475 /* Download the image to the processor */ 1476 if (cs4280_download_image(sc) != 0) { 1477 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1478 goto exit; 1479 } 1480 1481 /* Save playback parameter and then write zero. 1482 * this ensures that DMA doesn't immediately occur upon 1483 * starting the processor core 1484 */ 1485 mem = BA1READ4(sc, CS4280_PCTL); 1486 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1487 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1488 if (init != 0) 1489 sc->sc_prun = 0; 1490 1491 /* Save capture parameter and then write zero. 1492 * this ensures that DMA doesn't immediately occur upon 1493 * starting the processor core 1494 */ 1495 mem = BA1READ4(sc, CS4280_CCTL); 1496 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1497 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1498 if (init != 0) 1499 sc->sc_rrun = 0; 1500 1501 /* Processor Startup Procedure */ 1502 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1503 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1504 1505 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1506 n = 0; 1507 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1508 delay(10); 1509 if (++n > 1000) { 1510 printf("SPCR 1->0 transition timeout\n"); 1511 goto exit; 1512 } 1513 } 1514 1515 n = 0; 1516 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1517 delay(10); 1518 if (++n > 1000) { 1519 printf("SPCS 0->1 transition timeout\n"); 1520 goto exit; 1521 } 1522 } 1523 /* Processor is now running !!! */ 1524 1525 /* Setup volume */ 1526 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1527 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1528 1529 /* Interrupt enable */ 1530 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1531 1532 /* playback interrupt enable */ 1533 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1534 mem |= PFIE_PI_ENABLE; 1535 BA1WRITE4(sc, CS4280_PFIE, mem); 1536 /* capture interrupt enable */ 1537 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1538 mem |= CIE_CI_ENABLE; 1539 BA1WRITE4(sc, CS4280_CIE, mem); 1540 1541 #if NMIDI > 0 1542 /* Reset midi port */ 1543 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1544 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1545 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1546 /* midi interrupt enable */ 1547 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1548 BA0WRITE4(sc, CS4280_MIDCR, mem); 1549 #endif 1550 1551 rv = 0; 1552 1553 exit: 1554 cs4280_clkrun_hack(sc, -1); 1555 return rv; 1556 } 1557 1558 static void 1559 cs4280_clear_fifos(struct cs428x_softc *sc) 1560 { 1561 int pd, cnt, n; 1562 uint32_t mem; 1563 1564 pd = 0; 1565 /* 1566 * If device power down, power up the device and keep power down 1567 * state. 1568 */ 1569 mem = BA0READ4(sc, CS4280_CLKCR1); 1570 if (!(mem & CLKCR1_SWCE)) { 1571 printf("cs4280_clear_fifo: power down found.\n"); 1572 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1573 pd = 1; 1574 } 1575 BA0WRITE4(sc, CS4280_SERBWP, 0); 1576 for (cnt = 0; cnt < 256; cnt++) { 1577 n = 0; 1578 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1579 delay(1000); 1580 if (++n > 1000) { 1581 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1582 break; 1583 } 1584 } 1585 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1586 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1587 } 1588 if (pd) 1589 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1590 } 1591 1592 #if NMIDI > 0 1593 static int 1594 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1595 void (*ointr)(void *), void *arg) 1596 { 1597 struct cs428x_softc *sc; 1598 uint32_t mem; 1599 1600 DPRINTF(("midi_open\n")); 1601 sc = addr; 1602 sc->sc_iintr = iintr; 1603 sc->sc_ointr = ointr; 1604 sc->sc_arg = arg; 1605 1606 /* midi interrupt enable */ 1607 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1608 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1609 BA0WRITE4(sc, CS4280_MIDCR, mem); 1610 #ifdef CS4280_DEBUG 1611 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1612 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1613 return(EINVAL); 1614 } 1615 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1616 #endif 1617 return 0; 1618 } 1619 1620 static void 1621 cs4280_midi_close(void *addr) 1622 { 1623 struct cs428x_softc *sc; 1624 uint32_t mem; 1625 1626 DPRINTF(("midi_close\n")); 1627 sc = addr; 1628 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1629 mem = BA0READ4(sc, CS4280_MIDCR); 1630 mem &= ~MIDCR_MASK; 1631 BA0WRITE4(sc, CS4280_MIDCR, mem); 1632 1633 sc->sc_iintr = 0; 1634 sc->sc_ointr = 0; 1635 } 1636 1637 static int 1638 cs4280_midi_output(void *addr, int d) 1639 { 1640 struct cs428x_softc *sc; 1641 uint32_t mem; 1642 int x; 1643 1644 sc = addr; 1645 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1646 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1647 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1648 mem |= d & MIDWP_MASK; 1649 DPRINTFN(5,("midi_output d=0x%08x",d)); 1650 BA0WRITE4(sc, CS4280_MIDWP, mem); 1651 #ifdef DIAGNOSTIC 1652 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1653 DPRINTF(("Bad write data: %d %d", 1654 mem, BA0READ4(sc, CS4280_MIDWP))); 1655 return EIO; 1656 } 1657 #endif 1658 return 0; 1659 } 1660 delay(MIDI_BUSY_DELAY); 1661 } 1662 return EIO; 1663 } 1664 1665 static void 1666 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1667 { 1668 1669 mi->name = "CS4280 MIDI UART"; 1670 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1671 } 1672 1673 #endif /* NMIDI */ 1674 1675 /* DEBUG functions */ 1676 #if CS4280_DEBUG > 10 1677 static int 1678 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1679 uint32_t offset, uint32_t len) 1680 { 1681 uint32_t ctr, data; 1682 int err; 1683 1684 if ((offset & 3) || (len & 3)) 1685 return -1; 1686 1687 err = 0; 1688 len /= sizeof(uint32_t); 1689 for (ctr = 0; ctr < len; ctr++) { 1690 /* I cannot confirm this is the right thing 1691 * on BIG-ENDIAN machines 1692 */ 1693 data = BA1READ4(sc, offset+ctr*4); 1694 if (data != htole32(*(src+ctr))) { 1695 printf("0x%06x: 0x%08x(0x%08x)\n", 1696 offset+ctr*4, data, *(src+ctr)); 1697 *(src+ctr) = data; 1698 ++err; 1699 } 1700 } 1701 return err; 1702 } 1703 1704 static int 1705 cs4280_check_images(struct cs428x_softc *sc) 1706 { 1707 int idx, err; 1708 uint32_t offset; 1709 1710 offset = 0; 1711 err = 0; 1712 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1713 for (idx = 0; idx < 1; ++idx) { 1714 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1715 BA1Struct.memory[idx].offset, 1716 BA1Struct.memory[idx].size); 1717 if (err != 0) { 1718 printf("%s: check_image failed at %d\n", 1719 sc->sc_dev.dv_xname, idx); 1720 } 1721 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1722 } 1723 return err; 1724 } 1725 1726 #endif /* CS4280_DEBUG */ 1727
Indexes created Thu Oct 02 14:10:14 GMT 2025