cs4280.c revision 1.48.6.1
1 /* $NetBSD: cs4280.c,v 1.48.6.1 2008/03/24 07:15:47 keiichi Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.48.6.1 2008/03/24 07:15:47 keiichi Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <sys/bus.h> 86 #include <sys/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(struct device *, struct cfdata *, void *); 93 static void cs4280_attach(struct device *, struct device *, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 107 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 108 #if 0 109 static int cs4280_reset_codec(void *); 110 #endif 111 static enum ac97_host_flags cs4280_flags_codec(void *); 112 113 static bool cs4280_resume(device_t PMF_FN_PROTO); 114 static bool cs4280_suspend(device_t PMF_FN_PROTO); 115 116 /* Internal functions */ 117 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *); 118 static int cs4280_piix4_match(struct pci_attach_args *); 119 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 120 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 121 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 122 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 123 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 124 uint32_t); 125 static int cs4280_download_image(struct cs428x_softc *); 126 static void cs4280_reset(void *); 127 static int cs4280_init(struct cs428x_softc *, int); 128 static void cs4280_clear_fifos(struct cs428x_softc *); 129 130 #if CS4280_DEBUG > 10 131 /* Thease two function is only for checking image loading is succeeded or not. */ 132 static int cs4280_check_images(struct cs428x_softc *); 133 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 134 uint32_t); 135 #endif 136 137 /* Special cards */ 138 struct cs4280_card_t 139 { 140 pcireg_t id; 141 enum cs428x_flags flags; 142 }; 143 144 #define _card(vend, prod, flags) \ 145 {PCI_ID_CODE(vend, prod), flags} 146 147 static const struct cs4280_card_t cs4280_cards[] = { 148 #if 0 /* untested, from ALSA driver */ 149 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 150 CS428X_FLAG_INVAC97EAMP), 151 #endif 152 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 153 CS428X_FLAG_INVAC97EAMP), 154 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 155 CS428X_FLAG_CLKRUNHACK) 156 }; 157 158 #undef _card 159 160 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 161 162 static const struct audio_hw_if cs4280_hw_if = { 163 NULL, /* open */ 164 NULL, /* close */ 165 NULL, 166 cs4280_query_encoding, 167 cs4280_set_params, 168 cs428x_round_blocksize, 169 NULL, 170 NULL, 171 NULL, 172 NULL, 173 NULL, 174 cs4280_halt_output, 175 cs4280_halt_input, 176 NULL, 177 cs4280_getdev, 178 NULL, 179 cs428x_mixer_set_port, 180 cs428x_mixer_get_port, 181 cs428x_query_devinfo, 182 cs428x_malloc, 183 cs428x_free, 184 cs428x_round_buffersize, 185 cs428x_mappage, 186 cs428x_get_props, 187 cs4280_trigger_output, 188 cs4280_trigger_input, 189 NULL, 190 NULL, 191 }; 192 193 #if NMIDI > 0 194 /* Midi Interface */ 195 static int cs4280_midi_open(void *, int, void (*)(void *, int), 196 void (*)(void *), void *); 197 static void cs4280_midi_close(void*); 198 static int cs4280_midi_output(void *, int); 199 static void cs4280_midi_getinfo(void *, struct midi_info *); 200 201 static const struct midi_hw_if cs4280_midi_hw_if = { 202 cs4280_midi_open, 203 cs4280_midi_close, 204 cs4280_midi_output, 205 cs4280_midi_getinfo, 206 0, 207 }; 208 #endif 209 210 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 211 cs4280_match, cs4280_attach, NULL, NULL); 212 213 static struct audio_device cs4280_device = { 214 "CS4280", 215 "", 216 "cs4280" 217 }; 218 219 220 static int 221 cs4280_match(struct device *parent, struct cfdata *match, 222 void *aux) 223 { 224 struct pci_attach_args *pa; 225 226 pa = (struct pci_attach_args *)aux; 227 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 228 return 0; 229 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 230 #if 0 /* I can't confirm */ 231 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 232 #endif 233 ) 234 return 1; 235 return 0; 236 } 237 238 static void 239 cs4280_attach(struct device *parent, struct device *self, void *aux) 240 { 241 struct cs428x_softc *sc; 242 struct pci_attach_args *pa; 243 pci_chipset_tag_t pc; 244 const struct cs4280_card_t *cs_card; 245 char const *intrstr; 246 pcireg_t reg; 247 char devinfo[256]; 248 uint32_t mem; 249 int error; 250 251 sc = (struct cs428x_softc *)self; 252 pa = (struct pci_attach_args *)aux; 253 pc = pa->pa_pc; 254 aprint_naive(": Audio controller\n"); 255 256 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 257 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 258 PCI_REVISION(pa->pa_class)); 259 260 cs_card = cs4280_identify_card(pa); 261 if (cs_card != NULL) { 262 aprint_normal_dev(&sc->sc_dev, "%s %s\n", 263 pci_findvendor(cs_card->id), 264 pci_findproduct(cs_card->id)); 265 sc->sc_flags = cs_card->flags; 266 } else { 267 sc->sc_flags = CS428X_FLAG_NONE; 268 } 269 270 sc->sc_pc = pa->pa_pc; 271 sc->sc_pt = pa->pa_tag; 272 273 /* Map I/O register */ 274 if (pci_mapreg_map(pa, PCI_BA0, 275 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 276 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 277 aprint_error_dev(&sc->sc_dev, "can't map BA0 space\n"); 278 return; 279 } 280 if (pci_mapreg_map(pa, PCI_BA1, 281 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 282 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 283 aprint_error_dev(&sc->sc_dev, "can't map BA1 space\n"); 284 return; 285 } 286 287 sc->sc_dmatag = pa->pa_dmat; 288 289 /* power up chip */ 290 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 291 pci_activate_null)) && error != EOPNOTSUPP) { 292 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 293 return; 294 } 295 296 /* Enable the device (set bus master flag) */ 297 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 298 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 299 reg | PCI_COMMAND_MASTER_ENABLE); 300 301 /* LATENCY_TIMER setting */ 302 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 303 if ( PCI_LATTIMER(mem) < 32 ) { 304 mem &= 0xffff00ff; 305 mem |= 0x00002000; 306 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 307 } 308 309 /* CLKRUN hack initialization */ 310 cs4280_clkrun_hack_init(sc); 311 312 /* Map and establish the interrupt. */ 313 if (pci_intr_map(pa, &sc->intrh)) { 314 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 315 return; 316 } 317 intrstr = pci_intr_string(pc, sc->intrh); 318 319 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 320 cs4280_intr, sc); 321 if (sc->sc_ih == NULL) { 322 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 323 if (intrstr != NULL) 324 aprint_normal(" at %s", intrstr); 325 aprint_normal("\n"); 326 return; 327 } 328 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 329 330 /* Initialization */ 331 if(cs4280_init(sc, 1) != 0) 332 return; 333 334 sc->type = TYPE_CS4280; 335 sc->halt_input = cs4280_halt_input; 336 sc->halt_output = cs4280_halt_output; 337 338 /* setup buffer related parameters */ 339 sc->dma_size = CS4280_DCHUNK; 340 sc->dma_align = CS4280_DALIGN; 341 sc->hw_blocksize = CS4280_ICHUNK; 342 343 /* AC 97 attachment */ 344 sc->host_if.arg = sc; 345 sc->host_if.attach = cs428x_attach_codec; 346 sc->host_if.read = cs4280_read_codec; 347 sc->host_if.write = cs4280_write_codec; 348 #if 0 349 sc->host_if.reset = cs4280_reset_codec; 350 #else 351 sc->host_if.reset = NULL; 352 #endif 353 sc->host_if.flags = cs4280_flags_codec; 354 if (ac97_attach(&sc->host_if, self) != 0) { 355 aprint_error_dev(&sc->sc_dev, "ac97_attach failed\n"); 356 return; 357 } 358 359 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 360 361 #if NMIDI > 0 362 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 363 #endif 364 365 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 366 aprint_error_dev(self, "couldn't establish power handler\n"); 367 } 368 369 /* Interrupt handling function */ 370 static int 371 cs4280_intr(void *p) 372 { 373 /* 374 * XXX 375 * 376 * Since CS4280 has only 4kB DMA buffer and 377 * interrupt occurs every 2kB block, I create dummy buffer 378 * which returns to audio driver and actual DMA buffer 379 * using in DMA transfer. 380 * 381 * 382 * ring buffer in audio.c is pointed by BUFADDR 383 * <------ ring buffer size == 64kB ------> 384 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 385 * |= = = =|= = = =|= = = =|= = = =|= = = =| 386 * | | | | | | <- call audio_intp every 387 * sc->sc_[pr]_count time. 388 * 389 * actual DMA buffer is pointed by KERNADDR 390 * <-> DMA buffer size = 4kB 391 * |= =| 392 * 393 * 394 */ 395 struct cs428x_softc *sc; 396 uint32_t intr, mem; 397 char * empty_dma; 398 int handled; 399 400 sc = p; 401 handled = 0; 402 /* grab interrupt register then clear it */ 403 intr = BA0READ4(sc, CS4280_HISR); 404 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 405 406 /* not for us ? */ 407 if ((intr & HISR_INTENA) == 0) 408 return 0; 409 410 /* Playback Interrupt */ 411 if (intr & HISR_PINT) { 412 handled = 1; 413 mem = BA1READ4(sc, CS4280_PFIE); 414 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 415 if (sc->sc_prun) { 416 if ((sc->sc_pi%sc->sc_pcount) == 0) 417 sc->sc_pintr(sc->sc_parg); 418 /* copy buffer */ 419 ++sc->sc_pi; 420 empty_dma = sc->sc_pdma->addr; 421 if (sc->sc_pi&1) 422 empty_dma += sc->hw_blocksize; 423 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 424 sc->sc_pn += sc->hw_blocksize; 425 if (sc->sc_pn >= sc->sc_pe) 426 sc->sc_pn = sc->sc_ps; 427 } else { 428 aprint_error_dev(&sc->sc_dev, "unexpected play intr\n"); 429 } 430 BA1WRITE4(sc, CS4280_PFIE, mem); 431 } 432 /* Capture Interrupt */ 433 if (intr & HISR_CINT) { 434 int i; 435 int16_t rdata; 436 437 handled = 1; 438 mem = BA1READ4(sc, CS4280_CIE); 439 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 440 441 if (sc->sc_rrun) { 442 ++sc->sc_ri; 443 empty_dma = sc->sc_rdma->addr; 444 if ((sc->sc_ri&1) == 0) 445 empty_dma += sc->hw_blocksize; 446 447 /* 448 * XXX 449 * I think this audio data conversion should be 450 * happend in upper layer, but I put this here 451 * since there is no conversion function available. 452 */ 453 switch(sc->sc_rparam) { 454 case CF_16BIT_STEREO: 455 /* just copy it */ 456 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 457 sc->sc_rn += sc->hw_blocksize; 458 break; 459 case CF_16BIT_MONO: 460 for (i = 0; i < 512; i++) { 461 rdata = *((int16_t *)empty_dma)>>1; 462 empty_dma += 2; 463 rdata += *((int16_t *)empty_dma)>>1; 464 empty_dma += 2; 465 *((int16_t *)sc->sc_rn) = rdata; 466 sc->sc_rn += 2; 467 } 468 break; 469 case CF_8BIT_STEREO: 470 for (i = 0; i < 512; i++) { 471 rdata = *((int16_t*)empty_dma); 472 empty_dma += 2; 473 *sc->sc_rn++ = rdata >> 8; 474 rdata = *((int16_t*)empty_dma); 475 empty_dma += 2; 476 *sc->sc_rn++ = rdata >> 8; 477 } 478 break; 479 case CF_8BIT_MONO: 480 for (i = 0; i < 512; i++) { 481 rdata = *((int16_t*)empty_dma) >>1; 482 empty_dma += 2; 483 rdata += *((int16_t*)empty_dma) >>1; 484 empty_dma += 2; 485 *sc->sc_rn++ = rdata >>8; 486 } 487 break; 488 default: 489 /* Should not reach here */ 490 aprint_error_dev(&sc->sc_dev, 491 "unknown sc->sc_rparam: %d\n", 492 sc->sc_rparam); 493 } 494 if (sc->sc_rn >= sc->sc_re) 495 sc->sc_rn = sc->sc_rs; 496 } 497 BA1WRITE4(sc, CS4280_CIE, mem); 498 499 if (sc->sc_rrun) { 500 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 501 sc->sc_rintr(sc->sc_rarg); 502 } else { 503 aprint_error_dev(&sc->sc_dev, 504 "unexpected record intr\n"); 505 } 506 } 507 508 #if NMIDI > 0 509 /* Midi port Interrupt */ 510 if (intr & HISR_MIDI) { 511 int data; 512 513 handled = 1; 514 DPRINTF(("i: %d: ", 515 BA0READ4(sc, CS4280_MIDSR))); 516 /* Read the received data */ 517 while ((sc->sc_iintr != NULL) && 518 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 519 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 520 DPRINTF(("r:%x\n",data)); 521 sc->sc_iintr(sc->sc_arg, data); 522 } 523 524 /* Write the data */ 525 #if 1 526 /* XXX: 527 * It seems "Transmit Buffer Full" never activate until EOI 528 * is deliverd. Shall I throw EOI top of this routine ? 529 */ 530 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 531 DPRINTF(("w: ")); 532 if (sc->sc_ointr != NULL) 533 sc->sc_ointr(sc->sc_arg); 534 } 535 #else 536 while ((sc->sc_ointr != NULL) && 537 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 538 DPRINTF(("w: ")); 539 sc->sc_ointr(sc->sc_arg); 540 } 541 #endif 542 DPRINTF(("\n")); 543 } 544 #endif 545 546 return handled; 547 } 548 549 static int 550 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 551 { 552 switch (fp->index) { 553 case 0: 554 strcpy(fp->name, AudioEulinear); 555 fp->encoding = AUDIO_ENCODING_ULINEAR; 556 fp->precision = 8; 557 fp->flags = 0; 558 break; 559 case 1: 560 strcpy(fp->name, AudioEmulaw); 561 fp->encoding = AUDIO_ENCODING_ULAW; 562 fp->precision = 8; 563 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 564 break; 565 case 2: 566 strcpy(fp->name, AudioEalaw); 567 fp->encoding = AUDIO_ENCODING_ALAW; 568 fp->precision = 8; 569 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 570 break; 571 case 3: 572 strcpy(fp->name, AudioEslinear); 573 fp->encoding = AUDIO_ENCODING_SLINEAR; 574 fp->precision = 8; 575 fp->flags = 0; 576 break; 577 case 4: 578 strcpy(fp->name, AudioEslinear_le); 579 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 580 fp->precision = 16; 581 fp->flags = 0; 582 break; 583 case 5: 584 strcpy(fp->name, AudioEulinear_le); 585 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 586 fp->precision = 16; 587 fp->flags = 0; 588 break; 589 case 6: 590 strcpy(fp->name, AudioEslinear_be); 591 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 592 fp->precision = 16; 593 fp->flags = 0; 594 break; 595 case 7: 596 strcpy(fp->name, AudioEulinear_be); 597 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 598 fp->precision = 16; 599 fp->flags = 0; 600 break; 601 default: 602 return EINVAL; 603 } 604 return 0; 605 } 606 607 static int 608 cs4280_set_params(void *addr, int setmode, int usemode, 609 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 610 stream_filter_list_t *rfil) 611 { 612 audio_params_t hw; 613 struct cs428x_softc *sc; 614 struct audio_params *p; 615 stream_filter_list_t *fil; 616 int mode; 617 618 sc = addr; 619 for (mode = AUMODE_RECORD; mode != -1; 620 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 621 if ((setmode & mode) == 0) 622 continue; 623 624 p = mode == AUMODE_PLAY ? play : rec; 625 626 if (p == play) { 627 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 628 p->sample_rate, p->precision, p->channels)); 629 /* play back data format may be 8- or 16-bit and 630 * either stereo or mono. 631 * playback rate may range from 8000Hz to 48000Hz 632 */ 633 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 634 (p->precision != 8 && p->precision != 16) || 635 (p->channels != 1 && p->channels != 2) ) { 636 return EINVAL; 637 } 638 } else { 639 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 640 p->sample_rate, p->precision, p->channels)); 641 /* capture data format must be 16bit stereo 642 * and sample rate range from 11025Hz to 48000Hz. 643 * 644 * XXX: it looks like to work with 8000Hz, 645 * although data sheets say lower limit is 646 * 11025 Hz. 647 */ 648 649 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 650 (p->precision != 8 && p->precision != 16) || 651 (p->channels != 1 && p->channels != 2) ) { 652 return EINVAL; 653 } 654 } 655 fil = mode == AUMODE_PLAY ? pfil : rfil; 656 hw = *p; 657 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 658 659 /* capturing data is slinear */ 660 switch (p->encoding) { 661 case AUDIO_ENCODING_SLINEAR_BE: 662 if (mode == AUMODE_RECORD && p->precision == 16) { 663 fil->append(fil, swap_bytes, &hw); 664 } 665 break; 666 case AUDIO_ENCODING_SLINEAR_LE: 667 break; 668 case AUDIO_ENCODING_ULINEAR_BE: 669 if (mode == AUMODE_RECORD) { 670 fil->append(fil, p->precision == 16 671 ? swap_bytes_change_sign16 672 : change_sign8, &hw); 673 } 674 break; 675 case AUDIO_ENCODING_ULINEAR_LE: 676 if (mode == AUMODE_RECORD) { 677 fil->append(fil, p->precision == 16 678 ? change_sign16 : change_sign8, 679 &hw); 680 } 681 break; 682 case AUDIO_ENCODING_ULAW: 683 if (mode == AUMODE_PLAY) { 684 hw.precision = 16; 685 hw.validbits = 16; 686 fil->append(fil, mulaw_to_linear16, &hw); 687 } else { 688 fil->append(fil, linear8_to_mulaw, &hw); 689 } 690 break; 691 case AUDIO_ENCODING_ALAW: 692 if (mode == AUMODE_PLAY) { 693 hw.precision = 16; 694 hw.validbits = 16; 695 fil->append(fil, alaw_to_linear16, &hw); 696 } else { 697 fil->append(fil, linear8_to_alaw, &hw); 698 } 699 break; 700 default: 701 return EINVAL; 702 } 703 } 704 705 /* set sample rate */ 706 cs4280_set_dac_rate(sc, play->sample_rate); 707 cs4280_set_adc_rate(sc, rec->sample_rate); 708 return 0; 709 } 710 711 static int 712 cs4280_halt_output(void *addr) 713 { 714 struct cs428x_softc *sc; 715 uint32_t mem; 716 717 sc = addr; 718 mem = BA1READ4(sc, CS4280_PCTL); 719 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 720 sc->sc_prun = 0; 721 cs4280_clkrun_hack(sc, -1); 722 723 return 0; 724 } 725 726 static int 727 cs4280_halt_input(void *addr) 728 { 729 struct cs428x_softc *sc; 730 uint32_t mem; 731 732 sc = addr; 733 mem = BA1READ4(sc, CS4280_CCTL); 734 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 735 sc->sc_rrun = 0; 736 cs4280_clkrun_hack(sc, -1); 737 738 return 0; 739 } 740 741 static int 742 cs4280_getdev(void *addr, struct audio_device *retp) 743 { 744 745 *retp = cs4280_device; 746 return 0; 747 } 748 749 static int 750 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 751 void (*intr)(void *), void *arg, 752 const audio_params_t *param) 753 { 754 struct cs428x_softc *sc; 755 uint32_t pfie, pctl, pdtc; 756 struct cs428x_dma *p; 757 758 sc = addr; 759 #ifdef DIAGNOSTIC 760 if (sc->sc_prun) 761 printf("cs4280_trigger_output: already running\n"); 762 #endif 763 sc->sc_prun = 1; 764 cs4280_clkrun_hack(sc, 1); 765 766 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 767 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 768 sc->sc_pintr = intr; 769 sc->sc_parg = arg; 770 771 /* stop playback DMA */ 772 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 773 774 /* setup PDTC */ 775 pdtc = BA1READ4(sc, CS4280_PDTC); 776 pdtc &= ~PDTC_MASK; 777 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 778 BA1WRITE4(sc, CS4280_PDTC, pdtc); 779 780 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 781 param->precision, param->channels, param->encoding)); 782 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 783 continue; 784 if (p == NULL) { 785 printf("cs4280_trigger_output: bad addr %p\n", start); 786 return EINVAL; 787 } 788 if (DMAADDR(p) % sc->dma_align != 0 ) { 789 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 790 "4kB align\n", (ulong)DMAADDR(p)); 791 return EINVAL; 792 } 793 794 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 795 sc->sc_ps = (char *)start; 796 sc->sc_pe = (char *)end; 797 sc->sc_pdma = p; 798 sc->sc_pbuf = KERNADDR(p); 799 sc->sc_pi = 0; 800 sc->sc_pn = sc->sc_ps; 801 if (blksize >= sc->dma_size) { 802 sc->sc_pn = sc->sc_ps + sc->dma_size; 803 memcpy(sc->sc_pbuf, start, sc->dma_size); 804 ++sc->sc_pi; 805 } else { 806 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 807 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 808 } 809 810 /* initiate playback DMA */ 811 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 812 813 /* set PFIE */ 814 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 815 816 if (param->precision == 8) 817 pfie |= PFIE_8BIT; 818 if (param->channels == 1) 819 pfie |= PFIE_MONO; 820 821 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 822 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 823 pfie |= PFIE_SWAPPED; 824 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 825 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 826 pfie |= PFIE_UNSIGNED; 827 828 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 829 830 sc->sc_prate = param->sample_rate; 831 cs4280_set_dac_rate(sc, param->sample_rate); 832 833 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 834 pctl |= sc->pctl; 835 BA1WRITE4(sc, CS4280_PCTL, pctl); 836 return 0; 837 } 838 839 static int 840 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 841 void (*intr)(void *), void *arg, 842 const audio_params_t *param) 843 { 844 struct cs428x_softc *sc; 845 uint32_t cctl, cie; 846 struct cs428x_dma *p; 847 848 sc = addr; 849 #ifdef DIAGNOSTIC 850 if (sc->sc_rrun) 851 printf("cs4280_trigger_input: already running\n"); 852 #endif 853 sc->sc_rrun = 1; 854 cs4280_clkrun_hack(sc, 1); 855 856 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 857 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 858 sc->sc_rintr = intr; 859 sc->sc_rarg = arg; 860 861 /* stop capture DMA */ 862 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 863 864 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 865 continue; 866 if (p == NULL) { 867 printf("cs4280_trigger_input: bad addr %p\n", start); 868 return EINVAL; 869 } 870 if (DMAADDR(p) % sc->dma_align != 0) { 871 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 872 "4kB align\n", (ulong)DMAADDR(p)); 873 return EINVAL; 874 } 875 876 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 877 sc->sc_rs = (char *)start; 878 sc->sc_re = (char *)end; 879 sc->sc_rdma = p; 880 sc->sc_rbuf = KERNADDR(p); 881 sc->sc_ri = 0; 882 sc->sc_rn = sc->sc_rs; 883 884 /* initiate capture DMA */ 885 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 886 887 /* setup format information for internal converter */ 888 sc->sc_rparam = 0; 889 if (param->precision == 8) { 890 sc->sc_rparam += CF_8BIT; 891 sc->sc_rcount <<= 1; 892 } 893 if (param->channels == 1) { 894 sc->sc_rparam += CF_MONO; 895 sc->sc_rcount <<= 1; 896 } 897 898 /* set CIE */ 899 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 900 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 901 902 sc->sc_rrate = param->sample_rate; 903 cs4280_set_adc_rate(sc, param->sample_rate); 904 905 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 906 cctl |= sc->cctl; 907 BA1WRITE4(sc, CS4280_CCTL, cctl); 908 return 0; 909 } 910 911 static bool 912 cs4280_suspend(device_t dv PMF_FN_ARGS) 913 { 914 struct cs428x_softc *sc = device_private(dv); 915 916 if (sc->sc_prun) { 917 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 918 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 919 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 920 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 921 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 922 sc->sc_suspend_state.cs4280.pctl, 923 sc->sc_suspend_state.cs4280.pfie, 924 sc->sc_suspend_state.cs4280.pba, 925 sc->sc_suspend_state.cs4280.pdtc)); 926 } 927 928 /* save current capture status */ 929 if (sc->sc_rrun) { 930 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 931 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 932 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 933 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 934 sc->sc_suspend_state.cs4280.cctl, 935 sc->sc_suspend_state.cs4280.cie, 936 sc->sc_suspend_state.cs4280.cba)); 937 } 938 939 /* Stop DMA */ 940 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 941 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 942 943 return true; 944 } 945 946 static bool 947 cs4280_resume(device_t dv PMF_FN_ARGS) 948 { 949 struct cs428x_softc *sc = device_private(dv); 950 951 cs4280_init(sc, 0); 952 #if 0 953 cs4280_reset_codec(sc); 954 #endif 955 /* restore ac97 registers */ 956 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 957 958 /* restore DMA related status */ 959 if(sc->sc_prun) { 960 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 961 sc->sc_suspend_state.cs4280.pctl, 962 sc->sc_suspend_state.cs4280.pfie, 963 sc->sc_suspend_state.cs4280.pba, 964 sc->sc_suspend_state.cs4280.pdtc)); 965 cs4280_set_dac_rate(sc, sc->sc_prate); 966 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 967 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 968 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 969 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 970 } 971 972 if (sc->sc_rrun) { 973 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 974 sc->sc_suspend_state.cs4280.cctl, 975 sc->sc_suspend_state.cs4280.cie, 976 sc->sc_suspend_state.cs4280.cba)); 977 cs4280_set_adc_rate(sc, sc->sc_rrate); 978 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 979 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 980 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 981 } 982 983 return true; 984 } 985 986 static int 987 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 988 { 989 struct cs428x_softc *sc = addr; 990 int rv; 991 992 cs4280_clkrun_hack(sc, 1); 993 rv = cs428x_read_codec(addr, reg, result); 994 cs4280_clkrun_hack(sc, -1); 995 996 return rv; 997 } 998 999 static int 1000 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1001 { 1002 struct cs428x_softc *sc = addr; 1003 int rv; 1004 1005 cs4280_clkrun_hack(sc, 1); 1006 rv = cs428x_write_codec(addr, reg, data); 1007 cs4280_clkrun_hack(sc, -1); 1008 1009 return rv; 1010 } 1011 1012 #if 0 /* XXX buggy and not required */ 1013 /* control AC97 codec */ 1014 static int 1015 cs4280_reset_codec(void *addr) 1016 { 1017 struct cs428x_softc *sc; 1018 int n; 1019 1020 sc = addr; 1021 1022 /* Reset codec */ 1023 BA0WRITE4(sc, CS428X_ACCTL, 0); 1024 delay(100); /* delay 100us */ 1025 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1026 1027 /* 1028 * It looks like we do the following procedure, too 1029 */ 1030 1031 /* Enable AC-link sync generation */ 1032 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1033 delay(50*1000); /* XXX delay 50ms */ 1034 1035 /* Assert valid frame signal */ 1036 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1037 1038 /* Wait for valid AC97 input slot */ 1039 n = 0; 1040 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1041 (ACISV_ISV3 | ACISV_ISV4)) { 1042 delay(1000); 1043 if (++n > 1000) { 1044 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1045 return ETIMEDOUT; 1046 } 1047 } 1048 1049 return 0; 1050 } 1051 #endif 1052 1053 static enum ac97_host_flags cs4280_flags_codec(void *addr) 1054 { 1055 struct cs428x_softc *sc; 1056 1057 sc = addr; 1058 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1059 return AC97_HOST_INVERTED_EAMP; 1060 1061 return 0; 1062 } 1063 1064 /* Internal functions */ 1065 1066 static const struct cs4280_card_t * 1067 cs4280_identify_card(struct pci_attach_args *pa) 1068 { 1069 pcireg_t idreg; 1070 u_int16_t i; 1071 1072 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1073 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1074 if (idreg == cs4280_cards[i].id) 1075 return &cs4280_cards[i]; 1076 } 1077 1078 return NULL; 1079 } 1080 1081 static int 1082 cs4280_piix4_match(struct pci_attach_args *pa) 1083 { 1084 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1085 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1086 return 1; 1087 } 1088 1089 return 0; 1090 } 1091 1092 static void 1093 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1094 { 1095 uint16_t control, val; 1096 1097 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1098 return; 1099 1100 sc->sc_active += change; 1101 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1102 if (!sc->sc_active) 1103 val |= 0x2000; 1104 else 1105 val &= ~0x2000; 1106 if (val != control) 1107 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1108 } 1109 1110 static void 1111 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1112 { 1113 struct pci_attach_args smbuspa; 1114 uint16_t reg; 1115 pcireg_t port; 1116 1117 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1118 return; 1119 1120 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1121 sc->sc_active = 0; 1122 aprint_normal_dev(&sc->sc_dev, "enabling CLKRUN hack\n"); 1123 1124 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1125 port = reg & 0xffc0; 1126 aprint_normal_dev(&sc->sc_dev, "power management port 0x%x\n", 1127 port); 1128 1129 sc->sc_pm_iot = smbuspa.pa_iot; 1130 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1131 &sc->sc_pm_ioh) == 0) 1132 return; 1133 } 1134 1135 /* handle error */ 1136 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1137 aprint_normal_dev(&sc->sc_dev, "disabling CLKRUN hack\n"); 1138 } 1139 1140 static void 1141 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1142 { 1143 /* calculate capture rate: 1144 * 1145 * capture_coefficient_increment = -round(rate*128*65536/48000; 1146 * capture_phase_increment = floor(48000*65536*1024/rate); 1147 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1148 * cy = floor(cx/200); 1149 * capture_sample_rate_correction = cx - 200*cy; 1150 * capture_delay = ceil(24*48000/rate); 1151 * capture_num_triplets = floor(65536*rate/24000); 1152 * capture_group_length = 24000/GCD(rate, 24000); 1153 * where GCD means "Greatest Common Divisor". 1154 * 1155 * capture_coefficient_increment, capture_phase_increment and 1156 * capture_num_triplets are 32-bit signed quantities. 1157 * capture_sample_rate_correction and capture_group_length are 1158 * 16-bit signed quantities. 1159 * capture_delay is a 14-bit unsigned quantity. 1160 */ 1161 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1162 uint16_t csrc, cgl, cdlay; 1163 1164 /* XXX 1165 * Even though, embedded_audio_spec says capture rate range 11025 to 1166 * 48000, dhwiface.cpp says, 1167 * 1168 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1169 * Return an error if an attempt is made to stray outside that limit." 1170 * 1171 * so assume range as 48000/9 to 48000 1172 */ 1173 1174 if (rate < 8000) 1175 rate = 8000; 1176 if (rate > 48000) 1177 rate = 48000; 1178 1179 cx = rate << 16; 1180 cci = cx / 48000; 1181 cx -= cci * 48000; 1182 cx <<= 7; 1183 cci <<= 7; 1184 cci += cx / 48000; 1185 cci = - cci; 1186 1187 cx = 48000 << 16; 1188 cpi = cx / rate; 1189 cx -= cpi * rate; 1190 cx <<= 10; 1191 cpi <<= 10; 1192 cy = cx / rate; 1193 cpi += cy; 1194 cx -= cy * rate; 1195 1196 cy = cx / 200; 1197 csrc = cx - 200*cy; 1198 1199 cdlay = ((48000 * 24) + rate - 1) / rate; 1200 #if 0 1201 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1202 #endif 1203 1204 cnt = rate << 16; 1205 cnt /= 24000; 1206 1207 cgl = 1; 1208 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1209 if (((rate / tmp1) * tmp1) != rate) 1210 cgl *= 2; 1211 } 1212 if (((rate / 3) * 3) != rate) 1213 cgl *= 3; 1214 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1215 if (((rate / tmp1) * tmp1) != rate) 1216 cgl *= 5; 1217 } 1218 #if 0 1219 /* XXX what manual says */ 1220 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1221 tmp1 |= csrc<<16; 1222 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1223 #else 1224 /* suggested by cs461x.c (ALSA driver) */ 1225 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1226 #endif 1227 1228 #if 0 1229 /* I am confused. The sample rate calculation section says 1230 * cci *is* 32-bit signed quantity but in the parameter description 1231 * section, CCI only assigned 16bit. 1232 * I believe size of the variable. 1233 */ 1234 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1235 tmp1 |= cci<<16; 1236 BA1WRITE4(sc, CS4280_CCI, tmp1); 1237 #else 1238 BA1WRITE4(sc, CS4280_CCI, cci); 1239 #endif 1240 1241 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1242 tmp1 |= cdlay <<18; 1243 BA1WRITE4(sc, CS4280_CD, tmp1); 1244 1245 BA1WRITE4(sc, CS4280_CPI, cpi); 1246 1247 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1248 tmp1 |= cgl; 1249 BA1WRITE4(sc, CS4280_CGL, tmp1); 1250 1251 BA1WRITE4(sc, CS4280_CNT, cnt); 1252 1253 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1254 tmp1 |= cgl; 1255 BA1WRITE4(sc, CS4280_CGC, tmp1); 1256 } 1257 1258 static void 1259 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1260 { 1261 /* 1262 * playback rate may range from 8000Hz to 48000Hz 1263 * 1264 * play_phase_increment = floor(rate*65536*1024/48000) 1265 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1266 * py=floor(px/200) 1267 * play_sample_rate_correction = px - 200*py 1268 * 1269 * play_phase_increment is a 32bit signed quantity. 1270 * play_sample_rate_correction is a 16bit signed quantity. 1271 */ 1272 int32_t ppi; 1273 int16_t psrc; 1274 uint32_t px, py; 1275 1276 if (rate < 8000) 1277 rate = 8000; 1278 if (rate > 48000) 1279 rate = 48000; 1280 px = rate << 16; 1281 ppi = px/48000; 1282 px -= ppi*48000; 1283 ppi <<= 10; 1284 px <<= 10; 1285 py = px / 48000; 1286 ppi += py; 1287 px -= py*48000; 1288 py = px/200; 1289 px -= py*200; 1290 psrc = px; 1291 #if 0 1292 /* what manual says */ 1293 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1294 BA1WRITE4(sc, CS4280_PSRC, 1295 ( ((psrc<<16) & PSRC_MASK) | px )); 1296 #else 1297 /* suggested by cs461x.c (ALSA driver) */ 1298 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1299 #endif 1300 BA1WRITE4(sc, CS4280_PPI, ppi); 1301 } 1302 1303 /* Download Processor Code and Data image */ 1304 static int 1305 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1306 uint32_t offset, uint32_t len) 1307 { 1308 uint32_t ctr; 1309 #if CS4280_DEBUG > 10 1310 uint32_t con, data; 1311 uint8_t c0, c1, c2, c3; 1312 #endif 1313 if ((offset & 3) || (len & 3)) 1314 return -1; 1315 1316 len /= sizeof(uint32_t); 1317 for (ctr = 0; ctr < len; ctr++) { 1318 /* XXX: 1319 * I cannot confirm this is the right thing or not 1320 * on BIG-ENDIAN machines. 1321 */ 1322 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1323 #if CS4280_DEBUG > 10 1324 data = htole32(*(src+ctr)); 1325 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1326 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1327 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1328 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1329 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1330 if (data != con ) { 1331 printf("0x%06x: write=0x%08x read=0x%08x\n", 1332 offset+ctr*4, data, con); 1333 return -1; 1334 } 1335 #endif 1336 } 1337 return 0; 1338 } 1339 1340 static int 1341 cs4280_download_image(struct cs428x_softc *sc) 1342 { 1343 int idx, err; 1344 uint32_t offset = 0; 1345 1346 err = 0; 1347 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1348 err = cs4280_download(sc, &BA1Struct.map[offset], 1349 BA1Struct.memory[idx].offset, 1350 BA1Struct.memory[idx].size); 1351 if (err != 0) { 1352 aprint_error_dev(&sc->sc_dev, 1353 "load_image failed at %d\n", idx); 1354 return -1; 1355 } 1356 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1357 } 1358 return err; 1359 } 1360 1361 /* Processor Soft Reset */ 1362 static void 1363 cs4280_reset(void *sc_) 1364 { 1365 struct cs428x_softc *sc; 1366 1367 sc = sc_; 1368 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1369 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1370 delay(100); 1371 /* Clear RSTSP bit in SPCR */ 1372 BA1WRITE4(sc, CS4280_SPCR, 0); 1373 /* enable DMA reqest */ 1374 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1375 } 1376 1377 static int 1378 cs4280_init(struct cs428x_softc *sc, int init) 1379 { 1380 int n; 1381 uint32_t mem; 1382 int rv; 1383 1384 rv = 1; 1385 cs4280_clkrun_hack(sc, 1); 1386 1387 /* Start PLL out in known state */ 1388 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1389 /* Start serial ports out in known state */ 1390 BA0WRITE4(sc, CS4280_SERMC1, 0); 1391 1392 /* Specify type of CODEC */ 1393 /* XXX should not be here */ 1394 #define SERACC_CODEC_TYPE_1_03 1395 #ifdef SERACC_CODEC_TYPE_1_03 1396 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1397 #else 1398 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1399 #endif 1400 1401 /* Reset codec */ 1402 BA0WRITE4(sc, CS428X_ACCTL, 0); 1403 delay(100); /* delay 100us */ 1404 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1405 1406 /* Enable AC-link sync generation */ 1407 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1408 delay(50*1000); /* delay 50ms */ 1409 1410 /* Set the serial port timing configuration */ 1411 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1412 1413 /* Setup clock control */ 1414 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1415 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1416 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1417 1418 /* Power up the PLL */ 1419 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1420 delay(50*1000); /* delay 50ms */ 1421 1422 /* Turn on clock */ 1423 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1424 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1425 1426 /* Set the serial port FIFO pointer to the 1427 * first sample in FIFO. (not documented) */ 1428 cs4280_clear_fifos(sc); 1429 1430 #if 0 1431 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1432 BA0WRITE4(sc, CS4280_SERBSP, 0); 1433 #endif 1434 1435 /* Configure the serial port */ 1436 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1437 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1438 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1439 1440 /* Wait for CODEC ready */ 1441 n = 0; 1442 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1443 delay(125); 1444 if (++n > 1000) { 1445 aprint_error_dev(&sc->sc_dev, "codec ready timeout\n"); 1446 goto exit; 1447 } 1448 } 1449 1450 /* Assert valid frame signal */ 1451 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1452 1453 /* Wait for valid AC97 input slot */ 1454 n = 0; 1455 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1456 (ACISV_ISV3 | ACISV_ISV4)) { 1457 delay(1000); 1458 if (++n > 1000) { 1459 printf("AC97 inputs slot ready timeout\n"); 1460 goto exit; 1461 } 1462 } 1463 1464 /* Set AC97 output slot valid signals */ 1465 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1466 1467 /* reset the processor */ 1468 cs4280_reset(sc); 1469 1470 /* Download the image to the processor */ 1471 if (cs4280_download_image(sc) != 0) { 1472 aprint_error_dev(&sc->sc_dev, "image download error\n"); 1473 goto exit; 1474 } 1475 1476 /* Save playback parameter and then write zero. 1477 * this ensures that DMA doesn't immediately occur upon 1478 * starting the processor core 1479 */ 1480 mem = BA1READ4(sc, CS4280_PCTL); 1481 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1482 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1483 if (init != 0) 1484 sc->sc_prun = 0; 1485 1486 /* Save capture parameter and then write zero. 1487 * this ensures that DMA doesn't immediately occur upon 1488 * starting the processor core 1489 */ 1490 mem = BA1READ4(sc, CS4280_CCTL); 1491 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1492 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1493 if (init != 0) 1494 sc->sc_rrun = 0; 1495 1496 /* Processor Startup Procedure */ 1497 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1498 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1499 1500 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1501 n = 0; 1502 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1503 delay(10); 1504 if (++n > 1000) { 1505 printf("SPCR 1->0 transition timeout\n"); 1506 goto exit; 1507 } 1508 } 1509 1510 n = 0; 1511 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1512 delay(10); 1513 if (++n > 1000) { 1514 printf("SPCS 0->1 transition timeout\n"); 1515 goto exit; 1516 } 1517 } 1518 /* Processor is now running !!! */ 1519 1520 /* Setup volume */ 1521 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1522 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1523 1524 /* Interrupt enable */ 1525 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1526 1527 /* playback interrupt enable */ 1528 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1529 mem |= PFIE_PI_ENABLE; 1530 BA1WRITE4(sc, CS4280_PFIE, mem); 1531 /* capture interrupt enable */ 1532 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1533 mem |= CIE_CI_ENABLE; 1534 BA1WRITE4(sc, CS4280_CIE, mem); 1535 1536 #if NMIDI > 0 1537 /* Reset midi port */ 1538 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1539 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1540 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1541 /* midi interrupt enable */ 1542 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1543 BA0WRITE4(sc, CS4280_MIDCR, mem); 1544 #endif 1545 1546 rv = 0; 1547 1548 exit: 1549 cs4280_clkrun_hack(sc, -1); 1550 return rv; 1551 } 1552 1553 static void 1554 cs4280_clear_fifos(struct cs428x_softc *sc) 1555 { 1556 int pd, cnt, n; 1557 uint32_t mem; 1558 1559 pd = 0; 1560 /* 1561 * If device power down, power up the device and keep power down 1562 * state. 1563 */ 1564 mem = BA0READ4(sc, CS4280_CLKCR1); 1565 if (!(mem & CLKCR1_SWCE)) { 1566 printf("cs4280_clear_fifo: power down found.\n"); 1567 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1568 pd = 1; 1569 } 1570 BA0WRITE4(sc, CS4280_SERBWP, 0); 1571 for (cnt = 0; cnt < 256; cnt++) { 1572 n = 0; 1573 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1574 delay(1000); 1575 if (++n > 1000) { 1576 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1577 break; 1578 } 1579 } 1580 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1581 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1582 } 1583 if (pd) 1584 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1585 } 1586 1587 #if NMIDI > 0 1588 static int 1589 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1590 void (*ointr)(void *), void *arg) 1591 { 1592 struct cs428x_softc *sc; 1593 uint32_t mem; 1594 1595 DPRINTF(("midi_open\n")); 1596 sc = addr; 1597 sc->sc_iintr = iintr; 1598 sc->sc_ointr = ointr; 1599 sc->sc_arg = arg; 1600 1601 /* midi interrupt enable */ 1602 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1603 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1604 BA0WRITE4(sc, CS4280_MIDCR, mem); 1605 #ifdef CS4280_DEBUG 1606 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1607 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1608 return(EINVAL); 1609 } 1610 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1611 #endif 1612 return 0; 1613 } 1614 1615 static void 1616 cs4280_midi_close(void *addr) 1617 { 1618 struct cs428x_softc *sc; 1619 uint32_t mem; 1620 1621 DPRINTF(("midi_close\n")); 1622 sc = addr; 1623 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1624 mem = BA0READ4(sc, CS4280_MIDCR); 1625 mem &= ~MIDCR_MASK; 1626 BA0WRITE4(sc, CS4280_MIDCR, mem); 1627 1628 sc->sc_iintr = 0; 1629 sc->sc_ointr = 0; 1630 } 1631 1632 static int 1633 cs4280_midi_output(void *addr, int d) 1634 { 1635 struct cs428x_softc *sc; 1636 uint32_t mem; 1637 int x; 1638 1639 sc = addr; 1640 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1641 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1642 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1643 mem |= d & MIDWP_MASK; 1644 DPRINTFN(5,("midi_output d=0x%08x",d)); 1645 BA0WRITE4(sc, CS4280_MIDWP, mem); 1646 #ifdef DIAGNOSTIC 1647 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1648 DPRINTF(("Bad write data: %d %d", 1649 mem, BA0READ4(sc, CS4280_MIDWP))); 1650 return EIO; 1651 } 1652 #endif 1653 return 0; 1654 } 1655 delay(MIDI_BUSY_DELAY); 1656 } 1657 return EIO; 1658 } 1659 1660 static void 1661 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1662 { 1663 1664 mi->name = "CS4280 MIDI UART"; 1665 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1666 } 1667 1668 #endif /* NMIDI */ 1669 1670 /* DEBUG functions */ 1671 #if CS4280_DEBUG > 10 1672 static int 1673 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1674 uint32_t offset, uint32_t len) 1675 { 1676 uint32_t ctr, data; 1677 int err; 1678 1679 if ((offset & 3) || (len & 3)) 1680 return -1; 1681 1682 err = 0; 1683 len /= sizeof(uint32_t); 1684 for (ctr = 0; ctr < len; ctr++) { 1685 /* I cannot confirm this is the right thing 1686 * on BIG-ENDIAN machines 1687 */ 1688 data = BA1READ4(sc, offset+ctr*4); 1689 if (data != htole32(*(src+ctr))) { 1690 printf("0x%06x: 0x%08x(0x%08x)\n", 1691 offset+ctr*4, data, *(src+ctr)); 1692 *(src+ctr) = data; 1693 ++err; 1694 } 1695 } 1696 return err; 1697 } 1698 1699 static int 1700 cs4280_check_images(struct cs428x_softc *sc) 1701 { 1702 int idx, err; 1703 uint32_t offset; 1704 1705 offset = 0; 1706 err = 0; 1707 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1708 for (idx = 0; idx < 1; ++idx) { 1709 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1710 BA1Struct.memory[idx].offset, 1711 BA1Struct.memory[idx].size); 1712 if (err != 0) { 1713 aprint_error_dev(&sc->sc_dev, 1714 "check_image failed at %d\n", idx); 1715 } 1716 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1717 } 1718 return err; 1719 } 1720 1721 #endif /* CS4280_DEBUG */ 1722
Indexes created Thu Oct 02 14:10:14 GMT 2025