cs4280.c revision 1.51.16.1
1 /* $NetBSD: cs4280.c,v 1.51.16.1 2008/12/11 19:49:30 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.51.16.1 2008/12/11 19:49:30 ad Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <sys/bus.h> 86 #include <sys/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(struct device *, struct cfdata *, void *); 93 static void cs4280_attach(struct device *, struct device *, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 107 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 108 #if 0 109 static int cs4280_reset_codec(void *); 110 #endif 111 static enum ac97_host_flags cs4280_flags_codec(void *); 112 113 static bool cs4280_resume(device_t PMF_FN_PROTO); 114 static bool cs4280_suspend(device_t PMF_FN_PROTO); 115 116 /* Internal functions */ 117 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *); 118 static int cs4280_piix4_match(struct pci_attach_args *); 119 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 120 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 121 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 122 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 123 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 124 uint32_t); 125 static int cs4280_download_image(struct cs428x_softc *); 126 static void cs4280_reset(void *); 127 static int cs4280_init(struct cs428x_softc *, int); 128 static void cs4280_clear_fifos(struct cs428x_softc *); 129 130 #if CS4280_DEBUG > 10 131 /* Thease two function is only for checking image loading is succeeded or not. */ 132 static int cs4280_check_images(struct cs428x_softc *); 133 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 134 uint32_t); 135 #endif 136 137 /* Special cards */ 138 struct cs4280_card_t 139 { 140 pcireg_t id; 141 enum cs428x_flags flags; 142 }; 143 144 #define _card(vend, prod, flags) \ 145 {PCI_ID_CODE(vend, prod), flags} 146 147 static const struct cs4280_card_t cs4280_cards[] = { 148 #if 0 /* untested, from ALSA driver */ 149 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 150 CS428X_FLAG_INVAC97EAMP), 151 #endif 152 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 153 CS428X_FLAG_INVAC97EAMP), 154 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 155 CS428X_FLAG_CLKRUNHACK) 156 }; 157 158 #undef _card 159 160 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 161 162 static const struct audio_hw_if cs4280_hw_if = { 163 NULL, /* open */ 164 NULL, /* close */ 165 NULL, 166 cs4280_query_encoding, 167 cs4280_set_params, 168 cs428x_round_blocksize, 169 NULL, 170 NULL, 171 NULL, 172 NULL, 173 NULL, 174 cs4280_halt_output, 175 cs4280_halt_input, 176 NULL, 177 cs4280_getdev, 178 NULL, 179 cs428x_mixer_set_port, 180 cs428x_mixer_get_port, 181 cs428x_query_devinfo, 182 cs428x_malloc, 183 cs428x_free, 184 cs428x_round_buffersize, 185 cs428x_mappage, 186 cs428x_get_props, 187 cs4280_trigger_output, 188 cs4280_trigger_input, 189 NULL, 190 NULL, 191 cs428x_get_locks, 192 }; 193 194 #if NMIDI > 0 195 /* Midi Interface */ 196 static int cs4280_midi_open(void *, int, void (*)(void *, int), 197 void (*)(void *), void *); 198 static void cs4280_midi_close(void*); 199 static int cs4280_midi_output(void *, int); 200 static void cs4280_midi_getinfo(void *, struct midi_info *); 201 202 static const struct midi_hw_if cs4280_midi_hw_if = { 203 cs4280_midi_open, 204 cs4280_midi_close, 205 cs4280_midi_output, 206 cs4280_midi_getinfo, 207 0, 208 cs428x_get_locks, 209 }; 210 #endif 211 212 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 213 cs4280_match, cs4280_attach, NULL, NULL); 214 215 static struct audio_device cs4280_device = { 216 "CS4280", 217 "", 218 "cs4280" 219 }; 220 221 222 static int 223 cs4280_match(struct device *parent, struct cfdata *match, 224 void *aux) 225 { 226 struct pci_attach_args *pa; 227 228 pa = (struct pci_attach_args *)aux; 229 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 230 return 0; 231 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 232 #if 0 /* I can't confirm */ 233 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 234 #endif 235 ) 236 return 1; 237 return 0; 238 } 239 240 static void 241 cs4280_attach(struct device *parent, struct device *self, void *aux) 242 { 243 struct cs428x_softc *sc; 244 struct pci_attach_args *pa; 245 pci_chipset_tag_t pc; 246 const struct cs4280_card_t *cs_card; 247 char const *intrstr; 248 pcireg_t reg; 249 char devinfo[256]; 250 uint32_t mem; 251 int error; 252 253 sc = (struct cs428x_softc *)self; 254 pa = (struct pci_attach_args *)aux; 255 pc = pa->pa_pc; 256 aprint_naive(": Audio controller\n"); 257 258 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 259 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 260 PCI_REVISION(pa->pa_class)); 261 262 cs_card = cs4280_identify_card(pa); 263 if (cs_card != NULL) { 264 aprint_normal_dev(&sc->sc_dev, "%s %s\n", 265 pci_findvendor(cs_card->id), 266 pci_findproduct(cs_card->id)); 267 sc->sc_flags = cs_card->flags; 268 } else { 269 sc->sc_flags = CS428X_FLAG_NONE; 270 } 271 272 sc->sc_pc = pa->pa_pc; 273 sc->sc_pt = pa->pa_tag; 274 275 /* Map I/O register */ 276 if (pci_mapreg_map(pa, PCI_BA0, 277 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 278 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 279 aprint_error_dev(&sc->sc_dev, "can't map BA0 space\n"); 280 return; 281 } 282 if (pci_mapreg_map(pa, PCI_BA1, 283 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 284 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 285 aprint_error_dev(&sc->sc_dev, "can't map BA1 space\n"); 286 return; 287 } 288 289 sc->sc_dmatag = pa->pa_dmat; 290 291 /* power up chip */ 292 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 293 pci_activate_null)) && error != EOPNOTSUPP) { 294 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 295 return; 296 } 297 298 /* Enable the device (set bus master flag) */ 299 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 300 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 301 reg | PCI_COMMAND_MASTER_ENABLE); 302 303 /* LATENCY_TIMER setting */ 304 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 305 if ( PCI_LATTIMER(mem) < 32 ) { 306 mem &= 0xffff00ff; 307 mem |= 0x00002000; 308 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 309 } 310 311 /* CLKRUN hack initialization */ 312 cs4280_clkrun_hack_init(sc); 313 314 /* Map and establish the interrupt. */ 315 if (pci_intr_map(pa, &sc->intrh)) { 316 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 317 return; 318 } 319 intrstr = pci_intr_string(pc, sc->intrh); 320 321 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 322 cs4280_intr, sc); 323 if (sc->sc_ih == NULL) { 324 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 325 if (intrstr != NULL) 326 aprint_normal(" at %s", intrstr); 327 aprint_normal("\n"); 328 return; 329 } 330 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 331 332 /* Initialization */ 333 if(cs4280_init(sc, 1) != 0) 334 return; 335 336 sc->type = TYPE_CS4280; 337 sc->halt_input = cs4280_halt_input; 338 sc->halt_output = cs4280_halt_output; 339 340 /* setup buffer related parameters */ 341 sc->dma_size = CS4280_DCHUNK; 342 sc->dma_align = CS4280_DALIGN; 343 sc->hw_blocksize = CS4280_ICHUNK; 344 345 /* AC 97 attachment */ 346 sc->host_if.arg = sc; 347 sc->host_if.attach = cs428x_attach_codec; 348 sc->host_if.read = cs4280_read_codec; 349 sc->host_if.write = cs4280_write_codec; 350 #if 0 351 sc->host_if.reset = cs4280_reset_codec; 352 #else 353 sc->host_if.reset = NULL; 354 #endif 355 sc->host_if.flags = cs4280_flags_codec; 356 if (ac97_attach(&sc->host_if, self) != 0) { 357 aprint_error_dev(&sc->sc_dev, "ac97_attach failed\n"); 358 return; 359 } 360 361 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 362 363 #if NMIDI > 0 364 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 365 #endif 366 367 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 368 aprint_error_dev(self, "couldn't establish power handler\n"); 369 } 370 371 /* Interrupt handling function */ 372 static int 373 cs4280_intr(void *p) 374 { 375 /* 376 * XXX 377 * 378 * Since CS4280 has only 4kB DMA buffer and 379 * interrupt occurs every 2kB block, I create dummy buffer 380 * which returns to audio driver and actual DMA buffer 381 * using in DMA transfer. 382 * 383 * 384 * ring buffer in audio.c is pointed by BUFADDR 385 * <------ ring buffer size == 64kB ------> 386 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 387 * |= = = =|= = = =|= = = =|= = = =|= = = =| 388 * | | | | | | <- call audio_intp every 389 * sc->sc_[pr]_count time. 390 * 391 * actual DMA buffer is pointed by KERNADDR 392 * <-> DMA buffer size = 4kB 393 * |= =| 394 * 395 * 396 */ 397 struct cs428x_softc *sc; 398 uint32_t intr, mem; 399 char * empty_dma; 400 int handled; 401 402 sc = p; 403 handled = 0; 404 405 mutex_enter(&sc->sc_intr_lock); 406 407 /* grab interrupt register then clear it */ 408 intr = BA0READ4(sc, CS4280_HISR); 409 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 410 411 /* not for us ? */ 412 if ((intr & HISR_INTENA) == 0) { 413 mutex_spin_exit(&sc->sc_intr_lock); 414 return 0; 415 } 416 417 /* Playback Interrupt */ 418 if (intr & HISR_PINT) { 419 handled = 1; 420 mem = BA1READ4(sc, CS4280_PFIE); 421 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 422 if (sc->sc_prun) { 423 if ((sc->sc_pi%sc->sc_pcount) == 0) 424 sc->sc_pintr(sc->sc_parg); 425 /* copy buffer */ 426 ++sc->sc_pi; 427 empty_dma = sc->sc_pdma->addr; 428 if (sc->sc_pi&1) 429 empty_dma += sc->hw_blocksize; 430 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 431 sc->sc_pn += sc->hw_blocksize; 432 if (sc->sc_pn >= sc->sc_pe) 433 sc->sc_pn = sc->sc_ps; 434 } else { 435 aprint_error_dev(&sc->sc_dev, "unexpected play intr\n"); 436 } 437 BA1WRITE4(sc, CS4280_PFIE, mem); 438 } 439 /* Capture Interrupt */ 440 if (intr & HISR_CINT) { 441 int i; 442 int16_t rdata; 443 444 handled = 1; 445 mem = BA1READ4(sc, CS4280_CIE); 446 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 447 448 if (sc->sc_rrun) { 449 ++sc->sc_ri; 450 empty_dma = sc->sc_rdma->addr; 451 if ((sc->sc_ri&1) == 0) 452 empty_dma += sc->hw_blocksize; 453 454 /* 455 * XXX 456 * I think this audio data conversion should be 457 * happend in upper layer, but I put this here 458 * since there is no conversion function available. 459 */ 460 switch(sc->sc_rparam) { 461 case CF_16BIT_STEREO: 462 /* just copy it */ 463 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 464 sc->sc_rn += sc->hw_blocksize; 465 break; 466 case CF_16BIT_MONO: 467 for (i = 0; i < 512; i++) { 468 rdata = *((int16_t *)empty_dma)>>1; 469 empty_dma += 2; 470 rdata += *((int16_t *)empty_dma)>>1; 471 empty_dma += 2; 472 *((int16_t *)sc->sc_rn) = rdata; 473 sc->sc_rn += 2; 474 } 475 break; 476 case CF_8BIT_STEREO: 477 for (i = 0; i < 512; i++) { 478 rdata = *((int16_t*)empty_dma); 479 empty_dma += 2; 480 *sc->sc_rn++ = rdata >> 8; 481 rdata = *((int16_t*)empty_dma); 482 empty_dma += 2; 483 *sc->sc_rn++ = rdata >> 8; 484 } 485 break; 486 case CF_8BIT_MONO: 487 for (i = 0; i < 512; i++) { 488 rdata = *((int16_t*)empty_dma) >>1; 489 empty_dma += 2; 490 rdata += *((int16_t*)empty_dma) >>1; 491 empty_dma += 2; 492 *sc->sc_rn++ = rdata >>8; 493 } 494 break; 495 default: 496 /* Should not reach here */ 497 aprint_error_dev(&sc->sc_dev, 498 "unknown sc->sc_rparam: %d\n", 499 sc->sc_rparam); 500 } 501 if (sc->sc_rn >= sc->sc_re) 502 sc->sc_rn = sc->sc_rs; 503 } 504 BA1WRITE4(sc, CS4280_CIE, mem); 505 506 if (sc->sc_rrun) { 507 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 508 sc->sc_rintr(sc->sc_rarg); 509 } else { 510 aprint_error_dev(&sc->sc_dev, 511 "unexpected record intr\n"); 512 } 513 } 514 515 #if NMIDI > 0 516 /* Midi port Interrupt */ 517 if (intr & HISR_MIDI) { 518 int data; 519 520 handled = 1; 521 DPRINTF(("i: %d: ", 522 BA0READ4(sc, CS4280_MIDSR))); 523 /* Read the received data */ 524 while ((sc->sc_iintr != NULL) && 525 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 526 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 527 DPRINTF(("r:%x\n",data)); 528 sc->sc_iintr(sc->sc_arg, data); 529 } 530 531 /* Write the data */ 532 #if 1 533 /* XXX: 534 * It seems "Transmit Buffer Full" never activate until EOI 535 * is deliverd. Shall I throw EOI top of this routine ? 536 */ 537 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 538 DPRINTF(("w: ")); 539 if (sc->sc_ointr != NULL) 540 sc->sc_ointr(sc->sc_arg); 541 } 542 #else 543 while ((sc->sc_ointr != NULL) && 544 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 545 DPRINTF(("w: ")); 546 sc->sc_ointr(sc->sc_arg); 547 } 548 #endif 549 DPRINTF(("\n")); 550 } 551 #endif 552 553 mutex_spin_exit(&sc->sc_intr_lock); 554 return handled; 555 } 556 557 static int 558 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 559 { 560 switch (fp->index) { 561 case 0: 562 strcpy(fp->name, AudioEulinear); 563 fp->encoding = AUDIO_ENCODING_ULINEAR; 564 fp->precision = 8; 565 fp->flags = 0; 566 break; 567 case 1: 568 strcpy(fp->name, AudioEmulaw); 569 fp->encoding = AUDIO_ENCODING_ULAW; 570 fp->precision = 8; 571 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 572 break; 573 case 2: 574 strcpy(fp->name, AudioEalaw); 575 fp->encoding = AUDIO_ENCODING_ALAW; 576 fp->precision = 8; 577 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 578 break; 579 case 3: 580 strcpy(fp->name, AudioEslinear); 581 fp->encoding = AUDIO_ENCODING_SLINEAR; 582 fp->precision = 8; 583 fp->flags = 0; 584 break; 585 case 4: 586 strcpy(fp->name, AudioEslinear_le); 587 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 588 fp->precision = 16; 589 fp->flags = 0; 590 break; 591 case 5: 592 strcpy(fp->name, AudioEulinear_le); 593 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 594 fp->precision = 16; 595 fp->flags = 0; 596 break; 597 case 6: 598 strcpy(fp->name, AudioEslinear_be); 599 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 600 fp->precision = 16; 601 fp->flags = 0; 602 break; 603 case 7: 604 strcpy(fp->name, AudioEulinear_be); 605 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 606 fp->precision = 16; 607 fp->flags = 0; 608 break; 609 default: 610 return EINVAL; 611 } 612 return 0; 613 } 614 615 static int 616 cs4280_set_params(void *addr, int setmode, int usemode, 617 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 618 stream_filter_list_t *rfil) 619 { 620 audio_params_t hw; 621 struct cs428x_softc *sc; 622 struct audio_params *p; 623 stream_filter_list_t *fil; 624 int mode; 625 626 sc = addr; 627 for (mode = AUMODE_RECORD; mode != -1; 628 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 629 if ((setmode & mode) == 0) 630 continue; 631 632 p = mode == AUMODE_PLAY ? play : rec; 633 634 if (p == play) { 635 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 636 p->sample_rate, p->precision, p->channels)); 637 /* play back data format may be 8- or 16-bit and 638 * either stereo or mono. 639 * playback rate may range from 8000Hz to 48000Hz 640 */ 641 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 642 (p->precision != 8 && p->precision != 16) || 643 (p->channels != 1 && p->channels != 2) ) { 644 return EINVAL; 645 } 646 } else { 647 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 648 p->sample_rate, p->precision, p->channels)); 649 /* capture data format must be 16bit stereo 650 * and sample rate range from 11025Hz to 48000Hz. 651 * 652 * XXX: it looks like to work with 8000Hz, 653 * although data sheets say lower limit is 654 * 11025 Hz. 655 */ 656 657 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 658 (p->precision != 8 && p->precision != 16) || 659 (p->channels != 1 && p->channels != 2) ) { 660 return EINVAL; 661 } 662 } 663 fil = mode == AUMODE_PLAY ? pfil : rfil; 664 hw = *p; 665 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 666 667 /* capturing data is slinear */ 668 switch (p->encoding) { 669 case AUDIO_ENCODING_SLINEAR_BE: 670 if (mode == AUMODE_RECORD && p->precision == 16) { 671 fil->append(fil, swap_bytes, &hw); 672 } 673 break; 674 case AUDIO_ENCODING_SLINEAR_LE: 675 break; 676 case AUDIO_ENCODING_ULINEAR_BE: 677 if (mode == AUMODE_RECORD) { 678 fil->append(fil, p->precision == 16 679 ? swap_bytes_change_sign16 680 : change_sign8, &hw); 681 } 682 break; 683 case AUDIO_ENCODING_ULINEAR_LE: 684 if (mode == AUMODE_RECORD) { 685 fil->append(fil, p->precision == 16 686 ? change_sign16 : change_sign8, 687 &hw); 688 } 689 break; 690 case AUDIO_ENCODING_ULAW: 691 if (mode == AUMODE_PLAY) { 692 hw.precision = 16; 693 hw.validbits = 16; 694 fil->append(fil, mulaw_to_linear16, &hw); 695 } else { 696 fil->append(fil, linear8_to_mulaw, &hw); 697 } 698 break; 699 case AUDIO_ENCODING_ALAW: 700 if (mode == AUMODE_PLAY) { 701 hw.precision = 16; 702 hw.validbits = 16; 703 fil->append(fil, alaw_to_linear16, &hw); 704 } else { 705 fil->append(fil, linear8_to_alaw, &hw); 706 } 707 break; 708 default: 709 return EINVAL; 710 } 711 } 712 713 /* set sample rate */ 714 cs4280_set_dac_rate(sc, play->sample_rate); 715 cs4280_set_adc_rate(sc, rec->sample_rate); 716 return 0; 717 } 718 719 static int 720 cs4280_halt_output(void *addr) 721 { 722 struct cs428x_softc *sc; 723 uint32_t mem; 724 725 sc = addr; 726 mem = BA1READ4(sc, CS4280_PCTL); 727 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 728 sc->sc_prun = 0; 729 cs4280_clkrun_hack(sc, -1); 730 731 return 0; 732 } 733 734 static int 735 cs4280_halt_input(void *addr) 736 { 737 struct cs428x_softc *sc; 738 uint32_t mem; 739 740 sc = addr; 741 mem = BA1READ4(sc, CS4280_CCTL); 742 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 743 sc->sc_rrun = 0; 744 cs4280_clkrun_hack(sc, -1); 745 746 return 0; 747 } 748 749 static int 750 cs4280_getdev(void *addr, struct audio_device *retp) 751 { 752 753 *retp = cs4280_device; 754 return 0; 755 } 756 757 static int 758 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 759 void (*intr)(void *), void *arg, 760 const audio_params_t *param) 761 { 762 struct cs428x_softc *sc; 763 uint32_t pfie, pctl, pdtc; 764 struct cs428x_dma *p; 765 766 sc = addr; 767 #ifdef DIAGNOSTIC 768 if (sc->sc_prun) 769 printf("cs4280_trigger_output: already running\n"); 770 #endif 771 sc->sc_prun = 1; 772 cs4280_clkrun_hack(sc, 1); 773 774 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 775 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 776 sc->sc_pintr = intr; 777 sc->sc_parg = arg; 778 779 /* stop playback DMA */ 780 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 781 782 /* setup PDTC */ 783 pdtc = BA1READ4(sc, CS4280_PDTC); 784 pdtc &= ~PDTC_MASK; 785 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 786 BA1WRITE4(sc, CS4280_PDTC, pdtc); 787 788 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 789 param->precision, param->channels, param->encoding)); 790 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 791 continue; 792 if (p == NULL) { 793 printf("cs4280_trigger_output: bad addr %p\n", start); 794 return EINVAL; 795 } 796 if (DMAADDR(p) % sc->dma_align != 0 ) { 797 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 798 "4kB align\n", (ulong)DMAADDR(p)); 799 return EINVAL; 800 } 801 802 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 803 sc->sc_ps = (char *)start; 804 sc->sc_pe = (char *)end; 805 sc->sc_pdma = p; 806 sc->sc_pbuf = KERNADDR(p); 807 sc->sc_pi = 0; 808 sc->sc_pn = sc->sc_ps; 809 if (blksize >= sc->dma_size) { 810 sc->sc_pn = sc->sc_ps + sc->dma_size; 811 memcpy(sc->sc_pbuf, start, sc->dma_size); 812 ++sc->sc_pi; 813 } else { 814 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 815 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 816 } 817 818 /* initiate playback DMA */ 819 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 820 821 /* set PFIE */ 822 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 823 824 if (param->precision == 8) 825 pfie |= PFIE_8BIT; 826 if (param->channels == 1) 827 pfie |= PFIE_MONO; 828 829 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 830 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 831 pfie |= PFIE_SWAPPED; 832 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 833 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 834 pfie |= PFIE_UNSIGNED; 835 836 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 837 838 sc->sc_prate = param->sample_rate; 839 cs4280_set_dac_rate(sc, param->sample_rate); 840 841 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 842 pctl |= sc->pctl; 843 BA1WRITE4(sc, CS4280_PCTL, pctl); 844 return 0; 845 } 846 847 static int 848 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 849 void (*intr)(void *), void *arg, 850 const audio_params_t *param) 851 { 852 struct cs428x_softc *sc; 853 uint32_t cctl, cie; 854 struct cs428x_dma *p; 855 856 sc = addr; 857 #ifdef DIAGNOSTIC 858 if (sc->sc_rrun) 859 printf("cs4280_trigger_input: already running\n"); 860 #endif 861 sc->sc_rrun = 1; 862 cs4280_clkrun_hack(sc, 1); 863 864 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 865 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 866 sc->sc_rintr = intr; 867 sc->sc_rarg = arg; 868 869 /* stop capture DMA */ 870 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 871 872 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 873 continue; 874 if (p == NULL) { 875 printf("cs4280_trigger_input: bad addr %p\n", start); 876 return EINVAL; 877 } 878 if (DMAADDR(p) % sc->dma_align != 0) { 879 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 880 "4kB align\n", (ulong)DMAADDR(p)); 881 return EINVAL; 882 } 883 884 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 885 sc->sc_rs = (char *)start; 886 sc->sc_re = (char *)end; 887 sc->sc_rdma = p; 888 sc->sc_rbuf = KERNADDR(p); 889 sc->sc_ri = 0; 890 sc->sc_rn = sc->sc_rs; 891 892 /* initiate capture DMA */ 893 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 894 895 /* setup format information for internal converter */ 896 sc->sc_rparam = 0; 897 if (param->precision == 8) { 898 sc->sc_rparam += CF_8BIT; 899 sc->sc_rcount <<= 1; 900 } 901 if (param->channels == 1) { 902 sc->sc_rparam += CF_MONO; 903 sc->sc_rcount <<= 1; 904 } 905 906 /* set CIE */ 907 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 908 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 909 910 sc->sc_rrate = param->sample_rate; 911 cs4280_set_adc_rate(sc, param->sample_rate); 912 913 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 914 cctl |= sc->cctl; 915 BA1WRITE4(sc, CS4280_CCTL, cctl); 916 return 0; 917 } 918 919 static bool 920 cs4280_suspend(device_t dv PMF_FN_ARGS) 921 { 922 struct cs428x_softc *sc = device_private(dv); 923 924 if (sc->sc_prun) { 925 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 926 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 927 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 928 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 929 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 930 sc->sc_suspend_state.cs4280.pctl, 931 sc->sc_suspend_state.cs4280.pfie, 932 sc->sc_suspend_state.cs4280.pba, 933 sc->sc_suspend_state.cs4280.pdtc)); 934 } 935 936 /* save current capture status */ 937 if (sc->sc_rrun) { 938 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 939 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 940 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 941 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 942 sc->sc_suspend_state.cs4280.cctl, 943 sc->sc_suspend_state.cs4280.cie, 944 sc->sc_suspend_state.cs4280.cba)); 945 } 946 947 /* Stop DMA */ 948 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 949 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 950 951 return true; 952 } 953 954 static bool 955 cs4280_resume(device_t dv PMF_FN_ARGS) 956 { 957 struct cs428x_softc *sc = device_private(dv); 958 959 cs4280_init(sc, 0); 960 #if 0 961 cs4280_reset_codec(sc); 962 #endif 963 /* restore ac97 registers */ 964 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 965 966 /* restore DMA related status */ 967 if(sc->sc_prun) { 968 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 969 sc->sc_suspend_state.cs4280.pctl, 970 sc->sc_suspend_state.cs4280.pfie, 971 sc->sc_suspend_state.cs4280.pba, 972 sc->sc_suspend_state.cs4280.pdtc)); 973 cs4280_set_dac_rate(sc, sc->sc_prate); 974 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 975 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 976 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 977 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 978 } 979 980 if (sc->sc_rrun) { 981 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 982 sc->sc_suspend_state.cs4280.cctl, 983 sc->sc_suspend_state.cs4280.cie, 984 sc->sc_suspend_state.cs4280.cba)); 985 cs4280_set_adc_rate(sc, sc->sc_rrate); 986 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 987 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 988 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 989 } 990 991 return true; 992 } 993 994 static int 995 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 996 { 997 struct cs428x_softc *sc = addr; 998 int rv; 999 1000 cs4280_clkrun_hack(sc, 1); 1001 rv = cs428x_read_codec(addr, reg, result); 1002 cs4280_clkrun_hack(sc, -1); 1003 1004 return rv; 1005 } 1006 1007 static int 1008 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1009 { 1010 struct cs428x_softc *sc = addr; 1011 int rv; 1012 1013 cs4280_clkrun_hack(sc, 1); 1014 rv = cs428x_write_codec(addr, reg, data); 1015 cs4280_clkrun_hack(sc, -1); 1016 1017 return rv; 1018 } 1019 1020 #if 0 /* XXX buggy and not required */ 1021 /* control AC97 codec */ 1022 static int 1023 cs4280_reset_codec(void *addr) 1024 { 1025 struct cs428x_softc *sc; 1026 int n; 1027 1028 sc = addr; 1029 1030 /* Reset codec */ 1031 BA0WRITE4(sc, CS428X_ACCTL, 0); 1032 delay(100); /* delay 100us */ 1033 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1034 1035 /* 1036 * It looks like we do the following procedure, too 1037 */ 1038 1039 /* Enable AC-link sync generation */ 1040 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1041 delay(50*1000); /* XXX delay 50ms */ 1042 1043 /* Assert valid frame signal */ 1044 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1045 1046 /* Wait for valid AC97 input slot */ 1047 n = 0; 1048 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1049 (ACISV_ISV3 | ACISV_ISV4)) { 1050 delay(1000); 1051 if (++n > 1000) { 1052 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1053 return ETIMEDOUT; 1054 } 1055 } 1056 1057 return 0; 1058 } 1059 #endif 1060 1061 static enum ac97_host_flags cs4280_flags_codec(void *addr) 1062 { 1063 struct cs428x_softc *sc; 1064 1065 sc = addr; 1066 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1067 return AC97_HOST_INVERTED_EAMP; 1068 1069 return 0; 1070 } 1071 1072 /* Internal functions */ 1073 1074 static const struct cs4280_card_t * 1075 cs4280_identify_card(struct pci_attach_args *pa) 1076 { 1077 pcireg_t idreg; 1078 u_int16_t i; 1079 1080 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1081 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1082 if (idreg == cs4280_cards[i].id) 1083 return &cs4280_cards[i]; 1084 } 1085 1086 return NULL; 1087 } 1088 1089 static int 1090 cs4280_piix4_match(struct pci_attach_args *pa) 1091 { 1092 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1093 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1094 return 1; 1095 } 1096 1097 return 0; 1098 } 1099 1100 static void 1101 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1102 { 1103 uint16_t control, val; 1104 1105 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1106 return; 1107 1108 sc->sc_active += change; 1109 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1110 if (!sc->sc_active) 1111 val |= 0x2000; 1112 else 1113 val &= ~0x2000; 1114 if (val != control) 1115 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1116 } 1117 1118 static void 1119 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1120 { 1121 struct pci_attach_args smbuspa; 1122 uint16_t reg; 1123 pcireg_t port; 1124 1125 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1126 return; 1127 1128 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1129 sc->sc_active = 0; 1130 aprint_normal_dev(&sc->sc_dev, "enabling CLKRUN hack\n"); 1131 1132 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1133 port = reg & 0xffc0; 1134 aprint_normal_dev(&sc->sc_dev, "power management port 0x%x\n", 1135 port); 1136 1137 sc->sc_pm_iot = smbuspa.pa_iot; 1138 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1139 &sc->sc_pm_ioh) == 0) 1140 return; 1141 } 1142 1143 /* handle error */ 1144 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1145 aprint_normal_dev(&sc->sc_dev, "disabling CLKRUN hack\n"); 1146 } 1147 1148 static void 1149 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1150 { 1151 /* calculate capture rate: 1152 * 1153 * capture_coefficient_increment = -round(rate*128*65536/48000; 1154 * capture_phase_increment = floor(48000*65536*1024/rate); 1155 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1156 * cy = floor(cx/200); 1157 * capture_sample_rate_correction = cx - 200*cy; 1158 * capture_delay = ceil(24*48000/rate); 1159 * capture_num_triplets = floor(65536*rate/24000); 1160 * capture_group_length = 24000/GCD(rate, 24000); 1161 * where GCD means "Greatest Common Divisor". 1162 * 1163 * capture_coefficient_increment, capture_phase_increment and 1164 * capture_num_triplets are 32-bit signed quantities. 1165 * capture_sample_rate_correction and capture_group_length are 1166 * 16-bit signed quantities. 1167 * capture_delay is a 14-bit unsigned quantity. 1168 */ 1169 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1170 uint16_t csrc, cgl, cdlay; 1171 1172 /* XXX 1173 * Even though, embedded_audio_spec says capture rate range 11025 to 1174 * 48000, dhwiface.cpp says, 1175 * 1176 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1177 * Return an error if an attempt is made to stray outside that limit." 1178 * 1179 * so assume range as 48000/9 to 48000 1180 */ 1181 1182 if (rate < 8000) 1183 rate = 8000; 1184 if (rate > 48000) 1185 rate = 48000; 1186 1187 cx = rate << 16; 1188 cci = cx / 48000; 1189 cx -= cci * 48000; 1190 cx <<= 7; 1191 cci <<= 7; 1192 cci += cx / 48000; 1193 cci = - cci; 1194 1195 cx = 48000 << 16; 1196 cpi = cx / rate; 1197 cx -= cpi * rate; 1198 cx <<= 10; 1199 cpi <<= 10; 1200 cy = cx / rate; 1201 cpi += cy; 1202 cx -= cy * rate; 1203 1204 cy = cx / 200; 1205 csrc = cx - 200*cy; 1206 1207 cdlay = ((48000 * 24) + rate - 1) / rate; 1208 #if 0 1209 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1210 #endif 1211 1212 cnt = rate << 16; 1213 cnt /= 24000; 1214 1215 cgl = 1; 1216 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1217 if (((rate / tmp1) * tmp1) != rate) 1218 cgl *= 2; 1219 } 1220 if (((rate / 3) * 3) != rate) 1221 cgl *= 3; 1222 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1223 if (((rate / tmp1) * tmp1) != rate) 1224 cgl *= 5; 1225 } 1226 #if 0 1227 /* XXX what manual says */ 1228 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1229 tmp1 |= csrc<<16; 1230 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1231 #else 1232 /* suggested by cs461x.c (ALSA driver) */ 1233 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1234 #endif 1235 1236 #if 0 1237 /* I am confused. The sample rate calculation section says 1238 * cci *is* 32-bit signed quantity but in the parameter description 1239 * section, CCI only assigned 16bit. 1240 * I believe size of the variable. 1241 */ 1242 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1243 tmp1 |= cci<<16; 1244 BA1WRITE4(sc, CS4280_CCI, tmp1); 1245 #else 1246 BA1WRITE4(sc, CS4280_CCI, cci); 1247 #endif 1248 1249 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1250 tmp1 |= cdlay <<18; 1251 BA1WRITE4(sc, CS4280_CD, tmp1); 1252 1253 BA1WRITE4(sc, CS4280_CPI, cpi); 1254 1255 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1256 tmp1 |= cgl; 1257 BA1WRITE4(sc, CS4280_CGL, tmp1); 1258 1259 BA1WRITE4(sc, CS4280_CNT, cnt); 1260 1261 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1262 tmp1 |= cgl; 1263 BA1WRITE4(sc, CS4280_CGC, tmp1); 1264 } 1265 1266 static void 1267 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1268 { 1269 /* 1270 * playback rate may range from 8000Hz to 48000Hz 1271 * 1272 * play_phase_increment = floor(rate*65536*1024/48000) 1273 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1274 * py=floor(px/200) 1275 * play_sample_rate_correction = px - 200*py 1276 * 1277 * play_phase_increment is a 32bit signed quantity. 1278 * play_sample_rate_correction is a 16bit signed quantity. 1279 */ 1280 int32_t ppi; 1281 int16_t psrc; 1282 uint32_t px, py; 1283 1284 if (rate < 8000) 1285 rate = 8000; 1286 if (rate > 48000) 1287 rate = 48000; 1288 px = rate << 16; 1289 ppi = px/48000; 1290 px -= ppi*48000; 1291 ppi <<= 10; 1292 px <<= 10; 1293 py = px / 48000; 1294 ppi += py; 1295 px -= py*48000; 1296 py = px/200; 1297 px -= py*200; 1298 psrc = px; 1299 #if 0 1300 /* what manual says */ 1301 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1302 BA1WRITE4(sc, CS4280_PSRC, 1303 ( ((psrc<<16) & PSRC_MASK) | px )); 1304 #else 1305 /* suggested by cs461x.c (ALSA driver) */ 1306 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1307 #endif 1308 BA1WRITE4(sc, CS4280_PPI, ppi); 1309 } 1310 1311 /* Download Processor Code and Data image */ 1312 static int 1313 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1314 uint32_t offset, uint32_t len) 1315 { 1316 uint32_t ctr; 1317 #if CS4280_DEBUG > 10 1318 uint32_t con, data; 1319 uint8_t c0, c1, c2, c3; 1320 #endif 1321 if ((offset & 3) || (len & 3)) 1322 return -1; 1323 1324 len /= sizeof(uint32_t); 1325 for (ctr = 0; ctr < len; ctr++) { 1326 /* XXX: 1327 * I cannot confirm this is the right thing or not 1328 * on BIG-ENDIAN machines. 1329 */ 1330 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1331 #if CS4280_DEBUG > 10 1332 data = htole32(*(src+ctr)); 1333 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1334 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1335 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1336 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1337 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1338 if (data != con ) { 1339 printf("0x%06x: write=0x%08x read=0x%08x\n", 1340 offset+ctr*4, data, con); 1341 return -1; 1342 } 1343 #endif 1344 } 1345 return 0; 1346 } 1347 1348 static int 1349 cs4280_download_image(struct cs428x_softc *sc) 1350 { 1351 int idx, err; 1352 uint32_t offset = 0; 1353 1354 err = 0; 1355 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1356 err = cs4280_download(sc, &BA1Struct.map[offset], 1357 BA1Struct.memory[idx].offset, 1358 BA1Struct.memory[idx].size); 1359 if (err != 0) { 1360 aprint_error_dev(&sc->sc_dev, 1361 "load_image failed at %d\n", idx); 1362 return -1; 1363 } 1364 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1365 } 1366 return err; 1367 } 1368 1369 /* Processor Soft Reset */ 1370 static void 1371 cs4280_reset(void *sc_) 1372 { 1373 struct cs428x_softc *sc; 1374 1375 sc = sc_; 1376 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1377 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1378 delay(100); 1379 /* Clear RSTSP bit in SPCR */ 1380 BA1WRITE4(sc, CS4280_SPCR, 0); 1381 /* enable DMA reqest */ 1382 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1383 } 1384 1385 static int 1386 cs4280_init(struct cs428x_softc *sc, int init) 1387 { 1388 int n; 1389 uint32_t mem; 1390 int rv; 1391 1392 rv = 1; 1393 cs4280_clkrun_hack(sc, 1); 1394 1395 /* Start PLL out in known state */ 1396 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1397 /* Start serial ports out in known state */ 1398 BA0WRITE4(sc, CS4280_SERMC1, 0); 1399 1400 /* Specify type of CODEC */ 1401 /* XXX should not be here */ 1402 #define SERACC_CODEC_TYPE_1_03 1403 #ifdef SERACC_CODEC_TYPE_1_03 1404 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1405 #else 1406 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1407 #endif 1408 1409 /* Reset codec */ 1410 BA0WRITE4(sc, CS428X_ACCTL, 0); 1411 delay(100); /* delay 100us */ 1412 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1413 1414 /* Enable AC-link sync generation */ 1415 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1416 delay(50*1000); /* delay 50ms */ 1417 1418 /* Set the serial port timing configuration */ 1419 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1420 1421 /* Setup clock control */ 1422 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1423 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1424 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1425 1426 /* Power up the PLL */ 1427 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1428 delay(50*1000); /* delay 50ms */ 1429 1430 /* Turn on clock */ 1431 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1432 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1433 1434 /* Set the serial port FIFO pointer to the 1435 * first sample in FIFO. (not documented) */ 1436 cs4280_clear_fifos(sc); 1437 1438 #if 0 1439 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1440 BA0WRITE4(sc, CS4280_SERBSP, 0); 1441 #endif 1442 1443 /* Configure the serial port */ 1444 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1445 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1446 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1447 1448 /* Wait for CODEC ready */ 1449 n = 0; 1450 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1451 delay(125); 1452 if (++n > 1000) { 1453 aprint_error_dev(&sc->sc_dev, "codec ready timeout\n"); 1454 goto exit; 1455 } 1456 } 1457 1458 /* Assert valid frame signal */ 1459 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1460 1461 /* Wait for valid AC97 input slot */ 1462 n = 0; 1463 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1464 (ACISV_ISV3 | ACISV_ISV4)) { 1465 delay(1000); 1466 if (++n > 1000) { 1467 printf("AC97 inputs slot ready timeout\n"); 1468 goto exit; 1469 } 1470 } 1471 1472 /* Set AC97 output slot valid signals */ 1473 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1474 1475 /* reset the processor */ 1476 cs4280_reset(sc); 1477 1478 /* Download the image to the processor */ 1479 if (cs4280_download_image(sc) != 0) { 1480 aprint_error_dev(&sc->sc_dev, "image download error\n"); 1481 goto exit; 1482 } 1483 1484 /* Save playback parameter and then write zero. 1485 * this ensures that DMA doesn't immediately occur upon 1486 * starting the processor core 1487 */ 1488 mem = BA1READ4(sc, CS4280_PCTL); 1489 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1490 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1491 if (init != 0) 1492 sc->sc_prun = 0; 1493 1494 /* Save capture parameter and then write zero. 1495 * this ensures that DMA doesn't immediately occur upon 1496 * starting the processor core 1497 */ 1498 mem = BA1READ4(sc, CS4280_CCTL); 1499 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1500 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1501 if (init != 0) 1502 sc->sc_rrun = 0; 1503 1504 /* Processor Startup Procedure */ 1505 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1506 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1507 1508 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1509 n = 0; 1510 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1511 delay(10); 1512 if (++n > 1000) { 1513 printf("SPCR 1->0 transition timeout\n"); 1514 goto exit; 1515 } 1516 } 1517 1518 n = 0; 1519 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1520 delay(10); 1521 if (++n > 1000) { 1522 printf("SPCS 0->1 transition timeout\n"); 1523 goto exit; 1524 } 1525 } 1526 /* Processor is now running !!! */ 1527 1528 /* Setup volume */ 1529 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1530 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1531 1532 /* Interrupt enable */ 1533 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1534 1535 /* playback interrupt enable */ 1536 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1537 mem |= PFIE_PI_ENABLE; 1538 BA1WRITE4(sc, CS4280_PFIE, mem); 1539 /* capture interrupt enable */ 1540 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1541 mem |= CIE_CI_ENABLE; 1542 BA1WRITE4(sc, CS4280_CIE, mem); 1543 1544 #if NMIDI > 0 1545 /* Reset midi port */ 1546 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1547 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1548 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1549 /* midi interrupt enable */ 1550 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1551 BA0WRITE4(sc, CS4280_MIDCR, mem); 1552 #endif 1553 1554 rv = 0; 1555 1556 exit: 1557 cs4280_clkrun_hack(sc, -1); 1558 return rv; 1559 } 1560 1561 static void 1562 cs4280_clear_fifos(struct cs428x_softc *sc) 1563 { 1564 int pd, cnt, n; 1565 uint32_t mem; 1566 1567 pd = 0; 1568 /* 1569 * If device power down, power up the device and keep power down 1570 * state. 1571 */ 1572 mem = BA0READ4(sc, CS4280_CLKCR1); 1573 if (!(mem & CLKCR1_SWCE)) { 1574 printf("cs4280_clear_fifo: power down found.\n"); 1575 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1576 pd = 1; 1577 } 1578 BA0WRITE4(sc, CS4280_SERBWP, 0); 1579 for (cnt = 0; cnt < 256; cnt++) { 1580 n = 0; 1581 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1582 delay(1000); 1583 if (++n > 1000) { 1584 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1585 break; 1586 } 1587 } 1588 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1589 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1590 } 1591 if (pd) 1592 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1593 } 1594 1595 #if NMIDI > 0 1596 static int 1597 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1598 void (*ointr)(void *), void *arg) 1599 { 1600 struct cs428x_softc *sc; 1601 uint32_t mem; 1602 1603 DPRINTF(("midi_open\n")); 1604 sc = addr; 1605 sc->sc_iintr = iintr; 1606 sc->sc_ointr = ointr; 1607 sc->sc_arg = arg; 1608 1609 /* midi interrupt enable */ 1610 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1611 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1612 BA0WRITE4(sc, CS4280_MIDCR, mem); 1613 #ifdef CS4280_DEBUG 1614 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1615 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1616 return(EINVAL); 1617 } 1618 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1619 #endif 1620 return 0; 1621 } 1622 1623 static void 1624 cs4280_midi_close(void *addr) 1625 { 1626 struct cs428x_softc *sc; 1627 uint32_t mem; 1628 1629 DPRINTF(("midi_close\n")); 1630 sc = addr; 1631 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1632 mem = BA0READ4(sc, CS4280_MIDCR); 1633 mem &= ~MIDCR_MASK; 1634 BA0WRITE4(sc, CS4280_MIDCR, mem); 1635 1636 sc->sc_iintr = 0; 1637 sc->sc_ointr = 0; 1638 } 1639 1640 static int 1641 cs4280_midi_output(void *addr, int d) 1642 { 1643 struct cs428x_softc *sc; 1644 uint32_t mem; 1645 int x; 1646 1647 sc = addr; 1648 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1649 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1650 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1651 mem |= d & MIDWP_MASK; 1652 DPRINTFN(5,("midi_output d=0x%08x",d)); 1653 BA0WRITE4(sc, CS4280_MIDWP, mem); 1654 #ifdef DIAGNOSTIC 1655 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1656 DPRINTF(("Bad write data: %d %d", 1657 mem, BA0READ4(sc, CS4280_MIDWP))); 1658 return EIO; 1659 } 1660 #endif 1661 return 0; 1662 } 1663 delay(MIDI_BUSY_DELAY); 1664 } 1665 return EIO; 1666 } 1667 1668 static void 1669 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1670 { 1671 1672 mi->name = "CS4280 MIDI UART"; 1673 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1674 } 1675 1676 #endif /* NMIDI */ 1677 1678 /* DEBUG functions */ 1679 #if CS4280_DEBUG > 10 1680 static int 1681 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1682 uint32_t offset, uint32_t len) 1683 { 1684 uint32_t ctr, data; 1685 int err; 1686 1687 if ((offset & 3) || (len & 3)) 1688 return -1; 1689 1690 err = 0; 1691 len /= sizeof(uint32_t); 1692 for (ctr = 0; ctr < len; ctr++) { 1693 /* I cannot confirm this is the right thing 1694 * on BIG-ENDIAN machines 1695 */ 1696 data = BA1READ4(sc, offset+ctr*4); 1697 if (data != htole32(*(src+ctr))) { 1698 printf("0x%06x: 0x%08x(0x%08x)\n", 1699 offset+ctr*4, data, *(src+ctr)); 1700 *(src+ctr) = data; 1701 ++err; 1702 } 1703 } 1704 return err; 1705 } 1706 1707 static int 1708 cs4280_check_images(struct cs428x_softc *sc) 1709 { 1710 int idx, err; 1711 uint32_t offset; 1712 1713 offset = 0; 1714 err = 0; 1715 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1716 for (idx = 0; idx < 1; ++idx) { 1717 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1718 BA1Struct.memory[idx].offset, 1719 BA1Struct.memory[idx].size); 1720 if (err != 0) { 1721 aprint_error_dev(&sc->sc_dev, 1722 "check_image failed at %d\n", idx); 1723 } 1724 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1725 } 1726 return err; 1727 } 1728 1729 #endif /* CS4280_DEBUG */ 1730
Indexes created Thu Oct 02 14:10:14 GMT 2025