cs4280.c revision 1.61.6.1
1 /* $NetBSD: cs4280.c,v 1.61.6.1 2011/11/19 21:49:42 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.61.6.1 2011/11/19 21:49:42 jmcneill Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 #include <sys/audioio.h> 68 #include <sys/bus.h> 69 #include <sys/bswap.h> 70 71 #include <dev/audio_if.h> 72 #include <dev/midi_if.h> 73 #include <dev/mulaw.h> 74 #include <dev/auconv.h> 75 76 #include <dev/ic/ac97reg.h> 77 #include <dev/ic/ac97var.h> 78 79 #include <dev/pci/pcidevs.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/cs4280reg.h> 82 #include <dev/pci/cs4280_image.h> 83 #include <dev/pci/cs428xreg.h> 84 #include <dev/pci/cs428x.h> 85 86 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 87 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 88 89 /* IF functions for audio driver */ 90 static int cs4280_match(device_t, cfdata_t, void *); 91 static void cs4280_attach(device_t, device_t, void *); 92 static int cs4280_intr(void *); 93 static int cs4280_query_encoding(void *, struct audio_encoding *); 94 static int cs4280_set_params(void *, int, int, audio_params_t *, 95 audio_params_t *, stream_filter_list_t *, 96 stream_filter_list_t *); 97 static int cs4280_halt_output(void *); 98 static int cs4280_halt_input(void *); 99 static int cs4280_getdev(void *, struct audio_device *); 100 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 101 void *, const audio_params_t *); 102 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 105 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 106 #if 0 107 static int cs4280_reset_codec(void *); 108 #endif 109 static enum ac97_host_flags cs4280_flags_codec(void *); 110 111 static bool cs4280_resume(device_t, const pmf_qual_t *); 112 static bool cs4280_suspend(device_t, const pmf_qual_t *); 113 114 /* Internal functions */ 115 static const struct cs4280_card_t * cs4280_identify_card(const struct pci_attach_args *); 116 static int cs4280_piix4_match(const struct pci_attach_args *); 117 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 118 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 119 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 120 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 121 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 122 uint32_t); 123 static int cs4280_download_image(struct cs428x_softc *); 124 static void cs4280_reset(void *); 125 static int cs4280_init(struct cs428x_softc *, int); 126 static void cs4280_clear_fifos(struct cs428x_softc *); 127 128 #if CS4280_DEBUG > 10 129 /* Thease two function is only for checking image loading is succeeded or not. */ 130 static int cs4280_check_images(struct cs428x_softc *); 131 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 132 uint32_t); 133 #endif 134 135 /* Special cards */ 136 struct cs4280_card_t 137 { 138 pcireg_t id; 139 enum cs428x_flags flags; 140 }; 141 142 #define _card(vend, prod, flags) \ 143 {PCI_ID_CODE(vend, prod), flags} 144 145 static const struct cs4280_card_t cs4280_cards[] = { 146 #if 0 /* untested, from ALSA driver */ 147 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 148 CS428X_FLAG_INVAC97EAMP), 149 #endif 150 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 151 CS428X_FLAG_INVAC97EAMP), 152 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 153 CS428X_FLAG_CLKRUNHACK) 154 }; 155 156 #undef _card 157 158 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 159 160 static const struct audio_hw_if cs4280_hw_if = { 161 NULL, /* open */ 162 NULL, /* close */ 163 NULL, 164 cs4280_query_encoding, 165 cs4280_set_params, 166 cs428x_round_blocksize, 167 NULL, 168 NULL, 169 NULL, 170 NULL, 171 NULL, 172 cs4280_halt_output, 173 cs4280_halt_input, 174 NULL, 175 cs4280_getdev, 176 NULL, 177 cs428x_mixer_set_port, 178 cs428x_mixer_get_port, 179 cs428x_query_devinfo, 180 cs428x_malloc, 181 cs428x_free, 182 cs428x_round_buffersize, 183 cs428x_mappage, 184 cs428x_get_props, 185 cs4280_trigger_output, 186 cs4280_trigger_input, 187 NULL, 188 NULL, 189 cs428x_get_locks, 190 }; 191 192 #if NMIDI > 0 193 /* Midi Interface */ 194 static int cs4280_midi_open(void *, int, void (*)(void *, int), 195 void (*)(void *), void *); 196 static void cs4280_midi_close(void*); 197 static int cs4280_midi_output(void *, int); 198 static void cs4280_midi_getinfo(void *, struct midi_info *); 199 200 static const struct midi_hw_if cs4280_midi_hw_if = { 201 cs4280_midi_open, 202 cs4280_midi_close, 203 cs4280_midi_output, 204 cs4280_midi_getinfo, 205 0, 206 cs428x_get_locks, 207 }; 208 #endif 209 210 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 211 cs4280_match, cs4280_attach, NULL, NULL); 212 213 static struct audio_device cs4280_device = { 214 "CS4280", 215 "", 216 "cs4280" 217 }; 218 219 220 static int 221 cs4280_match(device_t parent, cfdata_t match, void *aux) 222 { 223 struct pci_attach_args *pa; 224 225 pa = (struct pci_attach_args *)aux; 226 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 227 return 0; 228 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 229 #if 0 /* I can't confirm */ 230 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 231 #endif 232 ) 233 return 1; 234 return 0; 235 } 236 237 static void 238 cs4280_attach(device_t parent, device_t self, void *aux) 239 { 240 struct cs428x_softc *sc; 241 struct pci_attach_args *pa; 242 pci_chipset_tag_t pc; 243 const struct cs4280_card_t *cs_card; 244 char const *intrstr; 245 const char *vendor, *product; 246 pcireg_t reg; 247 char devinfo[256]; 248 uint32_t mem; 249 int error; 250 251 sc = device_private(self); 252 pa = (struct pci_attach_args *)aux; 253 pc = pa->pa_pc; 254 aprint_naive(": Audio controller\n"); 255 256 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 257 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 258 PCI_REVISION(pa->pa_class)); 259 260 cs_card = cs4280_identify_card(pa); 261 if (cs_card != NULL) { 262 vendor = pci_findvendor(cs_card->id); 263 product = pci_findproduct(cs_card->id); 264 if (vendor == NULL) 265 aprint_normal_dev(&sc->sc_dev, 266 "vendor 0x%04x product 0x%04x\n", 267 PCI_VENDOR(cs_card->id), 268 PCI_PRODUCT(cs_card->id)); 269 else if (product == NULL) 270 aprint_normal_dev(&sc->sc_dev, "%s product 0x%04x\n", 271 vendor, PCI_PRODUCT(cs_card->id)); 272 else 273 aprint_normal_dev(&sc->sc_dev, "%s %s\n", 274 vendor, product); 275 sc->sc_flags = cs_card->flags; 276 } else { 277 sc->sc_flags = CS428X_FLAG_NONE; 278 } 279 280 sc->sc_pc = pa->pa_pc; 281 sc->sc_pt = pa->pa_tag; 282 283 /* Map I/O register */ 284 if (pci_mapreg_map(pa, PCI_BA0, 285 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 286 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 287 aprint_error_dev(&sc->sc_dev, "can't map BA0 space\n"); 288 return; 289 } 290 if (pci_mapreg_map(pa, PCI_BA1, 291 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 292 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 293 aprint_error_dev(&sc->sc_dev, "can't map BA1 space\n"); 294 return; 295 } 296 297 sc->sc_dmatag = pa->pa_dmat; 298 299 /* power up chip */ 300 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 301 pci_activate_null)) && error != EOPNOTSUPP) { 302 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 303 return; 304 } 305 306 /* Enable the device (set bus master flag) */ 307 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 308 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 309 reg | PCI_COMMAND_MASTER_ENABLE); 310 311 /* LATENCY_TIMER setting */ 312 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 313 if ( PCI_LATTIMER(mem) < 32 ) { 314 mem &= 0xffff00ff; 315 mem |= 0x00002000; 316 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 317 } 318 319 /* CLKRUN hack initialization */ 320 cs4280_clkrun_hack_init(sc); 321 322 /* Map and establish the interrupt. */ 323 if (pci_intr_map(pa, &sc->intrh)) { 324 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 325 return; 326 } 327 intrstr = pci_intr_string(pc, sc->intrh); 328 329 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 330 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 331 332 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_SCHED, 333 cs4280_intr, sc); 334 if (sc->sc_ih == NULL) { 335 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 336 if (intrstr != NULL) 337 aprint_error(" at %s", intrstr); 338 aprint_error("\n"); 339 mutex_destroy(&sc->sc_lock); 340 mutex_destroy(&sc->sc_intr_lock); 341 return; 342 } 343 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 344 345 /* Initialization */ 346 if(cs4280_init(sc, 1) != 0) { 347 mutex_destroy(&sc->sc_lock); 348 mutex_destroy(&sc->sc_intr_lock); 349 return; 350 } 351 352 sc->type = TYPE_CS4280; 353 sc->halt_input = cs4280_halt_input; 354 sc->halt_output = cs4280_halt_output; 355 356 /* setup buffer related parameters */ 357 sc->dma_size = CS4280_DCHUNK; 358 sc->dma_align = CS4280_DALIGN; 359 sc->hw_blocksize = CS4280_ICHUNK; 360 361 /* AC 97 attachment */ 362 sc->host_if.arg = sc; 363 sc->host_if.attach = cs428x_attach_codec; 364 sc->host_if.read = cs4280_read_codec; 365 sc->host_if.write = cs4280_write_codec; 366 #if 0 367 sc->host_if.reset = cs4280_reset_codec; 368 #else 369 sc->host_if.reset = NULL; 370 #endif 371 sc->host_if.flags = cs4280_flags_codec; 372 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 373 aprint_error_dev(&sc->sc_dev, "ac97_attach failed\n"); 374 return; 375 } 376 377 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 378 379 #if NMIDI > 0 380 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 381 #endif 382 383 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 384 aprint_error_dev(self, "couldn't establish power handler\n"); 385 } 386 387 /* Interrupt handling function */ 388 static int 389 cs4280_intr(void *p) 390 { 391 /* 392 * XXX 393 * 394 * Since CS4280 has only 4kB DMA buffer and 395 * interrupt occurs every 2kB block, I create dummy buffer 396 * which returns to audio driver and actual DMA buffer 397 * using in DMA transfer. 398 * 399 * 400 * ring buffer in audio.c is pointed by BUFADDR 401 * <------ ring buffer size == 64kB ------> 402 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 403 * |= = = =|= = = =|= = = =|= = = =|= = = =| 404 * | | | | | | <- call audio_intp every 405 * sc->sc_[pr]_count time. 406 * 407 * actual DMA buffer is pointed by KERNADDR 408 * <-> DMA buffer size = 4kB 409 * |= =| 410 * 411 * 412 */ 413 struct cs428x_softc *sc; 414 uint32_t intr, mem; 415 char * empty_dma; 416 int handled; 417 418 sc = p; 419 handled = 0; 420 421 mutex_spin_enter(&sc->sc_intr_lock); 422 423 /* grab interrupt register then clear it */ 424 intr = BA0READ4(sc, CS4280_HISR); 425 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 426 427 /* not for us ? */ 428 if ((intr & HISR_INTENA) == 0) { 429 mutex_spin_exit(&sc->sc_intr_lock); 430 return 0; 431 } 432 433 /* Playback Interrupt */ 434 if (intr & HISR_PINT) { 435 handled = 1; 436 mem = BA1READ4(sc, CS4280_PFIE); 437 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 438 if (sc->sc_prun) { 439 if ((sc->sc_pi%sc->sc_pcount) == 0) 440 sc->sc_pintr(sc->sc_parg); 441 /* copy buffer */ 442 ++sc->sc_pi; 443 empty_dma = sc->sc_pdma->addr; 444 if (sc->sc_pi&1) 445 empty_dma += sc->hw_blocksize; 446 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 447 sc->sc_pn += sc->hw_blocksize; 448 if (sc->sc_pn >= sc->sc_pe) 449 sc->sc_pn = sc->sc_ps; 450 } else { 451 aprint_error_dev(&sc->sc_dev, "unexpected play intr\n"); 452 } 453 BA1WRITE4(sc, CS4280_PFIE, mem); 454 } 455 /* Capture Interrupt */ 456 if (intr & HISR_CINT) { 457 int i; 458 int16_t rdata; 459 460 handled = 1; 461 mem = BA1READ4(sc, CS4280_CIE); 462 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 463 464 if (sc->sc_rrun) { 465 ++sc->sc_ri; 466 empty_dma = sc->sc_rdma->addr; 467 if ((sc->sc_ri&1) == 0) 468 empty_dma += sc->hw_blocksize; 469 470 /* 471 * XXX 472 * I think this audio data conversion should be 473 * happend in upper layer, but I put this here 474 * since there is no conversion function available. 475 */ 476 switch(sc->sc_rparam) { 477 case CF_16BIT_STEREO: 478 /* just copy it */ 479 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 480 sc->sc_rn += sc->hw_blocksize; 481 break; 482 case CF_16BIT_MONO: 483 for (i = 0; i < 512; i++) { 484 rdata = *((int16_t *)empty_dma)>>1; 485 empty_dma += 2; 486 rdata += *((int16_t *)empty_dma)>>1; 487 empty_dma += 2; 488 *((int16_t *)sc->sc_rn) = rdata; 489 sc->sc_rn += 2; 490 } 491 break; 492 case CF_8BIT_STEREO: 493 for (i = 0; i < 512; i++) { 494 rdata = *((int16_t*)empty_dma); 495 empty_dma += 2; 496 *sc->sc_rn++ = rdata >> 8; 497 rdata = *((int16_t*)empty_dma); 498 empty_dma += 2; 499 *sc->sc_rn++ = rdata >> 8; 500 } 501 break; 502 case CF_8BIT_MONO: 503 for (i = 0; i < 512; i++) { 504 rdata = *((int16_t*)empty_dma) >>1; 505 empty_dma += 2; 506 rdata += *((int16_t*)empty_dma) >>1; 507 empty_dma += 2; 508 *sc->sc_rn++ = rdata >>8; 509 } 510 break; 511 default: 512 /* Should not reach here */ 513 aprint_error_dev(&sc->sc_dev, 514 "unknown sc->sc_rparam: %d\n", 515 sc->sc_rparam); 516 } 517 if (sc->sc_rn >= sc->sc_re) 518 sc->sc_rn = sc->sc_rs; 519 } 520 BA1WRITE4(sc, CS4280_CIE, mem); 521 522 if (sc->sc_rrun) { 523 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 524 sc->sc_rintr(sc->sc_rarg); 525 } else { 526 aprint_error_dev(&sc->sc_dev, 527 "unexpected record intr\n"); 528 } 529 } 530 531 #if NMIDI > 0 532 /* Midi port Interrupt */ 533 if (intr & HISR_MIDI) { 534 int data; 535 536 handled = 1; 537 DPRINTF(("i: %d: ", 538 BA0READ4(sc, CS4280_MIDSR))); 539 /* Read the received data */ 540 while ((sc->sc_iintr != NULL) && 541 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 542 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 543 DPRINTF(("r:%x\n",data)); 544 sc->sc_iintr(sc->sc_arg, data); 545 } 546 547 /* Write the data */ 548 #if 1 549 /* XXX: 550 * It seems "Transmit Buffer Full" never activate until EOI 551 * is deliverd. Shall I throw EOI top of this routine ? 552 */ 553 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 554 DPRINTF(("w: ")); 555 if (sc->sc_ointr != NULL) 556 sc->sc_ointr(sc->sc_arg); 557 } 558 #else 559 while ((sc->sc_ointr != NULL) && 560 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 561 DPRINTF(("w: ")); 562 sc->sc_ointr(sc->sc_arg); 563 } 564 #endif 565 DPRINTF(("\n")); 566 } 567 #endif 568 569 mutex_spin_exit(&sc->sc_intr_lock); 570 return handled; 571 } 572 573 static int 574 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 575 { 576 switch (fp->index) { 577 case 0: 578 strcpy(fp->name, AudioEulinear); 579 fp->encoding = AUDIO_ENCODING_ULINEAR; 580 fp->precision = 8; 581 fp->flags = 0; 582 break; 583 case 1: 584 strcpy(fp->name, AudioEmulaw); 585 fp->encoding = AUDIO_ENCODING_ULAW; 586 fp->precision = 8; 587 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 588 break; 589 case 2: 590 strcpy(fp->name, AudioEalaw); 591 fp->encoding = AUDIO_ENCODING_ALAW; 592 fp->precision = 8; 593 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 594 break; 595 case 3: 596 strcpy(fp->name, AudioEslinear); 597 fp->encoding = AUDIO_ENCODING_SLINEAR; 598 fp->precision = 8; 599 fp->flags = 0; 600 break; 601 case 4: 602 strcpy(fp->name, AudioEslinear_le); 603 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 604 fp->precision = 16; 605 fp->flags = 0; 606 break; 607 case 5: 608 strcpy(fp->name, AudioEulinear_le); 609 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 610 fp->precision = 16; 611 fp->flags = 0; 612 break; 613 case 6: 614 strcpy(fp->name, AudioEslinear_be); 615 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 616 fp->precision = 16; 617 fp->flags = 0; 618 break; 619 case 7: 620 strcpy(fp->name, AudioEulinear_be); 621 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 622 fp->precision = 16; 623 fp->flags = 0; 624 break; 625 default: 626 return EINVAL; 627 } 628 return 0; 629 } 630 631 static int 632 cs4280_set_params(void *addr, int setmode, int usemode, 633 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 634 stream_filter_list_t *rfil) 635 { 636 audio_params_t hw; 637 struct cs428x_softc *sc; 638 struct audio_params *p; 639 stream_filter_list_t *fil; 640 int mode; 641 642 sc = addr; 643 for (mode = AUMODE_RECORD; mode != -1; 644 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 645 if ((setmode & mode) == 0) 646 continue; 647 648 p = mode == AUMODE_PLAY ? play : rec; 649 650 if (p == play) { 651 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 652 p->sample_rate, p->precision, p->channels)); 653 /* play back data format may be 8- or 16-bit and 654 * either stereo or mono. 655 * playback rate may range from 8000Hz to 48000Hz 656 */ 657 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 658 (p->precision != 8 && p->precision != 16) || 659 (p->channels != 1 && p->channels != 2) ) { 660 return EINVAL; 661 } 662 } else { 663 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 664 p->sample_rate, p->precision, p->channels)); 665 /* capture data format must be 16bit stereo 666 * and sample rate range from 11025Hz to 48000Hz. 667 * 668 * XXX: it looks like to work with 8000Hz, 669 * although data sheets say lower limit is 670 * 11025 Hz. 671 */ 672 673 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 674 (p->precision != 8 && p->precision != 16) || 675 (p->channels != 1 && p->channels != 2) ) { 676 return EINVAL; 677 } 678 } 679 fil = mode == AUMODE_PLAY ? pfil : rfil; 680 hw = *p; 681 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 682 683 /* capturing data is slinear */ 684 switch (p->encoding) { 685 case AUDIO_ENCODING_SLINEAR_BE: 686 if (mode == AUMODE_RECORD && p->precision == 16) { 687 fil->append(fil, swap_bytes, &hw); 688 } 689 break; 690 case AUDIO_ENCODING_SLINEAR_LE: 691 break; 692 case AUDIO_ENCODING_ULINEAR_BE: 693 if (mode == AUMODE_RECORD) { 694 fil->append(fil, p->precision == 16 695 ? swap_bytes_change_sign16 696 : change_sign8, &hw); 697 } 698 break; 699 case AUDIO_ENCODING_ULINEAR_LE: 700 if (mode == AUMODE_RECORD) { 701 fil->append(fil, p->precision == 16 702 ? change_sign16 : change_sign8, 703 &hw); 704 } 705 break; 706 case AUDIO_ENCODING_ULAW: 707 if (mode == AUMODE_PLAY) { 708 hw.precision = 16; 709 hw.validbits = 16; 710 fil->append(fil, mulaw_to_linear16, &hw); 711 } else { 712 fil->append(fil, linear8_to_mulaw, &hw); 713 } 714 break; 715 case AUDIO_ENCODING_ALAW: 716 if (mode == AUMODE_PLAY) { 717 hw.precision = 16; 718 hw.validbits = 16; 719 fil->append(fil, alaw_to_linear16, &hw); 720 } else { 721 fil->append(fil, linear8_to_alaw, &hw); 722 } 723 break; 724 default: 725 return EINVAL; 726 } 727 } 728 729 /* set sample rate */ 730 cs4280_set_dac_rate(sc, play->sample_rate); 731 cs4280_set_adc_rate(sc, rec->sample_rate); 732 return 0; 733 } 734 735 static int 736 cs4280_halt_output(void *addr) 737 { 738 struct cs428x_softc *sc; 739 uint32_t mem; 740 741 sc = addr; 742 mem = BA1READ4(sc, CS4280_PCTL); 743 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 744 sc->sc_prun = 0; 745 cs4280_clkrun_hack(sc, -1); 746 747 return 0; 748 } 749 750 static int 751 cs4280_halt_input(void *addr) 752 { 753 struct cs428x_softc *sc; 754 uint32_t mem; 755 756 sc = addr; 757 mem = BA1READ4(sc, CS4280_CCTL); 758 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 759 sc->sc_rrun = 0; 760 cs4280_clkrun_hack(sc, -1); 761 762 return 0; 763 } 764 765 static int 766 cs4280_getdev(void *addr, struct audio_device *retp) 767 { 768 769 *retp = cs4280_device; 770 return 0; 771 } 772 773 static int 774 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 775 void (*intr)(void *), void *arg, 776 const audio_params_t *param) 777 { 778 struct cs428x_softc *sc; 779 uint32_t pfie, pctl, pdtc; 780 struct cs428x_dma *p; 781 782 sc = addr; 783 #ifdef DIAGNOSTIC 784 if (sc->sc_prun) 785 printf("cs4280_trigger_output: already running\n"); 786 #endif 787 sc->sc_prun = 1; 788 cs4280_clkrun_hack(sc, 1); 789 790 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 791 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 792 sc->sc_pintr = intr; 793 sc->sc_parg = arg; 794 795 /* stop playback DMA */ 796 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 797 798 /* setup PDTC */ 799 pdtc = BA1READ4(sc, CS4280_PDTC); 800 pdtc &= ~PDTC_MASK; 801 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 802 BA1WRITE4(sc, CS4280_PDTC, pdtc); 803 804 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 805 param->precision, param->channels, param->encoding)); 806 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 807 continue; 808 if (p == NULL) { 809 printf("cs4280_trigger_output: bad addr %p\n", start); 810 return EINVAL; 811 } 812 if (DMAADDR(p) % sc->dma_align != 0 ) { 813 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 814 "4kB align\n", (ulong)DMAADDR(p)); 815 return EINVAL; 816 } 817 818 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 819 sc->sc_ps = (char *)start; 820 sc->sc_pe = (char *)end; 821 sc->sc_pdma = p; 822 sc->sc_pbuf = KERNADDR(p); 823 sc->sc_pi = 0; 824 sc->sc_pn = sc->sc_ps; 825 if (blksize >= sc->dma_size) { 826 sc->sc_pn = sc->sc_ps + sc->dma_size; 827 memcpy(sc->sc_pbuf, start, sc->dma_size); 828 ++sc->sc_pi; 829 } else { 830 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 831 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 832 } 833 834 /* initiate playback DMA */ 835 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 836 837 /* set PFIE */ 838 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 839 840 if (param->precision == 8) 841 pfie |= PFIE_8BIT; 842 if (param->channels == 1) 843 pfie |= PFIE_MONO; 844 845 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 846 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 847 pfie |= PFIE_SWAPPED; 848 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 849 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 850 pfie |= PFIE_UNSIGNED; 851 852 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 853 854 sc->sc_prate = param->sample_rate; 855 cs4280_set_dac_rate(sc, param->sample_rate); 856 857 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 858 pctl |= sc->pctl; 859 BA1WRITE4(sc, CS4280_PCTL, pctl); 860 return 0; 861 } 862 863 static int 864 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 865 void (*intr)(void *), void *arg, 866 const audio_params_t *param) 867 { 868 struct cs428x_softc *sc; 869 uint32_t cctl, cie; 870 struct cs428x_dma *p; 871 872 sc = addr; 873 #ifdef DIAGNOSTIC 874 if (sc->sc_rrun) 875 printf("cs4280_trigger_input: already running\n"); 876 #endif 877 sc->sc_rrun = 1; 878 cs4280_clkrun_hack(sc, 1); 879 880 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 881 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 882 sc->sc_rintr = intr; 883 sc->sc_rarg = arg; 884 885 /* stop capture DMA */ 886 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 887 888 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 889 continue; 890 if (p == NULL) { 891 printf("cs4280_trigger_input: bad addr %p\n", start); 892 return EINVAL; 893 } 894 if (DMAADDR(p) % sc->dma_align != 0) { 895 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 896 "4kB align\n", (ulong)DMAADDR(p)); 897 return EINVAL; 898 } 899 900 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 901 sc->sc_rs = (char *)start; 902 sc->sc_re = (char *)end; 903 sc->sc_rdma = p; 904 sc->sc_rbuf = KERNADDR(p); 905 sc->sc_ri = 0; 906 sc->sc_rn = sc->sc_rs; 907 908 /* initiate capture DMA */ 909 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 910 911 /* setup format information for internal converter */ 912 sc->sc_rparam = 0; 913 if (param->precision == 8) { 914 sc->sc_rparam += CF_8BIT; 915 sc->sc_rcount <<= 1; 916 } 917 if (param->channels == 1) { 918 sc->sc_rparam += CF_MONO; 919 sc->sc_rcount <<= 1; 920 } 921 922 /* set CIE */ 923 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 924 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 925 926 sc->sc_rrate = param->sample_rate; 927 cs4280_set_adc_rate(sc, param->sample_rate); 928 929 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 930 cctl |= sc->cctl; 931 BA1WRITE4(sc, CS4280_CCTL, cctl); 932 return 0; 933 } 934 935 static bool 936 cs4280_suspend(device_t dv, const pmf_qual_t *qual) 937 { 938 struct cs428x_softc *sc = device_private(dv); 939 940 mutex_exit(&sc->sc_lock); 941 mutex_spin_enter(&sc->sc_intr_lock); 942 943 if (sc->sc_prun) { 944 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 945 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 946 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 947 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 948 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 949 sc->sc_suspend_state.cs4280.pctl, 950 sc->sc_suspend_state.cs4280.pfie, 951 sc->sc_suspend_state.cs4280.pba, 952 sc->sc_suspend_state.cs4280.pdtc)); 953 } 954 955 /* save current capture status */ 956 if (sc->sc_rrun) { 957 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 958 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 959 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 960 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 961 sc->sc_suspend_state.cs4280.cctl, 962 sc->sc_suspend_state.cs4280.cie, 963 sc->sc_suspend_state.cs4280.cba)); 964 } 965 966 /* Stop DMA */ 967 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 968 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 969 970 mutex_spin_exit(&sc->sc_intr_lock); 971 mutex_exit(&sc->sc_lock); 972 973 return true; 974 } 975 976 static bool 977 cs4280_resume(device_t dv, const pmf_qual_t *qual) 978 { 979 struct cs428x_softc *sc = device_private(dv); 980 981 mutex_exit(&sc->sc_lock); 982 mutex_spin_enter(&sc->sc_intr_lock); 983 cs4280_init(sc, 0); 984 #if 0 985 cs4280_reset_codec(sc); 986 #endif 987 988 /* restore DMA related status */ 989 if(sc->sc_prun) { 990 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 991 sc->sc_suspend_state.cs4280.pctl, 992 sc->sc_suspend_state.cs4280.pfie, 993 sc->sc_suspend_state.cs4280.pba, 994 sc->sc_suspend_state.cs4280.pdtc)); 995 cs4280_set_dac_rate(sc, sc->sc_prate); 996 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 997 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 998 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 999 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 1000 } 1001 1002 if (sc->sc_rrun) { 1003 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 1004 sc->sc_suspend_state.cs4280.cctl, 1005 sc->sc_suspend_state.cs4280.cie, 1006 sc->sc_suspend_state.cs4280.cba)); 1007 cs4280_set_adc_rate(sc, sc->sc_rrate); 1008 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 1009 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 1010 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 1011 } 1012 1013 mutex_spin_exit(&sc->sc_intr_lock); 1014 1015 /* restore ac97 registers */ 1016 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1017 1018 mutex_exit(&sc->sc_lock); 1019 1020 return true; 1021 } 1022 1023 static int 1024 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 1025 { 1026 struct cs428x_softc *sc = addr; 1027 int rv; 1028 1029 cs4280_clkrun_hack(sc, 1); 1030 rv = cs428x_read_codec(addr, reg, result); 1031 cs4280_clkrun_hack(sc, -1); 1032 1033 return rv; 1034 } 1035 1036 static int 1037 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1038 { 1039 struct cs428x_softc *sc = addr; 1040 int rv; 1041 1042 cs4280_clkrun_hack(sc, 1); 1043 rv = cs428x_write_codec(addr, reg, data); 1044 cs4280_clkrun_hack(sc, -1); 1045 1046 return rv; 1047 } 1048 1049 #if 0 /* XXX buggy and not required */ 1050 /* control AC97 codec */ 1051 static int 1052 cs4280_reset_codec(void *addr) 1053 { 1054 struct cs428x_softc *sc; 1055 int n; 1056 1057 sc = addr; 1058 1059 /* Reset codec */ 1060 BA0WRITE4(sc, CS428X_ACCTL, 0); 1061 delay(100); /* delay 100us */ 1062 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1063 1064 /* 1065 * It looks like we do the following procedure, too 1066 */ 1067 1068 /* Enable AC-link sync generation */ 1069 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1070 delay(50*1000); /* XXX delay 50ms */ 1071 1072 /* Assert valid frame signal */ 1073 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1074 1075 /* Wait for valid AC97 input slot */ 1076 n = 0; 1077 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1078 (ACISV_ISV3 | ACISV_ISV4)) { 1079 delay(1000); 1080 if (++n > 1000) { 1081 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1082 return ETIMEDOUT; 1083 } 1084 } 1085 1086 return 0; 1087 } 1088 #endif 1089 1090 static enum ac97_host_flags 1091 cs4280_flags_codec(void *addr) 1092 { 1093 struct cs428x_softc *sc; 1094 1095 sc = addr; 1096 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1097 return AC97_HOST_INVERTED_EAMP; 1098 1099 return 0; 1100 } 1101 1102 /* Internal functions */ 1103 1104 static const struct cs4280_card_t * 1105 cs4280_identify_card(const struct pci_attach_args *pa) 1106 { 1107 pcireg_t idreg; 1108 u_int16_t i; 1109 1110 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1111 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1112 if (idreg == cs4280_cards[i].id) 1113 return &cs4280_cards[i]; 1114 } 1115 1116 return NULL; 1117 } 1118 1119 static int 1120 cs4280_piix4_match(const struct pci_attach_args *pa) 1121 { 1122 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1123 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1124 return 1; 1125 } 1126 1127 return 0; 1128 } 1129 1130 static void 1131 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1132 { 1133 uint16_t control, val; 1134 1135 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1136 return; 1137 1138 sc->sc_active += change; 1139 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1140 if (!sc->sc_active) 1141 val |= 0x2000; 1142 else 1143 val &= ~0x2000; 1144 if (val != control) 1145 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1146 } 1147 1148 static void 1149 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1150 { 1151 struct pci_attach_args smbuspa; 1152 uint16_t reg; 1153 pcireg_t port; 1154 1155 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1156 return; 1157 1158 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1159 sc->sc_active = 0; 1160 aprint_normal_dev(&sc->sc_dev, "enabling CLKRUN hack\n"); 1161 1162 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1163 port = reg & 0xffc0; 1164 aprint_normal_dev(&sc->sc_dev, "power management port 0x%x\n", 1165 port); 1166 1167 sc->sc_pm_iot = smbuspa.pa_iot; 1168 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1169 &sc->sc_pm_ioh) == 0) 1170 return; 1171 } 1172 1173 /* handle error */ 1174 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1175 aprint_normal_dev(&sc->sc_dev, "disabling CLKRUN hack\n"); 1176 } 1177 1178 static void 1179 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1180 { 1181 /* calculate capture rate: 1182 * 1183 * capture_coefficient_increment = -round(rate*128*65536/48000; 1184 * capture_phase_increment = floor(48000*65536*1024/rate); 1185 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1186 * cy = floor(cx/200); 1187 * capture_sample_rate_correction = cx - 200*cy; 1188 * capture_delay = ceil(24*48000/rate); 1189 * capture_num_triplets = floor(65536*rate/24000); 1190 * capture_group_length = 24000/GCD(rate, 24000); 1191 * where GCD means "Greatest Common Divisor". 1192 * 1193 * capture_coefficient_increment, capture_phase_increment and 1194 * capture_num_triplets are 32-bit signed quantities. 1195 * capture_sample_rate_correction and capture_group_length are 1196 * 16-bit signed quantities. 1197 * capture_delay is a 14-bit unsigned quantity. 1198 */ 1199 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1200 uint16_t csrc, cgl, cdlay; 1201 1202 /* XXX 1203 * Even though, embedded_audio_spec says capture rate range 11025 to 1204 * 48000, dhwiface.cpp says, 1205 * 1206 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1207 * Return an error if an attempt is made to stray outside that limit." 1208 * 1209 * so assume range as 48000/9 to 48000 1210 */ 1211 1212 if (rate < 8000) 1213 rate = 8000; 1214 if (rate > 48000) 1215 rate = 48000; 1216 1217 cx = rate << 16; 1218 cci = cx / 48000; 1219 cx -= cci * 48000; 1220 cx <<= 7; 1221 cci <<= 7; 1222 cci += cx / 48000; 1223 cci = - cci; 1224 1225 cx = 48000 << 16; 1226 cpi = cx / rate; 1227 cx -= cpi * rate; 1228 cx <<= 10; 1229 cpi <<= 10; 1230 cy = cx / rate; 1231 cpi += cy; 1232 cx -= cy * rate; 1233 1234 cy = cx / 200; 1235 csrc = cx - 200*cy; 1236 1237 cdlay = ((48000 * 24) + rate - 1) / rate; 1238 #if 0 1239 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1240 #endif 1241 1242 cnt = rate << 16; 1243 cnt /= 24000; 1244 1245 cgl = 1; 1246 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1247 if (((rate / tmp1) * tmp1) != rate) 1248 cgl *= 2; 1249 } 1250 if (((rate / 3) * 3) != rate) 1251 cgl *= 3; 1252 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1253 if (((rate / tmp1) * tmp1) != rate) 1254 cgl *= 5; 1255 } 1256 #if 0 1257 /* XXX what manual says */ 1258 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1259 tmp1 |= csrc<<16; 1260 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1261 #else 1262 /* suggested by cs461x.c (ALSA driver) */ 1263 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1264 #endif 1265 1266 #if 0 1267 /* I am confused. The sample rate calculation section says 1268 * cci *is* 32-bit signed quantity but in the parameter description 1269 * section, CCI only assigned 16bit. 1270 * I believe size of the variable. 1271 */ 1272 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1273 tmp1 |= cci<<16; 1274 BA1WRITE4(sc, CS4280_CCI, tmp1); 1275 #else 1276 BA1WRITE4(sc, CS4280_CCI, cci); 1277 #endif 1278 1279 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1280 tmp1 |= cdlay <<18; 1281 BA1WRITE4(sc, CS4280_CD, tmp1); 1282 1283 BA1WRITE4(sc, CS4280_CPI, cpi); 1284 1285 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1286 tmp1 |= cgl; 1287 BA1WRITE4(sc, CS4280_CGL, tmp1); 1288 1289 BA1WRITE4(sc, CS4280_CNT, cnt); 1290 1291 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1292 tmp1 |= cgl; 1293 BA1WRITE4(sc, CS4280_CGC, tmp1); 1294 } 1295 1296 static void 1297 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1298 { 1299 /* 1300 * playback rate may range from 8000Hz to 48000Hz 1301 * 1302 * play_phase_increment = floor(rate*65536*1024/48000) 1303 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1304 * py=floor(px/200) 1305 * play_sample_rate_correction = px - 200*py 1306 * 1307 * play_phase_increment is a 32bit signed quantity. 1308 * play_sample_rate_correction is a 16bit signed quantity. 1309 */ 1310 int32_t ppi; 1311 int16_t psrc; 1312 uint32_t px, py; 1313 1314 if (rate < 8000) 1315 rate = 8000; 1316 if (rate > 48000) 1317 rate = 48000; 1318 px = rate << 16; 1319 ppi = px/48000; 1320 px -= ppi*48000; 1321 ppi <<= 10; 1322 px <<= 10; 1323 py = px / 48000; 1324 ppi += py; 1325 px -= py*48000; 1326 py = px/200; 1327 px -= py*200; 1328 psrc = px; 1329 #if 0 1330 /* what manual says */ 1331 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1332 BA1WRITE4(sc, CS4280_PSRC, 1333 ( ((psrc<<16) & PSRC_MASK) | px )); 1334 #else 1335 /* suggested by cs461x.c (ALSA driver) */ 1336 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1337 #endif 1338 BA1WRITE4(sc, CS4280_PPI, ppi); 1339 } 1340 1341 /* Download Processor Code and Data image */ 1342 static int 1343 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1344 uint32_t offset, uint32_t len) 1345 { 1346 uint32_t ctr; 1347 #if CS4280_DEBUG > 10 1348 uint32_t con, data; 1349 uint8_t c0, c1, c2, c3; 1350 #endif 1351 if ((offset & 3) || (len & 3)) 1352 return -1; 1353 1354 len /= sizeof(uint32_t); 1355 for (ctr = 0; ctr < len; ctr++) { 1356 /* XXX: 1357 * I cannot confirm this is the right thing or not 1358 * on BIG-ENDIAN machines. 1359 */ 1360 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1361 #if CS4280_DEBUG > 10 1362 data = htole32(*(src+ctr)); 1363 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1364 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1365 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1366 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1367 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1368 if (data != con ) { 1369 printf("0x%06x: write=0x%08x read=0x%08x\n", 1370 offset+ctr*4, data, con); 1371 return -1; 1372 } 1373 #endif 1374 } 1375 return 0; 1376 } 1377 1378 static int 1379 cs4280_download_image(struct cs428x_softc *sc) 1380 { 1381 int idx, err; 1382 uint32_t offset = 0; 1383 1384 err = 0; 1385 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1386 err = cs4280_download(sc, &BA1Struct.map[offset], 1387 BA1Struct.memory[idx].offset, 1388 BA1Struct.memory[idx].size); 1389 if (err != 0) { 1390 aprint_error_dev(&sc->sc_dev, 1391 "load_image failed at %d\n", idx); 1392 return -1; 1393 } 1394 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1395 } 1396 return err; 1397 } 1398 1399 /* Processor Soft Reset */ 1400 static void 1401 cs4280_reset(void *sc_) 1402 { 1403 struct cs428x_softc *sc; 1404 1405 sc = sc_; 1406 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1407 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1408 delay(100); 1409 /* Clear RSTSP bit in SPCR */ 1410 BA1WRITE4(sc, CS4280_SPCR, 0); 1411 /* enable DMA reqest */ 1412 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1413 } 1414 1415 static int 1416 cs4280_init(struct cs428x_softc *sc, int init) 1417 { 1418 int n; 1419 uint32_t mem; 1420 int rv; 1421 1422 rv = 1; 1423 cs4280_clkrun_hack(sc, 1); 1424 1425 /* Start PLL out in known state */ 1426 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1427 /* Start serial ports out in known state */ 1428 BA0WRITE4(sc, CS4280_SERMC1, 0); 1429 1430 /* Specify type of CODEC */ 1431 /* XXX should not be here */ 1432 #define SERACC_CODEC_TYPE_1_03 1433 #ifdef SERACC_CODEC_TYPE_1_03 1434 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1435 #else 1436 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1437 #endif 1438 1439 /* Reset codec */ 1440 BA0WRITE4(sc, CS428X_ACCTL, 0); 1441 delay(100); /* delay 100us */ 1442 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1443 1444 /* Enable AC-link sync generation */ 1445 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1446 delay(50*1000); /* delay 50ms */ 1447 1448 /* Set the serial port timing configuration */ 1449 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1450 1451 /* Setup clock control */ 1452 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1453 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1454 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1455 1456 /* Power up the PLL */ 1457 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1458 delay(50*1000); /* delay 50ms */ 1459 1460 /* Turn on clock */ 1461 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1462 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1463 1464 /* Set the serial port FIFO pointer to the 1465 * first sample in FIFO. (not documented) */ 1466 cs4280_clear_fifos(sc); 1467 1468 #if 0 1469 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1470 BA0WRITE4(sc, CS4280_SERBSP, 0); 1471 #endif 1472 1473 /* Configure the serial port */ 1474 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1475 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1476 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1477 1478 /* Wait for CODEC ready */ 1479 n = 0; 1480 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1481 delay(125); 1482 if (++n > 1000) { 1483 aprint_error_dev(&sc->sc_dev, "codec ready timeout\n"); 1484 goto exit; 1485 } 1486 } 1487 1488 /* Assert valid frame signal */ 1489 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1490 1491 /* Wait for valid AC97 input slot */ 1492 n = 0; 1493 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1494 (ACISV_ISV3 | ACISV_ISV4)) { 1495 delay(1000); 1496 if (++n > 1000) { 1497 printf("AC97 inputs slot ready timeout\n"); 1498 goto exit; 1499 } 1500 } 1501 1502 /* Set AC97 output slot valid signals */ 1503 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1504 1505 /* reset the processor */ 1506 cs4280_reset(sc); 1507 1508 /* Download the image to the processor */ 1509 if (cs4280_download_image(sc) != 0) { 1510 aprint_error_dev(&sc->sc_dev, "image download error\n"); 1511 goto exit; 1512 } 1513 1514 /* Save playback parameter and then write zero. 1515 * this ensures that DMA doesn't immediately occur upon 1516 * starting the processor core 1517 */ 1518 mem = BA1READ4(sc, CS4280_PCTL); 1519 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1520 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1521 if (init != 0) 1522 sc->sc_prun = 0; 1523 1524 /* Save capture parameter and then write zero. 1525 * this ensures that DMA doesn't immediately occur upon 1526 * starting the processor core 1527 */ 1528 mem = BA1READ4(sc, CS4280_CCTL); 1529 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1530 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1531 if (init != 0) 1532 sc->sc_rrun = 0; 1533 1534 /* Processor Startup Procedure */ 1535 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1536 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1537 1538 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1539 n = 0; 1540 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1541 delay(10); 1542 if (++n > 1000) { 1543 printf("SPCR 1->0 transition timeout\n"); 1544 goto exit; 1545 } 1546 } 1547 1548 n = 0; 1549 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1550 delay(10); 1551 if (++n > 1000) { 1552 printf("SPCS 0->1 transition timeout\n"); 1553 goto exit; 1554 } 1555 } 1556 /* Processor is now running !!! */ 1557 1558 /* Setup volume */ 1559 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1560 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1561 1562 /* Interrupt enable */ 1563 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1564 1565 /* playback interrupt enable */ 1566 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1567 mem |= PFIE_PI_ENABLE; 1568 BA1WRITE4(sc, CS4280_PFIE, mem); 1569 /* capture interrupt enable */ 1570 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1571 mem |= CIE_CI_ENABLE; 1572 BA1WRITE4(sc, CS4280_CIE, mem); 1573 1574 #if NMIDI > 0 1575 /* Reset midi port */ 1576 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1577 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1578 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1579 /* midi interrupt enable */ 1580 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1581 BA0WRITE4(sc, CS4280_MIDCR, mem); 1582 #endif 1583 1584 rv = 0; 1585 1586 exit: 1587 cs4280_clkrun_hack(sc, -1); 1588 return rv; 1589 } 1590 1591 static void 1592 cs4280_clear_fifos(struct cs428x_softc *sc) 1593 { 1594 int pd, cnt, n; 1595 uint32_t mem; 1596 1597 pd = 0; 1598 /* 1599 * If device power down, power up the device and keep power down 1600 * state. 1601 */ 1602 mem = BA0READ4(sc, CS4280_CLKCR1); 1603 if (!(mem & CLKCR1_SWCE)) { 1604 printf("cs4280_clear_fifo: power down found.\n"); 1605 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1606 pd = 1; 1607 } 1608 BA0WRITE4(sc, CS4280_SERBWP, 0); 1609 for (cnt = 0; cnt < 256; cnt++) { 1610 n = 0; 1611 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1612 delay(1000); 1613 if (++n > 1000) { 1614 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1615 break; 1616 } 1617 } 1618 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1619 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1620 } 1621 if (pd) 1622 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1623 } 1624 1625 #if NMIDI > 0 1626 static int 1627 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1628 void (*ointr)(void *), void *arg) 1629 { 1630 struct cs428x_softc *sc; 1631 uint32_t mem; 1632 1633 DPRINTF(("midi_open\n")); 1634 sc = addr; 1635 sc->sc_iintr = iintr; 1636 sc->sc_ointr = ointr; 1637 sc->sc_arg = arg; 1638 1639 /* midi interrupt enable */ 1640 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1641 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1642 BA0WRITE4(sc, CS4280_MIDCR, mem); 1643 #ifdef CS4280_DEBUG 1644 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1645 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1646 return(EINVAL); 1647 } 1648 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1649 #endif 1650 return 0; 1651 } 1652 1653 static void 1654 cs4280_midi_close(void *addr) 1655 { 1656 struct cs428x_softc *sc; 1657 uint32_t mem; 1658 1659 DPRINTF(("midi_close\n")); 1660 sc = addr; 1661 /* give uart a chance to drain */ 1662 kpause("cs0clm", false, hz/10, &sc->sc_intr_lock); 1663 mem = BA0READ4(sc, CS4280_MIDCR); 1664 mem &= ~MIDCR_MASK; 1665 BA0WRITE4(sc, CS4280_MIDCR, mem); 1666 1667 sc->sc_iintr = 0; 1668 sc->sc_ointr = 0; 1669 } 1670 1671 static int 1672 cs4280_midi_output(void *addr, int d) 1673 { 1674 struct cs428x_softc *sc; 1675 uint32_t mem; 1676 int x; 1677 1678 sc = addr; 1679 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1680 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1681 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1682 mem |= d & MIDWP_MASK; 1683 DPRINTFN(5,("midi_output d=0x%08x",d)); 1684 BA0WRITE4(sc, CS4280_MIDWP, mem); 1685 #ifdef DIAGNOSTIC 1686 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1687 DPRINTF(("Bad write data: %d %d", 1688 mem, BA0READ4(sc, CS4280_MIDWP))); 1689 return EIO; 1690 } 1691 #endif 1692 return 0; 1693 } 1694 delay(MIDI_BUSY_DELAY); 1695 } 1696 return EIO; 1697 } 1698 1699 static void 1700 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1701 { 1702 1703 mi->name = "CS4280 MIDI UART"; 1704 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1705 } 1706 1707 #endif /* NMIDI */ 1708 1709 /* DEBUG functions */ 1710 #if CS4280_DEBUG > 10 1711 static int 1712 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1713 uint32_t offset, uint32_t len) 1714 { 1715 uint32_t ctr, data; 1716 int err; 1717 1718 if ((offset & 3) || (len & 3)) 1719 return -1; 1720 1721 err = 0; 1722 len /= sizeof(uint32_t); 1723 for (ctr = 0; ctr < len; ctr++) { 1724 /* I cannot confirm this is the right thing 1725 * on BIG-ENDIAN machines 1726 */ 1727 data = BA1READ4(sc, offset+ctr*4); 1728 if (data != htole32(*(src+ctr))) { 1729 printf("0x%06x: 0x%08x(0x%08x)\n", 1730 offset+ctr*4, data, *(src+ctr)); 1731 *(src+ctr) = data; 1732 ++err; 1733 } 1734 } 1735 return err; 1736 } 1737 1738 static int 1739 cs4280_check_images(struct cs428x_softc *sc) 1740 { 1741 int idx, err; 1742 uint32_t offset; 1743 1744 offset = 0; 1745 err = 0; 1746 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1747 for (idx = 0; idx < 1; ++idx) { 1748 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1749 BA1Struct.memory[idx].offset, 1750 BA1Struct.memory[idx].size); 1751 if (err != 0) { 1752 aprint_error_dev(&sc->sc_dev, 1753 "check_image failed at %d\n", idx); 1754 } 1755 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1756 } 1757 return err; 1758 } 1759 1760 #endif /* CS4280_DEBUG */ 1761
Indexes created Thu Oct 02 14:10:14 GMT 2025