cs4280.c revision 1.64
1 /* $NetBSD: cs4280.c,v 1.64 2012/01/30 19:41:18 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.64 2012/01/30 19:41:18 drochner Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 #include <sys/audioio.h> 68 #include <sys/bus.h> 69 #include <sys/bswap.h> 70 71 #include <dev/audio_if.h> 72 #include <dev/midi_if.h> 73 #include <dev/mulaw.h> 74 #include <dev/auconv.h> 75 76 #include <dev/ic/ac97reg.h> 77 #include <dev/ic/ac97var.h> 78 79 #include <dev/pci/pcidevs.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/cs4280reg.h> 82 #include <dev/pci/cs4280_image.h> 83 #include <dev/pci/cs428xreg.h> 84 #include <dev/pci/cs428x.h> 85 86 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 87 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 88 89 /* IF functions for audio driver */ 90 static int cs4280_match(device_t, cfdata_t, void *); 91 static void cs4280_attach(device_t, device_t, void *); 92 static int cs4280_intr(void *); 93 static int cs4280_query_encoding(void *, struct audio_encoding *); 94 static int cs4280_set_params(void *, int, int, audio_params_t *, 95 audio_params_t *, stream_filter_list_t *, 96 stream_filter_list_t *); 97 static int cs4280_halt_output(void *); 98 static int cs4280_halt_input(void *); 99 static int cs4280_getdev(void *, struct audio_device *); 100 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 101 void *, const audio_params_t *); 102 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 105 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 106 #if 0 107 static int cs4280_reset_codec(void *); 108 #endif 109 static enum ac97_host_flags cs4280_flags_codec(void *); 110 111 static bool cs4280_resume(device_t, const pmf_qual_t *); 112 static bool cs4280_suspend(device_t, const pmf_qual_t *); 113 114 /* Internal functions */ 115 static const struct cs4280_card_t * cs4280_identify_card(const struct pci_attach_args *); 116 static int cs4280_piix4_match(const struct pci_attach_args *); 117 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 118 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 119 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 120 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 121 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 122 uint32_t); 123 static int cs4280_download_image(struct cs428x_softc *); 124 static void cs4280_reset(void *); 125 static int cs4280_init(struct cs428x_softc *, int); 126 static void cs4280_clear_fifos(struct cs428x_softc *); 127 128 #if CS4280_DEBUG > 10 129 /* Thease two function is only for checking image loading is succeeded or not. */ 130 static int cs4280_check_images(struct cs428x_softc *); 131 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 132 uint32_t); 133 #endif 134 135 /* Special cards */ 136 struct cs4280_card_t 137 { 138 pcireg_t id; 139 enum cs428x_flags flags; 140 }; 141 142 #define _card(vend, prod, flags) \ 143 {PCI_ID_CODE(vend, prod), flags} 144 145 static const struct cs4280_card_t cs4280_cards[] = { 146 #if 0 /* untested, from ALSA driver */ 147 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 148 CS428X_FLAG_INVAC97EAMP), 149 #endif 150 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 151 CS428X_FLAG_INVAC97EAMP), 152 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 153 CS428X_FLAG_CLKRUNHACK) 154 }; 155 156 #undef _card 157 158 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 159 160 static const struct audio_hw_if cs4280_hw_if = { 161 NULL, /* open */ 162 NULL, /* close */ 163 NULL, 164 cs4280_query_encoding, 165 cs4280_set_params, 166 cs428x_round_blocksize, 167 NULL, 168 NULL, 169 NULL, 170 NULL, 171 NULL, 172 cs4280_halt_output, 173 cs4280_halt_input, 174 NULL, 175 cs4280_getdev, 176 NULL, 177 cs428x_mixer_set_port, 178 cs428x_mixer_get_port, 179 cs428x_query_devinfo, 180 cs428x_malloc, 181 cs428x_free, 182 cs428x_round_buffersize, 183 cs428x_mappage, 184 cs428x_get_props, 185 cs4280_trigger_output, 186 cs4280_trigger_input, 187 NULL, 188 cs428x_get_locks, 189 }; 190 191 #if NMIDI > 0 192 /* Midi Interface */ 193 static int cs4280_midi_open(void *, int, void (*)(void *, int), 194 void (*)(void *), void *); 195 static void cs4280_midi_close(void*); 196 static int cs4280_midi_output(void *, int); 197 static void cs4280_midi_getinfo(void *, struct midi_info *); 198 199 static const struct midi_hw_if cs4280_midi_hw_if = { 200 cs4280_midi_open, 201 cs4280_midi_close, 202 cs4280_midi_output, 203 cs4280_midi_getinfo, 204 0, 205 cs428x_get_locks, 206 }; 207 #endif 208 209 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 210 cs4280_match, cs4280_attach, NULL, NULL); 211 212 static struct audio_device cs4280_device = { 213 "CS4280", 214 "", 215 "cs4280" 216 }; 217 218 219 static int 220 cs4280_match(device_t parent, cfdata_t match, void *aux) 221 { 222 struct pci_attach_args *pa; 223 224 pa = (struct pci_attach_args *)aux; 225 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 226 return 0; 227 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 228 #if 0 /* I can't confirm */ 229 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 230 #endif 231 ) 232 return 1; 233 return 0; 234 } 235 236 static void 237 cs4280_attach(device_t parent, device_t self, void *aux) 238 { 239 struct cs428x_softc *sc; 240 struct pci_attach_args *pa; 241 pci_chipset_tag_t pc; 242 const struct cs4280_card_t *cs_card; 243 char const *intrstr; 244 const char *vendor, *product; 245 pcireg_t reg; 246 uint32_t mem; 247 int error; 248 249 sc = device_private(self); 250 pa = (struct pci_attach_args *)aux; 251 pc = pa->pa_pc; 252 253 pci_aprint_devinfo(pa, "Audio controller"); 254 255 cs_card = cs4280_identify_card(pa); 256 if (cs_card != NULL) { 257 vendor = pci_findvendor(cs_card->id); 258 product = pci_findproduct(cs_card->id); 259 if (vendor == NULL) 260 aprint_normal_dev(&sc->sc_dev, 261 "vendor 0x%04x product 0x%04x\n", 262 PCI_VENDOR(cs_card->id), 263 PCI_PRODUCT(cs_card->id)); 264 else if (product == NULL) 265 aprint_normal_dev(&sc->sc_dev, "%s product 0x%04x\n", 266 vendor, PCI_PRODUCT(cs_card->id)); 267 else 268 aprint_normal_dev(&sc->sc_dev, "%s %s\n", 269 vendor, product); 270 sc->sc_flags = cs_card->flags; 271 } else { 272 sc->sc_flags = CS428X_FLAG_NONE; 273 } 274 275 sc->sc_pc = pa->pa_pc; 276 sc->sc_pt = pa->pa_tag; 277 278 /* Map I/O register */ 279 if (pci_mapreg_map(pa, PCI_BA0, 280 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 281 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 282 aprint_error_dev(&sc->sc_dev, "can't map BA0 space\n"); 283 return; 284 } 285 if (pci_mapreg_map(pa, PCI_BA1, 286 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 287 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 288 aprint_error_dev(&sc->sc_dev, "can't map BA1 space\n"); 289 return; 290 } 291 292 sc->sc_dmatag = pa->pa_dmat; 293 294 /* power up chip */ 295 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 296 pci_activate_null)) && error != EOPNOTSUPP) { 297 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 298 return; 299 } 300 301 /* Enable the device (set bus master flag) */ 302 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 303 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 304 reg | PCI_COMMAND_MASTER_ENABLE); 305 306 /* LATENCY_TIMER setting */ 307 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 308 if ( PCI_LATTIMER(mem) < 32 ) { 309 mem &= 0xffff00ff; 310 mem |= 0x00002000; 311 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 312 } 313 314 /* CLKRUN hack initialization */ 315 cs4280_clkrun_hack_init(sc); 316 317 /* Map and establish the interrupt. */ 318 if (pci_intr_map(pa, &sc->intrh)) { 319 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 320 return; 321 } 322 intrstr = pci_intr_string(pc, sc->intrh); 323 324 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 325 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 326 327 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 328 cs4280_intr, sc); 329 if (sc->sc_ih == NULL) { 330 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 331 if (intrstr != NULL) 332 aprint_error(" at %s", intrstr); 333 aprint_error("\n"); 334 mutex_destroy(&sc->sc_lock); 335 mutex_destroy(&sc->sc_intr_lock); 336 return; 337 } 338 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 339 340 /* Initialization */ 341 if(cs4280_init(sc, 1) != 0) { 342 mutex_destroy(&sc->sc_lock); 343 mutex_destroy(&sc->sc_intr_lock); 344 return; 345 } 346 347 sc->type = TYPE_CS4280; 348 sc->halt_input = cs4280_halt_input; 349 sc->halt_output = cs4280_halt_output; 350 351 /* setup buffer related parameters */ 352 sc->dma_size = CS4280_DCHUNK; 353 sc->dma_align = CS4280_DALIGN; 354 sc->hw_blocksize = CS4280_ICHUNK; 355 356 /* AC 97 attachment */ 357 sc->host_if.arg = sc; 358 sc->host_if.attach = cs428x_attach_codec; 359 sc->host_if.read = cs4280_read_codec; 360 sc->host_if.write = cs4280_write_codec; 361 #if 0 362 sc->host_if.reset = cs4280_reset_codec; 363 #else 364 sc->host_if.reset = NULL; 365 #endif 366 sc->host_if.flags = cs4280_flags_codec; 367 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 368 aprint_error_dev(&sc->sc_dev, "ac97_attach failed\n"); 369 return; 370 } 371 372 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 373 374 #if NMIDI > 0 375 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 376 #endif 377 378 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 379 aprint_error_dev(self, "couldn't establish power handler\n"); 380 } 381 382 /* Interrupt handling function */ 383 static int 384 cs4280_intr(void *p) 385 { 386 /* 387 * XXX 388 * 389 * Since CS4280 has only 4kB DMA buffer and 390 * interrupt occurs every 2kB block, I create dummy buffer 391 * which returns to audio driver and actual DMA buffer 392 * using in DMA transfer. 393 * 394 * 395 * ring buffer in audio.c is pointed by BUFADDR 396 * <------ ring buffer size == 64kB ------> 397 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 398 * |= = = =|= = = =|= = = =|= = = =|= = = =| 399 * | | | | | | <- call audio_intp every 400 * sc->sc_[pr]_count time. 401 * 402 * actual DMA buffer is pointed by KERNADDR 403 * <-> DMA buffer size = 4kB 404 * |= =| 405 * 406 * 407 */ 408 struct cs428x_softc *sc; 409 uint32_t intr, mem; 410 char * empty_dma; 411 int handled; 412 413 sc = p; 414 handled = 0; 415 416 mutex_spin_enter(&sc->sc_intr_lock); 417 418 /* grab interrupt register then clear it */ 419 intr = BA0READ4(sc, CS4280_HISR); 420 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 421 422 /* not for us ? */ 423 if ((intr & HISR_INTENA) == 0) { 424 mutex_spin_exit(&sc->sc_intr_lock); 425 return 0; 426 } 427 428 /* Playback Interrupt */ 429 if (intr & HISR_PINT) { 430 handled = 1; 431 mem = BA1READ4(sc, CS4280_PFIE); 432 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 433 if (sc->sc_prun) { 434 if ((sc->sc_pi%sc->sc_pcount) == 0) 435 sc->sc_pintr(sc->sc_parg); 436 /* copy buffer */ 437 ++sc->sc_pi; 438 empty_dma = sc->sc_pdma->addr; 439 if (sc->sc_pi&1) 440 empty_dma += sc->hw_blocksize; 441 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 442 sc->sc_pn += sc->hw_blocksize; 443 if (sc->sc_pn >= sc->sc_pe) 444 sc->sc_pn = sc->sc_ps; 445 } else { 446 aprint_error_dev(&sc->sc_dev, "unexpected play intr\n"); 447 } 448 BA1WRITE4(sc, CS4280_PFIE, mem); 449 } 450 /* Capture Interrupt */ 451 if (intr & HISR_CINT) { 452 int i; 453 int16_t rdata; 454 455 handled = 1; 456 mem = BA1READ4(sc, CS4280_CIE); 457 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 458 459 if (sc->sc_rrun) { 460 ++sc->sc_ri; 461 empty_dma = sc->sc_rdma->addr; 462 if ((sc->sc_ri&1) == 0) 463 empty_dma += sc->hw_blocksize; 464 465 /* 466 * XXX 467 * I think this audio data conversion should be 468 * happend in upper layer, but I put this here 469 * since there is no conversion function available. 470 */ 471 switch(sc->sc_rparam) { 472 case CF_16BIT_STEREO: 473 /* just copy it */ 474 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 475 sc->sc_rn += sc->hw_blocksize; 476 break; 477 case CF_16BIT_MONO: 478 for (i = 0; i < 512; i++) { 479 rdata = *((int16_t *)empty_dma)>>1; 480 empty_dma += 2; 481 rdata += *((int16_t *)empty_dma)>>1; 482 empty_dma += 2; 483 *((int16_t *)sc->sc_rn) = rdata; 484 sc->sc_rn += 2; 485 } 486 break; 487 case CF_8BIT_STEREO: 488 for (i = 0; i < 512; i++) { 489 rdata = *((int16_t*)empty_dma); 490 empty_dma += 2; 491 *sc->sc_rn++ = rdata >> 8; 492 rdata = *((int16_t*)empty_dma); 493 empty_dma += 2; 494 *sc->sc_rn++ = rdata >> 8; 495 } 496 break; 497 case CF_8BIT_MONO: 498 for (i = 0; i < 512; i++) { 499 rdata = *((int16_t*)empty_dma) >>1; 500 empty_dma += 2; 501 rdata += *((int16_t*)empty_dma) >>1; 502 empty_dma += 2; 503 *sc->sc_rn++ = rdata >>8; 504 } 505 break; 506 default: 507 /* Should not reach here */ 508 aprint_error_dev(&sc->sc_dev, 509 "unknown sc->sc_rparam: %d\n", 510 sc->sc_rparam); 511 } 512 if (sc->sc_rn >= sc->sc_re) 513 sc->sc_rn = sc->sc_rs; 514 } 515 BA1WRITE4(sc, CS4280_CIE, mem); 516 517 if (sc->sc_rrun) { 518 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 519 sc->sc_rintr(sc->sc_rarg); 520 } else { 521 aprint_error_dev(&sc->sc_dev, 522 "unexpected record intr\n"); 523 } 524 } 525 526 #if NMIDI > 0 527 /* Midi port Interrupt */ 528 if (intr & HISR_MIDI) { 529 int data; 530 531 handled = 1; 532 DPRINTF(("i: %d: ", 533 BA0READ4(sc, CS4280_MIDSR))); 534 /* Read the received data */ 535 while ((sc->sc_iintr != NULL) && 536 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 537 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 538 DPRINTF(("r:%x\n",data)); 539 sc->sc_iintr(sc->sc_arg, data); 540 } 541 542 /* Write the data */ 543 #if 1 544 /* XXX: 545 * It seems "Transmit Buffer Full" never activate until EOI 546 * is deliverd. Shall I throw EOI top of this routine ? 547 */ 548 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 549 DPRINTF(("w: ")); 550 if (sc->sc_ointr != NULL) 551 sc->sc_ointr(sc->sc_arg); 552 } 553 #else 554 while ((sc->sc_ointr != NULL) && 555 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 556 DPRINTF(("w: ")); 557 sc->sc_ointr(sc->sc_arg); 558 } 559 #endif 560 DPRINTF(("\n")); 561 } 562 #endif 563 564 mutex_spin_exit(&sc->sc_intr_lock); 565 return handled; 566 } 567 568 static int 569 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 570 { 571 switch (fp->index) { 572 case 0: 573 strcpy(fp->name, AudioEulinear); 574 fp->encoding = AUDIO_ENCODING_ULINEAR; 575 fp->precision = 8; 576 fp->flags = 0; 577 break; 578 case 1: 579 strcpy(fp->name, AudioEmulaw); 580 fp->encoding = AUDIO_ENCODING_ULAW; 581 fp->precision = 8; 582 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 583 break; 584 case 2: 585 strcpy(fp->name, AudioEalaw); 586 fp->encoding = AUDIO_ENCODING_ALAW; 587 fp->precision = 8; 588 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 589 break; 590 case 3: 591 strcpy(fp->name, AudioEslinear); 592 fp->encoding = AUDIO_ENCODING_SLINEAR; 593 fp->precision = 8; 594 fp->flags = 0; 595 break; 596 case 4: 597 strcpy(fp->name, AudioEslinear_le); 598 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 599 fp->precision = 16; 600 fp->flags = 0; 601 break; 602 case 5: 603 strcpy(fp->name, AudioEulinear_le); 604 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 605 fp->precision = 16; 606 fp->flags = 0; 607 break; 608 case 6: 609 strcpy(fp->name, AudioEslinear_be); 610 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 611 fp->precision = 16; 612 fp->flags = 0; 613 break; 614 case 7: 615 strcpy(fp->name, AudioEulinear_be); 616 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 617 fp->precision = 16; 618 fp->flags = 0; 619 break; 620 default: 621 return EINVAL; 622 } 623 return 0; 624 } 625 626 static int 627 cs4280_set_params(void *addr, int setmode, int usemode, 628 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 629 stream_filter_list_t *rfil) 630 { 631 audio_params_t hw; 632 struct cs428x_softc *sc; 633 struct audio_params *p; 634 stream_filter_list_t *fil; 635 int mode; 636 637 sc = addr; 638 for (mode = AUMODE_RECORD; mode != -1; 639 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 640 if ((setmode & mode) == 0) 641 continue; 642 643 p = mode == AUMODE_PLAY ? play : rec; 644 645 if (p == play) { 646 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 647 p->sample_rate, p->precision, p->channels)); 648 /* play back data format may be 8- or 16-bit and 649 * either stereo or mono. 650 * playback rate may range from 8000Hz to 48000Hz 651 */ 652 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 653 (p->precision != 8 && p->precision != 16) || 654 (p->channels != 1 && p->channels != 2) ) { 655 return EINVAL; 656 } 657 } else { 658 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 659 p->sample_rate, p->precision, p->channels)); 660 /* capture data format must be 16bit stereo 661 * and sample rate range from 11025Hz to 48000Hz. 662 * 663 * XXX: it looks like to work with 8000Hz, 664 * although data sheets say lower limit is 665 * 11025 Hz. 666 */ 667 668 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 669 (p->precision != 8 && p->precision != 16) || 670 (p->channels != 1 && p->channels != 2) ) { 671 return EINVAL; 672 } 673 } 674 fil = mode == AUMODE_PLAY ? pfil : rfil; 675 hw = *p; 676 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 677 678 /* capturing data is slinear */ 679 switch (p->encoding) { 680 case AUDIO_ENCODING_SLINEAR_BE: 681 if (mode == AUMODE_RECORD && p->precision == 16) { 682 fil->append(fil, swap_bytes, &hw); 683 } 684 break; 685 case AUDIO_ENCODING_SLINEAR_LE: 686 break; 687 case AUDIO_ENCODING_ULINEAR_BE: 688 if (mode == AUMODE_RECORD) { 689 fil->append(fil, p->precision == 16 690 ? swap_bytes_change_sign16 691 : change_sign8, &hw); 692 } 693 break; 694 case AUDIO_ENCODING_ULINEAR_LE: 695 if (mode == AUMODE_RECORD) { 696 fil->append(fil, p->precision == 16 697 ? change_sign16 : change_sign8, 698 &hw); 699 } 700 break; 701 case AUDIO_ENCODING_ULAW: 702 if (mode == AUMODE_PLAY) { 703 hw.precision = 16; 704 hw.validbits = 16; 705 fil->append(fil, mulaw_to_linear16, &hw); 706 } else { 707 fil->append(fil, linear8_to_mulaw, &hw); 708 } 709 break; 710 case AUDIO_ENCODING_ALAW: 711 if (mode == AUMODE_PLAY) { 712 hw.precision = 16; 713 hw.validbits = 16; 714 fil->append(fil, alaw_to_linear16, &hw); 715 } else { 716 fil->append(fil, linear8_to_alaw, &hw); 717 } 718 break; 719 default: 720 return EINVAL; 721 } 722 } 723 724 /* set sample rate */ 725 cs4280_set_dac_rate(sc, play->sample_rate); 726 cs4280_set_adc_rate(sc, rec->sample_rate); 727 return 0; 728 } 729 730 static int 731 cs4280_halt_output(void *addr) 732 { 733 struct cs428x_softc *sc; 734 uint32_t mem; 735 736 sc = addr; 737 mem = BA1READ4(sc, CS4280_PCTL); 738 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 739 sc->sc_prun = 0; 740 cs4280_clkrun_hack(sc, -1); 741 742 return 0; 743 } 744 745 static int 746 cs4280_halt_input(void *addr) 747 { 748 struct cs428x_softc *sc; 749 uint32_t mem; 750 751 sc = addr; 752 mem = BA1READ4(sc, CS4280_CCTL); 753 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 754 sc->sc_rrun = 0; 755 cs4280_clkrun_hack(sc, -1); 756 757 return 0; 758 } 759 760 static int 761 cs4280_getdev(void *addr, struct audio_device *retp) 762 { 763 764 *retp = cs4280_device; 765 return 0; 766 } 767 768 static int 769 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 770 void (*intr)(void *), void *arg, 771 const audio_params_t *param) 772 { 773 struct cs428x_softc *sc; 774 uint32_t pfie, pctl, pdtc; 775 struct cs428x_dma *p; 776 777 sc = addr; 778 #ifdef DIAGNOSTIC 779 if (sc->sc_prun) 780 printf("cs4280_trigger_output: already running\n"); 781 #endif 782 sc->sc_prun = 1; 783 cs4280_clkrun_hack(sc, 1); 784 785 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 786 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 787 sc->sc_pintr = intr; 788 sc->sc_parg = arg; 789 790 /* stop playback DMA */ 791 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 792 793 /* setup PDTC */ 794 pdtc = BA1READ4(sc, CS4280_PDTC); 795 pdtc &= ~PDTC_MASK; 796 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 797 BA1WRITE4(sc, CS4280_PDTC, pdtc); 798 799 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 800 param->precision, param->channels, param->encoding)); 801 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 802 continue; 803 if (p == NULL) { 804 printf("cs4280_trigger_output: bad addr %p\n", start); 805 return EINVAL; 806 } 807 if (DMAADDR(p) % sc->dma_align != 0 ) { 808 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 809 "4kB align\n", (ulong)DMAADDR(p)); 810 return EINVAL; 811 } 812 813 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 814 sc->sc_ps = (char *)start; 815 sc->sc_pe = (char *)end; 816 sc->sc_pdma = p; 817 sc->sc_pbuf = KERNADDR(p); 818 sc->sc_pi = 0; 819 sc->sc_pn = sc->sc_ps; 820 if (blksize >= sc->dma_size) { 821 sc->sc_pn = sc->sc_ps + sc->dma_size; 822 memcpy(sc->sc_pbuf, start, sc->dma_size); 823 ++sc->sc_pi; 824 } else { 825 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 826 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 827 } 828 829 /* initiate playback DMA */ 830 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 831 832 /* set PFIE */ 833 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 834 835 if (param->precision == 8) 836 pfie |= PFIE_8BIT; 837 if (param->channels == 1) 838 pfie |= PFIE_MONO; 839 840 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 841 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 842 pfie |= PFIE_SWAPPED; 843 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 844 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 845 pfie |= PFIE_UNSIGNED; 846 847 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 848 849 sc->sc_prate = param->sample_rate; 850 cs4280_set_dac_rate(sc, param->sample_rate); 851 852 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 853 pctl |= sc->pctl; 854 BA1WRITE4(sc, CS4280_PCTL, pctl); 855 return 0; 856 } 857 858 static int 859 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 860 void (*intr)(void *), void *arg, 861 const audio_params_t *param) 862 { 863 struct cs428x_softc *sc; 864 uint32_t cctl, cie; 865 struct cs428x_dma *p; 866 867 sc = addr; 868 #ifdef DIAGNOSTIC 869 if (sc->sc_rrun) 870 printf("cs4280_trigger_input: already running\n"); 871 #endif 872 sc->sc_rrun = 1; 873 cs4280_clkrun_hack(sc, 1); 874 875 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 876 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 877 sc->sc_rintr = intr; 878 sc->sc_rarg = arg; 879 880 /* stop capture DMA */ 881 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 882 883 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 884 continue; 885 if (p == NULL) { 886 printf("cs4280_trigger_input: bad addr %p\n", start); 887 return EINVAL; 888 } 889 if (DMAADDR(p) % sc->dma_align != 0) { 890 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 891 "4kB align\n", (ulong)DMAADDR(p)); 892 return EINVAL; 893 } 894 895 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 896 sc->sc_rs = (char *)start; 897 sc->sc_re = (char *)end; 898 sc->sc_rdma = p; 899 sc->sc_rbuf = KERNADDR(p); 900 sc->sc_ri = 0; 901 sc->sc_rn = sc->sc_rs; 902 903 /* initiate capture DMA */ 904 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 905 906 /* setup format information for internal converter */ 907 sc->sc_rparam = 0; 908 if (param->precision == 8) { 909 sc->sc_rparam += CF_8BIT; 910 sc->sc_rcount <<= 1; 911 } 912 if (param->channels == 1) { 913 sc->sc_rparam += CF_MONO; 914 sc->sc_rcount <<= 1; 915 } 916 917 /* set CIE */ 918 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 919 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 920 921 sc->sc_rrate = param->sample_rate; 922 cs4280_set_adc_rate(sc, param->sample_rate); 923 924 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 925 cctl |= sc->cctl; 926 BA1WRITE4(sc, CS4280_CCTL, cctl); 927 return 0; 928 } 929 930 static bool 931 cs4280_suspend(device_t dv, const pmf_qual_t *qual) 932 { 933 struct cs428x_softc *sc = device_private(dv); 934 935 mutex_exit(&sc->sc_lock); 936 mutex_spin_enter(&sc->sc_intr_lock); 937 938 if (sc->sc_prun) { 939 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 940 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 941 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 942 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 943 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 944 sc->sc_suspend_state.cs4280.pctl, 945 sc->sc_suspend_state.cs4280.pfie, 946 sc->sc_suspend_state.cs4280.pba, 947 sc->sc_suspend_state.cs4280.pdtc)); 948 } 949 950 /* save current capture status */ 951 if (sc->sc_rrun) { 952 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 953 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 954 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 955 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 956 sc->sc_suspend_state.cs4280.cctl, 957 sc->sc_suspend_state.cs4280.cie, 958 sc->sc_suspend_state.cs4280.cba)); 959 } 960 961 /* Stop DMA */ 962 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 963 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 964 965 mutex_spin_exit(&sc->sc_intr_lock); 966 mutex_exit(&sc->sc_lock); 967 968 return true; 969 } 970 971 static bool 972 cs4280_resume(device_t dv, const pmf_qual_t *qual) 973 { 974 struct cs428x_softc *sc = device_private(dv); 975 976 mutex_exit(&sc->sc_lock); 977 mutex_spin_enter(&sc->sc_intr_lock); 978 cs4280_init(sc, 0); 979 #if 0 980 cs4280_reset_codec(sc); 981 #endif 982 983 /* restore DMA related status */ 984 if(sc->sc_prun) { 985 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 986 sc->sc_suspend_state.cs4280.pctl, 987 sc->sc_suspend_state.cs4280.pfie, 988 sc->sc_suspend_state.cs4280.pba, 989 sc->sc_suspend_state.cs4280.pdtc)); 990 cs4280_set_dac_rate(sc, sc->sc_prate); 991 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 992 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 993 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 994 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 995 } 996 997 if (sc->sc_rrun) { 998 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 999 sc->sc_suspend_state.cs4280.cctl, 1000 sc->sc_suspend_state.cs4280.cie, 1001 sc->sc_suspend_state.cs4280.cba)); 1002 cs4280_set_adc_rate(sc, sc->sc_rrate); 1003 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 1004 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 1005 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 1006 } 1007 1008 mutex_spin_exit(&sc->sc_intr_lock); 1009 1010 /* restore ac97 registers */ 1011 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1012 1013 mutex_exit(&sc->sc_lock); 1014 1015 return true; 1016 } 1017 1018 static int 1019 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 1020 { 1021 struct cs428x_softc *sc = addr; 1022 int rv; 1023 1024 cs4280_clkrun_hack(sc, 1); 1025 rv = cs428x_read_codec(addr, reg, result); 1026 cs4280_clkrun_hack(sc, -1); 1027 1028 return rv; 1029 } 1030 1031 static int 1032 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1033 { 1034 struct cs428x_softc *sc = addr; 1035 int rv; 1036 1037 cs4280_clkrun_hack(sc, 1); 1038 rv = cs428x_write_codec(addr, reg, data); 1039 cs4280_clkrun_hack(sc, -1); 1040 1041 return rv; 1042 } 1043 1044 #if 0 /* XXX buggy and not required */ 1045 /* control AC97 codec */ 1046 static int 1047 cs4280_reset_codec(void *addr) 1048 { 1049 struct cs428x_softc *sc; 1050 int n; 1051 1052 sc = addr; 1053 1054 /* Reset codec */ 1055 BA0WRITE4(sc, CS428X_ACCTL, 0); 1056 delay(100); /* delay 100us */ 1057 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1058 1059 /* 1060 * It looks like we do the following procedure, too 1061 */ 1062 1063 /* Enable AC-link sync generation */ 1064 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1065 delay(50*1000); /* XXX delay 50ms */ 1066 1067 /* Assert valid frame signal */ 1068 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1069 1070 /* Wait for valid AC97 input slot */ 1071 n = 0; 1072 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1073 (ACISV_ISV3 | ACISV_ISV4)) { 1074 delay(1000); 1075 if (++n > 1000) { 1076 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1077 return ETIMEDOUT; 1078 } 1079 } 1080 1081 return 0; 1082 } 1083 #endif 1084 1085 static enum ac97_host_flags 1086 cs4280_flags_codec(void *addr) 1087 { 1088 struct cs428x_softc *sc; 1089 1090 sc = addr; 1091 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1092 return AC97_HOST_INVERTED_EAMP; 1093 1094 return 0; 1095 } 1096 1097 /* Internal functions */ 1098 1099 static const struct cs4280_card_t * 1100 cs4280_identify_card(const struct pci_attach_args *pa) 1101 { 1102 pcireg_t idreg; 1103 u_int16_t i; 1104 1105 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1106 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1107 if (idreg == cs4280_cards[i].id) 1108 return &cs4280_cards[i]; 1109 } 1110 1111 return NULL; 1112 } 1113 1114 static int 1115 cs4280_piix4_match(const struct pci_attach_args *pa) 1116 { 1117 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1118 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1119 return 1; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static void 1126 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1127 { 1128 uint16_t control, val; 1129 1130 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1131 return; 1132 1133 sc->sc_active += change; 1134 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1135 if (!sc->sc_active) 1136 val |= 0x2000; 1137 else 1138 val &= ~0x2000; 1139 if (val != control) 1140 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1141 } 1142 1143 static void 1144 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1145 { 1146 struct pci_attach_args smbuspa; 1147 uint16_t reg; 1148 pcireg_t port; 1149 1150 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1151 return; 1152 1153 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1154 sc->sc_active = 0; 1155 aprint_normal_dev(&sc->sc_dev, "enabling CLKRUN hack\n"); 1156 1157 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1158 port = reg & 0xffc0; 1159 aprint_normal_dev(&sc->sc_dev, "power management port 0x%x\n", 1160 port); 1161 1162 sc->sc_pm_iot = smbuspa.pa_iot; 1163 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1164 &sc->sc_pm_ioh) == 0) 1165 return; 1166 } 1167 1168 /* handle error */ 1169 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1170 aprint_normal_dev(&sc->sc_dev, "disabling CLKRUN hack\n"); 1171 } 1172 1173 static void 1174 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1175 { 1176 /* calculate capture rate: 1177 * 1178 * capture_coefficient_increment = -round(rate*128*65536/48000; 1179 * capture_phase_increment = floor(48000*65536*1024/rate); 1180 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1181 * cy = floor(cx/200); 1182 * capture_sample_rate_correction = cx - 200*cy; 1183 * capture_delay = ceil(24*48000/rate); 1184 * capture_num_triplets = floor(65536*rate/24000); 1185 * capture_group_length = 24000/GCD(rate, 24000); 1186 * where GCD means "Greatest Common Divisor". 1187 * 1188 * capture_coefficient_increment, capture_phase_increment and 1189 * capture_num_triplets are 32-bit signed quantities. 1190 * capture_sample_rate_correction and capture_group_length are 1191 * 16-bit signed quantities. 1192 * capture_delay is a 14-bit unsigned quantity. 1193 */ 1194 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1195 uint16_t csrc, cgl, cdlay; 1196 1197 /* XXX 1198 * Even though, embedded_audio_spec says capture rate range 11025 to 1199 * 48000, dhwiface.cpp says, 1200 * 1201 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1202 * Return an error if an attempt is made to stray outside that limit." 1203 * 1204 * so assume range as 48000/9 to 48000 1205 */ 1206 1207 if (rate < 8000) 1208 rate = 8000; 1209 if (rate > 48000) 1210 rate = 48000; 1211 1212 cx = rate << 16; 1213 cci = cx / 48000; 1214 cx -= cci * 48000; 1215 cx <<= 7; 1216 cci <<= 7; 1217 cci += cx / 48000; 1218 cci = - cci; 1219 1220 cx = 48000 << 16; 1221 cpi = cx / rate; 1222 cx -= cpi * rate; 1223 cx <<= 10; 1224 cpi <<= 10; 1225 cy = cx / rate; 1226 cpi += cy; 1227 cx -= cy * rate; 1228 1229 cy = cx / 200; 1230 csrc = cx - 200*cy; 1231 1232 cdlay = ((48000 * 24) + rate - 1) / rate; 1233 #if 0 1234 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1235 #endif 1236 1237 cnt = rate << 16; 1238 cnt /= 24000; 1239 1240 cgl = 1; 1241 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1242 if (((rate / tmp1) * tmp1) != rate) 1243 cgl *= 2; 1244 } 1245 if (((rate / 3) * 3) != rate) 1246 cgl *= 3; 1247 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1248 if (((rate / tmp1) * tmp1) != rate) 1249 cgl *= 5; 1250 } 1251 #if 0 1252 /* XXX what manual says */ 1253 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1254 tmp1 |= csrc<<16; 1255 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1256 #else 1257 /* suggested by cs461x.c (ALSA driver) */ 1258 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1259 #endif 1260 1261 #if 0 1262 /* I am confused. The sample rate calculation section says 1263 * cci *is* 32-bit signed quantity but in the parameter description 1264 * section, CCI only assigned 16bit. 1265 * I believe size of the variable. 1266 */ 1267 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1268 tmp1 |= cci<<16; 1269 BA1WRITE4(sc, CS4280_CCI, tmp1); 1270 #else 1271 BA1WRITE4(sc, CS4280_CCI, cci); 1272 #endif 1273 1274 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1275 tmp1 |= cdlay <<18; 1276 BA1WRITE4(sc, CS4280_CD, tmp1); 1277 1278 BA1WRITE4(sc, CS4280_CPI, cpi); 1279 1280 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1281 tmp1 |= cgl; 1282 BA1WRITE4(sc, CS4280_CGL, tmp1); 1283 1284 BA1WRITE4(sc, CS4280_CNT, cnt); 1285 1286 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1287 tmp1 |= cgl; 1288 BA1WRITE4(sc, CS4280_CGC, tmp1); 1289 } 1290 1291 static void 1292 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1293 { 1294 /* 1295 * playback rate may range from 8000Hz to 48000Hz 1296 * 1297 * play_phase_increment = floor(rate*65536*1024/48000) 1298 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1299 * py=floor(px/200) 1300 * play_sample_rate_correction = px - 200*py 1301 * 1302 * play_phase_increment is a 32bit signed quantity. 1303 * play_sample_rate_correction is a 16bit signed quantity. 1304 */ 1305 int32_t ppi; 1306 int16_t psrc; 1307 uint32_t px, py; 1308 1309 if (rate < 8000) 1310 rate = 8000; 1311 if (rate > 48000) 1312 rate = 48000; 1313 px = rate << 16; 1314 ppi = px/48000; 1315 px -= ppi*48000; 1316 ppi <<= 10; 1317 px <<= 10; 1318 py = px / 48000; 1319 ppi += py; 1320 px -= py*48000; 1321 py = px/200; 1322 px -= py*200; 1323 psrc = px; 1324 #if 0 1325 /* what manual says */ 1326 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1327 BA1WRITE4(sc, CS4280_PSRC, 1328 ( ((psrc<<16) & PSRC_MASK) | px )); 1329 #else 1330 /* suggested by cs461x.c (ALSA driver) */ 1331 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1332 #endif 1333 BA1WRITE4(sc, CS4280_PPI, ppi); 1334 } 1335 1336 /* Download Processor Code and Data image */ 1337 static int 1338 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1339 uint32_t offset, uint32_t len) 1340 { 1341 uint32_t ctr; 1342 #if CS4280_DEBUG > 10 1343 uint32_t con, data; 1344 uint8_t c0, c1, c2, c3; 1345 #endif 1346 if ((offset & 3) || (len & 3)) 1347 return -1; 1348 1349 len /= sizeof(uint32_t); 1350 for (ctr = 0; ctr < len; ctr++) { 1351 /* XXX: 1352 * I cannot confirm this is the right thing or not 1353 * on BIG-ENDIAN machines. 1354 */ 1355 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1356 #if CS4280_DEBUG > 10 1357 data = htole32(*(src+ctr)); 1358 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1359 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1360 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1361 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1362 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1363 if (data != con ) { 1364 printf("0x%06x: write=0x%08x read=0x%08x\n", 1365 offset+ctr*4, data, con); 1366 return -1; 1367 } 1368 #endif 1369 } 1370 return 0; 1371 } 1372 1373 static int 1374 cs4280_download_image(struct cs428x_softc *sc) 1375 { 1376 int idx, err; 1377 uint32_t offset = 0; 1378 1379 err = 0; 1380 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1381 err = cs4280_download(sc, &BA1Struct.map[offset], 1382 BA1Struct.memory[idx].offset, 1383 BA1Struct.memory[idx].size); 1384 if (err != 0) { 1385 aprint_error_dev(&sc->sc_dev, 1386 "load_image failed at %d\n", idx); 1387 return -1; 1388 } 1389 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1390 } 1391 return err; 1392 } 1393 1394 /* Processor Soft Reset */ 1395 static void 1396 cs4280_reset(void *sc_) 1397 { 1398 struct cs428x_softc *sc; 1399 1400 sc = sc_; 1401 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1402 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1403 delay(100); 1404 /* Clear RSTSP bit in SPCR */ 1405 BA1WRITE4(sc, CS4280_SPCR, 0); 1406 /* enable DMA reqest */ 1407 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1408 } 1409 1410 static int 1411 cs4280_init(struct cs428x_softc *sc, int init) 1412 { 1413 int n; 1414 uint32_t mem; 1415 int rv; 1416 1417 rv = 1; 1418 cs4280_clkrun_hack(sc, 1); 1419 1420 /* Start PLL out in known state */ 1421 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1422 /* Start serial ports out in known state */ 1423 BA0WRITE4(sc, CS4280_SERMC1, 0); 1424 1425 /* Specify type of CODEC */ 1426 /* XXX should not be here */ 1427 #define SERACC_CODEC_TYPE_1_03 1428 #ifdef SERACC_CODEC_TYPE_1_03 1429 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1430 #else 1431 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1432 #endif 1433 1434 /* Reset codec */ 1435 BA0WRITE4(sc, CS428X_ACCTL, 0); 1436 delay(100); /* delay 100us */ 1437 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1438 1439 /* Enable AC-link sync generation */ 1440 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1441 delay(50*1000); /* delay 50ms */ 1442 1443 /* Set the serial port timing configuration */ 1444 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1445 1446 /* Setup clock control */ 1447 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1448 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1449 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1450 1451 /* Power up the PLL */ 1452 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1453 delay(50*1000); /* delay 50ms */ 1454 1455 /* Turn on clock */ 1456 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1457 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1458 1459 /* Set the serial port FIFO pointer to the 1460 * first sample in FIFO. (not documented) */ 1461 cs4280_clear_fifos(sc); 1462 1463 #if 0 1464 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1465 BA0WRITE4(sc, CS4280_SERBSP, 0); 1466 #endif 1467 1468 /* Configure the serial port */ 1469 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1470 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1471 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1472 1473 /* Wait for CODEC ready */ 1474 n = 0; 1475 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1476 delay(125); 1477 if (++n > 1000) { 1478 aprint_error_dev(&sc->sc_dev, "codec ready timeout\n"); 1479 goto exit; 1480 } 1481 } 1482 1483 /* Assert valid frame signal */ 1484 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1485 1486 /* Wait for valid AC97 input slot */ 1487 n = 0; 1488 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1489 (ACISV_ISV3 | ACISV_ISV4)) { 1490 delay(1000); 1491 if (++n > 1000) { 1492 printf("AC97 inputs slot ready timeout\n"); 1493 goto exit; 1494 } 1495 } 1496 1497 /* Set AC97 output slot valid signals */ 1498 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1499 1500 /* reset the processor */ 1501 cs4280_reset(sc); 1502 1503 /* Download the image to the processor */ 1504 if (cs4280_download_image(sc) != 0) { 1505 aprint_error_dev(&sc->sc_dev, "image download error\n"); 1506 goto exit; 1507 } 1508 1509 /* Save playback parameter and then write zero. 1510 * this ensures that DMA doesn't immediately occur upon 1511 * starting the processor core 1512 */ 1513 mem = BA1READ4(sc, CS4280_PCTL); 1514 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1515 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1516 if (init != 0) 1517 sc->sc_prun = 0; 1518 1519 /* Save capture parameter and then write zero. 1520 * this ensures that DMA doesn't immediately occur upon 1521 * starting the processor core 1522 */ 1523 mem = BA1READ4(sc, CS4280_CCTL); 1524 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1525 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1526 if (init != 0) 1527 sc->sc_rrun = 0; 1528 1529 /* Processor Startup Procedure */ 1530 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1531 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1532 1533 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1534 n = 0; 1535 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1536 delay(10); 1537 if (++n > 1000) { 1538 printf("SPCR 1->0 transition timeout\n"); 1539 goto exit; 1540 } 1541 } 1542 1543 n = 0; 1544 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1545 delay(10); 1546 if (++n > 1000) { 1547 printf("SPCS 0->1 transition timeout\n"); 1548 goto exit; 1549 } 1550 } 1551 /* Processor is now running !!! */ 1552 1553 /* Setup volume */ 1554 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1555 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1556 1557 /* Interrupt enable */ 1558 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1559 1560 /* playback interrupt enable */ 1561 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1562 mem |= PFIE_PI_ENABLE; 1563 BA1WRITE4(sc, CS4280_PFIE, mem); 1564 /* capture interrupt enable */ 1565 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1566 mem |= CIE_CI_ENABLE; 1567 BA1WRITE4(sc, CS4280_CIE, mem); 1568 1569 #if NMIDI > 0 1570 /* Reset midi port */ 1571 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1572 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1573 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1574 /* midi interrupt enable */ 1575 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1576 BA0WRITE4(sc, CS4280_MIDCR, mem); 1577 #endif 1578 1579 rv = 0; 1580 1581 exit: 1582 cs4280_clkrun_hack(sc, -1); 1583 return rv; 1584 } 1585 1586 static void 1587 cs4280_clear_fifos(struct cs428x_softc *sc) 1588 { 1589 int pd, cnt, n; 1590 uint32_t mem; 1591 1592 pd = 0; 1593 /* 1594 * If device power down, power up the device and keep power down 1595 * state. 1596 */ 1597 mem = BA0READ4(sc, CS4280_CLKCR1); 1598 if (!(mem & CLKCR1_SWCE)) { 1599 printf("cs4280_clear_fifo: power down found.\n"); 1600 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1601 pd = 1; 1602 } 1603 BA0WRITE4(sc, CS4280_SERBWP, 0); 1604 for (cnt = 0; cnt < 256; cnt++) { 1605 n = 0; 1606 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1607 delay(1000); 1608 if (++n > 1000) { 1609 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1610 break; 1611 } 1612 } 1613 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1614 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1615 } 1616 if (pd) 1617 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1618 } 1619 1620 #if NMIDI > 0 1621 static int 1622 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1623 void (*ointr)(void *), void *arg) 1624 { 1625 struct cs428x_softc *sc; 1626 uint32_t mem; 1627 1628 DPRINTF(("midi_open\n")); 1629 sc = addr; 1630 sc->sc_iintr = iintr; 1631 sc->sc_ointr = ointr; 1632 sc->sc_arg = arg; 1633 1634 /* midi interrupt enable */ 1635 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1636 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1637 BA0WRITE4(sc, CS4280_MIDCR, mem); 1638 #ifdef CS4280_DEBUG 1639 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1640 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1641 return(EINVAL); 1642 } 1643 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1644 #endif 1645 return 0; 1646 } 1647 1648 static void 1649 cs4280_midi_close(void *addr) 1650 { 1651 struct cs428x_softc *sc; 1652 uint32_t mem; 1653 1654 DPRINTF(("midi_close\n")); 1655 sc = addr; 1656 /* give uart a chance to drain */ 1657 kpause("cs0clm", false, hz/10, &sc->sc_intr_lock); 1658 mem = BA0READ4(sc, CS4280_MIDCR); 1659 mem &= ~MIDCR_MASK; 1660 BA0WRITE4(sc, CS4280_MIDCR, mem); 1661 1662 sc->sc_iintr = 0; 1663 sc->sc_ointr = 0; 1664 } 1665 1666 static int 1667 cs4280_midi_output(void *addr, int d) 1668 { 1669 struct cs428x_softc *sc; 1670 uint32_t mem; 1671 int x; 1672 1673 sc = addr; 1674 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1675 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1676 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1677 mem |= d & MIDWP_MASK; 1678 DPRINTFN(5,("midi_output d=0x%08x",d)); 1679 BA0WRITE4(sc, CS4280_MIDWP, mem); 1680 #ifdef DIAGNOSTIC 1681 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1682 DPRINTF(("Bad write data: %d %d", 1683 mem, BA0READ4(sc, CS4280_MIDWP))); 1684 return EIO; 1685 } 1686 #endif 1687 return 0; 1688 } 1689 delay(MIDI_BUSY_DELAY); 1690 } 1691 return EIO; 1692 } 1693 1694 static void 1695 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1696 { 1697 1698 mi->name = "CS4280 MIDI UART"; 1699 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1700 } 1701 1702 #endif /* NMIDI */ 1703 1704 /* DEBUG functions */ 1705 #if CS4280_DEBUG > 10 1706 static int 1707 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1708 uint32_t offset, uint32_t len) 1709 { 1710 uint32_t ctr, data; 1711 int err; 1712 1713 if ((offset & 3) || (len & 3)) 1714 return -1; 1715 1716 err = 0; 1717 len /= sizeof(uint32_t); 1718 for (ctr = 0; ctr < len; ctr++) { 1719 /* I cannot confirm this is the right thing 1720 * on BIG-ENDIAN machines 1721 */ 1722 data = BA1READ4(sc, offset+ctr*4); 1723 if (data != htole32(*(src+ctr))) { 1724 printf("0x%06x: 0x%08x(0x%08x)\n", 1725 offset+ctr*4, data, *(src+ctr)); 1726 *(src+ctr) = data; 1727 ++err; 1728 } 1729 } 1730 return err; 1731 } 1732 1733 static int 1734 cs4280_check_images(struct cs428x_softc *sc) 1735 { 1736 int idx, err; 1737 uint32_t offset; 1738 1739 offset = 0; 1740 err = 0; 1741 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1742 for (idx = 0; idx < 1; ++idx) { 1743 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1744 BA1Struct.memory[idx].offset, 1745 BA1Struct.memory[idx].size); 1746 if (err != 0) { 1747 aprint_error_dev(&sc->sc_dev, 1748 "check_image failed at %d\n", idx); 1749 } 1750 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1751 } 1752 return err; 1753 } 1754 1755 #endif /* CS4280_DEBUG */ 1756
Indexes created Thu Oct 02 14:10:14 GMT 2025