cs4280.c revision 1.65
1 /* $NetBSD: cs4280.c,v 1.65 2012/10/27 17:18:28 chs Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.65 2012/10/27 17:18:28 chs Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 #include <sys/audioio.h> 68 #include <sys/bus.h> 69 #include <sys/bswap.h> 70 71 #include <dev/audio_if.h> 72 #include <dev/midi_if.h> 73 #include <dev/mulaw.h> 74 #include <dev/auconv.h> 75 76 #include <dev/ic/ac97reg.h> 77 #include <dev/ic/ac97var.h> 78 79 #include <dev/pci/pcidevs.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/cs4280reg.h> 82 #include <dev/pci/cs4280_image.h> 83 #include <dev/pci/cs428xreg.h> 84 #include <dev/pci/cs428x.h> 85 86 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 87 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 88 89 /* IF functions for audio driver */ 90 static int cs4280_match(device_t, cfdata_t, void *); 91 static void cs4280_attach(device_t, device_t, void *); 92 static int cs4280_intr(void *); 93 static int cs4280_query_encoding(void *, struct audio_encoding *); 94 static int cs4280_set_params(void *, int, int, audio_params_t *, 95 audio_params_t *, stream_filter_list_t *, 96 stream_filter_list_t *); 97 static int cs4280_halt_output(void *); 98 static int cs4280_halt_input(void *); 99 static int cs4280_getdev(void *, struct audio_device *); 100 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 101 void *, const audio_params_t *); 102 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 105 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 106 #if 0 107 static int cs4280_reset_codec(void *); 108 #endif 109 static enum ac97_host_flags cs4280_flags_codec(void *); 110 111 static bool cs4280_resume(device_t, const pmf_qual_t *); 112 static bool cs4280_suspend(device_t, const pmf_qual_t *); 113 114 /* Internal functions */ 115 static const struct cs4280_card_t * cs4280_identify_card(const struct pci_attach_args *); 116 static int cs4280_piix4_match(const struct pci_attach_args *); 117 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 118 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 119 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 120 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 121 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 122 uint32_t); 123 static int cs4280_download_image(struct cs428x_softc *); 124 static void cs4280_reset(void *); 125 static int cs4280_init(struct cs428x_softc *, int); 126 static void cs4280_clear_fifos(struct cs428x_softc *); 127 128 #if CS4280_DEBUG > 10 129 /* Thease two function is only for checking image loading is succeeded or not. */ 130 static int cs4280_check_images(struct cs428x_softc *); 131 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 132 uint32_t); 133 #endif 134 135 /* Special cards */ 136 struct cs4280_card_t 137 { 138 pcireg_t id; 139 enum cs428x_flags flags; 140 }; 141 142 #define _card(vend, prod, flags) \ 143 {PCI_ID_CODE(vend, prod), flags} 144 145 static const struct cs4280_card_t cs4280_cards[] = { 146 #if 0 /* untested, from ALSA driver */ 147 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 148 CS428X_FLAG_INVAC97EAMP), 149 #endif 150 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 151 CS428X_FLAG_INVAC97EAMP), 152 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 153 CS428X_FLAG_CLKRUNHACK) 154 }; 155 156 #undef _card 157 158 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 159 160 static const struct audio_hw_if cs4280_hw_if = { 161 NULL, /* open */ 162 NULL, /* close */ 163 NULL, 164 cs4280_query_encoding, 165 cs4280_set_params, 166 cs428x_round_blocksize, 167 NULL, 168 NULL, 169 NULL, 170 NULL, 171 NULL, 172 cs4280_halt_output, 173 cs4280_halt_input, 174 NULL, 175 cs4280_getdev, 176 NULL, 177 cs428x_mixer_set_port, 178 cs428x_mixer_get_port, 179 cs428x_query_devinfo, 180 cs428x_malloc, 181 cs428x_free, 182 cs428x_round_buffersize, 183 cs428x_mappage, 184 cs428x_get_props, 185 cs4280_trigger_output, 186 cs4280_trigger_input, 187 NULL, 188 cs428x_get_locks, 189 }; 190 191 #if NMIDI > 0 192 /* Midi Interface */ 193 static int cs4280_midi_open(void *, int, void (*)(void *, int), 194 void (*)(void *), void *); 195 static void cs4280_midi_close(void*); 196 static int cs4280_midi_output(void *, int); 197 static void cs4280_midi_getinfo(void *, struct midi_info *); 198 199 static const struct midi_hw_if cs4280_midi_hw_if = { 200 cs4280_midi_open, 201 cs4280_midi_close, 202 cs4280_midi_output, 203 cs4280_midi_getinfo, 204 0, 205 cs428x_get_locks, 206 }; 207 #endif 208 209 CFATTACH_DECL_NEW(clcs, sizeof(struct cs428x_softc), 210 cs4280_match, cs4280_attach, NULL, NULL); 211 212 static struct audio_device cs4280_device = { 213 "CS4280", 214 "", 215 "cs4280" 216 }; 217 218 219 static int 220 cs4280_match(device_t parent, cfdata_t match, void *aux) 221 { 222 struct pci_attach_args *pa; 223 224 pa = (struct pci_attach_args *)aux; 225 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 226 return 0; 227 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 228 #if 0 /* I can't confirm */ 229 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 230 #endif 231 ) 232 return 1; 233 return 0; 234 } 235 236 static void 237 cs4280_attach(device_t parent, device_t self, void *aux) 238 { 239 struct cs428x_softc *sc; 240 struct pci_attach_args *pa; 241 pci_chipset_tag_t pc; 242 const struct cs4280_card_t *cs_card; 243 char const *intrstr; 244 const char *vendor, *product; 245 pcireg_t reg; 246 uint32_t mem; 247 int error; 248 249 sc = device_private(self); 250 sc->sc_dev = self; 251 pa = (struct pci_attach_args *)aux; 252 pc = pa->pa_pc; 253 254 pci_aprint_devinfo(pa, "Audio controller"); 255 256 cs_card = cs4280_identify_card(pa); 257 if (cs_card != NULL) { 258 vendor = pci_findvendor(cs_card->id); 259 product = pci_findproduct(cs_card->id); 260 if (vendor == NULL) 261 aprint_normal_dev(sc->sc_dev, 262 "vendor 0x%04x product 0x%04x\n", 263 PCI_VENDOR(cs_card->id), 264 PCI_PRODUCT(cs_card->id)); 265 else if (product == NULL) 266 aprint_normal_dev(sc->sc_dev, "%s product 0x%04x\n", 267 vendor, PCI_PRODUCT(cs_card->id)); 268 else 269 aprint_normal_dev(sc->sc_dev, "%s %s\n", 270 vendor, product); 271 sc->sc_flags = cs_card->flags; 272 } else { 273 sc->sc_flags = CS428X_FLAG_NONE; 274 } 275 276 sc->sc_pc = pa->pa_pc; 277 sc->sc_pt = pa->pa_tag; 278 279 /* Map I/O register */ 280 if (pci_mapreg_map(pa, PCI_BA0, 281 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 282 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 283 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 284 return; 285 } 286 if (pci_mapreg_map(pa, PCI_BA1, 287 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 288 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 289 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 290 return; 291 } 292 293 sc->sc_dmatag = pa->pa_dmat; 294 295 /* power up chip */ 296 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 297 pci_activate_null)) && error != EOPNOTSUPP) { 298 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 299 return; 300 } 301 302 /* Enable the device (set bus master flag) */ 303 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 304 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 305 reg | PCI_COMMAND_MASTER_ENABLE); 306 307 /* LATENCY_TIMER setting */ 308 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 309 if ( PCI_LATTIMER(mem) < 32 ) { 310 mem &= 0xffff00ff; 311 mem |= 0x00002000; 312 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 313 } 314 315 /* CLKRUN hack initialization */ 316 cs4280_clkrun_hack_init(sc); 317 318 /* Map and establish the interrupt. */ 319 if (pci_intr_map(pa, &sc->intrh)) { 320 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 321 return; 322 } 323 intrstr = pci_intr_string(pc, sc->intrh); 324 325 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 326 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 327 328 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 329 cs4280_intr, sc); 330 if (sc->sc_ih == NULL) { 331 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 332 if (intrstr != NULL) 333 aprint_error(" at %s", intrstr); 334 aprint_error("\n"); 335 mutex_destroy(&sc->sc_lock); 336 mutex_destroy(&sc->sc_intr_lock); 337 return; 338 } 339 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 340 341 /* Initialization */ 342 if(cs4280_init(sc, 1) != 0) { 343 mutex_destroy(&sc->sc_lock); 344 mutex_destroy(&sc->sc_intr_lock); 345 return; 346 } 347 348 sc->type = TYPE_CS4280; 349 sc->halt_input = cs4280_halt_input; 350 sc->halt_output = cs4280_halt_output; 351 352 /* setup buffer related parameters */ 353 sc->dma_size = CS4280_DCHUNK; 354 sc->dma_align = CS4280_DALIGN; 355 sc->hw_blocksize = CS4280_ICHUNK; 356 357 /* AC 97 attachment */ 358 sc->host_if.arg = sc; 359 sc->host_if.attach = cs428x_attach_codec; 360 sc->host_if.read = cs4280_read_codec; 361 sc->host_if.write = cs4280_write_codec; 362 #if 0 363 sc->host_if.reset = cs4280_reset_codec; 364 #else 365 sc->host_if.reset = NULL; 366 #endif 367 sc->host_if.flags = cs4280_flags_codec; 368 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 369 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 370 return; 371 } 372 373 audio_attach_mi(&cs4280_hw_if, sc, sc->sc_dev); 374 375 #if NMIDI > 0 376 midi_attach_mi(&cs4280_midi_hw_if, sc, sc->sc_dev); 377 #endif 378 379 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 380 aprint_error_dev(self, "couldn't establish power handler\n"); 381 } 382 383 /* Interrupt handling function */ 384 static int 385 cs4280_intr(void *p) 386 { 387 /* 388 * XXX 389 * 390 * Since CS4280 has only 4kB DMA buffer and 391 * interrupt occurs every 2kB block, I create dummy buffer 392 * which returns to audio driver and actual DMA buffer 393 * using in DMA transfer. 394 * 395 * 396 * ring buffer in audio.c is pointed by BUFADDR 397 * <------ ring buffer size == 64kB ------> 398 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 399 * |= = = =|= = = =|= = = =|= = = =|= = = =| 400 * | | | | | | <- call audio_intp every 401 * sc->sc_[pr]_count time. 402 * 403 * actual DMA buffer is pointed by KERNADDR 404 * <-> DMA buffer size = 4kB 405 * |= =| 406 * 407 * 408 */ 409 struct cs428x_softc *sc; 410 uint32_t intr, mem; 411 char * empty_dma; 412 int handled; 413 414 sc = p; 415 handled = 0; 416 417 mutex_spin_enter(&sc->sc_intr_lock); 418 419 /* grab interrupt register then clear it */ 420 intr = BA0READ4(sc, CS4280_HISR); 421 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 422 423 /* not for us ? */ 424 if ((intr & HISR_INTENA) == 0) { 425 mutex_spin_exit(&sc->sc_intr_lock); 426 return 0; 427 } 428 429 /* Playback Interrupt */ 430 if (intr & HISR_PINT) { 431 handled = 1; 432 mem = BA1READ4(sc, CS4280_PFIE); 433 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 434 if (sc->sc_prun) { 435 if ((sc->sc_pi%sc->sc_pcount) == 0) 436 sc->sc_pintr(sc->sc_parg); 437 /* copy buffer */ 438 ++sc->sc_pi; 439 empty_dma = sc->sc_pdma->addr; 440 if (sc->sc_pi&1) 441 empty_dma += sc->hw_blocksize; 442 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 443 sc->sc_pn += sc->hw_blocksize; 444 if (sc->sc_pn >= sc->sc_pe) 445 sc->sc_pn = sc->sc_ps; 446 } else { 447 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 448 } 449 BA1WRITE4(sc, CS4280_PFIE, mem); 450 } 451 /* Capture Interrupt */ 452 if (intr & HISR_CINT) { 453 int i; 454 int16_t rdata; 455 456 handled = 1; 457 mem = BA1READ4(sc, CS4280_CIE); 458 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 459 460 if (sc->sc_rrun) { 461 ++sc->sc_ri; 462 empty_dma = sc->sc_rdma->addr; 463 if ((sc->sc_ri&1) == 0) 464 empty_dma += sc->hw_blocksize; 465 466 /* 467 * XXX 468 * I think this audio data conversion should be 469 * happend in upper layer, but I put this here 470 * since there is no conversion function available. 471 */ 472 switch(sc->sc_rparam) { 473 case CF_16BIT_STEREO: 474 /* just copy it */ 475 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 476 sc->sc_rn += sc->hw_blocksize; 477 break; 478 case CF_16BIT_MONO: 479 for (i = 0; i < 512; i++) { 480 rdata = *((int16_t *)empty_dma)>>1; 481 empty_dma += 2; 482 rdata += *((int16_t *)empty_dma)>>1; 483 empty_dma += 2; 484 *((int16_t *)sc->sc_rn) = rdata; 485 sc->sc_rn += 2; 486 } 487 break; 488 case CF_8BIT_STEREO: 489 for (i = 0; i < 512; i++) { 490 rdata = *((int16_t*)empty_dma); 491 empty_dma += 2; 492 *sc->sc_rn++ = rdata >> 8; 493 rdata = *((int16_t*)empty_dma); 494 empty_dma += 2; 495 *sc->sc_rn++ = rdata >> 8; 496 } 497 break; 498 case CF_8BIT_MONO: 499 for (i = 0; i < 512; i++) { 500 rdata = *((int16_t*)empty_dma) >>1; 501 empty_dma += 2; 502 rdata += *((int16_t*)empty_dma) >>1; 503 empty_dma += 2; 504 *sc->sc_rn++ = rdata >>8; 505 } 506 break; 507 default: 508 /* Should not reach here */ 509 aprint_error_dev(sc->sc_dev, 510 "unknown sc->sc_rparam: %d\n", 511 sc->sc_rparam); 512 } 513 if (sc->sc_rn >= sc->sc_re) 514 sc->sc_rn = sc->sc_rs; 515 } 516 BA1WRITE4(sc, CS4280_CIE, mem); 517 518 if (sc->sc_rrun) { 519 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 520 sc->sc_rintr(sc->sc_rarg); 521 } else { 522 aprint_error_dev(sc->sc_dev, 523 "unexpected record intr\n"); 524 } 525 } 526 527 #if NMIDI > 0 528 /* Midi port Interrupt */ 529 if (intr & HISR_MIDI) { 530 int data; 531 532 handled = 1; 533 DPRINTF(("i: %d: ", 534 BA0READ4(sc, CS4280_MIDSR))); 535 /* Read the received data */ 536 while ((sc->sc_iintr != NULL) && 537 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 538 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 539 DPRINTF(("r:%x\n",data)); 540 sc->sc_iintr(sc->sc_arg, data); 541 } 542 543 /* Write the data */ 544 #if 1 545 /* XXX: 546 * It seems "Transmit Buffer Full" never activate until EOI 547 * is deliverd. Shall I throw EOI top of this routine ? 548 */ 549 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 550 DPRINTF(("w: ")); 551 if (sc->sc_ointr != NULL) 552 sc->sc_ointr(sc->sc_arg); 553 } 554 #else 555 while ((sc->sc_ointr != NULL) && 556 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 557 DPRINTF(("w: ")); 558 sc->sc_ointr(sc->sc_arg); 559 } 560 #endif 561 DPRINTF(("\n")); 562 } 563 #endif 564 565 mutex_spin_exit(&sc->sc_intr_lock); 566 return handled; 567 } 568 569 static int 570 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 571 { 572 switch (fp->index) { 573 case 0: 574 strcpy(fp->name, AudioEulinear); 575 fp->encoding = AUDIO_ENCODING_ULINEAR; 576 fp->precision = 8; 577 fp->flags = 0; 578 break; 579 case 1: 580 strcpy(fp->name, AudioEmulaw); 581 fp->encoding = AUDIO_ENCODING_ULAW; 582 fp->precision = 8; 583 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 584 break; 585 case 2: 586 strcpy(fp->name, AudioEalaw); 587 fp->encoding = AUDIO_ENCODING_ALAW; 588 fp->precision = 8; 589 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 590 break; 591 case 3: 592 strcpy(fp->name, AudioEslinear); 593 fp->encoding = AUDIO_ENCODING_SLINEAR; 594 fp->precision = 8; 595 fp->flags = 0; 596 break; 597 case 4: 598 strcpy(fp->name, AudioEslinear_le); 599 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 600 fp->precision = 16; 601 fp->flags = 0; 602 break; 603 case 5: 604 strcpy(fp->name, AudioEulinear_le); 605 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 606 fp->precision = 16; 607 fp->flags = 0; 608 break; 609 case 6: 610 strcpy(fp->name, AudioEslinear_be); 611 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 612 fp->precision = 16; 613 fp->flags = 0; 614 break; 615 case 7: 616 strcpy(fp->name, AudioEulinear_be); 617 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 618 fp->precision = 16; 619 fp->flags = 0; 620 break; 621 default: 622 return EINVAL; 623 } 624 return 0; 625 } 626 627 static int 628 cs4280_set_params(void *addr, int setmode, int usemode, 629 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 630 stream_filter_list_t *rfil) 631 { 632 audio_params_t hw; 633 struct cs428x_softc *sc; 634 struct audio_params *p; 635 stream_filter_list_t *fil; 636 int mode; 637 638 sc = addr; 639 for (mode = AUMODE_RECORD; mode != -1; 640 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 641 if ((setmode & mode) == 0) 642 continue; 643 644 p = mode == AUMODE_PLAY ? play : rec; 645 646 if (p == play) { 647 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 648 p->sample_rate, p->precision, p->channels)); 649 /* play back data format may be 8- or 16-bit and 650 * either stereo or mono. 651 * playback rate may range from 8000Hz to 48000Hz 652 */ 653 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 654 (p->precision != 8 && p->precision != 16) || 655 (p->channels != 1 && p->channels != 2) ) { 656 return EINVAL; 657 } 658 } else { 659 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 660 p->sample_rate, p->precision, p->channels)); 661 /* capture data format must be 16bit stereo 662 * and sample rate range from 11025Hz to 48000Hz. 663 * 664 * XXX: it looks like to work with 8000Hz, 665 * although data sheets say lower limit is 666 * 11025 Hz. 667 */ 668 669 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 670 (p->precision != 8 && p->precision != 16) || 671 (p->channels != 1 && p->channels != 2) ) { 672 return EINVAL; 673 } 674 } 675 fil = mode == AUMODE_PLAY ? pfil : rfil; 676 hw = *p; 677 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 678 679 /* capturing data is slinear */ 680 switch (p->encoding) { 681 case AUDIO_ENCODING_SLINEAR_BE: 682 if (mode == AUMODE_RECORD && p->precision == 16) { 683 fil->append(fil, swap_bytes, &hw); 684 } 685 break; 686 case AUDIO_ENCODING_SLINEAR_LE: 687 break; 688 case AUDIO_ENCODING_ULINEAR_BE: 689 if (mode == AUMODE_RECORD) { 690 fil->append(fil, p->precision == 16 691 ? swap_bytes_change_sign16 692 : change_sign8, &hw); 693 } 694 break; 695 case AUDIO_ENCODING_ULINEAR_LE: 696 if (mode == AUMODE_RECORD) { 697 fil->append(fil, p->precision == 16 698 ? change_sign16 : change_sign8, 699 &hw); 700 } 701 break; 702 case AUDIO_ENCODING_ULAW: 703 if (mode == AUMODE_PLAY) { 704 hw.precision = 16; 705 hw.validbits = 16; 706 fil->append(fil, mulaw_to_linear16, &hw); 707 } else { 708 fil->append(fil, linear8_to_mulaw, &hw); 709 } 710 break; 711 case AUDIO_ENCODING_ALAW: 712 if (mode == AUMODE_PLAY) { 713 hw.precision = 16; 714 hw.validbits = 16; 715 fil->append(fil, alaw_to_linear16, &hw); 716 } else { 717 fil->append(fil, linear8_to_alaw, &hw); 718 } 719 break; 720 default: 721 return EINVAL; 722 } 723 } 724 725 /* set sample rate */ 726 cs4280_set_dac_rate(sc, play->sample_rate); 727 cs4280_set_adc_rate(sc, rec->sample_rate); 728 return 0; 729 } 730 731 static int 732 cs4280_halt_output(void *addr) 733 { 734 struct cs428x_softc *sc; 735 uint32_t mem; 736 737 sc = addr; 738 mem = BA1READ4(sc, CS4280_PCTL); 739 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 740 sc->sc_prun = 0; 741 cs4280_clkrun_hack(sc, -1); 742 743 return 0; 744 } 745 746 static int 747 cs4280_halt_input(void *addr) 748 { 749 struct cs428x_softc *sc; 750 uint32_t mem; 751 752 sc = addr; 753 mem = BA1READ4(sc, CS4280_CCTL); 754 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 755 sc->sc_rrun = 0; 756 cs4280_clkrun_hack(sc, -1); 757 758 return 0; 759 } 760 761 static int 762 cs4280_getdev(void *addr, struct audio_device *retp) 763 { 764 765 *retp = cs4280_device; 766 return 0; 767 } 768 769 static int 770 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 771 void (*intr)(void *), void *arg, 772 const audio_params_t *param) 773 { 774 struct cs428x_softc *sc; 775 uint32_t pfie, pctl, pdtc; 776 struct cs428x_dma *p; 777 778 sc = addr; 779 #ifdef DIAGNOSTIC 780 if (sc->sc_prun) 781 printf("cs4280_trigger_output: already running\n"); 782 #endif 783 sc->sc_prun = 1; 784 cs4280_clkrun_hack(sc, 1); 785 786 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 787 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 788 sc->sc_pintr = intr; 789 sc->sc_parg = arg; 790 791 /* stop playback DMA */ 792 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 793 794 /* setup PDTC */ 795 pdtc = BA1READ4(sc, CS4280_PDTC); 796 pdtc &= ~PDTC_MASK; 797 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 798 BA1WRITE4(sc, CS4280_PDTC, pdtc); 799 800 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 801 param->precision, param->channels, param->encoding)); 802 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 803 continue; 804 if (p == NULL) { 805 printf("cs4280_trigger_output: bad addr %p\n", start); 806 return EINVAL; 807 } 808 if (DMAADDR(p) % sc->dma_align != 0 ) { 809 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 810 "4kB align\n", (ulong)DMAADDR(p)); 811 return EINVAL; 812 } 813 814 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 815 sc->sc_ps = (char *)start; 816 sc->sc_pe = (char *)end; 817 sc->sc_pdma = p; 818 sc->sc_pbuf = KERNADDR(p); 819 sc->sc_pi = 0; 820 sc->sc_pn = sc->sc_ps; 821 if (blksize >= sc->dma_size) { 822 sc->sc_pn = sc->sc_ps + sc->dma_size; 823 memcpy(sc->sc_pbuf, start, sc->dma_size); 824 ++sc->sc_pi; 825 } else { 826 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 827 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 828 } 829 830 /* initiate playback DMA */ 831 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 832 833 /* set PFIE */ 834 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 835 836 if (param->precision == 8) 837 pfie |= PFIE_8BIT; 838 if (param->channels == 1) 839 pfie |= PFIE_MONO; 840 841 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 842 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 843 pfie |= PFIE_SWAPPED; 844 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 845 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 846 pfie |= PFIE_UNSIGNED; 847 848 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 849 850 sc->sc_prate = param->sample_rate; 851 cs4280_set_dac_rate(sc, param->sample_rate); 852 853 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 854 pctl |= sc->pctl; 855 BA1WRITE4(sc, CS4280_PCTL, pctl); 856 return 0; 857 } 858 859 static int 860 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 861 void (*intr)(void *), void *arg, 862 const audio_params_t *param) 863 { 864 struct cs428x_softc *sc; 865 uint32_t cctl, cie; 866 struct cs428x_dma *p; 867 868 sc = addr; 869 #ifdef DIAGNOSTIC 870 if (sc->sc_rrun) 871 printf("cs4280_trigger_input: already running\n"); 872 #endif 873 sc->sc_rrun = 1; 874 cs4280_clkrun_hack(sc, 1); 875 876 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 877 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 878 sc->sc_rintr = intr; 879 sc->sc_rarg = arg; 880 881 /* stop capture DMA */ 882 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 883 884 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 885 continue; 886 if (p == NULL) { 887 printf("cs4280_trigger_input: bad addr %p\n", start); 888 return EINVAL; 889 } 890 if (DMAADDR(p) % sc->dma_align != 0) { 891 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 892 "4kB align\n", (ulong)DMAADDR(p)); 893 return EINVAL; 894 } 895 896 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 897 sc->sc_rs = (char *)start; 898 sc->sc_re = (char *)end; 899 sc->sc_rdma = p; 900 sc->sc_rbuf = KERNADDR(p); 901 sc->sc_ri = 0; 902 sc->sc_rn = sc->sc_rs; 903 904 /* initiate capture DMA */ 905 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 906 907 /* setup format information for internal converter */ 908 sc->sc_rparam = 0; 909 if (param->precision == 8) { 910 sc->sc_rparam += CF_8BIT; 911 sc->sc_rcount <<= 1; 912 } 913 if (param->channels == 1) { 914 sc->sc_rparam += CF_MONO; 915 sc->sc_rcount <<= 1; 916 } 917 918 /* set CIE */ 919 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 920 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 921 922 sc->sc_rrate = param->sample_rate; 923 cs4280_set_adc_rate(sc, param->sample_rate); 924 925 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 926 cctl |= sc->cctl; 927 BA1WRITE4(sc, CS4280_CCTL, cctl); 928 return 0; 929 } 930 931 static bool 932 cs4280_suspend(device_t dv, const pmf_qual_t *qual) 933 { 934 struct cs428x_softc *sc = device_private(dv); 935 936 mutex_exit(&sc->sc_lock); 937 mutex_spin_enter(&sc->sc_intr_lock); 938 939 if (sc->sc_prun) { 940 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 941 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 942 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 943 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 944 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 945 sc->sc_suspend_state.cs4280.pctl, 946 sc->sc_suspend_state.cs4280.pfie, 947 sc->sc_suspend_state.cs4280.pba, 948 sc->sc_suspend_state.cs4280.pdtc)); 949 } 950 951 /* save current capture status */ 952 if (sc->sc_rrun) { 953 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 954 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 955 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 956 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 957 sc->sc_suspend_state.cs4280.cctl, 958 sc->sc_suspend_state.cs4280.cie, 959 sc->sc_suspend_state.cs4280.cba)); 960 } 961 962 /* Stop DMA */ 963 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 964 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 965 966 mutex_spin_exit(&sc->sc_intr_lock); 967 mutex_exit(&sc->sc_lock); 968 969 return true; 970 } 971 972 static bool 973 cs4280_resume(device_t dv, const pmf_qual_t *qual) 974 { 975 struct cs428x_softc *sc = device_private(dv); 976 977 mutex_exit(&sc->sc_lock); 978 mutex_spin_enter(&sc->sc_intr_lock); 979 cs4280_init(sc, 0); 980 #if 0 981 cs4280_reset_codec(sc); 982 #endif 983 984 /* restore DMA related status */ 985 if(sc->sc_prun) { 986 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 987 sc->sc_suspend_state.cs4280.pctl, 988 sc->sc_suspend_state.cs4280.pfie, 989 sc->sc_suspend_state.cs4280.pba, 990 sc->sc_suspend_state.cs4280.pdtc)); 991 cs4280_set_dac_rate(sc, sc->sc_prate); 992 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 993 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 994 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 995 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 996 } 997 998 if (sc->sc_rrun) { 999 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 1000 sc->sc_suspend_state.cs4280.cctl, 1001 sc->sc_suspend_state.cs4280.cie, 1002 sc->sc_suspend_state.cs4280.cba)); 1003 cs4280_set_adc_rate(sc, sc->sc_rrate); 1004 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 1005 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 1006 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 1007 } 1008 1009 mutex_spin_exit(&sc->sc_intr_lock); 1010 1011 /* restore ac97 registers */ 1012 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1013 1014 mutex_exit(&sc->sc_lock); 1015 1016 return true; 1017 } 1018 1019 static int 1020 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 1021 { 1022 struct cs428x_softc *sc = addr; 1023 int rv; 1024 1025 cs4280_clkrun_hack(sc, 1); 1026 rv = cs428x_read_codec(addr, reg, result); 1027 cs4280_clkrun_hack(sc, -1); 1028 1029 return rv; 1030 } 1031 1032 static int 1033 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1034 { 1035 struct cs428x_softc *sc = addr; 1036 int rv; 1037 1038 cs4280_clkrun_hack(sc, 1); 1039 rv = cs428x_write_codec(addr, reg, data); 1040 cs4280_clkrun_hack(sc, -1); 1041 1042 return rv; 1043 } 1044 1045 #if 0 /* XXX buggy and not required */ 1046 /* control AC97 codec */ 1047 static int 1048 cs4280_reset_codec(void *addr) 1049 { 1050 struct cs428x_softc *sc; 1051 int n; 1052 1053 sc = addr; 1054 1055 /* Reset codec */ 1056 BA0WRITE4(sc, CS428X_ACCTL, 0); 1057 delay(100); /* delay 100us */ 1058 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1059 1060 /* 1061 * It looks like we do the following procedure, too 1062 */ 1063 1064 /* Enable AC-link sync generation */ 1065 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1066 delay(50*1000); /* XXX delay 50ms */ 1067 1068 /* Assert valid frame signal */ 1069 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1070 1071 /* Wait for valid AC97 input slot */ 1072 n = 0; 1073 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1074 (ACISV_ISV3 | ACISV_ISV4)) { 1075 delay(1000); 1076 if (++n > 1000) { 1077 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1078 return ETIMEDOUT; 1079 } 1080 } 1081 1082 return 0; 1083 } 1084 #endif 1085 1086 static enum ac97_host_flags 1087 cs4280_flags_codec(void *addr) 1088 { 1089 struct cs428x_softc *sc; 1090 1091 sc = addr; 1092 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1093 return AC97_HOST_INVERTED_EAMP; 1094 1095 return 0; 1096 } 1097 1098 /* Internal functions */ 1099 1100 static const struct cs4280_card_t * 1101 cs4280_identify_card(const struct pci_attach_args *pa) 1102 { 1103 pcireg_t idreg; 1104 u_int16_t i; 1105 1106 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1107 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1108 if (idreg == cs4280_cards[i].id) 1109 return &cs4280_cards[i]; 1110 } 1111 1112 return NULL; 1113 } 1114 1115 static int 1116 cs4280_piix4_match(const struct pci_attach_args *pa) 1117 { 1118 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1119 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1120 return 1; 1121 } 1122 1123 return 0; 1124 } 1125 1126 static void 1127 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1128 { 1129 uint16_t control, val; 1130 1131 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1132 return; 1133 1134 sc->sc_active += change; 1135 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1136 if (!sc->sc_active) 1137 val |= 0x2000; 1138 else 1139 val &= ~0x2000; 1140 if (val != control) 1141 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1142 } 1143 1144 static void 1145 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1146 { 1147 struct pci_attach_args smbuspa; 1148 uint16_t reg; 1149 pcireg_t port; 1150 1151 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1152 return; 1153 1154 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1155 sc->sc_active = 0; 1156 aprint_normal_dev(sc->sc_dev, "enabling CLKRUN hack\n"); 1157 1158 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1159 port = reg & 0xffc0; 1160 aprint_normal_dev(sc->sc_dev, "power management port 0x%x\n", 1161 port); 1162 1163 sc->sc_pm_iot = smbuspa.pa_iot; 1164 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1165 &sc->sc_pm_ioh) == 0) 1166 return; 1167 } 1168 1169 /* handle error */ 1170 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1171 aprint_normal_dev(sc->sc_dev, "disabling CLKRUN hack\n"); 1172 } 1173 1174 static void 1175 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1176 { 1177 /* calculate capture rate: 1178 * 1179 * capture_coefficient_increment = -round(rate*128*65536/48000; 1180 * capture_phase_increment = floor(48000*65536*1024/rate); 1181 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1182 * cy = floor(cx/200); 1183 * capture_sample_rate_correction = cx - 200*cy; 1184 * capture_delay = ceil(24*48000/rate); 1185 * capture_num_triplets = floor(65536*rate/24000); 1186 * capture_group_length = 24000/GCD(rate, 24000); 1187 * where GCD means "Greatest Common Divisor". 1188 * 1189 * capture_coefficient_increment, capture_phase_increment and 1190 * capture_num_triplets are 32-bit signed quantities. 1191 * capture_sample_rate_correction and capture_group_length are 1192 * 16-bit signed quantities. 1193 * capture_delay is a 14-bit unsigned quantity. 1194 */ 1195 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1196 uint16_t csrc, cgl, cdlay; 1197 1198 /* XXX 1199 * Even though, embedded_audio_spec says capture rate range 11025 to 1200 * 48000, dhwiface.cpp says, 1201 * 1202 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1203 * Return an error if an attempt is made to stray outside that limit." 1204 * 1205 * so assume range as 48000/9 to 48000 1206 */ 1207 1208 if (rate < 8000) 1209 rate = 8000; 1210 if (rate > 48000) 1211 rate = 48000; 1212 1213 cx = rate << 16; 1214 cci = cx / 48000; 1215 cx -= cci * 48000; 1216 cx <<= 7; 1217 cci <<= 7; 1218 cci += cx / 48000; 1219 cci = - cci; 1220 1221 cx = 48000 << 16; 1222 cpi = cx / rate; 1223 cx -= cpi * rate; 1224 cx <<= 10; 1225 cpi <<= 10; 1226 cy = cx / rate; 1227 cpi += cy; 1228 cx -= cy * rate; 1229 1230 cy = cx / 200; 1231 csrc = cx - 200*cy; 1232 1233 cdlay = ((48000 * 24) + rate - 1) / rate; 1234 #if 0 1235 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1236 #endif 1237 1238 cnt = rate << 16; 1239 cnt /= 24000; 1240 1241 cgl = 1; 1242 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1243 if (((rate / tmp1) * tmp1) != rate) 1244 cgl *= 2; 1245 } 1246 if (((rate / 3) * 3) != rate) 1247 cgl *= 3; 1248 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1249 if (((rate / tmp1) * tmp1) != rate) 1250 cgl *= 5; 1251 } 1252 #if 0 1253 /* XXX what manual says */ 1254 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1255 tmp1 |= csrc<<16; 1256 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1257 #else 1258 /* suggested by cs461x.c (ALSA driver) */ 1259 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1260 #endif 1261 1262 #if 0 1263 /* I am confused. The sample rate calculation section says 1264 * cci *is* 32-bit signed quantity but in the parameter description 1265 * section, CCI only assigned 16bit. 1266 * I believe size of the variable. 1267 */ 1268 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1269 tmp1 |= cci<<16; 1270 BA1WRITE4(sc, CS4280_CCI, tmp1); 1271 #else 1272 BA1WRITE4(sc, CS4280_CCI, cci); 1273 #endif 1274 1275 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1276 tmp1 |= cdlay <<18; 1277 BA1WRITE4(sc, CS4280_CD, tmp1); 1278 1279 BA1WRITE4(sc, CS4280_CPI, cpi); 1280 1281 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1282 tmp1 |= cgl; 1283 BA1WRITE4(sc, CS4280_CGL, tmp1); 1284 1285 BA1WRITE4(sc, CS4280_CNT, cnt); 1286 1287 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1288 tmp1 |= cgl; 1289 BA1WRITE4(sc, CS4280_CGC, tmp1); 1290 } 1291 1292 static void 1293 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1294 { 1295 /* 1296 * playback rate may range from 8000Hz to 48000Hz 1297 * 1298 * play_phase_increment = floor(rate*65536*1024/48000) 1299 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1300 * py=floor(px/200) 1301 * play_sample_rate_correction = px - 200*py 1302 * 1303 * play_phase_increment is a 32bit signed quantity. 1304 * play_sample_rate_correction is a 16bit signed quantity. 1305 */ 1306 int32_t ppi; 1307 int16_t psrc; 1308 uint32_t px, py; 1309 1310 if (rate < 8000) 1311 rate = 8000; 1312 if (rate > 48000) 1313 rate = 48000; 1314 px = rate << 16; 1315 ppi = px/48000; 1316 px -= ppi*48000; 1317 ppi <<= 10; 1318 px <<= 10; 1319 py = px / 48000; 1320 ppi += py; 1321 px -= py*48000; 1322 py = px/200; 1323 px -= py*200; 1324 psrc = px; 1325 #if 0 1326 /* what manual says */ 1327 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1328 BA1WRITE4(sc, CS4280_PSRC, 1329 ( ((psrc<<16) & PSRC_MASK) | px )); 1330 #else 1331 /* suggested by cs461x.c (ALSA driver) */ 1332 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1333 #endif 1334 BA1WRITE4(sc, CS4280_PPI, ppi); 1335 } 1336 1337 /* Download Processor Code and Data image */ 1338 static int 1339 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1340 uint32_t offset, uint32_t len) 1341 { 1342 uint32_t ctr; 1343 #if CS4280_DEBUG > 10 1344 uint32_t con, data; 1345 uint8_t c0, c1, c2, c3; 1346 #endif 1347 if ((offset & 3) || (len & 3)) 1348 return -1; 1349 1350 len /= sizeof(uint32_t); 1351 for (ctr = 0; ctr < len; ctr++) { 1352 /* XXX: 1353 * I cannot confirm this is the right thing or not 1354 * on BIG-ENDIAN machines. 1355 */ 1356 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1357 #if CS4280_DEBUG > 10 1358 data = htole32(*(src+ctr)); 1359 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1360 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1361 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1362 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1363 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1364 if (data != con ) { 1365 printf("0x%06x: write=0x%08x read=0x%08x\n", 1366 offset+ctr*4, data, con); 1367 return -1; 1368 } 1369 #endif 1370 } 1371 return 0; 1372 } 1373 1374 static int 1375 cs4280_download_image(struct cs428x_softc *sc) 1376 { 1377 int idx, err; 1378 uint32_t offset = 0; 1379 1380 err = 0; 1381 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1382 err = cs4280_download(sc, &BA1Struct.map[offset], 1383 BA1Struct.memory[idx].offset, 1384 BA1Struct.memory[idx].size); 1385 if (err != 0) { 1386 aprint_error_dev(sc->sc_dev, 1387 "load_image failed at %d\n", idx); 1388 return -1; 1389 } 1390 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1391 } 1392 return err; 1393 } 1394 1395 /* Processor Soft Reset */ 1396 static void 1397 cs4280_reset(void *sc_) 1398 { 1399 struct cs428x_softc *sc; 1400 1401 sc = sc_; 1402 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1403 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1404 delay(100); 1405 /* Clear RSTSP bit in SPCR */ 1406 BA1WRITE4(sc, CS4280_SPCR, 0); 1407 /* enable DMA reqest */ 1408 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1409 } 1410 1411 static int 1412 cs4280_init(struct cs428x_softc *sc, int init) 1413 { 1414 int n; 1415 uint32_t mem; 1416 int rv; 1417 1418 rv = 1; 1419 cs4280_clkrun_hack(sc, 1); 1420 1421 /* Start PLL out in known state */ 1422 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1423 /* Start serial ports out in known state */ 1424 BA0WRITE4(sc, CS4280_SERMC1, 0); 1425 1426 /* Specify type of CODEC */ 1427 /* XXX should not be here */ 1428 #define SERACC_CODEC_TYPE_1_03 1429 #ifdef SERACC_CODEC_TYPE_1_03 1430 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1431 #else 1432 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1433 #endif 1434 1435 /* Reset codec */ 1436 BA0WRITE4(sc, CS428X_ACCTL, 0); 1437 delay(100); /* delay 100us */ 1438 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1439 1440 /* Enable AC-link sync generation */ 1441 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1442 delay(50*1000); /* delay 50ms */ 1443 1444 /* Set the serial port timing configuration */ 1445 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1446 1447 /* Setup clock control */ 1448 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1449 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1450 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1451 1452 /* Power up the PLL */ 1453 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1454 delay(50*1000); /* delay 50ms */ 1455 1456 /* Turn on clock */ 1457 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1458 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1459 1460 /* Set the serial port FIFO pointer to the 1461 * first sample in FIFO. (not documented) */ 1462 cs4280_clear_fifos(sc); 1463 1464 #if 0 1465 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1466 BA0WRITE4(sc, CS4280_SERBSP, 0); 1467 #endif 1468 1469 /* Configure the serial port */ 1470 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1471 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1472 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1473 1474 /* Wait for CODEC ready */ 1475 n = 0; 1476 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1477 delay(125); 1478 if (++n > 1000) { 1479 aprint_error_dev(sc->sc_dev, "codec ready timeout\n"); 1480 goto exit; 1481 } 1482 } 1483 1484 /* Assert valid frame signal */ 1485 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1486 1487 /* Wait for valid AC97 input slot */ 1488 n = 0; 1489 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1490 (ACISV_ISV3 | ACISV_ISV4)) { 1491 delay(1000); 1492 if (++n > 1000) { 1493 printf("AC97 inputs slot ready timeout\n"); 1494 goto exit; 1495 } 1496 } 1497 1498 /* Set AC97 output slot valid signals */ 1499 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1500 1501 /* reset the processor */ 1502 cs4280_reset(sc); 1503 1504 /* Download the image to the processor */ 1505 if (cs4280_download_image(sc) != 0) { 1506 aprint_error_dev(sc->sc_dev, "image download error\n"); 1507 goto exit; 1508 } 1509 1510 /* Save playback parameter and then write zero. 1511 * this ensures that DMA doesn't immediately occur upon 1512 * starting the processor core 1513 */ 1514 mem = BA1READ4(sc, CS4280_PCTL); 1515 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1516 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1517 if (init != 0) 1518 sc->sc_prun = 0; 1519 1520 /* Save capture parameter and then write zero. 1521 * this ensures that DMA doesn't immediately occur upon 1522 * starting the processor core 1523 */ 1524 mem = BA1READ4(sc, CS4280_CCTL); 1525 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1526 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1527 if (init != 0) 1528 sc->sc_rrun = 0; 1529 1530 /* Processor Startup Procedure */ 1531 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1532 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1533 1534 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1535 n = 0; 1536 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1537 delay(10); 1538 if (++n > 1000) { 1539 printf("SPCR 1->0 transition timeout\n"); 1540 goto exit; 1541 } 1542 } 1543 1544 n = 0; 1545 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1546 delay(10); 1547 if (++n > 1000) { 1548 printf("SPCS 0->1 transition timeout\n"); 1549 goto exit; 1550 } 1551 } 1552 /* Processor is now running !!! */ 1553 1554 /* Setup volume */ 1555 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1556 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1557 1558 /* Interrupt enable */ 1559 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1560 1561 /* playback interrupt enable */ 1562 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1563 mem |= PFIE_PI_ENABLE; 1564 BA1WRITE4(sc, CS4280_PFIE, mem); 1565 /* capture interrupt enable */ 1566 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1567 mem |= CIE_CI_ENABLE; 1568 BA1WRITE4(sc, CS4280_CIE, mem); 1569 1570 #if NMIDI > 0 1571 /* Reset midi port */ 1572 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1573 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1574 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1575 /* midi interrupt enable */ 1576 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1577 BA0WRITE4(sc, CS4280_MIDCR, mem); 1578 #endif 1579 1580 rv = 0; 1581 1582 exit: 1583 cs4280_clkrun_hack(sc, -1); 1584 return rv; 1585 } 1586 1587 static void 1588 cs4280_clear_fifos(struct cs428x_softc *sc) 1589 { 1590 int pd, cnt, n; 1591 uint32_t mem; 1592 1593 pd = 0; 1594 /* 1595 * If device power down, power up the device and keep power down 1596 * state. 1597 */ 1598 mem = BA0READ4(sc, CS4280_CLKCR1); 1599 if (!(mem & CLKCR1_SWCE)) { 1600 printf("cs4280_clear_fifo: power down found.\n"); 1601 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1602 pd = 1; 1603 } 1604 BA0WRITE4(sc, CS4280_SERBWP, 0); 1605 for (cnt = 0; cnt < 256; cnt++) { 1606 n = 0; 1607 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1608 delay(1000); 1609 if (++n > 1000) { 1610 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1611 break; 1612 } 1613 } 1614 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1615 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1616 } 1617 if (pd) 1618 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1619 } 1620 1621 #if NMIDI > 0 1622 static int 1623 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1624 void (*ointr)(void *), void *arg) 1625 { 1626 struct cs428x_softc *sc; 1627 uint32_t mem; 1628 1629 DPRINTF(("midi_open\n")); 1630 sc = addr; 1631 sc->sc_iintr = iintr; 1632 sc->sc_ointr = ointr; 1633 sc->sc_arg = arg; 1634 1635 /* midi interrupt enable */ 1636 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1637 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1638 BA0WRITE4(sc, CS4280_MIDCR, mem); 1639 #ifdef CS4280_DEBUG 1640 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1641 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1642 return(EINVAL); 1643 } 1644 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1645 #endif 1646 return 0; 1647 } 1648 1649 static void 1650 cs4280_midi_close(void *addr) 1651 { 1652 struct cs428x_softc *sc; 1653 uint32_t mem; 1654 1655 DPRINTF(("midi_close\n")); 1656 sc = addr; 1657 /* give uart a chance to drain */ 1658 kpause("cs0clm", false, hz/10, &sc->sc_intr_lock); 1659 mem = BA0READ4(sc, CS4280_MIDCR); 1660 mem &= ~MIDCR_MASK; 1661 BA0WRITE4(sc, CS4280_MIDCR, mem); 1662 1663 sc->sc_iintr = 0; 1664 sc->sc_ointr = 0; 1665 } 1666 1667 static int 1668 cs4280_midi_output(void *addr, int d) 1669 { 1670 struct cs428x_softc *sc; 1671 uint32_t mem; 1672 int x; 1673 1674 sc = addr; 1675 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1676 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1677 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1678 mem |= d & MIDWP_MASK; 1679 DPRINTFN(5,("midi_output d=0x%08x",d)); 1680 BA0WRITE4(sc, CS4280_MIDWP, mem); 1681 #ifdef DIAGNOSTIC 1682 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1683 DPRINTF(("Bad write data: %d %d", 1684 mem, BA0READ4(sc, CS4280_MIDWP))); 1685 return EIO; 1686 } 1687 #endif 1688 return 0; 1689 } 1690 delay(MIDI_BUSY_DELAY); 1691 } 1692 return EIO; 1693 } 1694 1695 static void 1696 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1697 { 1698 1699 mi->name = "CS4280 MIDI UART"; 1700 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1701 } 1702 1703 #endif /* NMIDI */ 1704 1705 /* DEBUG functions */ 1706 #if CS4280_DEBUG > 10 1707 static int 1708 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1709 uint32_t offset, uint32_t len) 1710 { 1711 uint32_t ctr, data; 1712 int err; 1713 1714 if ((offset & 3) || (len & 3)) 1715 return -1; 1716 1717 err = 0; 1718 len /= sizeof(uint32_t); 1719 for (ctr = 0; ctr < len; ctr++) { 1720 /* I cannot confirm this is the right thing 1721 * on BIG-ENDIAN machines 1722 */ 1723 data = BA1READ4(sc, offset+ctr*4); 1724 if (data != htole32(*(src+ctr))) { 1725 printf("0x%06x: 0x%08x(0x%08x)\n", 1726 offset+ctr*4, data, *(src+ctr)); 1727 *(src+ctr) = data; 1728 ++err; 1729 } 1730 } 1731 return err; 1732 } 1733 1734 static int 1735 cs4280_check_images(struct cs428x_softc *sc) 1736 { 1737 int idx, err; 1738 uint32_t offset; 1739 1740 offset = 0; 1741 err = 0; 1742 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1743 for (idx = 0; idx < 1; ++idx) { 1744 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1745 BA1Struct.memory[idx].offset, 1746 BA1Struct.memory[idx].size); 1747 if (err != 0) { 1748 aprint_error_dev(sc->sc_dev, 1749 "check_image failed at %d\n", idx); 1750 } 1751 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1752 } 1753 return err; 1754 } 1755 1756 #endif /* CS4280_DEBUG */ 1757
Indexes created Thu Oct 02 14:10:14 GMT 2025