cs4280.c revision 1.65.2.1
1 /* $NetBSD: cs4280.c,v 1.65.2.1 2014/05/18 17:45:39 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.65.2.1 2014/05/18 17:45:39 rmind Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 #include <sys/audioio.h> 68 #include <sys/bus.h> 69 #include <sys/bswap.h> 70 71 #include <dev/audio_if.h> 72 #include <dev/midi_if.h> 73 #include <dev/mulaw.h> 74 #include <dev/auconv.h> 75 76 #include <dev/ic/ac97reg.h> 77 #include <dev/ic/ac97var.h> 78 79 #include <dev/pci/pcidevs.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/cs4280reg.h> 82 #include <dev/pci/cs4280_image.h> 83 #include <dev/pci/cs428xreg.h> 84 #include <dev/pci/cs428x.h> 85 86 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 87 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 88 89 /* IF functions for audio driver */ 90 static int cs4280_match(device_t, cfdata_t, void *); 91 static void cs4280_attach(device_t, device_t, void *); 92 static int cs4280_intr(void *); 93 static int cs4280_query_encoding(void *, struct audio_encoding *); 94 static int cs4280_set_params(void *, int, int, audio_params_t *, 95 audio_params_t *, stream_filter_list_t *, 96 stream_filter_list_t *); 97 static int cs4280_halt_output(void *); 98 static int cs4280_halt_input(void *); 99 static int cs4280_getdev(void *, struct audio_device *); 100 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 101 void *, const audio_params_t *); 102 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 105 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 106 #if 0 107 static int cs4280_reset_codec(void *); 108 #endif 109 static enum ac97_host_flags cs4280_flags_codec(void *); 110 111 static bool cs4280_resume(device_t, const pmf_qual_t *); 112 static bool cs4280_suspend(device_t, const pmf_qual_t *); 113 114 /* Internal functions */ 115 static const struct cs4280_card_t * cs4280_identify_card(const struct pci_attach_args *); 116 static int cs4280_piix4_match(const struct pci_attach_args *); 117 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 118 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 119 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 120 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 121 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 122 uint32_t); 123 static int cs4280_download_image(struct cs428x_softc *); 124 static void cs4280_reset(void *); 125 static int cs4280_init(struct cs428x_softc *, int); 126 static void cs4280_clear_fifos(struct cs428x_softc *); 127 128 #if CS4280_DEBUG > 10 129 /* Thease two function is only for checking image loading is succeeded or not. */ 130 static int cs4280_check_images(struct cs428x_softc *); 131 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 132 uint32_t); 133 #endif 134 135 /* Special cards */ 136 struct cs4280_card_t 137 { 138 pcireg_t id; 139 enum cs428x_flags flags; 140 }; 141 142 #define _card(vend, prod, flags) \ 143 {PCI_ID_CODE(vend, prod), flags} 144 145 static const struct cs4280_card_t cs4280_cards[] = { 146 #if 0 /* untested, from ALSA driver */ 147 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 148 CS428X_FLAG_INVAC97EAMP), 149 #endif 150 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 151 CS428X_FLAG_INVAC97EAMP), 152 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 153 CS428X_FLAG_CLKRUNHACK) 154 }; 155 156 #undef _card 157 158 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 159 160 static const struct audio_hw_if cs4280_hw_if = { 161 NULL, /* open */ 162 NULL, /* close */ 163 NULL, 164 cs4280_query_encoding, 165 cs4280_set_params, 166 cs428x_round_blocksize, 167 NULL, 168 NULL, 169 NULL, 170 NULL, 171 NULL, 172 cs4280_halt_output, 173 cs4280_halt_input, 174 NULL, 175 cs4280_getdev, 176 NULL, 177 cs428x_mixer_set_port, 178 cs428x_mixer_get_port, 179 cs428x_query_devinfo, 180 cs428x_malloc, 181 cs428x_free, 182 cs428x_round_buffersize, 183 cs428x_mappage, 184 cs428x_get_props, 185 cs4280_trigger_output, 186 cs4280_trigger_input, 187 NULL, 188 cs428x_get_locks, 189 }; 190 191 #if NMIDI > 0 192 /* Midi Interface */ 193 static int cs4280_midi_open(void *, int, void (*)(void *, int), 194 void (*)(void *), void *); 195 static void cs4280_midi_close(void*); 196 static int cs4280_midi_output(void *, int); 197 static void cs4280_midi_getinfo(void *, struct midi_info *); 198 199 static const struct midi_hw_if cs4280_midi_hw_if = { 200 cs4280_midi_open, 201 cs4280_midi_close, 202 cs4280_midi_output, 203 cs4280_midi_getinfo, 204 0, 205 cs428x_get_locks, 206 }; 207 #endif 208 209 CFATTACH_DECL_NEW(clcs, sizeof(struct cs428x_softc), 210 cs4280_match, cs4280_attach, NULL, NULL); 211 212 static struct audio_device cs4280_device = { 213 "CS4280", 214 "", 215 "cs4280" 216 }; 217 218 219 static int 220 cs4280_match(device_t parent, cfdata_t match, void *aux) 221 { 222 struct pci_attach_args *pa; 223 224 pa = (struct pci_attach_args *)aux; 225 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 226 return 0; 227 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 228 #if 0 /* I can't confirm */ 229 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 230 #endif 231 ) 232 return 1; 233 return 0; 234 } 235 236 static void 237 cs4280_attach(device_t parent, device_t self, void *aux) 238 { 239 struct cs428x_softc *sc; 240 struct pci_attach_args *pa; 241 pci_chipset_tag_t pc; 242 const struct cs4280_card_t *cs_card; 243 char const *intrstr; 244 const char *vendor, *product; 245 pcireg_t reg; 246 uint32_t mem; 247 int error; 248 char intrbuf[PCI_INTRSTR_LEN]; 249 250 sc = device_private(self); 251 sc->sc_dev = self; 252 pa = (struct pci_attach_args *)aux; 253 pc = pa->pa_pc; 254 255 pci_aprint_devinfo(pa, "Audio controller"); 256 257 cs_card = cs4280_identify_card(pa); 258 if (cs_card != NULL) { 259 vendor = pci_findvendor(cs_card->id); 260 product = pci_findproduct(cs_card->id); 261 if (vendor == NULL) 262 aprint_normal_dev(sc->sc_dev, 263 "vendor 0x%04x product 0x%04x\n", 264 PCI_VENDOR(cs_card->id), 265 PCI_PRODUCT(cs_card->id)); 266 else if (product == NULL) 267 aprint_normal_dev(sc->sc_dev, "%s product 0x%04x\n", 268 vendor, PCI_PRODUCT(cs_card->id)); 269 else 270 aprint_normal_dev(sc->sc_dev, "%s %s\n", 271 vendor, product); 272 sc->sc_flags = cs_card->flags; 273 } else { 274 sc->sc_flags = CS428X_FLAG_NONE; 275 } 276 277 sc->sc_pc = pa->pa_pc; 278 sc->sc_pt = pa->pa_tag; 279 280 /* Map I/O register */ 281 if (pci_mapreg_map(pa, PCI_BA0, 282 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 283 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 284 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 285 return; 286 } 287 if (pci_mapreg_map(pa, PCI_BA1, 288 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 289 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 290 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 291 return; 292 } 293 294 sc->sc_dmatag = pa->pa_dmat; 295 296 /* power up chip */ 297 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 298 pci_activate_null)) && error != EOPNOTSUPP) { 299 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 300 return; 301 } 302 303 /* Enable the device (set bus master flag) */ 304 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 305 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 306 reg | PCI_COMMAND_MASTER_ENABLE); 307 308 /* LATENCY_TIMER setting */ 309 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 310 if ( PCI_LATTIMER(mem) < 32 ) { 311 mem &= 0xffff00ff; 312 mem |= 0x00002000; 313 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 314 } 315 316 /* CLKRUN hack initialization */ 317 cs4280_clkrun_hack_init(sc); 318 319 /* Map and establish the interrupt. */ 320 if (pci_intr_map(pa, &sc->intrh)) { 321 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 322 return; 323 } 324 intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf)); 325 326 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 327 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 328 329 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 330 cs4280_intr, sc); 331 if (sc->sc_ih == NULL) { 332 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 333 if (intrstr != NULL) 334 aprint_error(" at %s", intrstr); 335 aprint_error("\n"); 336 mutex_destroy(&sc->sc_lock); 337 mutex_destroy(&sc->sc_intr_lock); 338 return; 339 } 340 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 341 342 /* Initialization */ 343 if(cs4280_init(sc, 1) != 0) { 344 mutex_destroy(&sc->sc_lock); 345 mutex_destroy(&sc->sc_intr_lock); 346 return; 347 } 348 349 sc->type = TYPE_CS4280; 350 sc->halt_input = cs4280_halt_input; 351 sc->halt_output = cs4280_halt_output; 352 353 /* setup buffer related parameters */ 354 sc->dma_size = CS4280_DCHUNK; 355 sc->dma_align = CS4280_DALIGN; 356 sc->hw_blocksize = CS4280_ICHUNK; 357 358 /* AC 97 attachment */ 359 sc->host_if.arg = sc; 360 sc->host_if.attach = cs428x_attach_codec; 361 sc->host_if.read = cs4280_read_codec; 362 sc->host_if.write = cs4280_write_codec; 363 #if 0 364 sc->host_if.reset = cs4280_reset_codec; 365 #else 366 sc->host_if.reset = NULL; 367 #endif 368 sc->host_if.flags = cs4280_flags_codec; 369 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 370 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 371 return; 372 } 373 374 audio_attach_mi(&cs4280_hw_if, sc, sc->sc_dev); 375 376 #if NMIDI > 0 377 midi_attach_mi(&cs4280_midi_hw_if, sc, sc->sc_dev); 378 #endif 379 380 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 381 aprint_error_dev(self, "couldn't establish power handler\n"); 382 } 383 384 /* Interrupt handling function */ 385 static int 386 cs4280_intr(void *p) 387 { 388 /* 389 * XXX 390 * 391 * Since CS4280 has only 4kB DMA buffer and 392 * interrupt occurs every 2kB block, I create dummy buffer 393 * which returns to audio driver and actual DMA buffer 394 * using in DMA transfer. 395 * 396 * 397 * ring buffer in audio.c is pointed by BUFADDR 398 * <------ ring buffer size == 64kB ------> 399 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 400 * |= = = =|= = = =|= = = =|= = = =|= = = =| 401 * | | | | | | <- call audio_intp every 402 * sc->sc_[pr]_count time. 403 * 404 * actual DMA buffer is pointed by KERNADDR 405 * <-> DMA buffer size = 4kB 406 * |= =| 407 * 408 * 409 */ 410 struct cs428x_softc *sc; 411 uint32_t intr, mem; 412 char * empty_dma; 413 int handled; 414 415 sc = p; 416 handled = 0; 417 418 mutex_spin_enter(&sc->sc_intr_lock); 419 420 /* grab interrupt register then clear it */ 421 intr = BA0READ4(sc, CS4280_HISR); 422 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 423 424 /* not for us ? */ 425 if ((intr & HISR_INTENA) == 0) { 426 mutex_spin_exit(&sc->sc_intr_lock); 427 return 0; 428 } 429 430 /* Playback Interrupt */ 431 if (intr & HISR_PINT) { 432 handled = 1; 433 mem = BA1READ4(sc, CS4280_PFIE); 434 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 435 if (sc->sc_prun) { 436 if ((sc->sc_pi%sc->sc_pcount) == 0) 437 sc->sc_pintr(sc->sc_parg); 438 /* copy buffer */ 439 ++sc->sc_pi; 440 empty_dma = sc->sc_pdma->addr; 441 if (sc->sc_pi&1) 442 empty_dma += sc->hw_blocksize; 443 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 444 sc->sc_pn += sc->hw_blocksize; 445 if (sc->sc_pn >= sc->sc_pe) 446 sc->sc_pn = sc->sc_ps; 447 } else { 448 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 449 } 450 BA1WRITE4(sc, CS4280_PFIE, mem); 451 } 452 /* Capture Interrupt */ 453 if (intr & HISR_CINT) { 454 int i; 455 int16_t rdata; 456 457 handled = 1; 458 mem = BA1READ4(sc, CS4280_CIE); 459 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 460 461 if (sc->sc_rrun) { 462 ++sc->sc_ri; 463 empty_dma = sc->sc_rdma->addr; 464 if ((sc->sc_ri&1) == 0) 465 empty_dma += sc->hw_blocksize; 466 467 /* 468 * XXX 469 * I think this audio data conversion should be 470 * happend in upper layer, but I put this here 471 * since there is no conversion function available. 472 */ 473 switch(sc->sc_rparam) { 474 case CF_16BIT_STEREO: 475 /* just copy it */ 476 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 477 sc->sc_rn += sc->hw_blocksize; 478 break; 479 case CF_16BIT_MONO: 480 for (i = 0; i < 512; i++) { 481 rdata = *((int16_t *)empty_dma)>>1; 482 empty_dma += 2; 483 rdata += *((int16_t *)empty_dma)>>1; 484 empty_dma += 2; 485 *((int16_t *)sc->sc_rn) = rdata; 486 sc->sc_rn += 2; 487 } 488 break; 489 case CF_8BIT_STEREO: 490 for (i = 0; i < 512; i++) { 491 rdata = *((int16_t*)empty_dma); 492 empty_dma += 2; 493 *sc->sc_rn++ = rdata >> 8; 494 rdata = *((int16_t*)empty_dma); 495 empty_dma += 2; 496 *sc->sc_rn++ = rdata >> 8; 497 } 498 break; 499 case CF_8BIT_MONO: 500 for (i = 0; i < 512; i++) { 501 rdata = *((int16_t*)empty_dma) >>1; 502 empty_dma += 2; 503 rdata += *((int16_t*)empty_dma) >>1; 504 empty_dma += 2; 505 *sc->sc_rn++ = rdata >>8; 506 } 507 break; 508 default: 509 /* Should not reach here */ 510 aprint_error_dev(sc->sc_dev, 511 "unknown sc->sc_rparam: %d\n", 512 sc->sc_rparam); 513 } 514 if (sc->sc_rn >= sc->sc_re) 515 sc->sc_rn = sc->sc_rs; 516 } 517 BA1WRITE4(sc, CS4280_CIE, mem); 518 519 if (sc->sc_rrun) { 520 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 521 sc->sc_rintr(sc->sc_rarg); 522 } else { 523 aprint_error_dev(sc->sc_dev, 524 "unexpected record intr\n"); 525 } 526 } 527 528 #if NMIDI > 0 529 /* Midi port Interrupt */ 530 if (intr & HISR_MIDI) { 531 int data; 532 533 handled = 1; 534 DPRINTF(("i: %d: ", 535 BA0READ4(sc, CS4280_MIDSR))); 536 /* Read the received data */ 537 while ((sc->sc_iintr != NULL) && 538 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 539 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 540 DPRINTF(("r:%x\n",data)); 541 sc->sc_iintr(sc->sc_arg, data); 542 } 543 544 /* Write the data */ 545 #if 1 546 /* XXX: 547 * It seems "Transmit Buffer Full" never activate until EOI 548 * is deliverd. Shall I throw EOI top of this routine ? 549 */ 550 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 551 DPRINTF(("w: ")); 552 if (sc->sc_ointr != NULL) 553 sc->sc_ointr(sc->sc_arg); 554 } 555 #else 556 while ((sc->sc_ointr != NULL) && 557 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 558 DPRINTF(("w: ")); 559 sc->sc_ointr(sc->sc_arg); 560 } 561 #endif 562 DPRINTF(("\n")); 563 } 564 #endif 565 566 mutex_spin_exit(&sc->sc_intr_lock); 567 return handled; 568 } 569 570 static int 571 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 572 { 573 switch (fp->index) { 574 case 0: 575 strcpy(fp->name, AudioEulinear); 576 fp->encoding = AUDIO_ENCODING_ULINEAR; 577 fp->precision = 8; 578 fp->flags = 0; 579 break; 580 case 1: 581 strcpy(fp->name, AudioEmulaw); 582 fp->encoding = AUDIO_ENCODING_ULAW; 583 fp->precision = 8; 584 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 585 break; 586 case 2: 587 strcpy(fp->name, AudioEalaw); 588 fp->encoding = AUDIO_ENCODING_ALAW; 589 fp->precision = 8; 590 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 591 break; 592 case 3: 593 strcpy(fp->name, AudioEslinear); 594 fp->encoding = AUDIO_ENCODING_SLINEAR; 595 fp->precision = 8; 596 fp->flags = 0; 597 break; 598 case 4: 599 strcpy(fp->name, AudioEslinear_le); 600 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 601 fp->precision = 16; 602 fp->flags = 0; 603 break; 604 case 5: 605 strcpy(fp->name, AudioEulinear_le); 606 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 607 fp->precision = 16; 608 fp->flags = 0; 609 break; 610 case 6: 611 strcpy(fp->name, AudioEslinear_be); 612 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 613 fp->precision = 16; 614 fp->flags = 0; 615 break; 616 case 7: 617 strcpy(fp->name, AudioEulinear_be); 618 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 619 fp->precision = 16; 620 fp->flags = 0; 621 break; 622 default: 623 return EINVAL; 624 } 625 return 0; 626 } 627 628 static int 629 cs4280_set_params(void *addr, int setmode, int usemode, 630 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 631 stream_filter_list_t *rfil) 632 { 633 audio_params_t hw; 634 struct cs428x_softc *sc; 635 struct audio_params *p; 636 stream_filter_list_t *fil; 637 int mode; 638 639 sc = addr; 640 for (mode = AUMODE_RECORD; mode != -1; 641 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 642 if ((setmode & mode) == 0) 643 continue; 644 645 p = mode == AUMODE_PLAY ? play : rec; 646 647 if (p == play) { 648 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 649 p->sample_rate, p->precision, p->channels)); 650 /* play back data format may be 8- or 16-bit and 651 * either stereo or mono. 652 * playback rate may range from 8000Hz to 48000Hz 653 */ 654 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 655 (p->precision != 8 && p->precision != 16) || 656 (p->channels != 1 && p->channels != 2) ) { 657 return EINVAL; 658 } 659 } else { 660 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 661 p->sample_rate, p->precision, p->channels)); 662 /* capture data format must be 16bit stereo 663 * and sample rate range from 11025Hz to 48000Hz. 664 * 665 * XXX: it looks like to work with 8000Hz, 666 * although data sheets say lower limit is 667 * 11025 Hz. 668 */ 669 670 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 671 (p->precision != 8 && p->precision != 16) || 672 (p->channels != 1 && p->channels != 2) ) { 673 return EINVAL; 674 } 675 } 676 fil = mode == AUMODE_PLAY ? pfil : rfil; 677 hw = *p; 678 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 679 680 /* capturing data is slinear */ 681 switch (p->encoding) { 682 case AUDIO_ENCODING_SLINEAR_BE: 683 if (mode == AUMODE_RECORD && p->precision == 16) { 684 fil->append(fil, swap_bytes, &hw); 685 } 686 break; 687 case AUDIO_ENCODING_SLINEAR_LE: 688 break; 689 case AUDIO_ENCODING_ULINEAR_BE: 690 if (mode == AUMODE_RECORD) { 691 fil->append(fil, p->precision == 16 692 ? swap_bytes_change_sign16 693 : change_sign8, &hw); 694 } 695 break; 696 case AUDIO_ENCODING_ULINEAR_LE: 697 if (mode == AUMODE_RECORD) { 698 fil->append(fil, p->precision == 16 699 ? change_sign16 : change_sign8, 700 &hw); 701 } 702 break; 703 case AUDIO_ENCODING_ULAW: 704 if (mode == AUMODE_PLAY) { 705 hw.precision = 16; 706 hw.validbits = 16; 707 fil->append(fil, mulaw_to_linear16, &hw); 708 } else { 709 fil->append(fil, linear8_to_mulaw, &hw); 710 } 711 break; 712 case AUDIO_ENCODING_ALAW: 713 if (mode == AUMODE_PLAY) { 714 hw.precision = 16; 715 hw.validbits = 16; 716 fil->append(fil, alaw_to_linear16, &hw); 717 } else { 718 fil->append(fil, linear8_to_alaw, &hw); 719 } 720 break; 721 default: 722 return EINVAL; 723 } 724 } 725 726 /* set sample rate */ 727 cs4280_set_dac_rate(sc, play->sample_rate); 728 cs4280_set_adc_rate(sc, rec->sample_rate); 729 return 0; 730 } 731 732 static int 733 cs4280_halt_output(void *addr) 734 { 735 struct cs428x_softc *sc; 736 uint32_t mem; 737 738 sc = addr; 739 mem = BA1READ4(sc, CS4280_PCTL); 740 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 741 sc->sc_prun = 0; 742 cs4280_clkrun_hack(sc, -1); 743 744 return 0; 745 } 746 747 static int 748 cs4280_halt_input(void *addr) 749 { 750 struct cs428x_softc *sc; 751 uint32_t mem; 752 753 sc = addr; 754 mem = BA1READ4(sc, CS4280_CCTL); 755 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 756 sc->sc_rrun = 0; 757 cs4280_clkrun_hack(sc, -1); 758 759 return 0; 760 } 761 762 static int 763 cs4280_getdev(void *addr, struct audio_device *retp) 764 { 765 766 *retp = cs4280_device; 767 return 0; 768 } 769 770 static int 771 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 772 void (*intr)(void *), void *arg, 773 const audio_params_t *param) 774 { 775 struct cs428x_softc *sc; 776 uint32_t pfie, pctl, pdtc; 777 struct cs428x_dma *p; 778 779 sc = addr; 780 #ifdef DIAGNOSTIC 781 if (sc->sc_prun) 782 printf("cs4280_trigger_output: already running\n"); 783 #endif 784 sc->sc_prun = 1; 785 cs4280_clkrun_hack(sc, 1); 786 787 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 788 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 789 sc->sc_pintr = intr; 790 sc->sc_parg = arg; 791 792 /* stop playback DMA */ 793 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 794 795 /* setup PDTC */ 796 pdtc = BA1READ4(sc, CS4280_PDTC); 797 pdtc &= ~PDTC_MASK; 798 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 799 BA1WRITE4(sc, CS4280_PDTC, pdtc); 800 801 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 802 param->precision, param->channels, param->encoding)); 803 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 804 continue; 805 if (p == NULL) { 806 printf("cs4280_trigger_output: bad addr %p\n", start); 807 return EINVAL; 808 } 809 if (DMAADDR(p) % sc->dma_align != 0 ) { 810 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 811 "4kB align\n", (ulong)DMAADDR(p)); 812 return EINVAL; 813 } 814 815 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 816 sc->sc_ps = (char *)start; 817 sc->sc_pe = (char *)end; 818 sc->sc_pdma = p; 819 sc->sc_pbuf = KERNADDR(p); 820 sc->sc_pi = 0; 821 sc->sc_pn = sc->sc_ps; 822 if (blksize >= sc->dma_size) { 823 sc->sc_pn = sc->sc_ps + sc->dma_size; 824 memcpy(sc->sc_pbuf, start, sc->dma_size); 825 ++sc->sc_pi; 826 } else { 827 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 828 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 829 } 830 831 /* initiate playback DMA */ 832 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 833 834 /* set PFIE */ 835 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 836 837 if (param->precision == 8) 838 pfie |= PFIE_8BIT; 839 if (param->channels == 1) 840 pfie |= PFIE_MONO; 841 842 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 843 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 844 pfie |= PFIE_SWAPPED; 845 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 846 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 847 pfie |= PFIE_UNSIGNED; 848 849 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 850 851 sc->sc_prate = param->sample_rate; 852 cs4280_set_dac_rate(sc, param->sample_rate); 853 854 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 855 pctl |= sc->pctl; 856 BA1WRITE4(sc, CS4280_PCTL, pctl); 857 return 0; 858 } 859 860 static int 861 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 862 void (*intr)(void *), void *arg, 863 const audio_params_t *param) 864 { 865 struct cs428x_softc *sc; 866 uint32_t cctl, cie; 867 struct cs428x_dma *p; 868 869 sc = addr; 870 #ifdef DIAGNOSTIC 871 if (sc->sc_rrun) 872 printf("cs4280_trigger_input: already running\n"); 873 #endif 874 sc->sc_rrun = 1; 875 cs4280_clkrun_hack(sc, 1); 876 877 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 878 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 879 sc->sc_rintr = intr; 880 sc->sc_rarg = arg; 881 882 /* stop capture DMA */ 883 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 884 885 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 886 continue; 887 if (p == NULL) { 888 printf("cs4280_trigger_input: bad addr %p\n", start); 889 return EINVAL; 890 } 891 if (DMAADDR(p) % sc->dma_align != 0) { 892 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 893 "4kB align\n", (ulong)DMAADDR(p)); 894 return EINVAL; 895 } 896 897 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 898 sc->sc_rs = (char *)start; 899 sc->sc_re = (char *)end; 900 sc->sc_rdma = p; 901 sc->sc_rbuf = KERNADDR(p); 902 sc->sc_ri = 0; 903 sc->sc_rn = sc->sc_rs; 904 905 /* initiate capture DMA */ 906 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 907 908 /* setup format information for internal converter */ 909 sc->sc_rparam = 0; 910 if (param->precision == 8) { 911 sc->sc_rparam += CF_8BIT; 912 sc->sc_rcount <<= 1; 913 } 914 if (param->channels == 1) { 915 sc->sc_rparam += CF_MONO; 916 sc->sc_rcount <<= 1; 917 } 918 919 /* set CIE */ 920 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 921 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 922 923 sc->sc_rrate = param->sample_rate; 924 cs4280_set_adc_rate(sc, param->sample_rate); 925 926 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 927 cctl |= sc->cctl; 928 BA1WRITE4(sc, CS4280_CCTL, cctl); 929 return 0; 930 } 931 932 static bool 933 cs4280_suspend(device_t dv, const pmf_qual_t *qual) 934 { 935 struct cs428x_softc *sc = device_private(dv); 936 937 mutex_exit(&sc->sc_lock); 938 mutex_spin_enter(&sc->sc_intr_lock); 939 940 if (sc->sc_prun) { 941 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 942 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 943 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 944 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 945 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 946 sc->sc_suspend_state.cs4280.pctl, 947 sc->sc_suspend_state.cs4280.pfie, 948 sc->sc_suspend_state.cs4280.pba, 949 sc->sc_suspend_state.cs4280.pdtc)); 950 } 951 952 /* save current capture status */ 953 if (sc->sc_rrun) { 954 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 955 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 956 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 957 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 958 sc->sc_suspend_state.cs4280.cctl, 959 sc->sc_suspend_state.cs4280.cie, 960 sc->sc_suspend_state.cs4280.cba)); 961 } 962 963 /* Stop DMA */ 964 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 965 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 966 967 mutex_spin_exit(&sc->sc_intr_lock); 968 mutex_exit(&sc->sc_lock); 969 970 return true; 971 } 972 973 static bool 974 cs4280_resume(device_t dv, const pmf_qual_t *qual) 975 { 976 struct cs428x_softc *sc = device_private(dv); 977 978 mutex_exit(&sc->sc_lock); 979 mutex_spin_enter(&sc->sc_intr_lock); 980 cs4280_init(sc, 0); 981 #if 0 982 cs4280_reset_codec(sc); 983 #endif 984 985 /* restore DMA related status */ 986 if(sc->sc_prun) { 987 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 988 sc->sc_suspend_state.cs4280.pctl, 989 sc->sc_suspend_state.cs4280.pfie, 990 sc->sc_suspend_state.cs4280.pba, 991 sc->sc_suspend_state.cs4280.pdtc)); 992 cs4280_set_dac_rate(sc, sc->sc_prate); 993 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 994 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 995 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 996 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 997 } 998 999 if (sc->sc_rrun) { 1000 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 1001 sc->sc_suspend_state.cs4280.cctl, 1002 sc->sc_suspend_state.cs4280.cie, 1003 sc->sc_suspend_state.cs4280.cba)); 1004 cs4280_set_adc_rate(sc, sc->sc_rrate); 1005 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 1006 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 1007 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 1008 } 1009 1010 mutex_spin_exit(&sc->sc_intr_lock); 1011 1012 /* restore ac97 registers */ 1013 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1014 1015 mutex_exit(&sc->sc_lock); 1016 1017 return true; 1018 } 1019 1020 static int 1021 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 1022 { 1023 struct cs428x_softc *sc = addr; 1024 int rv; 1025 1026 cs4280_clkrun_hack(sc, 1); 1027 rv = cs428x_read_codec(addr, reg, result); 1028 cs4280_clkrun_hack(sc, -1); 1029 1030 return rv; 1031 } 1032 1033 static int 1034 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1035 { 1036 struct cs428x_softc *sc = addr; 1037 int rv; 1038 1039 cs4280_clkrun_hack(sc, 1); 1040 rv = cs428x_write_codec(addr, reg, data); 1041 cs4280_clkrun_hack(sc, -1); 1042 1043 return rv; 1044 } 1045 1046 #if 0 /* XXX buggy and not required */ 1047 /* control AC97 codec */ 1048 static int 1049 cs4280_reset_codec(void *addr) 1050 { 1051 struct cs428x_softc *sc; 1052 int n; 1053 1054 sc = addr; 1055 1056 /* Reset codec */ 1057 BA0WRITE4(sc, CS428X_ACCTL, 0); 1058 delay(100); /* delay 100us */ 1059 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1060 1061 /* 1062 * It looks like we do the following procedure, too 1063 */ 1064 1065 /* Enable AC-link sync generation */ 1066 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1067 delay(50*1000); /* XXX delay 50ms */ 1068 1069 /* Assert valid frame signal */ 1070 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1071 1072 /* Wait for valid AC97 input slot */ 1073 n = 0; 1074 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1075 (ACISV_ISV3 | ACISV_ISV4)) { 1076 delay(1000); 1077 if (++n > 1000) { 1078 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1079 return ETIMEDOUT; 1080 } 1081 } 1082 1083 return 0; 1084 } 1085 #endif 1086 1087 static enum ac97_host_flags 1088 cs4280_flags_codec(void *addr) 1089 { 1090 struct cs428x_softc *sc; 1091 1092 sc = addr; 1093 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1094 return AC97_HOST_INVERTED_EAMP; 1095 1096 return 0; 1097 } 1098 1099 /* Internal functions */ 1100 1101 static const struct cs4280_card_t * 1102 cs4280_identify_card(const struct pci_attach_args *pa) 1103 { 1104 pcireg_t idreg; 1105 u_int16_t i; 1106 1107 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1108 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1109 if (idreg == cs4280_cards[i].id) 1110 return &cs4280_cards[i]; 1111 } 1112 1113 return NULL; 1114 } 1115 1116 static int 1117 cs4280_piix4_match(const struct pci_attach_args *pa) 1118 { 1119 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1120 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1121 return 1; 1122 } 1123 1124 return 0; 1125 } 1126 1127 static void 1128 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1129 { 1130 uint16_t control, val; 1131 1132 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1133 return; 1134 1135 sc->sc_active += change; 1136 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1137 if (!sc->sc_active) 1138 val |= 0x2000; 1139 else 1140 val &= ~0x2000; 1141 if (val != control) 1142 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1143 } 1144 1145 static void 1146 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1147 { 1148 struct pci_attach_args smbuspa; 1149 uint16_t reg; 1150 pcireg_t port; 1151 1152 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1153 return; 1154 1155 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1156 sc->sc_active = 0; 1157 aprint_normal_dev(sc->sc_dev, "enabling CLKRUN hack\n"); 1158 1159 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1160 port = reg & 0xffc0; 1161 aprint_normal_dev(sc->sc_dev, "power management port 0x%x\n", 1162 port); 1163 1164 sc->sc_pm_iot = smbuspa.pa_iot; 1165 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1166 &sc->sc_pm_ioh) == 0) 1167 return; 1168 } 1169 1170 /* handle error */ 1171 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1172 aprint_normal_dev(sc->sc_dev, "disabling CLKRUN hack\n"); 1173 } 1174 1175 static void 1176 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1177 { 1178 /* calculate capture rate: 1179 * 1180 * capture_coefficient_increment = -round(rate*128*65536/48000; 1181 * capture_phase_increment = floor(48000*65536*1024/rate); 1182 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1183 * cy = floor(cx/200); 1184 * capture_sample_rate_correction = cx - 200*cy; 1185 * capture_delay = ceil(24*48000/rate); 1186 * capture_num_triplets = floor(65536*rate/24000); 1187 * capture_group_length = 24000/GCD(rate, 24000); 1188 * where GCD means "Greatest Common Divisor". 1189 * 1190 * capture_coefficient_increment, capture_phase_increment and 1191 * capture_num_triplets are 32-bit signed quantities. 1192 * capture_sample_rate_correction and capture_group_length are 1193 * 16-bit signed quantities. 1194 * capture_delay is a 14-bit unsigned quantity. 1195 */ 1196 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1197 uint16_t csrc, cgl, cdlay; 1198 1199 /* XXX 1200 * Even though, embedded_audio_spec says capture rate range 11025 to 1201 * 48000, dhwiface.cpp says, 1202 * 1203 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1204 * Return an error if an attempt is made to stray outside that limit." 1205 * 1206 * so assume range as 48000/9 to 48000 1207 */ 1208 1209 if (rate < 8000) 1210 rate = 8000; 1211 if (rate > 48000) 1212 rate = 48000; 1213 1214 cx = rate << 16; 1215 cci = cx / 48000; 1216 cx -= cci * 48000; 1217 cx <<= 7; 1218 cci <<= 7; 1219 cci += cx / 48000; 1220 cci = - cci; 1221 1222 cx = 48000 << 16; 1223 cpi = cx / rate; 1224 cx -= cpi * rate; 1225 cx <<= 10; 1226 cpi <<= 10; 1227 cy = cx / rate; 1228 cpi += cy; 1229 cx -= cy * rate; 1230 1231 cy = cx / 200; 1232 csrc = cx - 200*cy; 1233 1234 cdlay = ((48000 * 24) + rate - 1) / rate; 1235 #if 0 1236 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1237 #endif 1238 1239 cnt = rate << 16; 1240 cnt /= 24000; 1241 1242 cgl = 1; 1243 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1244 if (((rate / tmp1) * tmp1) != rate) 1245 cgl *= 2; 1246 } 1247 if (((rate / 3) * 3) != rate) 1248 cgl *= 3; 1249 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1250 if (((rate / tmp1) * tmp1) != rate) 1251 cgl *= 5; 1252 } 1253 #if 0 1254 /* XXX what manual says */ 1255 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1256 tmp1 |= csrc<<16; 1257 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1258 #else 1259 /* suggested by cs461x.c (ALSA driver) */ 1260 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1261 #endif 1262 1263 #if 0 1264 /* I am confused. The sample rate calculation section says 1265 * cci *is* 32-bit signed quantity but in the parameter description 1266 * section, CCI only assigned 16bit. 1267 * I believe size of the variable. 1268 */ 1269 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1270 tmp1 |= cci<<16; 1271 BA1WRITE4(sc, CS4280_CCI, tmp1); 1272 #else 1273 BA1WRITE4(sc, CS4280_CCI, cci); 1274 #endif 1275 1276 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1277 tmp1 |= cdlay <<18; 1278 BA1WRITE4(sc, CS4280_CD, tmp1); 1279 1280 BA1WRITE4(sc, CS4280_CPI, cpi); 1281 1282 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1283 tmp1 |= cgl; 1284 BA1WRITE4(sc, CS4280_CGL, tmp1); 1285 1286 BA1WRITE4(sc, CS4280_CNT, cnt); 1287 1288 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1289 tmp1 |= cgl; 1290 BA1WRITE4(sc, CS4280_CGC, tmp1); 1291 } 1292 1293 static void 1294 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1295 { 1296 /* 1297 * playback rate may range from 8000Hz to 48000Hz 1298 * 1299 * play_phase_increment = floor(rate*65536*1024/48000) 1300 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1301 * py=floor(px/200) 1302 * play_sample_rate_correction = px - 200*py 1303 * 1304 * play_phase_increment is a 32bit signed quantity. 1305 * play_sample_rate_correction is a 16bit signed quantity. 1306 */ 1307 int32_t ppi; 1308 int16_t psrc; 1309 uint32_t px, py; 1310 1311 if (rate < 8000) 1312 rate = 8000; 1313 if (rate > 48000) 1314 rate = 48000; 1315 px = rate << 16; 1316 ppi = px/48000; 1317 px -= ppi*48000; 1318 ppi <<= 10; 1319 px <<= 10; 1320 py = px / 48000; 1321 ppi += py; 1322 px -= py*48000; 1323 py = px/200; 1324 px -= py*200; 1325 psrc = px; 1326 #if 0 1327 /* what manual says */ 1328 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1329 BA1WRITE4(sc, CS4280_PSRC, 1330 ( ((psrc<<16) & PSRC_MASK) | px )); 1331 #else 1332 /* suggested by cs461x.c (ALSA driver) */ 1333 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1334 #endif 1335 BA1WRITE4(sc, CS4280_PPI, ppi); 1336 } 1337 1338 /* Download Processor Code and Data image */ 1339 static int 1340 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1341 uint32_t offset, uint32_t len) 1342 { 1343 uint32_t ctr; 1344 #if CS4280_DEBUG > 10 1345 uint32_t con, data; 1346 uint8_t c0, c1, c2, c3; 1347 #endif 1348 if ((offset & 3) || (len & 3)) 1349 return -1; 1350 1351 len /= sizeof(uint32_t); 1352 for (ctr = 0; ctr < len; ctr++) { 1353 /* XXX: 1354 * I cannot confirm this is the right thing or not 1355 * on BIG-ENDIAN machines. 1356 */ 1357 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1358 #if CS4280_DEBUG > 10 1359 data = htole32(*(src+ctr)); 1360 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1361 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1362 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1363 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1364 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1365 if (data != con ) { 1366 printf("0x%06x: write=0x%08x read=0x%08x\n", 1367 offset+ctr*4, data, con); 1368 return -1; 1369 } 1370 #endif 1371 } 1372 return 0; 1373 } 1374 1375 static int 1376 cs4280_download_image(struct cs428x_softc *sc) 1377 { 1378 int idx, err; 1379 uint32_t offset = 0; 1380 1381 err = 0; 1382 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1383 err = cs4280_download(sc, &BA1Struct.map[offset], 1384 BA1Struct.memory[idx].offset, 1385 BA1Struct.memory[idx].size); 1386 if (err != 0) { 1387 aprint_error_dev(sc->sc_dev, 1388 "load_image failed at %d\n", idx); 1389 return -1; 1390 } 1391 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1392 } 1393 return err; 1394 } 1395 1396 /* Processor Soft Reset */ 1397 static void 1398 cs4280_reset(void *sc_) 1399 { 1400 struct cs428x_softc *sc; 1401 1402 sc = sc_; 1403 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1404 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1405 delay(100); 1406 /* Clear RSTSP bit in SPCR */ 1407 BA1WRITE4(sc, CS4280_SPCR, 0); 1408 /* enable DMA reqest */ 1409 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1410 } 1411 1412 static int 1413 cs4280_init(struct cs428x_softc *sc, int init) 1414 { 1415 int n; 1416 uint32_t mem; 1417 int rv; 1418 1419 rv = 1; 1420 cs4280_clkrun_hack(sc, 1); 1421 1422 /* Start PLL out in known state */ 1423 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1424 /* Start serial ports out in known state */ 1425 BA0WRITE4(sc, CS4280_SERMC1, 0); 1426 1427 /* Specify type of CODEC */ 1428 /* XXX should not be here */ 1429 #define SERACC_CODEC_TYPE_1_03 1430 #ifdef SERACC_CODEC_TYPE_1_03 1431 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1432 #else 1433 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1434 #endif 1435 1436 /* Reset codec */ 1437 BA0WRITE4(sc, CS428X_ACCTL, 0); 1438 delay(100); /* delay 100us */ 1439 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1440 1441 /* Enable AC-link sync generation */ 1442 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1443 delay(50*1000); /* delay 50ms */ 1444 1445 /* Set the serial port timing configuration */ 1446 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1447 1448 /* Setup clock control */ 1449 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1450 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1451 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1452 1453 /* Power up the PLL */ 1454 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1455 delay(50*1000); /* delay 50ms */ 1456 1457 /* Turn on clock */ 1458 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1459 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1460 1461 /* Set the serial port FIFO pointer to the 1462 * first sample in FIFO. (not documented) */ 1463 cs4280_clear_fifos(sc); 1464 1465 #if 0 1466 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1467 BA0WRITE4(sc, CS4280_SERBSP, 0); 1468 #endif 1469 1470 /* Configure the serial port */ 1471 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1472 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1473 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1474 1475 /* Wait for CODEC ready */ 1476 n = 0; 1477 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1478 delay(125); 1479 if (++n > 1000) { 1480 aprint_error_dev(sc->sc_dev, "codec ready timeout\n"); 1481 goto exit; 1482 } 1483 } 1484 1485 /* Assert valid frame signal */ 1486 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1487 1488 /* Wait for valid AC97 input slot */ 1489 n = 0; 1490 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1491 (ACISV_ISV3 | ACISV_ISV4)) { 1492 delay(1000); 1493 if (++n > 1000) { 1494 printf("AC97 inputs slot ready timeout\n"); 1495 goto exit; 1496 } 1497 } 1498 1499 /* Set AC97 output slot valid signals */ 1500 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1501 1502 /* reset the processor */ 1503 cs4280_reset(sc); 1504 1505 /* Download the image to the processor */ 1506 if (cs4280_download_image(sc) != 0) { 1507 aprint_error_dev(sc->sc_dev, "image download error\n"); 1508 goto exit; 1509 } 1510 1511 /* Save playback parameter and then write zero. 1512 * this ensures that DMA doesn't immediately occur upon 1513 * starting the processor core 1514 */ 1515 mem = BA1READ4(sc, CS4280_PCTL); 1516 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1517 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1518 if (init != 0) 1519 sc->sc_prun = 0; 1520 1521 /* Save capture parameter and then write zero. 1522 * this ensures that DMA doesn't immediately occur upon 1523 * starting the processor core 1524 */ 1525 mem = BA1READ4(sc, CS4280_CCTL); 1526 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1527 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1528 if (init != 0) 1529 sc->sc_rrun = 0; 1530 1531 /* Processor Startup Procedure */ 1532 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1533 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1534 1535 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1536 n = 0; 1537 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1538 delay(10); 1539 if (++n > 1000) { 1540 printf("SPCR 1->0 transition timeout\n"); 1541 goto exit; 1542 } 1543 } 1544 1545 n = 0; 1546 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1547 delay(10); 1548 if (++n > 1000) { 1549 printf("SPCS 0->1 transition timeout\n"); 1550 goto exit; 1551 } 1552 } 1553 /* Processor is now running !!! */ 1554 1555 /* Setup volume */ 1556 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1557 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1558 1559 /* Interrupt enable */ 1560 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1561 1562 /* playback interrupt enable */ 1563 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1564 mem |= PFIE_PI_ENABLE; 1565 BA1WRITE4(sc, CS4280_PFIE, mem); 1566 /* capture interrupt enable */ 1567 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1568 mem |= CIE_CI_ENABLE; 1569 BA1WRITE4(sc, CS4280_CIE, mem); 1570 1571 #if NMIDI > 0 1572 /* Reset midi port */ 1573 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1574 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1575 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1576 /* midi interrupt enable */ 1577 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1578 BA0WRITE4(sc, CS4280_MIDCR, mem); 1579 #endif 1580 1581 rv = 0; 1582 1583 exit: 1584 cs4280_clkrun_hack(sc, -1); 1585 return rv; 1586 } 1587 1588 static void 1589 cs4280_clear_fifos(struct cs428x_softc *sc) 1590 { 1591 int pd, cnt, n; 1592 uint32_t mem; 1593 1594 pd = 0; 1595 /* 1596 * If device power down, power up the device and keep power down 1597 * state. 1598 */ 1599 mem = BA0READ4(sc, CS4280_CLKCR1); 1600 if (!(mem & CLKCR1_SWCE)) { 1601 printf("cs4280_clear_fifo: power down found.\n"); 1602 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1603 pd = 1; 1604 } 1605 BA0WRITE4(sc, CS4280_SERBWP, 0); 1606 for (cnt = 0; cnt < 256; cnt++) { 1607 n = 0; 1608 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1609 delay(1000); 1610 if (++n > 1000) { 1611 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1612 break; 1613 } 1614 } 1615 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1616 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1617 } 1618 if (pd) 1619 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1620 } 1621 1622 #if NMIDI > 0 1623 static int 1624 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1625 void (*ointr)(void *), void *arg) 1626 { 1627 struct cs428x_softc *sc; 1628 uint32_t mem; 1629 1630 DPRINTF(("midi_open\n")); 1631 sc = addr; 1632 sc->sc_iintr = iintr; 1633 sc->sc_ointr = ointr; 1634 sc->sc_arg = arg; 1635 1636 /* midi interrupt enable */ 1637 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1638 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1639 BA0WRITE4(sc, CS4280_MIDCR, mem); 1640 #ifdef CS4280_DEBUG 1641 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1642 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1643 return(EINVAL); 1644 } 1645 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1646 #endif 1647 return 0; 1648 } 1649 1650 static void 1651 cs4280_midi_close(void *addr) 1652 { 1653 struct cs428x_softc *sc; 1654 uint32_t mem; 1655 1656 DPRINTF(("midi_close\n")); 1657 sc = addr; 1658 /* give uart a chance to drain */ 1659 kpause("cs0clm", false, hz/10, &sc->sc_intr_lock); 1660 mem = BA0READ4(sc, CS4280_MIDCR); 1661 mem &= ~MIDCR_MASK; 1662 BA0WRITE4(sc, CS4280_MIDCR, mem); 1663 1664 sc->sc_iintr = 0; 1665 sc->sc_ointr = 0; 1666 } 1667 1668 static int 1669 cs4280_midi_output(void *addr, int d) 1670 { 1671 struct cs428x_softc *sc; 1672 uint32_t mem; 1673 int x; 1674 1675 sc = addr; 1676 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1677 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1678 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1679 mem |= d & MIDWP_MASK; 1680 DPRINTFN(5,("midi_output d=0x%08x",d)); 1681 BA0WRITE4(sc, CS4280_MIDWP, mem); 1682 #ifdef DIAGNOSTIC 1683 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1684 DPRINTF(("Bad write data: %d %d", 1685 mem, BA0READ4(sc, CS4280_MIDWP))); 1686 return EIO; 1687 } 1688 #endif 1689 return 0; 1690 } 1691 delay(MIDI_BUSY_DELAY); 1692 } 1693 return EIO; 1694 } 1695 1696 static void 1697 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1698 { 1699 1700 mi->name = "CS4280 MIDI UART"; 1701 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1702 } 1703 1704 #endif /* NMIDI */ 1705 1706 /* DEBUG functions */ 1707 #if CS4280_DEBUG > 10 1708 static int 1709 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1710 uint32_t offset, uint32_t len) 1711 { 1712 uint32_t ctr, data; 1713 int err; 1714 1715 if ((offset & 3) || (len & 3)) 1716 return -1; 1717 1718 err = 0; 1719 len /= sizeof(uint32_t); 1720 for (ctr = 0; ctr < len; ctr++) { 1721 /* I cannot confirm this is the right thing 1722 * on BIG-ENDIAN machines 1723 */ 1724 data = BA1READ4(sc, offset+ctr*4); 1725 if (data != htole32(*(src+ctr))) { 1726 printf("0x%06x: 0x%08x(0x%08x)\n", 1727 offset+ctr*4, data, *(src+ctr)); 1728 *(src+ctr) = data; 1729 ++err; 1730 } 1731 } 1732 return err; 1733 } 1734 1735 static int 1736 cs4280_check_images(struct cs428x_softc *sc) 1737 { 1738 int idx, err; 1739 uint32_t offset; 1740 1741 offset = 0; 1742 err = 0; 1743 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1744 for (idx = 0; idx < 1; ++idx) { 1745 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1746 BA1Struct.memory[idx].offset, 1747 BA1Struct.memory[idx].size); 1748 if (err != 0) { 1749 aprint_error_dev(sc->sc_dev, 1750 "check_image failed at %d\n", idx); 1751 } 1752 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1753 } 1754 return err; 1755 } 1756 1757 #endif /* CS4280_DEBUG */ 1758
Indexes created Thu Oct 02 14:10:14 GMT 2025