cs4280.c revision 1.7.2.3
1 /* $NetBSD: cs4280.c,v 1.7.2.3 2000/12/08 09:12:31 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * 44 */ 45 46 /* 47 * TODO 48 * Joystick support 49 */ 50 51 #if defined(CS4280_DEBUG) 52 #define DPRINTF(x) if (cs4280debug) printf x 53 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 54 int cs4280debug = 0; 55 #else 56 #define DPRINTF(x) 57 #define DPRINTFN(n,x) 58 #endif 59 60 #include "midi.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/fcntl.h> 66 #include <sys/malloc.h> 67 #include <sys/device.h> 68 #include <sys/types.h> 69 #include <sys/systm.h> 70 71 #include <dev/pci/pcidevs.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/cs4280reg.h> 74 #include <dev/pci/cs4280_image.h> 75 76 #include <sys/audioio.h> 77 #include <dev/audio_if.h> 78 #include <dev/midi_if.h> 79 #include <dev/mulaw.h> 80 #include <dev/auconv.h> 81 82 #include <dev/ic/ac97reg.h> 83 #include <dev/ic/ac97var.h> 84 85 #include <machine/bus.h> 86 #include <machine/bswap.h> 87 88 #define CSCC_PCI_BA0 0x10 89 #define CSCC_PCI_BA1 0x14 90 91 struct cs4280_dma { 92 bus_dmamap_t map; 93 caddr_t addr; /* real dma buffer */ 94 caddr_t dum; /* dummy buffer for audio driver */ 95 bus_dma_segment_t segs[1]; 96 int nsegs; 97 size_t size; 98 struct cs4280_dma *next; 99 }; 100 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 101 #define BUFADDR(p) ((void *)((p)->dum)) 102 #define KERNADDR(p) ((void *)((p)->addr)) 103 104 /* 105 * Software state 106 */ 107 struct cs4280_softc { 108 struct device sc_dev; 109 110 pci_intr_handle_t * sc_ih; 111 112 /* I/O (BA0) */ 113 bus_space_tag_t ba0t; 114 bus_space_handle_t ba0h; 115 116 /* BA1 */ 117 bus_space_tag_t ba1t; 118 bus_space_handle_t ba1h; 119 120 /* DMA */ 121 bus_dma_tag_t sc_dmatag; 122 struct cs4280_dma *sc_dmas; 123 124 void (*sc_pintr)(void *); /* dma completion intr handler */ 125 void *sc_parg; /* arg for sc_intr() */ 126 char *sc_ps, *sc_pe, *sc_pn; 127 int sc_pcount; 128 int sc_pi; 129 struct cs4280_dma *sc_pdma; 130 char *sc_pbuf; 131 #ifdef DIAGNOSTIC 132 char sc_prun; 133 #endif 134 135 void (*sc_rintr)(void *); /* dma completion intr handler */ 136 void *sc_rarg; /* arg for sc_intr() */ 137 char *sc_rs, *sc_re, *sc_rn; 138 int sc_rcount; 139 int sc_ri; 140 struct cs4280_dma *sc_rdma; 141 char *sc_rbuf; 142 int sc_rparam; /* record format */ 143 #ifdef DIAGNOSTIC 144 char sc_rrun; 145 #endif 146 147 #if NMIDI > 0 148 void (*sc_iintr)(void *, int); /* midi input ready handler */ 149 void (*sc_ointr)(void *); /* midi output ready handler */ 150 void *sc_arg; 151 #endif 152 153 u_int32_t pctl; 154 u_int32_t cctl; 155 156 struct ac97_codec_if *codec_if; 157 struct ac97_host_if host_if; 158 159 char sc_suspend; 160 void *sc_powerhook; /* Power Hook */ 161 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 162 }; 163 164 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 165 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 166 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 167 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 168 169 int cs4280_match __P((struct device *, struct cfdata *, void *)); 170 void cs4280_attach __P((struct device *, struct device *, void *)); 171 int cs4280_intr __P((void *)); 172 void cs4280_reset __P((void *)); 173 int cs4280_download_image __P((struct cs4280_softc *)); 174 175 int cs4280_download(struct cs4280_softc *, u_int32_t *, u_int32_t, u_int32_t); 176 int cs4280_allocmem __P((struct cs4280_softc *, size_t, size_t, 177 struct cs4280_dma *)); 178 int cs4280_freemem __P((struct cs4280_softc *, struct cs4280_dma *)); 179 180 #ifdef CS4280_DEBUG 181 int cs4280_check_images __P((struct cs4280_softc *)); 182 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 183 u_int32_t); 184 #endif 185 186 struct cfattach clcs_ca = { 187 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 188 }; 189 190 int cs4280_init __P((struct cs4280_softc *, int)); 191 int cs4280_open __P((void *, int)); 192 void cs4280_close __P((void *)); 193 194 int cs4280_query_encoding __P((void *, struct audio_encoding *)); 195 int cs4280_set_params __P((void *, int, int, struct audio_params *, struct audio_params *)); 196 int cs4280_round_blocksize __P((void *, int)); 197 198 int cs4280_halt_output __P((void *)); 199 int cs4280_halt_input __P((void *)); 200 201 int cs4280_getdev __P((void *, struct audio_device *)); 202 203 int cs4280_mixer_set_port __P((void *, mixer_ctrl_t *)); 204 int cs4280_mixer_get_port __P((void *, mixer_ctrl_t *)); 205 int cs4280_query_devinfo __P((void *addr, mixer_devinfo_t *dip)); 206 void *cs4280_malloc __P((void *, int, size_t, int, int)); 207 void cs4280_free __P((void *, void *, int)); 208 size_t cs4280_round_buffersize __P((void *, int, size_t)); 209 paddr_t cs4280_mappage __P((void *, void *, off_t, int)); 210 int cs4280_get_props __P((void *)); 211 int cs4280_trigger_output __P((void *, void *, void *, int, void (*)(void *), 212 void *, struct audio_params *)); 213 int cs4280_trigger_input __P((void *, void *, void *, int, void (*)(void *), 214 void *, struct audio_params *)); 215 216 217 void cs4280_set_dac_rate __P((struct cs4280_softc *, int )); 218 void cs4280_set_adc_rate __P((struct cs4280_softc *, int )); 219 int cs4280_get_portnum_by_name __P((struct cs4280_softc *, char *, char *, 220 char *)); 221 int cs4280_src_wait __P((struct cs4280_softc *)); 222 int cs4280_attach_codec __P((void *sc, struct ac97_codec_if *)); 223 int cs4280_read_codec __P((void *sc, u_int8_t a, u_int16_t *d)); 224 int cs4280_write_codec __P((void *sc, u_int8_t a, u_int16_t d)); 225 void cs4280_reset_codec __P((void *sc)); 226 227 void cs4280_power __P((int, void *)); 228 229 void cs4280_clear_fifos __P((struct cs4280_softc *)); 230 231 #if NMIDI > 0 232 void cs4280_midi_close __P((void*)); 233 void cs4280_midi_getinfo __P((void *, struct midi_info *)); 234 int cs4280_midi_open __P((void *, int, void (*)(void *, int), 235 void (*)(void *), void *)); 236 int cs4280_midi_output __P((void *, int)); 237 #endif 238 239 struct audio_hw_if cs4280_hw_if = { 240 cs4280_open, 241 cs4280_close, 242 NULL, 243 cs4280_query_encoding, 244 cs4280_set_params, 245 cs4280_round_blocksize, 246 NULL, 247 NULL, 248 NULL, 249 NULL, 250 NULL, 251 cs4280_halt_output, 252 cs4280_halt_input, 253 NULL, 254 cs4280_getdev, 255 NULL, 256 cs4280_mixer_set_port, 257 cs4280_mixer_get_port, 258 cs4280_query_devinfo, 259 cs4280_malloc, 260 cs4280_free, 261 cs4280_round_buffersize, 262 cs4280_mappage, 263 cs4280_get_props, 264 cs4280_trigger_output, 265 cs4280_trigger_input, 266 }; 267 268 #if NMIDI > 0 269 struct midi_hw_if cs4280_midi_hw_if = { 270 cs4280_midi_open, 271 cs4280_midi_close, 272 cs4280_midi_output, 273 cs4280_midi_getinfo, 274 0, 275 }; 276 #endif 277 278 279 280 struct audio_device cs4280_device = { 281 "CS4280", 282 "", 283 "cs4280" 284 }; 285 286 287 int 288 cs4280_match(parent, match, aux) 289 struct device *parent; 290 struct cfdata *match; 291 void *aux; 292 { 293 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 294 295 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 296 return (0); 297 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 298 #if 0 /* I can't confirm */ 299 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 300 #endif 301 ) 302 return (1); 303 return (0); 304 } 305 306 int 307 cs4280_read_codec(sc_, add, data) 308 void *sc_; 309 u_int8_t add; 310 u_int16_t *data; 311 { 312 struct cs4280_softc *sc = sc_; 313 int n; 314 315 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 316 /* 317 * Make sure that there is not data sitting around from a preivous 318 * uncompleted access. 319 */ 320 BA0READ4(sc, CS4280_ACSDA); 321 322 /* Set up AC97 control registers. */ 323 BA0WRITE4(sc, CS4280_ACCAD, add); 324 BA0WRITE4(sc, CS4280_ACCDA, 0); 325 BA0WRITE4(sc, CS4280_ACCTL, 326 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 327 328 if (cs4280_src_wait(sc) < 0) { 329 printf("%s: AC97 read prob. (DCV!=0) for add=0x%0x\n", 330 sc->sc_dev.dv_xname, add); 331 return (1); 332 } 333 334 /* wait for valid status bit is active */ 335 n = 0; 336 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 337 delay(1); 338 while (++n > 1000) { 339 printf("%s: AC97 read fail (VSTS==0) for add=0x%0x\n", 340 sc->sc_dev.dv_xname, add); 341 return (1); 342 } 343 } 344 *data = BA0READ4(sc, CS4280_ACSDA); 345 DPRINTFN(5,("data=0x%04x\n", *data)); 346 return (0); 347 } 348 349 int 350 cs4280_write_codec(sc_, add, data) 351 void *sc_; 352 u_int8_t add; 353 u_int16_t data; 354 { 355 struct cs4280_softc *sc = sc_; 356 357 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 358 BA0WRITE4(sc, CS4280_ACCAD, add); 359 BA0WRITE4(sc, CS4280_ACCDA, data); 360 BA0WRITE4(sc, CS4280_ACCTL, 361 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 362 363 if (cs4280_src_wait(sc) < 0) { 364 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 365 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 366 return (1); 367 } 368 return (0); 369 } 370 371 int 372 cs4280_src_wait(sc) 373 struct cs4280_softc *sc; 374 { 375 int n; 376 n = 0; 377 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 378 delay(1000); 379 while (++n > 1000) 380 return (-1); 381 } 382 return (0); 383 } 384 385 386 void 387 cs4280_set_adc_rate(sc, rate) 388 struct cs4280_softc *sc; 389 int rate; 390 { 391 /* calculate capture rate: 392 * 393 * capture_coefficient_increment = -round(rate*128*65536/48000; 394 * capture_phase_increment = floor(48000*65536*1024/rate); 395 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 396 * cy = floor(cx/200); 397 * capture_sample_rate_correction = cx - 200*cy; 398 * capture_delay = ceil(24*48000/rate); 399 * capture_num_triplets = floor(65536*rate/24000); 400 * capture_group_length = 24000/GCD(rate, 24000); 401 * where GCD means "Greatest Common Divisor". 402 * 403 * capture_coefficient_increment, capture_phase_increment and 404 * capture_num_triplets are 32-bit signed quantities. 405 * capture_sample_rate_correction and capture_group_length are 406 * 16-bit signed quantities. 407 * capture_delay is a 14-bit unsigned quantity. 408 */ 409 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 410 u_int16_t csrc, cgl, cdlay; 411 412 /* XXX 413 * Even though, embedded_audio_spec says capture rate range 11025 to 414 * 48000, dhwiface.cpp says, 415 * 416 * "We can only decimate by up to a factor of 1/9th the hardware rate. 417 * Return an error if an attempt is made to stray outside that limit." 418 * 419 * so assume range as 48000/9 to 48000 420 */ 421 422 if (rate < 8000) 423 rate = 8000; 424 if (rate > 48000) 425 rate = 48000; 426 427 cx = rate << 16; 428 cci = cx / 48000; 429 cx -= cci * 48000; 430 cx <<= 7; 431 cci <<= 7; 432 cci += cx / 48000; 433 cci = - cci; 434 435 cx = 48000 << 16; 436 cpi = cx / rate; 437 cx -= cpi * rate; 438 cx <<= 10; 439 cpi <<= 10; 440 cy = cx / rate; 441 cpi += cy; 442 cx -= cy * rate; 443 444 cy = cx / 200; 445 csrc = cx - 200*cy; 446 447 cdlay = ((48000 * 24) + rate - 1) / rate; 448 #if 0 449 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 450 #endif 451 452 cnt = rate << 16; 453 cnt /= 24000; 454 455 cgl = 1; 456 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 457 if (((rate / tmp1) * tmp1) != rate) 458 cgl *= 2; 459 } 460 if (((rate / 3) * 3) != rate) 461 cgl *= 3; 462 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 463 if (((rate / tmp1) * tmp1) != rate) 464 cgl *= 5; 465 } 466 #if 0 467 /* XXX what manual says */ 468 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 469 tmp1 |= csrc<<16; 470 BA1WRITE4(sc, CS4280_CSRC, tmp1); 471 #else 472 /* suggested by cs461x.c (ALSA driver) */ 473 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 474 #endif 475 476 #if 0 477 /* I am confused. The sample rate calculation section says 478 * cci *is* 32-bit signed quantity but in the parameter description 479 * section, CCI only assigned 16bit. 480 * I believe size of the variable. 481 */ 482 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 483 tmp1 |= cci<<16; 484 BA1WRITE4(sc, CS4280_CCI, tmp1); 485 #else 486 BA1WRITE4(sc, CS4280_CCI, cci); 487 #endif 488 489 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 490 tmp1 |= cdlay <<18; 491 BA1WRITE4(sc, CS4280_CD, tmp1); 492 493 BA1WRITE4(sc, CS4280_CPI, cpi); 494 495 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 496 tmp1 |= cgl; 497 BA1WRITE4(sc, CS4280_CGL, tmp1); 498 499 BA1WRITE4(sc, CS4280_CNT, cnt); 500 501 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 502 tmp1 |= cgl; 503 BA1WRITE4(sc, CS4280_CGC, tmp1); 504 } 505 506 void 507 cs4280_set_dac_rate(sc, rate) 508 struct cs4280_softc *sc; 509 int rate; 510 { 511 /* 512 * playback rate may range from 8000Hz to 48000Hz 513 * 514 * play_phase_increment = floor(rate*65536*1024/48000) 515 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 516 * py=floor(px/200) 517 * play_sample_rate_correction = px - 200*py 518 * 519 * play_phase_increment is a 32bit signed quantity. 520 * play_sample_rate_correction is a 16bit signed quantity. 521 */ 522 int32_t ppi; 523 int16_t psrc; 524 u_int32_t px, py; 525 526 if (rate < 8000) 527 rate = 8000; 528 if (rate > 48000) 529 rate = 48000; 530 px = rate << 16; 531 ppi = px/48000; 532 px -= ppi*48000; 533 ppi <<= 10; 534 px <<= 10; 535 py = px / 48000; 536 ppi += py; 537 px -= py*48000; 538 py = px/200; 539 px -= py*200; 540 psrc = px; 541 #if 0 542 /* what manual says */ 543 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 544 BA1WRITE4(sc, CS4280_PSRC, 545 ( ((psrc<<16) & PSRC_MASK) | px )); 546 #else 547 /* suggested by cs461x.c (ALSA driver) */ 548 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 549 #endif 550 BA1WRITE4(sc, CS4280_PPI, ppi); 551 } 552 553 void 554 cs4280_attach(parent, self, aux) 555 struct device *parent; 556 struct device *self; 557 void *aux; 558 { 559 struct cs4280_softc *sc = (struct cs4280_softc *)self; 560 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 561 pci_chipset_tag_t pc = pa->pa_pc; 562 char const *intrstr; 563 pci_intr_handle_t ih; 564 pcireg_t csr; 565 char devinfo[256]; 566 mixer_ctrl_t ctl; 567 u_int32_t mem; 568 569 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 570 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 571 572 /* Map I/O register */ 573 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 574 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 575 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 576 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 577 return; 578 } 579 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 580 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 581 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 582 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 583 return; 584 } 585 586 sc->sc_dmatag = pa->pa_dmat; 587 588 /* Enable the device (set bus master flag) */ 589 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 590 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 591 csr | PCI_COMMAND_MASTER_ENABLE); 592 593 /* LATENCY_TIMER setting */ 594 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 595 if ( PCI_LATTIMER(mem) < 32 ) { 596 mem &= 0xffff00ff; 597 mem |= 0x00002000; 598 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 599 } 600 601 /* Map and establish the interrupt. */ 602 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 603 pa->pa_intrline, &ih)) { 604 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 605 return; 606 } 607 intrstr = pci_intr_string(pc, ih); 608 609 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 610 if (sc->sc_ih == NULL) { 611 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 612 if (intrstr != NULL) 613 printf(" at %s", intrstr); 614 printf("\n"); 615 return; 616 } 617 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 618 619 /* Initialization */ 620 if(cs4280_init(sc, 1) != 0) 621 return; 622 623 /* AC 97 attachement */ 624 sc->host_if.arg = sc; 625 sc->host_if.attach = cs4280_attach_codec; 626 sc->host_if.read = cs4280_read_codec; 627 sc->host_if.write = cs4280_write_codec; 628 sc->host_if.reset = cs4280_reset_codec; 629 630 if (ac97_attach(&sc->host_if) != 0) { 631 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 632 return; 633 } 634 635 /* Turn mute off of DAC, CD and master volumes by default */ 636 ctl.type = AUDIO_MIXER_ENUM; 637 ctl.un.ord = 0; /* off */ 638 639 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 640 AudioNmaster, AudioNmute); 641 cs4280_mixer_set_port(sc, &ctl); 642 643 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 644 AudioNdac, AudioNmute); 645 cs4280_mixer_set_port(sc, &ctl); 646 647 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 648 AudioNcd, AudioNmute); 649 cs4280_mixer_set_port(sc, &ctl); 650 651 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 652 653 #if NMIDI > 0 654 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 655 #endif 656 sc->sc_suspend = PWR_RESUME; 657 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 658 } 659 660 int 661 cs4280_intr(p) 662 void *p; 663 { 664 /* 665 * XXX 666 * 667 * Since CS4280 has only 4kB dma buffer and 668 * interrupt occurs every 2kB block, I create dummy buffer 669 * which returns to audio driver and actual dma buffer 670 * using in DMA transfer. 671 * 672 * 673 * ring buffer in audio.c is pointed by BUFADDR 674 * <------ ring buffer size == 64kB ------> 675 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 676 * |= = = =|= = = =|= = = =|= = = =|= = = =| 677 * | | | | | | <- call audio_intp every 678 * sc->sc_[pr]_count time. 679 * 680 * actual dma buffer is pointed by KERNADDR 681 * <-> dma buffer size = 4kB 682 * |= =| 683 * 684 * 685 */ 686 struct cs4280_softc *sc = p; 687 u_int32_t intr, mem; 688 char * empty_dma; 689 690 /* grab interrupt register then clear it */ 691 intr = BA0READ4(sc, CS4280_HISR); 692 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 693 694 /* not for me */ 695 if((intr & HISR_INTENA) == 0 ) 696 return 0; 697 698 /* Playback Interrupt */ 699 if (intr & HISR_PINT) { 700 mem = BA1READ4(sc, CS4280_PFIE); 701 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 702 if (sc->sc_pintr) { 703 if ((sc->sc_pi%sc->sc_pcount) == 0) 704 sc->sc_pintr(sc->sc_parg); 705 } else { 706 printf("unexpected play intr\n"); 707 } 708 /* copy buffer */ 709 ++sc->sc_pi; 710 empty_dma = sc->sc_pdma->addr; 711 if (sc->sc_pi&1) 712 empty_dma += CS4280_ICHUNK; 713 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 714 sc->sc_pn += CS4280_ICHUNK; 715 if (sc->sc_pn >= sc->sc_pe) 716 sc->sc_pn = sc->sc_ps; 717 BA1WRITE4(sc, CS4280_PFIE, mem); 718 } 719 /* Capture Interrupt */ 720 if (intr & HISR_CINT) { 721 int i; 722 int16_t rdata; 723 724 mem = BA1READ4(sc, CS4280_CIE); 725 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 726 ++sc->sc_ri; 727 empty_dma = sc->sc_rdma->addr; 728 if ((sc->sc_ri&1) == 0) 729 empty_dma += CS4280_ICHUNK; 730 731 /* 732 * XXX 733 * I think this audio data conversion should be 734 * happend in upper layer, but I put this here 735 * since there is no conversion function available. 736 */ 737 switch(sc->sc_rparam) { 738 case CF_16BIT_STEREO: 739 /* just copy it */ 740 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 741 sc->sc_rn += CS4280_ICHUNK; 742 break; 743 case CF_16BIT_MONO: 744 for (i = 0; i < 512; i++) { 745 rdata = *((int16_t *)empty_dma)++>>1; 746 rdata += *((int16_t *)empty_dma)++>>1; 747 *((int16_t *)sc->sc_rn)++ = rdata; 748 } 749 break; 750 case CF_8BIT_STEREO: 751 for (i = 0; i < 512; i++) { 752 rdata = *((int16_t*)empty_dma)++; 753 *sc->sc_rn++ = rdata >> 8; 754 rdata = *((int16_t*)empty_dma)++; 755 *sc->sc_rn++ = rdata >> 8; 756 } 757 break; 758 case CF_8BIT_MONO: 759 for (i = 0; i < 512; i++) { 760 rdata = *((int16_t*)empty_dma)++ >>1; 761 rdata += *((int16_t*)empty_dma)++ >>1; 762 *sc->sc_rn++ = rdata >>8; 763 } 764 break; 765 default: 766 /* Should not reach here */ 767 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 768 } 769 if (sc->sc_rn >= sc->sc_re) 770 sc->sc_rn = sc->sc_rs; 771 BA1WRITE4(sc, CS4280_CIE, mem); 772 if (sc->sc_rintr) { 773 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 774 sc->sc_rintr(sc->sc_rarg); 775 } else { 776 printf("unexpected record intr\n"); 777 } 778 } 779 780 #if NMIDI > 0 781 /* Midi port Interrupt */ 782 if (intr & HISR_MIDI) { 783 int data; 784 785 DPRINTF(("i: %d: ", 786 BA0READ4(sc, CS4280_MIDSR))); 787 /* Read the received data */ 788 while ((sc->sc_iintr != NULL) && 789 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 790 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 791 DPRINTF(("r:%x\n",data)); 792 sc->sc_iintr(sc->sc_arg, data); 793 } 794 795 /* Write the data */ 796 #if 1 797 /* XXX: 798 * It seems "Transmit Buffer Full" never activate until EOI 799 * is deliverd. Shall I throw EOI top of this routine ? 800 */ 801 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 802 DPRINTF(("w: ")); 803 if (sc->sc_ointr != NULL) 804 sc->sc_ointr(sc->sc_arg); 805 } 806 #else 807 while ((sc->sc_ointr != NULL) && 808 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 809 DPRINTF(("w: ")); 810 sc->sc_ointr(sc->sc_arg); 811 } 812 #endif 813 DPRINTF(("\n")); 814 } 815 #endif 816 817 return (1); 818 } 819 820 821 /* Download Proceessor Code and Data image */ 822 823 int 824 cs4280_download(sc, src, offset, len) 825 struct cs4280_softc *sc; 826 u_int32_t *src; 827 u_int32_t offset, len; 828 { 829 u_int32_t ctr; 830 831 #ifdef CS4280_DEBUG 832 u_int32_t con, data; 833 u_int8_t c0,c1,c2,c3; 834 #endif 835 if ((offset&3) || (len&3)) 836 return (-1); 837 838 len /= sizeof(u_int32_t); 839 for (ctr = 0; ctr < len; ctr++) { 840 /* XXX: 841 * I cannot confirm this is the right thing or not 842 * on BIG-ENDIAN machines. 843 */ 844 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 845 #ifdef CS4280_DEBUG 846 data = htole32(*(src+ctr)); 847 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 848 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 849 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 850 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 851 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 852 if (data != con ) { 853 printf("0x%06x: write=0x%08x read=0x%08x\n", 854 offset+ctr*4, data, con); 855 return (-1); 856 } 857 #endif 858 } 859 return (0); 860 } 861 862 int 863 cs4280_download_image(sc) 864 struct cs4280_softc *sc; 865 { 866 int idx, err; 867 u_int32_t offset = 0; 868 869 err = 0; 870 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 871 err = cs4280_download(sc, &BA1Struct.map[offset], 872 BA1Struct.memory[idx].offset, 873 BA1Struct.memory[idx].size); 874 if (err != 0) { 875 printf("%s: load_image failed at %d\n", 876 sc->sc_dev.dv_xname, idx); 877 return (-1); 878 } 879 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 880 } 881 return (err); 882 } 883 884 #ifdef CS4280_DEBUG 885 int 886 cs4280_checkimage(sc, src, offset, len) 887 struct cs4280_softc *sc; 888 u_int32_t *src; 889 u_int32_t offset, len; 890 { 891 u_int32_t ctr, data; 892 int err = 0; 893 894 if ((offset&3) || (len&3)) 895 return -1; 896 897 len /= sizeof(u_int32_t); 898 for (ctr = 0; ctr < len; ctr++) { 899 /* I cannot confirm this is the right thing 900 * on BIG-ENDIAN machines 901 */ 902 data = BA1READ4(sc, offset+ctr*4); 903 if (data != htole32(*(src+ctr))) { 904 printf("0x%06x: 0x%08x(0x%08x)\n", 905 offset+ctr*4, data, *(src+ctr)); 906 *(src+ctr) = data; 907 ++err; 908 } 909 } 910 return (err); 911 } 912 913 int 914 cs4280_check_images(sc) 915 struct cs4280_softc *sc; 916 { 917 int idx, err; 918 u_int32_t offset = 0; 919 920 err = 0; 921 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 922 for (idx = 0; idx < 1; ++idx) { 923 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 924 BA1Struct.memory[idx].offset, 925 BA1Struct.memory[idx].size); 926 if (err != 0) { 927 printf("%s: check_image failed at %d\n", 928 sc->sc_dev.dv_xname, idx); 929 } 930 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 931 } 932 return (err); 933 } 934 935 #endif 936 937 int 938 cs4280_attach_codec(sc_, codec_if) 939 void *sc_; 940 struct ac97_codec_if *codec_if; 941 { 942 struct cs4280_softc *sc = sc_; 943 944 sc->codec_if = codec_if; 945 return (0); 946 } 947 948 void 949 cs4280_reset_codec(sc_) 950 void *sc_; 951 { 952 struct cs4280_softc *sc = sc_; 953 int n; 954 955 /* Reset codec */ 956 BA0WRITE4(sc, CS4280_ACCTL, 0); 957 delay(100); /* delay 100us */ 958 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 959 960 /* 961 * It looks like we do the following procedure, too 962 */ 963 964 /* Enable AC-link sync generation */ 965 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 966 delay(50*1000); /* XXX delay 50ms */ 967 968 /* Assert valid frame signal */ 969 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 970 971 /* Wait for valid AC97 input slot */ 972 n = 0; 973 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 974 delay(1000); 975 if (++n > 1000) { 976 printf("reset_codec: AC97 inputs slot ready timeout\n"); 977 return; 978 } 979 } 980 } 981 982 983 /* Processor Soft Reset */ 984 void 985 cs4280_reset(sc_) 986 void *sc_; 987 { 988 struct cs4280_softc *sc = sc_; 989 990 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 991 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 992 delay(100); 993 /* Clear RSTSP bit in SPCR */ 994 BA1WRITE4(sc, CS4280_SPCR, 0); 995 /* enable DMA reqest */ 996 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 997 } 998 999 int 1000 cs4280_open(addr, flags) 1001 void *addr; 1002 int flags; 1003 { 1004 return (0); 1005 } 1006 1007 void 1008 cs4280_close(addr) 1009 void *addr; 1010 { 1011 struct cs4280_softc *sc = addr; 1012 1013 cs4280_halt_output(sc); 1014 cs4280_halt_input(sc); 1015 1016 sc->sc_pintr = 0; 1017 sc->sc_rintr = 0; 1018 } 1019 1020 int 1021 cs4280_query_encoding(addr, fp) 1022 void *addr; 1023 struct audio_encoding *fp; 1024 { 1025 switch (fp->index) { 1026 case 0: 1027 strcpy(fp->name, AudioEulinear); 1028 fp->encoding = AUDIO_ENCODING_ULINEAR; 1029 fp->precision = 8; 1030 fp->flags = 0; 1031 break; 1032 case 1: 1033 strcpy(fp->name, AudioEmulaw); 1034 fp->encoding = AUDIO_ENCODING_ULAW; 1035 fp->precision = 8; 1036 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1037 break; 1038 case 2: 1039 strcpy(fp->name, AudioEalaw); 1040 fp->encoding = AUDIO_ENCODING_ALAW; 1041 fp->precision = 8; 1042 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1043 break; 1044 case 3: 1045 strcpy(fp->name, AudioEslinear); 1046 fp->encoding = AUDIO_ENCODING_SLINEAR; 1047 fp->precision = 8; 1048 fp->flags = 0; 1049 break; 1050 case 4: 1051 strcpy(fp->name, AudioEslinear_le); 1052 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1053 fp->precision = 16; 1054 fp->flags = 0; 1055 break; 1056 case 5: 1057 strcpy(fp->name, AudioEulinear_le); 1058 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1059 fp->precision = 16; 1060 fp->flags = 0; 1061 break; 1062 case 6: 1063 strcpy(fp->name, AudioEslinear_be); 1064 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1065 fp->precision = 16; 1066 fp->flags = 0; 1067 break; 1068 case 7: 1069 strcpy(fp->name, AudioEulinear_be); 1070 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1071 fp->precision = 16; 1072 fp->flags = 0; 1073 break; 1074 default: 1075 return (EINVAL); 1076 } 1077 return (0); 1078 } 1079 1080 int 1081 cs4280_set_params(addr, setmode, usemode, play, rec) 1082 void *addr; 1083 int setmode, usemode; 1084 struct audio_params *play, *rec; 1085 { 1086 struct cs4280_softc *sc = addr; 1087 struct audio_params *p; 1088 int mode; 1089 1090 for (mode = AUMODE_RECORD; mode != -1; 1091 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1092 if ((setmode & mode) == 0) 1093 continue; 1094 1095 p = mode == AUMODE_PLAY ? play : rec; 1096 1097 if (p == play) { 1098 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1099 p->sample_rate, p->precision, p->channels)); 1100 /* play back data format may be 8- or 16-bit and 1101 * either stereo or mono. 1102 * playback rate may range from 8000Hz to 48000Hz 1103 */ 1104 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1105 (p->precision != 8 && p->precision != 16) || 1106 (p->channels != 1 && p->channels != 2) ) { 1107 return (EINVAL); 1108 } 1109 } else { 1110 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1111 p->sample_rate, p->precision, p->channels)); 1112 /* capture data format must be 16bit stereo 1113 * and sample rate range from 11025Hz to 48000Hz. 1114 * 1115 * XXX: it looks like to work with 8000Hz, 1116 * although data sheets say lower limit is 1117 * 11025 Hz. 1118 */ 1119 1120 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1121 (p->precision != 8 && p->precision != 16) || 1122 (p->channels != 1 && p->channels != 2) ) { 1123 return (EINVAL); 1124 } 1125 } 1126 p->factor = 1; 1127 p->sw_code = 0; 1128 1129 /* capturing data is slinear */ 1130 switch (p->encoding) { 1131 case AUDIO_ENCODING_SLINEAR_BE: 1132 if (mode == AUMODE_RECORD) { 1133 if (p->precision == 16) 1134 p->sw_code = swap_bytes; 1135 } 1136 break; 1137 case AUDIO_ENCODING_SLINEAR_LE: 1138 break; 1139 case AUDIO_ENCODING_ULINEAR_BE: 1140 if (mode == AUMODE_RECORD) { 1141 if (p->precision == 16) 1142 p->sw_code = change_sign16_swap_bytes_le; 1143 else 1144 p->sw_code = change_sign8; 1145 } 1146 break; 1147 case AUDIO_ENCODING_ULINEAR_LE: 1148 if (mode == AUMODE_RECORD) { 1149 if (p->precision == 16) 1150 p->sw_code = change_sign16_le; 1151 else 1152 p->sw_code = change_sign8; 1153 } 1154 break; 1155 case AUDIO_ENCODING_ULAW: 1156 if (mode == AUMODE_PLAY) { 1157 p->factor = 2; 1158 p->sw_code = mulaw_to_slinear16_le; 1159 } else { 1160 p->sw_code = slinear8_to_mulaw; 1161 } 1162 break; 1163 case AUDIO_ENCODING_ALAW: 1164 if (mode == AUMODE_PLAY) { 1165 p->factor = 2; 1166 p->sw_code = alaw_to_slinear16_le; 1167 } else { 1168 p->sw_code = slinear8_to_alaw; 1169 } 1170 break; 1171 default: 1172 return (EINVAL); 1173 } 1174 } 1175 1176 /* set sample rate */ 1177 cs4280_set_dac_rate(sc, play->sample_rate); 1178 cs4280_set_adc_rate(sc, rec->sample_rate); 1179 return (0); 1180 } 1181 1182 int 1183 cs4280_round_blocksize(hdl, blk) 1184 void *hdl; 1185 int blk; 1186 { 1187 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1188 } 1189 1190 size_t 1191 cs4280_round_buffersize(addr, direction, size) 1192 void *addr; 1193 int direction; 1194 size_t size; 1195 { 1196 /* although real dma buffer size is 4KB, 1197 * let the audio.c driver use a larger buffer. 1198 * ( suggested by Lennart Augustsson. ) 1199 */ 1200 return (size); 1201 } 1202 1203 int 1204 cs4280_get_props(hdl) 1205 void *hdl; 1206 { 1207 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1208 #ifdef notyet 1209 /* XXX 1210 * How can I mmap ? 1211 */ 1212 AUDIO_PROP_MMAP 1213 #endif 1214 1215 } 1216 1217 int 1218 cs4280_mixer_get_port(addr, cp) 1219 void *addr; 1220 mixer_ctrl_t *cp; 1221 { 1222 struct cs4280_softc *sc = addr; 1223 1224 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1225 } 1226 1227 paddr_t 1228 cs4280_mappage(addr, mem, off, prot) 1229 void *addr; 1230 void *mem; 1231 off_t off; 1232 int prot; 1233 { 1234 struct cs4280_softc *sc = addr; 1235 struct cs4280_dma *p; 1236 1237 if (off < 0) 1238 return (-1); 1239 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1240 ; 1241 if (!p) { 1242 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1243 return (-1); 1244 } 1245 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1246 off, prot, BUS_DMA_WAITOK)); 1247 } 1248 1249 1250 int 1251 cs4280_query_devinfo(addr, dip) 1252 void *addr; 1253 mixer_devinfo_t *dip; 1254 { 1255 struct cs4280_softc *sc = addr; 1256 1257 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1258 } 1259 1260 int 1261 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1262 struct cs4280_softc *sc; 1263 char *class, *device, *qualifier; 1264 { 1265 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1266 device, qualifier)); 1267 } 1268 1269 int 1270 cs4280_halt_output(addr) 1271 void *addr; 1272 { 1273 struct cs4280_softc *sc = addr; 1274 u_int32_t mem; 1275 1276 mem = BA1READ4(sc, CS4280_PCTL); 1277 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1278 #ifdef DIAGNOSTIC 1279 sc->sc_prun = 0; 1280 #endif 1281 return (0); 1282 } 1283 1284 int 1285 cs4280_halt_input(addr) 1286 void *addr; 1287 { 1288 struct cs4280_softc *sc = addr; 1289 u_int32_t mem; 1290 1291 mem = BA1READ4(sc, CS4280_CCTL); 1292 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1293 #ifdef DIAGNOSTIC 1294 sc->sc_rrun = 0; 1295 #endif 1296 return (0); 1297 } 1298 1299 int 1300 cs4280_getdev(addr, retp) 1301 void *addr; 1302 struct audio_device *retp; 1303 { 1304 *retp = cs4280_device; 1305 return (0); 1306 } 1307 1308 int 1309 cs4280_mixer_set_port(addr, cp) 1310 void *addr; 1311 mixer_ctrl_t *cp; 1312 { 1313 struct cs4280_softc *sc = addr; 1314 int val; 1315 1316 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1317 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1318 return (val); 1319 } 1320 1321 1322 int 1323 cs4280_freemem(sc, p) 1324 struct cs4280_softc *sc; 1325 struct cs4280_dma *p; 1326 { 1327 bus_dmamap_unload(sc->sc_dmatag, p->map); 1328 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1329 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1330 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1331 return (0); 1332 } 1333 1334 int 1335 cs4280_allocmem(sc, size, align, p) 1336 struct cs4280_softc *sc; 1337 size_t size; 1338 size_t align; 1339 struct cs4280_dma *p; 1340 { 1341 int error; 1342 1343 /* XXX */ 1344 p->size = size; 1345 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1346 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1347 &p->nsegs, BUS_DMA_NOWAIT); 1348 if (error) { 1349 printf("%s: unable to allocate dma, error=%d\n", 1350 sc->sc_dev.dv_xname, error); 1351 return (error); 1352 } 1353 1354 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1355 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1356 if (error) { 1357 printf("%s: unable to map dma, error=%d\n", 1358 sc->sc_dev.dv_xname, error); 1359 goto free; 1360 } 1361 1362 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1363 0, BUS_DMA_NOWAIT, &p->map); 1364 if (error) { 1365 printf("%s: unable to create dma map, error=%d\n", 1366 sc->sc_dev.dv_xname, error); 1367 goto unmap; 1368 } 1369 1370 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1371 BUS_DMA_NOWAIT); 1372 if (error) { 1373 printf("%s: unable to load dma map, error=%d\n", 1374 sc->sc_dev.dv_xname, error); 1375 goto destroy; 1376 } 1377 return (0); 1378 1379 destroy: 1380 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1381 unmap: 1382 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1383 free: 1384 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1385 return (error); 1386 } 1387 1388 1389 void * 1390 cs4280_malloc(addr, direction, size, pool, flags) 1391 void *addr; 1392 int direction; 1393 size_t size; 1394 int pool, flags; 1395 { 1396 struct cs4280_softc *sc = addr; 1397 struct cs4280_dma *p; 1398 caddr_t q; 1399 int error; 1400 1401 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1402 q = malloc(size, pool, flags); 1403 if (!q) 1404 return (0); 1405 p = malloc(sizeof(*p), pool, flags); 1406 if (!p) { 1407 free(q,pool); 1408 return (0); 1409 } 1410 /* 1411 * cs4280 has fixed 4kB buffer 1412 */ 1413 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1414 1415 if (error) { 1416 free(q, pool); 1417 free(p, pool); 1418 return (0); 1419 } 1420 1421 p->next = sc->sc_dmas; 1422 sc->sc_dmas = p; 1423 p->dum = q; /* return to audio driver */ 1424 1425 return (p->dum); 1426 } 1427 1428 void 1429 cs4280_free(addr, ptr, pool) 1430 void *addr; 1431 void *ptr; 1432 int pool; 1433 { 1434 struct cs4280_softc *sc = addr; 1435 struct cs4280_dma **pp, *p; 1436 1437 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1438 if (BUFADDR(p) == ptr) { 1439 cs4280_freemem(sc, p); 1440 *pp = p->next; 1441 free(p->dum, pool); 1442 free(p, pool); 1443 return; 1444 } 1445 } 1446 } 1447 1448 int 1449 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1450 void *addr; 1451 void *start, *end; 1452 int blksize; 1453 void (*intr) __P((void *)); 1454 void *arg; 1455 struct audio_params *param; 1456 { 1457 struct cs4280_softc *sc = addr; 1458 u_int32_t pfie, pctl, mem, pdtc; 1459 struct cs4280_dma *p; 1460 1461 #ifdef DIAGNOSTIC 1462 if (sc->sc_prun) 1463 printf("cs4280_trigger_output: already running\n"); 1464 sc->sc_prun = 1; 1465 #endif 1466 1467 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1468 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1469 sc->sc_pintr = intr; 1470 sc->sc_parg = arg; 1471 1472 /* stop playback DMA */ 1473 mem = BA1READ4(sc, CS4280_PCTL); 1474 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1475 1476 /* setup PDTC */ 1477 pdtc = BA1READ4(sc, CS4280_PDTC); 1478 pdtc &= ~PDTC_MASK; 1479 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1480 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1481 1482 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1483 param->precision, param->factor, param->channels, 1484 param->encoding)); 1485 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1486 ; 1487 if (p == NULL) { 1488 printf("cs4280_trigger_output: bad addr %p\n", start); 1489 return (EINVAL); 1490 } 1491 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1492 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1493 "4kB align\n", DMAADDR(p)); 1494 return (EINVAL); 1495 } 1496 1497 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1498 sc->sc_ps = (char *)start; 1499 sc->sc_pe = (char *)end; 1500 sc->sc_pdma = p; 1501 sc->sc_pbuf = KERNADDR(p); 1502 sc->sc_pi = 0; 1503 sc->sc_pn = sc->sc_ps; 1504 if (blksize >= CS4280_DCHUNK) { 1505 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1506 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1507 ++sc->sc_pi; 1508 } else { 1509 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1510 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1511 } 1512 1513 /* initiate playback dma */ 1514 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1515 1516 /* set PFIE */ 1517 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1518 1519 if (param->precision * param->factor == 8) 1520 pfie |= PFIE_8BIT; 1521 if (param->channels == 1) 1522 pfie |= PFIE_MONO; 1523 1524 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1525 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1526 pfie |= PFIE_SWAPPED; 1527 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1528 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1529 pfie |= PFIE_UNSIGNED; 1530 1531 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1532 1533 cs4280_set_dac_rate(sc, param->sample_rate); 1534 1535 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1536 pctl |= sc->pctl; 1537 BA1WRITE4(sc, CS4280_PCTL, pctl); 1538 return (0); 1539 } 1540 1541 int 1542 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1543 void *addr; 1544 void *start, *end; 1545 int blksize; 1546 void (*intr) __P((void *)); 1547 void *arg; 1548 struct audio_params *param; 1549 { 1550 struct cs4280_softc *sc = addr; 1551 u_int32_t cctl, cie; 1552 struct cs4280_dma *p; 1553 1554 #ifdef DIAGNOSTIC 1555 if (sc->sc_rrun) 1556 printf("cs4280_trigger_input: already running\n"); 1557 sc->sc_rrun = 1; 1558 #endif 1559 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1560 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1561 sc->sc_rintr = intr; 1562 sc->sc_rarg = arg; 1563 1564 sc->sc_ri = 0; 1565 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1566 sc->sc_rs = (char *)start; 1567 sc->sc_re = (char *)end; 1568 sc->sc_rn = sc->sc_rs; 1569 1570 /* setup format information for internal converter */ 1571 sc->sc_rparam = 0; 1572 if (param->precision == 8) { 1573 sc->sc_rparam += CF_8BIT; 1574 sc->sc_rcount <<= 1; 1575 } 1576 if (param->channels == 1) { 1577 sc->sc_rparam += CF_MONO; 1578 sc->sc_rcount <<= 1; 1579 } 1580 1581 /* stop capture DMA */ 1582 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1583 BA1WRITE4(sc, CS4280_CCTL, cctl); 1584 1585 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1586 ; 1587 if (!p) { 1588 printf("cs4280_trigger_input: bad addr %p\n", start); 1589 return (EINVAL); 1590 } 1591 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1592 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1593 "4kB align\n", DMAADDR(p)); 1594 return (EINVAL); 1595 } 1596 sc->sc_rdma = p; 1597 sc->sc_rbuf = KERNADDR(p); 1598 1599 /* initiate capture dma */ 1600 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1601 1602 /* set CIE */ 1603 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1604 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1605 1606 cs4280_set_adc_rate(sc, param->sample_rate); 1607 1608 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1609 cctl |= sc->cctl; 1610 BA1WRITE4(sc, CS4280_CCTL, cctl); 1611 return (0); 1612 } 1613 1614 int 1615 cs4280_init(sc, init) 1616 struct cs4280_softc *sc; 1617 int init; 1618 { 1619 int n; 1620 u_int32_t mem; 1621 1622 /* Start PLL out in known state */ 1623 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1624 /* Start serial ports out in known state */ 1625 BA0WRITE4(sc, CS4280_SERMC1, 0); 1626 1627 /* Specify type of CODEC */ 1628 /* XXX should not be here */ 1629 #define SERACC_CODEC_TYPE_1_03 1630 #ifdef SERACC_CODEC_TYPE_1_03 1631 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1632 #else 1633 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1634 #endif 1635 1636 /* Reset codec */ 1637 BA0WRITE4(sc, CS4280_ACCTL, 0); 1638 delay(100); /* delay 100us */ 1639 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1640 1641 /* Enable AC-link sync generation */ 1642 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1643 delay(50*1000); /* delay 50ms */ 1644 1645 /* Set the serial port timing configuration */ 1646 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1647 1648 /* Setup clock control */ 1649 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1650 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1651 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1652 1653 /* Power up the PLL */ 1654 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1655 delay(50*1000); /* delay 50ms */ 1656 1657 /* Turn on clock */ 1658 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1659 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1660 1661 /* Set the serial port FIFO pointer to the 1662 * first sample in FIFO. (not documented) */ 1663 cs4280_clear_fifos(sc); 1664 1665 #if 0 1666 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1667 BA0WRITE4(sc, CS4280_SERBSP, 0); 1668 #endif 1669 1670 /* Configure the serial port */ 1671 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1672 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1673 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1674 1675 /* Wait for CODEC ready */ 1676 n = 0; 1677 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1678 delay(125); 1679 if (++n > 1000) { 1680 printf("%s: codec ready timeout\n", 1681 sc->sc_dev.dv_xname); 1682 return(1); 1683 } 1684 } 1685 1686 /* Assert valid frame signal */ 1687 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1688 1689 /* Wait for valid AC97 input slot */ 1690 n = 0; 1691 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1692 (ACISV_ISV3 | ACISV_ISV4)) { 1693 delay(1000); 1694 if (++n > 1000) { 1695 printf("AC97 inputs slot ready timeout\n"); 1696 return(1); 1697 } 1698 } 1699 1700 /* Set AC97 output slot valid signals */ 1701 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1702 1703 /* reset the processor */ 1704 cs4280_reset(sc); 1705 1706 /* Download the image to the processor */ 1707 if (cs4280_download_image(sc) != 0) { 1708 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1709 return(1); 1710 } 1711 1712 /* Save playback parameter and then write zero. 1713 * this ensures that DMA doesn't immediately occur upon 1714 * starting the processor core 1715 */ 1716 mem = BA1READ4(sc, CS4280_PCTL); 1717 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1718 cs4280_halt_output(sc); 1719 1720 /* Save capture parameter and then write zero. 1721 * this ensures that DMA doesn't immediately occur upon 1722 * starting the processor core 1723 */ 1724 mem = BA1READ4(sc, CS4280_CCTL); 1725 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1726 cs4280_halt_input(sc); 1727 1728 /* Processor Startup Procedure */ 1729 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1730 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1731 1732 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1733 n = 0; 1734 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1735 delay(10); 1736 if (++n > 1000) { 1737 printf("SPCR 1->0 transition timeout\n"); 1738 return(1); 1739 } 1740 } 1741 1742 n = 0; 1743 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1744 delay(10); 1745 if (++n > 1000) { 1746 printf("SPCS 0->1 transition timeout\n"); 1747 return(1); 1748 } 1749 } 1750 /* Processor is now running !!! */ 1751 1752 /* Setup volume */ 1753 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1754 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1755 1756 /* Interrupt enable */ 1757 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1758 1759 /* playback interrupt enable */ 1760 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1761 mem |= PFIE_PI_ENABLE; 1762 BA1WRITE4(sc, CS4280_PFIE, mem); 1763 /* capture interrupt enable */ 1764 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1765 mem |= CIE_CI_ENABLE; 1766 BA1WRITE4(sc, CS4280_CIE, mem); 1767 1768 #if NMIDI > 0 1769 /* Reset midi port */ 1770 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1771 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1772 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1773 /* midi interrupt enable */ 1774 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1775 BA0WRITE4(sc, CS4280_MIDCR, mem); 1776 #endif 1777 return(0); 1778 } 1779 1780 void 1781 cs4280_power(why, v) 1782 int why; 1783 void *v; 1784 { 1785 struct cs4280_softc *sc = (struct cs4280_softc *)v; 1786 int i; 1787 1788 DPRINTF(("%s: cs4280_power why=%d\n", 1789 sc->sc_dev.dv_xname, why)); 1790 switch (why) { 1791 case PWR_SUSPEND: 1792 case PWR_STANDBY: 1793 sc->sc_suspend = why; 1794 1795 cs4280_halt_output(sc); 1796 cs4280_halt_input(sc); 1797 /* Save AC97 registers */ 1798 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1799 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1800 continue; 1801 cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i]); 1802 } 1803 /* should I powerdown here ? */ 1804 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1805 break; 1806 case PWR_RESUME: 1807 if (sc->sc_suspend == PWR_RESUME) { 1808 printf("cs4280_power: odd, resume without suspend.\n"); 1809 sc->sc_suspend = why; 1810 return; 1811 } 1812 sc->sc_suspend = why; 1813 cs4280_init(sc, 0); 1814 cs4280_reset_codec(sc); 1815 1816 /* restore ac97 registers */ 1817 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1818 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1819 continue; 1820 cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]); 1821 } 1822 break; 1823 case PWR_SOFTSUSPEND: 1824 case PWR_SOFTSTANDBY: 1825 case PWR_SOFTRESUME: 1826 break; 1827 } 1828 } 1829 1830 void 1831 cs4280_clear_fifos(sc) 1832 struct cs4280_softc *sc; 1833 { 1834 int pd = 0, cnt, n; 1835 u_int32_t mem; 1836 1837 /* 1838 * If device power down, power up the device and keep power down 1839 * state. 1840 */ 1841 mem = BA0READ4(sc, CS4280_CLKCR1); 1842 if (!(mem & CLKCR1_SWCE)) { 1843 printf("cs4280_clear_fifo: power down found.\n"); 1844 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1845 pd = 1; 1846 } 1847 BA0WRITE4(sc, CS4280_SERBWP, 0); 1848 for (cnt = 0; cnt < 256; cnt++) { 1849 n = 0; 1850 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1851 delay(1000); 1852 if (++n > 1000) { 1853 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1854 break; 1855 } 1856 } 1857 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1858 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1859 } 1860 if (pd) 1861 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1862 } 1863 1864 #if NMIDI > 0 1865 int 1866 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1867 void *addr; 1868 int flags; 1869 void (*iintr)__P((void *, int)); 1870 void (*ointr)__P((void *)); 1871 void *arg; 1872 { 1873 struct cs4280_softc *sc = addr; 1874 u_int32_t mem; 1875 1876 DPRINTF(("midi_open\n")); 1877 sc->sc_iintr = iintr; 1878 sc->sc_ointr = ointr; 1879 sc->sc_arg = arg; 1880 1881 /* midi interrupt enable */ 1882 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1883 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1884 BA0WRITE4(sc, CS4280_MIDCR, mem); 1885 #ifdef CS4280_DEBUG 1886 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1887 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1888 return(EINVAL); 1889 } 1890 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1891 #endif 1892 return (0); 1893 } 1894 1895 void 1896 cs4280_midi_close(addr) 1897 void *addr; 1898 { 1899 struct cs4280_softc *sc = addr; 1900 u_int32_t mem; 1901 1902 DPRINTF(("midi_close\n")); 1903 mem = BA0READ4(sc, CS4280_MIDCR); 1904 mem &= ~MIDCR_MASK; 1905 BA0WRITE4(sc, CS4280_MIDCR, mem); 1906 1907 sc->sc_iintr = 0; 1908 sc->sc_ointr = 0; 1909 } 1910 1911 int 1912 cs4280_midi_output(addr, d) 1913 void *addr; 1914 int d; 1915 { 1916 struct cs4280_softc *sc = addr; 1917 u_int32_t mem; 1918 int x; 1919 1920 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1921 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1922 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1923 mem |= d & MIDWP_MASK; 1924 DPRINTFN(5,("midi_output d=0x%08x",d)); 1925 BA0WRITE4(sc, CS4280_MIDWP, mem); 1926 #ifdef DIAGNOSTIC 1927 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1928 DPRINTF(("Bad write data: %d %d", 1929 mem, BA0READ4(sc, CS4280_MIDWP))); 1930 return(EIO); 1931 } 1932 #endif 1933 return (0); 1934 } 1935 delay(MIDI_BUSY_DELAY); 1936 } 1937 return (EIO); 1938 } 1939 1940 void 1941 cs4280_midi_getinfo(addr, mi) 1942 void *addr; 1943 struct midi_info *mi; 1944 { 1945 mi->name = "CS4280 MIDI UART"; 1946 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1947 } 1948 1949 #endif 1950
Indexes created Thu Oct 02 14:10:14 GMT 2025